Log in
Register

Electrical and Electronics Engineering publications abstract of: 12-2016 sorted by title, page: 0

» "Anything as a Service" for 5G Mobile Systems
Abstract:
5G network architecture and its functions are yet to be defined. However, it is generally agreed that cloud computing, network function virtualization (NFV), and software defined networking (SDN) will be key enabling technologies for 5G. Indeed, putting all these technologies together ensures several advantages in terms of network configuration flexibility, scalability, and elasticity, which are highly needed to fulfill the numerous requirements of 5G. Furthermore, 5G network management procedures should be as simple as possible, allowing network operators to orchestrate and manage the lifecycle of their virtual network infrastructures (VNIs) and the corresponding virtual network functions (VNFs), in a cognitive and programmable fashion. To this end, we introduce the concept of “Anything as a Service” (ANYaaS), which allows a network operator to create and orchestrate 5G services on demand and in a dynamic way. ANYaaS relies on the reference ETSI NFV architecture to orchestrate and manage important services such as mobile Content Delivery Network as a Service (CDNaaS), Traffic Offload as a Service (TOFaaS), and Machine Type Communications as a Service (MTCaaS). Ultimately, ANYaaS aims for enabling dynamic creation and management of mobile services through agile approaches that handle 5G network resources and services.
Autors: Tarik Taleb;Adlen Ksentini;Riku Jantti;
Appeared in: IEEE Network
Publication date: Dec 2016, volume: 30, issue:6, pages: 84 - 91
Publisher: IEEE
 
» $4 times 4$ InP Switch Matrix With Electro-Optically Actuated Higher Order Micro-Ring Resonators
Abstract:
A crosspoint switch circuit based on resonant elements is demonstrated on a generic InP integrated photonics platform. The switch matrix is constructed from a crosspoint grid of the third-order ring resonator switch elements. Electro-optic tuning is used for actuation, with a tuning range of 0.46 times the free spectral range. Integrated optical amplifiers compensate on-chip losses. Physical layer characterization is performed to demonstrate 10- and 20-Gb/s data routing with a maximum power penalty of 2.6 dB. Fast switching transients of under 10 ns are shown.
Autors: R. Stabile;P. DasMahapatra;K. A. Williams;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2016, volume: 28, issue:24, pages: 2874 - 2877
Publisher: IEEE
 
» ${V}$ -Band Integrated on-Chip Antenna Implemented With a Partially Reflective Surface in Standard 0.13- $mu text{m}$ BiCMOS Technology
Abstract:
A -band on-chip triangular planar monopole antenna implemented with a partially reflective surface (PRS) using standard 0.13- BiCMOS technology is presented. The PRS, which is realized with a dual-layered gangbuster type-4 frequency selective surface structure, is designed to obtain 90% reflection of the incident power, thus reducing the power loss caused by the lossy silicon substrate and increasing the radiation efficiency simultaneously. The antenna-PRS codesign technique to optimize the antenna geometry and the radiation power is discussed. The total area of the antenna, including the GSG pad and the PRS, is 0.868 mm2. The measured is smaller than −17 dB from 54 to 66 GHz, while the maximum measured antenna gain is 1.42 dB at 69.5 GHz. The maximum simulated antenna efficiency is 41% at 65 GHz.
Autors: Chuan-Chang Liu;Roberto G. Rojas;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2016, volume: 64, issue:12, pages: 5102 - 5109
Publisher: IEEE
 
» "Ethics"
Abstract:
In an age of high competition and innovation, often companies push to be first on the market, in full knowledge that the initial version isn't perfect, with plans to improve it or address other functionalities in updates. Where should the ethical line be drawn, though, between market competitiveness and quality assurance in engineering?
Autors: Vinton G. Cerf;
Appeared in: IEEE Internet Computing
Publication date: Dec 2016, volume: 20, issue:6, pages: 79 - 80
Publisher: IEEE
 
» 100-Gb/s 3R Regeneration With Cross Gain Compression in Semiconductor Optical Amplifiers
Abstract:
All optical 3R regeneration of 100-Gb/s return-to-zero on-off-keying (OOK) signal based on cross gain compression effect using semiconductor optical amplifiers is experimentally demonstrated for the first time. The shape of optical filters and signal powers are carefully adjusted to obtain the regenerative result. Bit error rate (BER) measurement is performed, and the receiving sensitivity is improved by 2 to 3 dB in the regenerative signal, compared with the degraded signal. Regenerative capability for different degrees of degradation has been studied.
Autors: Xin Chen;Li Huo;Qiang Wang;Caiyun Lou;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2016, volume: 8, issue:6, pages: 1 - 7
Publisher: IEEE
 
» 120 Gbit/s 2 × 2 Vector-Modes-Division- Multiplexing DD-OFDM-32QAM Free-Space Transmission
Abstract:
We demonstrate a 120-Gbit/s mode-division-multiplexing (MDM) system based on two typical vector modes of TE01 and TM01 with direct detection orthogonal frequency division multiplexing (DD-OFDM) and 32-quadrature-amplitude-modulation (32-QAM) signal. The vector mode conversion is achieved by the key q-plate and the mode crosstalk between the converted two vector modes are both less than –20 dB. This crosstalk can be further minimized by high-quality q-plate. In this demonstration, error-free transmission has been realized with the power penalties less than 2 dB. The experimental results show that the scheme proposed in this paper can be a good candidate in large-capacity short-reach optical interconnect.
Autors: Jianbo Zhang;Fan Li;Jianping Li;Yuanhua Feng;Zhaohui Li;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2016, volume: 8, issue:6, pages: 1 - 8
Publisher: IEEE
 
» 14.8-MeV Neutron Irradiation on H-Terminated Diamond-Based MESFETs
Abstract:
Field-effect transistors (FETs) fabricated on hydrogen-terminated diamond surface have been heavily irradiated with 14.8-MeV neutrons in order to evaluate their possible application in very high neutron fluence environments. The dc performance of the diamond-based FETs, such as drain saturation current and maximum transconductance, has been studied as a function of a 14.8-MeV neutron fluence up to n/cm2, delivered in five steps. The effects on electrical properties of H-terminated diamond surface have also been investigated during the neutron irradiation experiments. The Hall parameters, i.e., sheet hole concentration, hole mobility, and sheet resistance, were monitored before and after each irradiation. The performance remains stable during all the neutron fluence steps, thus assessing a remarkable radiation hardness of diamond-based devices. To the best of our knowledge, this is the first published data on 14-MeV neutron tolerance of diamond FET devices.
Autors: C. Verona;W. Ciccognani;S. Colangeli;E. Limiti;Marco Marinelli;G. Verona-Rinati;E. Santoni;M. Angelone;M. Pillon;F. Pompili;M. Benetti;D. Cannatà;F. Di Pietrantonio;
Appeared in: IEEE Electron Device Letters
Publication date: Dec 2016, volume: 37, issue:12, pages: 1597 - 1600
Publisher: IEEE
 
» 2-D Ultrasound Sparse Arrays Multidepth Radiation Optimization Using Simulated Annealing and Spiral-Array Inspired Energy Functions
Abstract:
Full matrix arrays are excellent tools for 3-D ultrasound imaging, but the required number of active elements is too high to be individually controlled by an equal number of scanner channels. The number of active elements is significantly reduced by the sparse array techniques, but the position of the remaining elements must be carefully optimized. This issue is faced here by introducing novel energy functions in the simulated annealing (SA) algorithm. At each iteration step of the optimization process, one element is freely translated and the associated radiated pattern is simulated. To control the pressure field behavior at multiple depths, three energy functions inspired by the pressure field radiated by a Blackman-tapered spiral array are introduced. Such energy functions aim at limiting the main lobe width while lowering the side lobe and grating lobe levels at multiple depths. Numerical optimization results illustrate the influence of the number of iterations, pressure measurement points, and depths, as well as the influence of the energy function definition on the optimized layout. It is also shown that performance close to or even better than the one provided by a spiral array, here assumed as reference, may be obtained. The finite-time convergence properties of SA allow the duration of the optimization process to be set in advance.
Autors: Emmanuel Roux;Alessandro Ramalli;Piero Tortoli;Christian Cachard;Marc C. Robini;Hervé Liebgott;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Dec 2016, volume: 63, issue:12, pages: 2138 - 2149
Publisher: IEEE
 
» 2015 International Symposium on Computer Architecture Influential Paper Award
Abstract:
This column discusses the 2015 ISCA Influential Paper Award, which recognized "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations" by David Brooks, Vivek Tiwari, and Margaret Martonosi.
Autors: David H. Albonesi;
Appeared in: IEEE Micro
Publication date: Dec 2016, volume: 36, issue:6, pages: 60 - 61
Publisher: IEEE
 
» 2016 Holiday Gift Guide
Abstract:
The Vintage Computer Federation is the world's largest group of collectors and restorers of historic computing systems. Member activities include hands-on exhibitions conducted at all manner of tech-themed gatherings around the United States, in addition to the federation’s own Vintage Computer Festival events. At the World Maker Faire in New York City, in October, two of our mid-Atlantic chapter members born in the 1970s decided to demonstrate computers and robotic kits from the 1980s, using programming languages developed in the 1960s.
Autors: Jeffrey Brace;Evan Koblentz;
Appeared in: IEEE Spectrum
Publication date: Dec 2016, volume: 53, issue:12, pages: 22 - 23
Publisher: IEEE
 
» 2016 Joint Rail Conference [From the Guest Editor]
Abstract:
Autors: Bih-Yuan Ku;
Appeared in: IEEE Vehicular Technology Magazine
Publication date: Dec 2016, volume: 11, issue:4, pages: 17 - 18
Publisher: IEEE
 
» 2016~Scott Helt Memorial Award for the Best Paper Published in the IEEE Transactions on Broadcasting
Abstract:
Presents the recipients of the Broadcasting Society's 2016 Scott Helt Memorial Award.
Autors: ;
Appeared in: IEEE Transactions on Broadcasting
Publication date: Dec 2016, volume: 62, issue:4, pages: 749 - 750
Publisher: IEEE
 
» 3-D Integration and ESD Protection: Design and Analysis
Abstract:
A set of design of experiments matrix was created to evaluate the possibilities of electrostatic-discharge (ESD) failures during the complex 3-D integration process as a function of the ESD protection level. A detailed set of pass/fail criteria based on circuit performance was established. Various phases of 3-D integration are monitored for ESD failures. Based on measured samples, it was observed that the functionality test and leakage test show circuit performance degradation and a larger fail rate after chip-to-chip bonding on designs without ESD protection.
Autors: Souvick Mitra;Ephrem Gebreselasie;You Li;Robert Gauthier;Thuy Tran-Quinn;Koushik Ramachandran;
Appeared in: IEEE Transactions on Device and Materials Reliability
Publication date: Dec 2016, volume: 16, issue:4, pages: 497 - 503
Publisher: IEEE
 
» 3-D Magnetohydrodynamic Modeling of DC Arc in Power System
Abstract:
With the rise of large-scale photovoltaic arrays and dc buses in power systems, dc-arc hazards have raised great concerns. Currently, the IEEE Std. 1584-2002 pertains to arc flashes originating in only ac systems. Little research has been conducted to investigate the theoretical or semiempirical methods to estimate dc arcs. The theoretical method, based on the maximum power transfer theorem, overall produces the estimations on the conservative side; the semiempirical methods are limited by the experiment scale, which cannot provide the comprehensive dc-arc prediction to the industry. This paper presents a magnetohydrodynamic (MHD) model of dc arcs. The MHD equations are solved by using computational fluid dynamic (CFD) software Code Saturne, which is based on collocated finite volume. The simulation results are compatible with the lab testing. The proposed MHD modeling provides an innovative approach to study dc-arc phenomena.
Autors: Shiuan-Hau Rau;Zhenyuan Zhang;Wei-Jen Lee;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Dec 2016, volume: 52, issue:6, pages: 4549 - 4555
Publisher: IEEE
 
» 3-D Numerical Characterization of a Microwave Argon PECVD Plasma Reactor at Low Pressure
Abstract:
A 3-D model of a microwave plasma (mwp)-enhanced chemical vapor deposition (PECVD) reactor at 2.45 GHz in argon at low pressure describing self-consistently, the coupling of the microwave energy into the plasma is presented. The characteristics of the discharge are simulated using a fluid plasma model which solves the electron and ion continuity equations, electron energy balance equation, and the Poisson’s equation by finite element method, using COMSOL Multiphysics software. The physical behavior of the microwave PECVD discharge, such as plasma density, electron temperature, electric field and plasma potential, are simulated and analyzed. The chemical reactions considered in this paper are: elastic, superelastic, excitation, ionization, penning ionization and metastable quenching processes, involving electrons, ions (Ar+), neutral atoms (Ar), and excited metastable argon atoms (Ar*). The plasma characterization results are studied for a gas temperature of 300 K, a gas pressure of 100 mtorr and a microwave power of 600 W. The effect of varying gas pressure from 50 to 200 mTorr has been studied. The obtained results turn out to be in agreement with previous measurements and show that this kind of model can lead to a better understanding of the physical processes occurring in this kind of microwave reactor and thus allow optimization of this device.
Autors: K. Bouherine;A. Tibouche;N. Ikhlef;O. Leroy;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Dec 2016, volume: 44, issue:12, pages: 3409 - 3416
Publisher: IEEE
 
» 3-D Quasi-Atomistic Model for Line Edge Roughness in Nonplanar MOSFETs
Abstract:
As the physical sizes of devices have been scaled down, the negative impact of process-induced random variation on device performance has increased; therefore, there is an urgent demand for advanced simulation methods for variation. In this paper, a 3-D quasi-atomistic simulation methodology for line edge roughness (LER) in nonplanar devices, such as FinFETs and gate-all-around (GAA) FETs, is proposed. In addition, a simple gate oxide layer model is proposed to analyze the impact of LER on device performance while excluding the impact of oxide thickness variation. To verify the importance of the quasi-atomistic 3-D LER model and to compare the LER-induced performance variation in a FinFET to that in a GAA FET, the case studies using the 3-D quasi-atomistic LER model for FinFETs and GAA FETs are performed.
Autors: Sangheon Oh;Changhwan Shin;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2016, volume: 63, issue:12, pages: 4617 - 4623
Publisher: IEEE
 
» 3-D Reconstruction Algorithm of Flame Based on Inversion Calculation of Thermal Radiation
Abstract:
This paper presents the design, method, and evaluation of a 3-D field reconstruction of a combustion flame. Three images under three different wavelengths were captured together using charge-coupled device cameras, which were specially processed by filters. Three sets of data about the value of radiation under different wavelengths were transformed from the images that were obtained according to the law of thermal radiation and derivation. For a pixel point in flame image, its irradiance can be expressed as the accumulation of the emissive power from luminous flame with different temperatures along the rays through the pixel. Then, through the calculation of the thermal radiation inversion based on the data from pixels in images, the 3-D temperature field of the flame is obtained and displayed. Experimental tests were done using candle flame to evaluate the effectiveness of the system. Ultimately, this method can restore the temperature distribution of the flame temperature field effectively. Compared with other methods, such as the two-color pyrometric method, the device of this method can get synchronous monochromatic images under three different wavelengths, the beams of which were through a beam splitter at the same time to avoid the errors of spatiotemporal matching. Else, we can reproduce the validity and efficiency of temperature field using the reconstruction algorithm that is built on improved simulated annealing algorithm.
Autors: Zhenhua Wei;Yan Li;Zhihong Li;Shibo Song;Binyang Li;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Dec 2016, volume: 65, issue:12, pages: 2808 - 2815
Publisher: IEEE
 
» 3-D Shaping of a Focused Aperture in the Near Field
Abstract:
The manipulation of the near-field (NF) is a challenging topic in electromagnetics, carrying essential importance for several applications. In this paper, we develop an algorithm capable of shaping the NF in 3-D domains according to given specifications. The algorithm is based on a set theoretic approach and a front-and-back iterative propagation scheme. The latter is realized using fast Fourier transforms (FFT), reducing the required computational time. The algorithm is applied on a focal shaping scenario. In this case, a full control of the depth of focus, spot diameter, and sidelobe level of the generated radiation is achieved. In particular, the proposed procedure is successfully adopted to control the normal component of a radiating aperture over a range of at 30 GHz. The derived aperture field distribution is then synthesized by a radial line slot antenna (RLSA) by means of an in-house method of moments (MoM) code. NF measurements have validated the proposed approach and prototype.
Autors: Ioannis Iliopoulos;Massimiliano Casaletti;Ronan Sauleau;Philippe Pouliguen;Patrick Potier;Mauro Ettorre;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2016, volume: 64, issue:12, pages: 5262 - 5271
Publisher: IEEE
 
» 360° Beam-Steering Reconfigurable Wideband Substrate Integrated Waveguide Horn Antenna
Abstract:
A novel beam-steering reconfigurable substrate integrated waveguide (SIW) horn antenna is presented. By employing p-i-n diodes as tuning mechanisms, the states of copper posts of the SIW horn can be electronically controlled. Accordingly, the aperture direction of the horn can be switched, and a 360° beam-scanning ability is realized. A pair of bowl-shaped reflectors is introduced for achieving a wide impedance bandwidth and good directional radiation patterns. A fully functional prototype with a 26.2% impedance bandwidth is developed and tested, demonstrating the antenna with a measured gain varying between 8 and 10 dBi and a radiation efficiency of approximately 75% over the impedance band. Moreover, owning to its symmetrical structure, the proposed antenna is capable of steering the radiation beam every 22.5° with identical radiation patterns in the H-plane.
Autors: Lei Ge;Kwai Man Luk;Shichang Chen;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2016, volume: 64, issue:12, pages: 5005 - 5011
Publisher: IEEE
 
» 3D Human Gait Reconstruction and Monitoring Using Body-Worn Inertial Sensors and Kinematic Modeling
Abstract:
In this paper, we present a novel low-cost computationally efficient method to accurately assess human gait by monitoring the 3D trajectory of the lower limb, both left and right legs outside the lab in any unconstrained environment. Our method utilizes a network of miniaturized wireless inertial sensors, coupled with a suite of real-time analysis algorithms and can operate in any unconstrained environment. First, we adopt a modified computationally efficient, highly accurate, and near real-time gradient descent algorithm to compute the direction of the gyroscope measurement error as a quaternion derivative in order to obtain the 3D orientation of each of the six segments. Second, by utilizing the foot sensor, we successfully detect the stance phase of the human gait cycle, which allows us to obtain drift-free velocity and the 3D position of the left and right feet during functional phases of a gait cycle. Third, by setting the foot segment as the root node we calculate the 3D orientation and position of the other two segments as well as the left and right ankle, knee, and hip joints. We then employ a customized kinematic model adjustment technique to ensure that the motion is coherent with human biomechanical behavior of the leg. Pearson’s correlation coefficient () and significant difference test results () were used to quantify the relationship between the calculated and measured movements for all joints in the sagittal plane. The correlation between the calculated and the reference was found to have similar trends for all six joints .
Autors: Amin Ahmadi;François Destelle;Luis Unzueta;David S. Monaghan;Maria Teresa Linaza;Kieran Moran;Noel E. O’Connor;
Appeared in: IEEE Sensors Journal
Publication date: Dec 2016, volume: 16, issue:24, pages: 8823 - 8831
Publisher: IEEE
 
» 3D Human Model Reconstruction from Sparse Uncalibrated Views
Abstract:
Using a two-stage algorithm, the proposed technique can tackle the challenges of reconstructing high-quality 3D models of humans wearing regular clothes from sparse uncalibrated cameras. The proposed algorithm based on nonrigid dense correspondences (NRDC) requires fewer images than previous methods because it does not require an initial sparse matching. The authors validated the proposed algorithm using images from an existing dataset and images captured by a cell phone camera.
Autors: Xiaoguang Han;Kwan-Yee K. Wong;Yizhou Yu;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Dec 2016, volume: 36, issue:6, pages: 46 - 56
Publisher: IEEE
 
» 4-D ICE: A 2-D Array Transducer With Integrated ASIC in a 10-Fr Catheter for Real-Time 3-D Intracardiac Echocardiography
Abstract:
We developed a mm-D array transducer with integrated transmit/receive application-specific integrated circuit (ASIC) for real-time 3-D intracardiac echocardiography (4-D ICE) applications. The ASIC and transducer design were optimized so that the high-voltage transmit, low-voltage time-gain control and preamp, subaperture beamformer, and digital control circuits for each transducer element all fit within the 0.019-mm area of the element. The transducer assembly was deployed in a 10-Fr (3.3-mm diameter) catheter, integrated with a GE Vivid E9 ultrasound imaging system, and evaluated in three preclinical studies. The 2-D image quality and imaging modes were comparable to commercial 2-D ICE catheters. The 4-D field of view was at least cm and could be imaged at 30 vol/s, sufficient to visualize cardiac anatomy and other diagnostic and therapy catheters. 4-D ICE should significantly reduce X-ray fluoroscopy use and dose during electrophysiology ablation procedures. 4-D ICE may be able to replace transesophageal echocardiography (TEE), and the associated risks and costs of general anesthesia, for guidance of some structural heart procedures.
Autors: Douglas Wildes;Warren Lee;Bruno Haider;Scott Cogan;Krishnakumar Sundaresan;David M. Mills;Christopher Yetter;Patrick H. Hart;Christopher R. Haun;Mikael Concepcion;Johan Kirkhorn;Marc Bitoun;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Dec 2016, volume: 63, issue:12, pages: 2159 - 2173
Publisher: IEEE
 
» 5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications
Abstract:
This paper presents a 5-bit noninterleaved time-based analog-to-digital converter (ADC), which operates at a 5-GS/s rate. The ADC is designed for the use in radio-astronomy telescopes, for which time interleaving is not acceptable. The ADC employs a dynamic, differential voltage-to-time converter, a folded-flash time-to-digital converter (TDC), and calibration circuitry. To generate reference delays, the calibration circuitry utilizes a delay-time reference network, which is designed to map the input voltage range into 16 equal time intervals that are used for the calibration of the TDC. The 65-nm CMOS ADC achieves the Signal-to-noise plus distortion ratio/spurious-free dynamic range of 27/32 dB at Nyquist, an effective number of bits (ENOB) of 4.7 bit at low frequencies and 4.1 bit at high frequencies with a power consumption of 21.5 mW at Nyquist.
Autors: Yongsheng Xu;Ge Wu;Leonid Belostotski;James W. Haslett;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2016, volume: 24, issue:12, pages: 3513 - 3525
Publisher: IEEE
 
» 53.3 W Visible-Waveband Extra High Power Supercontinuum All-Fiber Laser
Abstract:
A visible-waveband extra high power supercontinuum (SC) all-fiber laser is demonstrated. The laser structure includes a seed laser, master power amplifier, and the SC generation system, which usually adopts photonic crystal fiber (PCF) with small mode area as the nonlinear (NL) medium. A repetition frequency multiplier is utilized in the seed laser to adjust the pulse peak power and suppress the NL effects in the amplification process. Additionally, a homemade all-fiber high power mode field adaptor, which is used to couple the pump pulses into the small mode area PCF, works successfully at the incident pulse power of 120 W with high coupling efficiency of 83%. Eventually, 53.3 W visible-waveband extra high power SC fiber laser is obtained with spectrum ranging from 430 to 2400 nm and spectral width below 10 dB flatness exceeding 1700 nm (except pump wavelength). In addition, the visible-waveband power (below 850 nm) takes up about 22% of the total SC power. To the best of our knowledge, this is the highest average power of visible-waveband extra SC source ever reported in such broad spectrum range and high spectrum flatness.
Autors: Chang Sun;Tingwu Ge;Siyuan Li;Na An;Kang Cao;Zhiyong Wang;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2016, volume: 8, issue:6, pages: 1 - 7
Publisher: IEEE
 
» 550 °C 4H-SiC p-i-n Photodiode Array With Two-Layer Metallization
Abstract:
The p-i-n ultraviolet (UV) photodiodes based on 4H-SiC have been fabricated and characterized from room temperature (RT) to 550 °C. Due to bandgap narrowing at higher temperatures, the photocurrent of the photodiode increases by 9 times at 365 nm and reduces by 2.6 times at 275 nm from RT to 550 °C. Moreover, a 4H-SiC p-i-n photodiode array has been fabricated. Each column and row of the array is separately connected by two-layer metallization.
Autors: Shuoben Hou;Per-Erik Hellström;Carl-Mikael Zetterling;Mikael Östling;
Appeared in: IEEE Electron Device Letters
Publication date: Dec 2016, volume: 37, issue:12, pages: 1594 - 1596
Publisher: IEEE
 
» 60 GHz Low Phase Error Rotman Lens Combined With Wideband Microstrip Antenna Array Using LTCC Technology
Abstract:
This paper presents a new design technique and analysis for a microstrip Rotman lens which is feeding a wide bandwidth series-fed microstrip patch antenna array. In the proposed Rotman lens method, the length of the transmission lines does not affect the progressive phase delay. This reduces the complexity of the design and improves the performance parameters. An antenna array is utilized using open ended stubs to support high gain, directivity, and a wide bandwidth. The Rotman lens and antenna arrays are fabricated on the top layer of a multilayer low temperature cofired ceramic substrate. The Rotman lens has been designed based on the presented technique, which has five beam ports, five array ports, four dummy ports, and a footprint as small as 11 mm mm at 60 GHz operation frequency. The implemented lens and antenna array exhibits good insertion loss, return loss, and wide bandwidth and shows phase error as small as 0.45° in the worst case scenario.
Autors: Ali Attaran;Rashid Rashidzadeh;Ammar Kouki;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2016, volume: 64, issue:12, pages: 5172 - 5180
Publisher: IEEE
 
» 64QAM Vector Radio-Frequency Signal Generation Based on Phase Precoding and Optical Carrier Suppression Modulation
Abstract:
We propose a 64-quadrature-amplitude-modulation (QAM) vector radio-frequency (RF) signal generation and detection via one intensity Mach–Zehnder modulator (MZM) by using optical carrier suppression modulation. In order to obtain an ordinary QAM modulated RF signal after the square-law detection of the photodiode, amplitude preequalization and phase precoding technique are employed. The 1Gbaud 64QAM vector signals performed on various RF carrier frequencies from 20 to 444 GHz are experimentally demonstrated. The bit-error-rate (BER) performance of unbalanced phase precoding adopting 64QAM modulation is investigated. The digital filter based on blind Decision-Directed Least-Mean-Squares (DD-LMS) algorithm is the key digital-signal-processing, which is used to improve system performance. This concept of the generation of 64QAM-modulated vector signal can be employed in the radio-over-fiber (ROF) system.
Autors: Ze Dong;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2016, volume: 8, issue:6, pages: 1 - 7
Publisher: IEEE
 
» Ka-Band Wideband Large Depth-of-Field Beam Generation Through a Phase Shifting Surface Antenna
Abstract:
A wideband phase shifting surface (PSS) antenna is presented with stable and large quasi-nondiffraction range. The operation principles and design procedures for the wideband near-field focusing antenna with large depth-of-field are introduced. Then, the difference between the depth-of-field ()-fixed and the half-power beamwidth-fixed wideband design is demonstrated. As an example, a wideband -fixed PSS antenna is designed and fabricated. Phase shifts of PSS elements are synthesized by using a least mean-square error minimization method to approximate the ideal phase shift on the aperture of the antenna within the entire bandwidth. The developed prototype can be used as a -fixed beam launcher from 26.5 to 30.5 GHz. This type of antenna can be easily fabricated with the standard Printed Circuit Board process and fed by a horn antenna with an arbitrary polarization. The proposed structure has unique advantages: wideband applicable, large depth-of-field, and variable polarizations.
Autors: Yi Cheng Zhong;Yu Jian Cheng;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2016, volume: 64, issue:12, pages: 5038 - 5045
Publisher: IEEE
 
» V2O5 MISFETs on H-Terminated Diamond
Abstract:
We report for the first time on the dc and RF performance of novel MISFETs fabricated on hydrogen-terminated (H-terminated) single crystal diamond film using vanadium pentoxide (V2O5) as insulating material. The active devices were characterized in terms of static – characteristics and static transconductance as well as of S-parameters for the calculation of the maximum cutoff frequency and the maximum oscillation frequency. Time stability of the drain current was evaluated overnight observing a maximum fluctuation of 7%. Investigations on temperature dependence of diamond-based MISFET were also performed up to 130 °C. The experimental results were compared with the better established diamond MESFET technology. Finally, the surface transfer doping of H-terminated diamond by very thin V2O5 insulator was also investigated in terms of conductivity, stability in air, and resistance to high temperatures.
Autors: Claudio Verona;Walter Ciccognani;Sergio Colangeli;Ernesto Limiti;Marco Marinelli;Gianluca Verona-Rinati;Domenico Cannatà;Massimiliano Benetti;Fabio Di Pietrantonio;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2016, volume: 63, issue:12, pages: 4647 - 4653
Publisher: IEEE
 
» ghost: A Combinatorial Optimization Framework for Real-Time Problems
Abstract:
This paper presents GHOST, a combinatorial optimization framework that a real-time strategy (RTS) AI developer can use to model and solve any problem encoded as a constraint satisfaction/optimization problem (CSP/COP). We show a way to model three different problems as a CSP/COP, using instances from the RTS game StarCraft as test beds. Each problem belongs to a specific level of abstraction (the target selection as reactive control problem, the wall-in as a tactics problem, and the build order planning as a strategy problem). In our experiments, GHOST shows good results computed within some tens of milliseconds. We also show that GHOST outperforms state-of-the-art constraint solvers, matching them on the resources allocation problem, a common combinatorial optimization problem.
Autors: Florian Richoux;Alberto Uriarte;Jean-François Baffier;
Appeared in: IEEE Transactions on Computational Intelligence and AI in Games
Publication date: Dec 2016, volume: 8, issue:4, pages: 377 - 388
Publisher: IEEE
 
» A $2 times 70$ W Monolithic Five-Level Class-D Audio Power Amplifier in 180 nm BCD
Abstract:
A W from 24 V into 4 class-D audio power amplifier in 30/40 V 180 nm bipolar CMOS DMOS is presented. The device employs a flying capacitor (FC) three-level half bridge topology to reduce switching frequency and filter/load power losses in near-idle operation. This is combined with a fourth-order analog feedback system for shaping noise introduced by the digital FC voltage control loop. A power-efficient gate drive scheme suitable for power converters with multiple floating switching devices is also presented, including a compact fast low-power dV/dt robust high-voltage level shifter circuit. Power-efficient operation from idle to full-power operation is demonstrated along with a very high audio performance of 0.003% THD + N at 10 W/1 kHz into 4 .
Autors: Mikkel Høyerby;Jørgen Kragh Jakobsen;Jesper Midtgaard;Thomas Holm Hansen;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 2819 - 2829
Publisher: IEEE
 
» A $V$ -Band Stacked HEMT Power Amplifier With 25-dBm Saturated Output Power in 0.1- $mu text{m}$ InGaAs Technology
Abstract:
A stacked high-electron mobility transistor (HEMT) power amplifier (PA) has been designed and implemented in a commercial 0.1- InGaAs pHEMT process to increase gain and output power at millimeter-wave frequencies. The stability problem of the stacked HEMT has been analyzed. A new layout of the stacked HEMT for improving the high frequency stability is proposed and used in the PA design. Measurements on the three-stage PA with parallel devices verify the saturated output power of 25 dBm and the maximum power added efficiency of 15% at 61 GHz, which is the highest reported output power of stacked HEMT PAs. The chip size measures 3.2 mm2 which makes this the most power dense -band amplifier reported from GaAs with 100 mW/mm2.
Autors: Marcus Gavell;Iltcho Angelov;Mattias Ferndahl;Herbert Zirath;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2016, volume: 64, issue:12, pages: 4232 - 4240
Publisher: IEEE
 
» A +70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends
Abstract:
An electrical-balance duplexer achieving the state-of-the-art linearity and insertion loss (IL) performance is presented, enabled by a partially depleted RF silicon-on-insulator CMOS technology. A single-ended configuration avoids the common-mode isolation problem suffered by topologies with a differential low-noise amplifier. Highly linear switched capacitors allow for impedance balancing to antennas with <1.5:1 voltage standing wave ratio from 1.9 to 2.2 GHz. +70-dBm input-referred third-order intercept point is achieved under high transmitter (TX) power (+30.5 dBm max.). TX IL is <3.7 dB, and receiver IL is <3.9 dB.
Autors: Barend van Liempd;Benjamin Hershberg;Saneaki Ariumi;Kuba Raczkowski;Karl-Frederik Bink;Udo Karthaus;Ewout Martens;Piet Wambacq;Jan Craninckx;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2016, volume: 64, issue:12, pages: 4274 - 4286
Publisher: IEEE
 
» A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR- $Delta Sigma $ ADC With On-Chip Buffer in 28 nm CMOS
Abstract:
A 0.076 mm2 12b 28 nm 600 MS/s 4-way time interleaved ADC with on chip buffer is presented. The usage of a subranging scheme consisting of a coarse SAR ADC followed by an incremental fine converter provides better suppression of thermal noise added during conversion for a given power compared to a conventional SAR. The ADC area has been optimized by using a segmented charge-sharing charge-redistribution DAC. The prototype achieves an SNDR of 60.7 dB and 58 dB at low and high frequency, respectively, while consuming 26 mW.
Autors: Alessandro Venca;Nicola Ghittori;Alessandro Bosi;Claudio Nani;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 2951 - 2962
Publisher: IEEE
 
» A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS
Abstract:
This brief presents a 0.3-V energy-efficient 10-bit successive approximation register analog-to-digital converter. A shifted monotonic switching procedure is proposed to achieve an average digital-to-analog converter switching energy of 63.75 CV2. Two redundant bits are implemented with error tolerance of ±12 mV for dynamic comparator offset and common-mode reference (Vcm) sensitivity. The prototype is designed and fabricated in a 90-nm CMOS with a core size of (0.0125 mm2). At 250 KS/s and Nyquist rate input, it consumes 52.3 nW at 0.3-V supply with an achieved signal-to-noise-and-distortion ratio of 51.21 dB and a resulting figure of merit of 0.705 fJ/conv.-step.
Autors: Sung-En Hsieh;Chih-Cheng Hsieh;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2016, volume: 63, issue:12, pages: 1171 - 1175
Publisher: IEEE
 
» A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching
Abstract:
This paper presents a low-voltage and power-efficient 10 bit successive-approximation register (SAR) analog-to-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog convertor (DAC) by 91% compared with the conventional approach. By utilizing the comparator as a voltage-to-time converter (VTC) with a time-domain quantizer, the implemented early-late (E/L) detection circuit, the input range is detected to eliminate the unnecessary DAC switching power efficiently. A prototype ADC chip is fabricated in 90 nm CMOS technology with an active area of 0.038 mm2. At 0.35-to-0.5 V supply voltage and 0.3-to-2 MS/s sampling rate with a Nyquist input, the ADC achieves a signal-to-noise-plus-distortion ratio (SNDR) of 55.5 dB to 56.3 dB and a corresponding effective number of bits (ENOB) of 8.92 bit to 9.06 bit respectively with a power consumption of to and a resulting figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32 fJ/conversion-step.
Autors: Pei-Chen Lee;Jin-Yi Lin;Chih-Cheng Hsieh;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2016, volume: 63, issue:12, pages: 2149 - 2157
Publisher: IEEE
 
» A 0.55 THz Near-Field Sensor With a $mu text{m}$ -Range Lateral Resolution Fully Integrated in 130 nm SiGe BiCMOS
Abstract:
This paper presents a room-temperature operating superresolution terahertz (THz) planar near-field solid-state sensor breaking the diffraction limit. Contrary to classical superresolution imagers implemented in the optical domain, the sensor features inbuilt illumination, evanescent-field sensing, and detection on a single chip, eliminating the need for any external optics. Both metallic and dielectric objects can be imaged with the sensor and mapped into a monotonic sensor response. It is operated around 533–555 GHz in 130 nm SiGe HBT technology and is capable of resolving structural details with a -range resolution and a high response of up to 21.7 with no amplification stages in the readout path. Here, the stop-band characteristic of a differentially driven 3-D split-ring resonator with high spatial confinement of evanescent surface fields is exploited as an object-tunable transmission modulator inserted in-plane between a tunable 3-push Colpitts oscillator and a broadband power detector. A separate antenna-coupled oscillator breakout provides a radiated power of up to 45 (−13.4 dBm). This paper further demonstrates the 2-D scanned superresolution image with a remarkable SNR of up to 40 dB for the sensor operating at dc.
Autors: Janusz Grzyb;Bernd Heinemann;Ullrich R. Pfeiffer;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3063 - 3077
Publisher: IEEE
 
» A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology
Abstract:
This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53–0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7–2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than −74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.
Autors: Yan Zhao;Zuow-Zun Chen;Yuan Du;Yilei Li;Richard Al Hadi;Gabriel Virbila;Yinuo Xu;Yanghyo Kim;Adrian Tang;Theodore J. Reck;Mau-Chung Frank Chang;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3005 - 3019
Publisher: IEEE
 
» A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS
Abstract:
An energy-efficient forwarded-clock transmitter that offers a scalable pre-emphasis equalization and output voltage swing is presented. A resistive-feedback inverter-based driver is used to overcome the drawbacks of the conventional drivers. Moreover, half-rate clocking structure is employed in order to minimize power consumption in 65-nm CMOS technology. The proposed transmitter consists of two data lanes, a shared clock lane, and a global impedance regulator. The prototype chip is fabricated in 65-nm CMOS technology and occupies an active area of 0.15 mm. The proposed transmitter achieves 100–250 mV single-ended swing and exhibits the energy efficiency of 1 pJ/bit at the per-pin data rate of 10 Gb/s.
Autors: Woorham Bae;Gyu-Seob Jeong;Deog-Kyoon Jeong;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2016, volume: 63, issue:12, pages: 1106 - 1110
Publisher: IEEE
 
» A 1.3 nJ/b IEEE 802.11ah Fully-Digital Polar Transmitter for IoT Applications
Abstract:
A 1.3 nJ/b IEEE 802.11ah TX for IoT applications is presented. A fully-digital polar architecture consisting of an all-digital PLL-based frequency modulator and an AM-retiming switched-capacitor PA (SC-PA) achieves more than power reduction than state-of-the-art OFDM TXs. Several circuit-design techniques such as LSB truncation error feedback are proposed to efficiently pre-process the AM/PM data to improve the TX performance. A design approach of the SC-PA for optimum overall efficiency is introduced. The PLL spur level is reduced to 55 dBc by a switched-capacitor based digital-to-time converter. A dynamic divider is implemented together with a 1.8 GHz oscillator for efficient LO generation. Fabricated in a 40 nm CMOS process, this TX fulfills all the IEEE 802.11ah mandatory-mode PHY requirements with 4.4% EVM and > 4.8 dB spectral mask margin, while consuming 7.1 mW from a 1 V supply when delivering 0 dBm output power.
Autors: Ao Ba;Yao-Hong Liu;Johan van den Heuvel;Paul Mateman;Benjamin Büsze;Johan Dijkhuis;Christian Bachmann;Guido Dolmans;Kathleen Philips;Harmke De Groot;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3103 - 3113
Publisher: IEEE
 
» A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications
Abstract:
Adapting the processor to the target application is essential in the Internet-of-Things (IoT), and thus requires customizability in order to improve energy efficiency and scalability to provide sufficient performance. In this paper, a reconfigurable and scalable control-centric architecture is proposed, and a processor consisting of two cores and an on-chip multi-mode router is implemented. Reconfigurability is enabled by a programmable sequence mapping table (SMT) which reorganizes functional units in each cycle, thus increasing hardware utilization and reducing excessive data movement for high energy efficiency. The router facilitates both wormhole and circuit switching to construct intra- or inter-chip interconnections, providing scalable performance. Fabricated in a 65-nm process, the chip exhibits 101.4 GOPS/W energy efficiency with a die size of 3.5 mm2. The processor carries out general-purpose processing with a code size 29% smaller than the ARM Cortex M4, and improves the performance of application-specific processing by over ten times when implementing AES and RSA using SMTs instead of general-purpose C. By utilizing the on-chip router, the processor can be interconnected up to 256 nodes, with a single link bandwidth of 1.4 Gbps.
Autors: Yuxiang Huan;Ning Ma;Jia Mao;Stefan Blixt;Zhonghai Lu;Zhuo Zou;Li-Rong Zheng;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2016, volume: 63, issue:12, pages: 2245 - 2256
Publisher: IEEE
 
» A 118 dB PSRR, 0.00067% (-103.5 dB) THD+N and 3.1 W Fully Differential Class-D Audio Amplifier With PWM Common Mode Control
Abstract:
This paper presents a fully differential Class-D audio amplifier using pulse-width modulation (PWM) common-mode control to enhance the power supply rejection ratio (PSRR) and linearity. The input feed-forward technique with resistive summation is adopted in the loop filter to reduce internal swing and signal-dependent terms for further linearity enhancement. Moreover, a single amplifier biaquad (SAB) technique is utilized to reduce the number of op-amps for low-power consideration. The Class-D audio amplifier achieves a high PSRR of 118 dB for 217 Hz power supply ripples and a low total harmonic distortion plus noise (THD+N) of 0.00067% (-103.5 dB). The proposed Class-D amplifier with 1.45 mA quiescent current shows a peak SNR (A-weighted) of 108 dB, the maximum output power of 3.1 W at 1% THD+N, and 89.5% efficiency with a load. The Class-D audio amplifier, which occupies the active area of 1.85 mm2 in a m 1P5M CMOS process, can be operated from 3 V to 5.5 V.
Autors: Wen-Chieh Wang;Yu-Hsin Lin;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 2808 - 2818
Publisher: IEEE
 
» A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC
Abstract:
This paper presents an energy-efficient successive approximation register (SAR)-assisted digital-slope analog-to-digital converter (ADC) architecture for high-resolution applications. The proposed hybrid ADC combines a low-noise fine digital-slope ADC with a low-power coarse SAR ADC. The coarse SAR ADC rapidly approximates the input signal and produces a small residue signal for the succeeding fine ADC. The fine digital-slope ADC linearly approaches the small residue signal. A prototype was fabricated in 1P8M 28 nm CMOS technology. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio of 64.43 dB and a spurious free dynamic range of 75.42 dB at the Nyquist input frequency while consuming 0.35 mW from a 0.9 V supply. The resultant Walden and Schreier figures of merit are 2.6 fJ/conversion-step and 176.0 dB, respectively. The ADC occupies an active area of .
Autors: Chun-Cheng Liu;Mu-Chen Huang;Yu-Hsuan Tu;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 2941 - 2950
Publisher: IEEE
 
» A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture
Abstract:
A wide band, low power, injection-locked oscillator (ILO)-type clock and data recovery (CDR) with high jitter tolerance is implemented in 28 nm CMOS. A robust phase and frequency detection algorithm independently controls ILO free running frequency and clock phase without an external time reference. A wide capture range of −25/+15% enables reference-free frequency acquisition. Jitter tolerance is 0.56 UI at 300 MHz and 1 UI at 120 MHz, with 2 UI locking time after optional calibration. The CDR operates from 1 to 12 Gbps, consuming 11 mW from 0.9 V supply at 12 Gbps for a power efficiency of 0.9 mW/Gbps. A comparison with published results shows a substantial improvement on the trend of wide CDR bandwidth coupled to degraded power efficiency.
Autors: Takashi Masuda;Ryota Shinoda;Jeremy Chatwin;Jacob Wysocki;Koki Uchino;Yoshifumi Miyajima;Yosuke Ueno;Kenichi Maruko;Zhiwei Zhou;Hideyuki Suzuki;Norio Shoji;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3204 - 3215
Publisher: IEEE
 
» A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <−80 dBc IM3 up to 1 GHz in 65 nm CMOS
Abstract:
This paper presents a 12-bit 2 GS/s dual-rate hybrid DAC using bandwidth- and linearity-enhancement techniques. The proposed pulsed-error pre-distortion scheme enhances DAC linearity at both low and high signal frequencies by leveraging the fine time-and-voltage resolution from the oversampling path of the hybrid DAC structure. To further widen the DAC bandwidth, a noise-cancellation scheme is proposed to suppress the quantization noise of the delta-sigma modulator within DC to the 1 GHz band without increasing modulator complexity. The analytical derivations and numerical simulations of the proposed techniques are provided to demonstrate the technique’s effectiveness, as well as its practical design constraints. A proof-of-concept silicon prototype is implemented in 65 nm standard CMOS that achieves SFDR of 74–98 dBc over the DC-1GHz Nyquist band. In a two-tone measurement, the IM3 product is measured from 101 dBc to 80 dBc across the Nyquist band. The SFDR improvement after enabling the proposed pulsed pre-distortion scheme measures from 67.5 to 74.4dBc, while the in-band noise floor demonstrates 6 dB suppression at the Nyquist band edge after enabling the noise-cancellation scheme.
Autors: Shiyu Su;Mike Shuo-Wei Chen;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 2963 - 2978
Publisher: IEEE
 
» A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC
Abstract:
This brief presents a 0.9-V 8-bit 800-MS/s energy-efficient two-step successive-approximation register (SAR) analog-to-digital converter (ADC) without an inter-stage residue amplifier. A charge-sharing technique is used to avoid large static current consumption of the residue amplifier and to eliminate the distortion caused by insufficient amplifier output headroom. Besides, a self-triggered latch technique not only saves the digital power but also accelerates the conversion speed by reducing the SAR loop loading. The prototype ADC consumes 1.59 mW at 800 MS/s and achieves a Nyquist signal-to-noise and distortion ratio of 45.8 dB in 40-nm CMOS technology. It results in an figure of merit of 12.5 fJ/c.-s.
Autors: Yao-Sheng Hu;Po-Chao Huang;Hung-Yen Tai;Hsin-Shu Chen;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2016, volume: 63, issue:12, pages: 1166 - 1170
Publisher: IEEE
 
» A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS
Abstract:
This paper presents a 2 GHz digital-to-time converter (DTC) with 244 fs time resolution. The DTC consists of a multi-modulus divider (MMD) and a phase interpolator (PI) as coarse and fine tuning blocks, respectively. Control logic is implemented to prevent shoot-through current during the interpolation process in order to linearize the PI. The measured DTC’s peak integral nonlinearity (INL) is 1.2 ps and limited by the PI. The interpolation process is analyzed in detail, describing the root cause of the nonlinearity and indicating key parameters to improve it. Furthermore, a measurement method for DTCs is presented that enables femtosecond accuracy. The DTC has been implemented in standard 28 nm CMOS technology.
Autors: Sebastian Sievert;Ofir Degani;Assaf Ben-Bassat;Rotem Banin;Ashoke Ravi;Wolfgang Thomann;Bernd-Ulrich Klepser;Zdravko Boos;Doris Schmitt-Landsiedel;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 2992 - 3004
Publisher: IEEE
 
» A 2 MHz 12–100 V 90% Efficiency Self-Balancing ZVS Reconfigurable Three-Level DC-DC Regulator With Constant-Frequency Adaptive-On-Time $V^{2}$ Control and Nanosecond-Scale ZVS Turn-On Delay
Abstract:
This paper presents a miniaturized wide-input-range integrated reconfigurable three-level dc-dc voltage regulator. A three-level buck converter topology with zero-voltage switching (ZVS) is adopted to remove the dominant switching power loss under high-input-voltage condition, thereby enabling the converter to achieve high power efficiency in the megahertz range and reduce the required values of power passives. A constant-frequency adaptive-on-time control is proposed to not only regulate the output voltage, but also offer the flying capacitor self-balancing in the megahertz range and over a wide input range for improving the converter reliability. A body diode-based floating ZVS detector is also developed to enable full-ZVS operation of power transistors in high-frequency low duty-ratio conditions with ns ZVS turn-on delay. Implemented in a 120 V 0.5 CMOS process, the proposed voltage regulator uses four 50 V on-chip power nMOS to support an input voltage from 12 to 100 V and regulates the output voltage at 10 V with a maximum output power of 5 W. The proposed regulator achieves a maximum power efficiency of 90% under the nominal 48 V input and 2 MHz switching frequency. Compared with the state-of-the-art counterparts, the proposed regulator provides >66 times and >2.6 times reductions in the inductance and the total capacitance, respectively.
Autors: Jing Xue;Hoi Lee;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 2854 - 2866
Publisher: IEEE
 
» A 2–15-GHz Accurate Built-in-Self-Test System for Wideband Phased Arrays Using Self-Correcting Eight-State $I/Q$ Mixers
Abstract:
A built-in-self-test (BIST) system for wideband phase arrays channels is presented. The BIST is implemented using an on-chip in-phase/quadrature () receiver with an integrated ring oscillator that provides both the channel test signal and the mixer local oscillator (LO). The BIST achieves wideband accuracy for relative phase and gain measurements at 2–15 GHz with a one-time self-correction algorithm with eight LO phases. The sequential algorithm determines the errors, such as dc offset, gain and phase imbalances from the outputs resulting from different LO phase states. An rms power detector network is also implemented for absolute gain measurements. The BIST can operate at rates >1 MHz (less than 1- sampling time) with signal-to-noise ratio greater than 50 dB and provides measurements that agree well with the vector network analyzer S-parameter data over a wide frequency range. To the best of our knowledge, this is the first implementation of high accuracy wideband BIST system for phased-array channels.
Autors: Tumay Kanar;Samet Zihir;Gabriel M. Rebeiz;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2016, volume: 64, issue:12, pages: 4250 - 4261
Publisher: IEEE
 
» A 2.2 GHz Continuous-Time $mathrm {Delta !Sigma }$ ADC With −102 dBc THD and 25 MHz Bandwidth
Abstract:
This paper presents a 2.2 GHz continuous-time ADC that achieves −102 dBc THD and 77 dB SNDR in 25 MHz bandwidth over process, voltage, and temperature (PVT) variations. Measured second-order intermodulation distortion (IM2) and the third-order intermodulation distortion (IM3) are −115 dBc and −114 dBc, respectively. The modulator comprises a 4th-order loop filter with inverter-based single-opamp resonators, a 1-bit quantizer with dither circuitry and ELD compensation and 1-bit feedback DACs that are highly insensitive to process spread and mismatch. The 1-bit DAC incorporates a wideband high precision series-shunt voltage regulator to mitigate dynamic errors associated with DAC switching. The ADC was fabricated in TSMC 65 nm CMOS and the active die area including the regulators is 0.6 mm2. The total power consumption of the 1.2 V supplied modulator core is 41.4 mW.
Autors: Lucien Breems;Muhammed Bolatkale;Hans Brekelmans;Shagun Bajoria;Jan Niehof;Robert Rutten;Bert Oude-Essink;Franco Fritschij;Jagdip Singh;Gerard Lassche;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 2906 - 2916
Publisher: IEEE
 
» A 24.7 mW 65 nm CMOS SAR-Assisted CT $DeltaSigma $ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR
Abstract:
A continuous-time (CT) sixth-order modulator, employing a 4 bit asynchronous successive-approximation-register (ASAR) quantizer, incorporates second-order noise coupling (NC) and excess-loop-delay compensation, all are tightly integrated into the switched-capacitor (SC) SAR digital-to-analog converter (DAC). The mixed-mode second-order NC structure is implemented in both discrete-time (DT) and CT domains. Clocked at 900 MHz, the 65 nm CMOS prototype measures a 120 dB/decade shaped noise slope and a peak 75.3 dB SNDR at an over-sampling ratio (OSR) of 10, yielding a Schreier FoM of 167.9 dB and a Walden FoM of 57.7 fJ/conversion-step. The modulator occupies an active area of 0.16 mm2 and consumes 24.7 mW.
Autors: Bo Wu;Shuang Zhu;Benwei Xu;Yun Chiu;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 2893 - 2905
Publisher: IEEE
 
» A 28.8-MHz 23-dBm-IIP3 3.2-mW Sallen-Key Fourth-Order Filter With Out-of-Band Zeros Cancellation
Abstract:
In this brief, a 28.8-MHz −3-dB frequency low-pass analog filter is presented. The filter synthesizes a fourth-order Butterworth transfer function, exploiting the well-known Sallen-Key (SK) biquadratic cell. The out-of-band zeros typically present in SK implementations are hereby completely canceled by using a low-power auxiliary path. This leads to a significant improvement of the stop-band rejection, at the cost of a small power for the same auxiliary path biasing. The design exhibits very large in-band IIP3 over the entire filter bandwidth (20 dBm at 10 MHz and 11 MHz), at 3.2-mW power consumption. The filter prototype has been designed in CMOS 0.18- technological node. The total area occupancy is 0.12 mm and the in-band integrated noise is .
Autors: Marcello De Matteis;Federica Resta;Alessandra Pipino;Stefano D’Amico;Andrea Baschirotto;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2016, volume: 63, issue:12, pages: 1116 - 1120
Publisher: IEEE
 
» A 2D Particle Velocity Sensor With Minimal Flow Disturbance
Abstract:
A 2D sound particle velocity sensor, consisting of a cross of two connected, heated wires is presented. We developed a fabrication process by which the wires become freely suspended 350 above the chip surface. This largely eliminates the influence of boundary layer effects and increases the temperature gradient along the wires, both due to the large distance to the silicon substrate. As a result, the sensor has increased sensitivity and reduced power consumption compared with an earlier design. Furthermore, due to the fully symmetrical structure of the sensor, the sensitive directions are exactly orthogonal to each other and have near identical sensitivity, thus requiring no individual calibration.
Autors: Olti Pjetri;Remco J. Wiegerink;Gijs J. M. Krijnen;
Appeared in: IEEE Sensors Journal
Publication date: Dec 2016, volume: 16, issue:24, pages: 8706 - 8714
Publisher: IEEE
 
» A 3-D Riesz-Covariance Texture Model for Prediction of Nodule Recurrence in Lung CT
Abstract:
This paper proposes a novel imaging biomarker of lung cancer relapse from 3-D texture analysis of CT images. Three-dimensional morphological nodular tissue properties are described in terms of 3-D Riesz-wavelets. The responses of the latter are aggregated within nodular regions by means of feature covariances, which leverage rich intra- and inter-variations of the feature space dimensions. When compared to the classical use of the average for feature aggregation, feature covariances preserve spatial co-variations between features. The obtained Riesz-covariance descriptors lie on a manifold governed by Riemannian geometry allowing geodesic measurements and differentiations. The latter property is incorporated both into a kernel for support vector machines (SVM) and a manifold-aware sparse regularized classifier. The effectiveness of the presented models is evaluated on a dataset of 110 patients with non-small cell lung carcinoma (NSCLC) and cancer recurrence information. Disease recurrence within a timeframe of 12 months could be predicted with an accuracy of 81.3–82.7%. The anatomical location of recurrence could be discriminated between local, regional and distant failure with an accuracy of 78.3–93.3%. The obtained results open novel research perspectives by revealing the importance of the nodular regions used to build the predictive models.
Autors: Pol Cirujeda;Yashin Dicente Cid;Henning Müller;Daniel Rubin;Todd A. Aguilera;Billy W. Loo;Maximilian Diehn;Xavier Binefa;Adrien Depeursinge;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Dec 2016, volume: 35, issue:12, pages: 2620 - 2630
Publisher: IEEE
 
» A 3-Lead ECG-on-Chip with QRS Detection and Lossless Compression for Wireless Sensors
Abstract:
This brief presents the design of a low-power 3-lead electrocardiogram (ECG)-on-chip with integrated real-time QRS detection and lossless data compression for wearable wireless ECG sensors. Data compression and QRS detection can reduce the sensor power by up to 2–5 times. A joint QRS detection and lossless data compression circuit allows computational resources to be shared among multiple functions, thus lowering the overall system power. The proposed technique achieves an average compression ratio of 2.15 times on standard test data. The QRS detector achieves a sensitivity (Se) of 99.58% and positive productivity (+P) of 99.57% @ 256 Hz when tested with the MIT/BIH database. Implemented in 0.35 process, the circuit consumes 0.96 @ 2.4 V with a core area of 1.56 mm for two-channel ECG compression and QRS detection. Small size and ultralow-power consumption makes the chip suitable for usage in wearable/ambulatory ECG sensors.
Autors: Chacko John Deepu;Xiaoyang Zhang;Chun Huat Heng;YongLian Lian;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2016, volume: 63, issue:12, pages: 1151 - 1155
Publisher: IEEE
 
» A 300 GHz CMOS Transmitter With 32-QAM 17.5 Gb/s/ch Capability Over Six Channels
Abstract:
A 300 GHz transmitter (TX) fabricated using a 40 nm CMOS process is presented. It achieves 17.5 Gb/s/ch 32-quadrature amplitude modulation (QAM) transmission over six 5 GHz-wide channels covering the frequency range from 275 to 305 GHz. With the unity-power-gain frequency of the NMOS transistor being below 300 GHz, the TX adopts a power amplifier-less QAM-capable architecture employing a highly linear subharmonic mixer called a cubic mixer. It is based on and as compact as a tripler and enables the massive power combining necessary above without undue layout complication. The frequency-dependent characteristics of the cubic mixer are studied, and it is shown that even higher data rates of up to 30 Gb/s are possible at certain frequencies, where the channel signal-to-noise ratio is high. The design and the operation of the power-splitting and power-combining circuits are also described in detail. The measurements reported herein were all made “wired” via a WR3.4 waveguide.
Autors: Kosuke Katayama;Kyoya Takano;Shuhei Amakawa;Shinsuke Hara;Akifumi Kasamatsu;Koichi Mizuno;Kazuaki Takahashi;Takeshi Yoshida;Minoru Fujishima;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3037 - 3048
Publisher: IEEE
 
» A 32 Gb/s Bidirectional 4-channel 4 pJ/b Capacitively Coupled Link in 14 nm CMOS for Proximity Communication
Abstract:
Board-to-board near mm-range proximity communication offers connector-less, sealed energy-efficient high-speed interfaces for computing devices. This work presents a 4-channel 4 pJ/b capacitively coupled interface supporting an aggregate data-rate of 32 Gb/s up to a 0.8 mm air gap. By employing a self-crosstalk cancelling coupler and self-resonance mitigating IC design, the prototype enables board-to-board high-density bidirectional signaling capability.
Autors: Chintan Thakkar;Shreyas Sen;James Jaussi;Bryan Casper;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3231 - 3245
Publisher: IEEE
 
» A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET
Abstract:
A 3-tap 64 Gb/s NRZ transmitter using a quad-rate architecture is designed in 16 nm FinFET. The design incorporates circuit techniques and topologies that take into account device properties specific to FinFET process. A 4:1 MUX consisting of static CMOS pulse generators and a tailless CML multiplexing stage is used at the final stage of serialization. An on-chip regulator provides power to the pulse generators and CMOS clock buffers. A phase error correction circuit corrects the phase errors of the four-phase clocks generated by an LC-PLL. The transmitter achieves 800 mV-ppd with 150 fs RJ while consuming 225 mW at 64 Gb/s.
Autors: Yohan Frans;Scott McLeod;Hiva Hedayati;Mohamed Elzeftawi;Jin Namkoong;Winson Lin;Jay Im;Parag Upadhyaya;Ken Chang;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3167 - 3177
Publisher: IEEE
 
» A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS
Abstract:
This paper presents a low-power hybrid-loop receiver (RX) with high-interference tolerance for Bluetooth low energy (BLE). The hybrid-loop structure based on an all-digital phase-locked loop enables the RX to both enhance the interference tolerance and digitize the frequency-modulated signal without an ADC. A novel single channel receiving method, which enables the conversion of the constellation from frequency shift keying to differential binary phase shift keying signal, is adopted to eliminate the Q-channel signal processing to reduce the power consumption. The prototype RX fabricated in a 65 nm CMOS technology consumes only 5.5 mW and fulfills the BLE requirements of the adjacent channel rejection and out-of-band blocker tolerance without exception. The sensitivity level is −90 dBm.
Autors: Akihide Sai;Hidenori Okuni;Tuan Thanh Ta;Satoshi Kondo;Takashi Tokairin;Masanori Furuta;Tetsuro Itakura;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3125 - 3136
Publisher: IEEE
 
» A 6-m OOK VLC Link Using CMOS-Compatible p-n Photodiode and Red LED
Abstract:
This letter presents an onoff-keying visible-light-communication (VLC) link realized over 6-m distance. The transmitter is implemented with a commercially available red LED source at 650 nm. While most of the reported high-performance VLC links are using p-insulator-n photodetectors, this receiver employs a simple CMOS-compatible p-n photo-detector. A 150-Mb/s optical wireless transmission is measured with a bit-error rate of , which falls below the forward error correction limit of . The second-order L-C-R equalization is used in both the transmitter and the receiver circuits to achieve maximum bandwidth extension. The VLC link is realized with a low illuminance of 250 lux. This power is below the common indoor illumination levels which enables advanced lighting-compatible VLC applications. The receiver and the source circuits consume around 240 and 105 mW, respectively, which represents to our knowledge a record energy-per-bit level of 2.3 nJ/b.
Autors: Bassem Fahs;Jeffrey Chellis;Matthew J. Senneca;Asif Chowdhury;Sagar Ray;Ali Mirvakili;Brandon Mazzara;Yiwen Zhang;Javad Ghasemi;Yun Miao;Payman Zarkesh-Ha;Valencia J. Koomson;Mona M. Hella;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2016, volume: 28, issue:24, pages: 2846 - 2849
Publisher: IEEE
 
» A 6.5- $mu text{W}$ /MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing
Abstract:
This brief presents a CMOS charge buffer with femtofarad-range input capacitance for applications in capacitive electropotential sensing. We analyze and verify a feedback mechanism to negate parasitic capacitances seen at the input of a CMOS amplifier. Measurements are presented from a prototype fabricated in 65-nm CMOS occupying an active area of 193 with an efficiency of 6.5 /MHz. Over-the-air measurements validate its applicability to electropotential sensing.
Autors: Siddharth Joshi;Chul Kim;Gert Cauwenberghs;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2016, volume: 63, issue:12, pages: 1161 - 1165
Publisher: IEEE
 
» A 65 nm Temporally Hardened Flip-Flop Circuit
Abstract:
A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance– only one (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm2/mg. Simulation results from the TFIT further validate the experimental results.
Autors: Y.-Q. Li;H.-B. Wang;Rui Liu;Li Chen;Issam Nofal;Q.-Y. Chen;A.-L. He;Gang Guo;Sang H. Baeg;Shi-Jie Wen;Richard Wong;Qiong Wu;Mo Chen;
Appeared in: IEEE Transactions on Nuclear Science
Publication date: Dec 2016, volume: 63, issue:6, pages: 2934 - 2940
Publisher: IEEE
 
» A 71–86-GHz Switchless Asymmetric Bidirectional Transceiver in a 90-nm SiGe BiCMOS
Abstract:
An -band (71–86-GHz) bidirectional transceiver is presented in this paper. The time-division duplex architecture avoids transmit (TX)/receive (RX) switches through the use of transistor biasing in the signal path to minimize high-frequency loss. The low-noise amplifier (LNA) and power amplifier (PA) are combined into a wideband PA/LNA circuit, which alleviates the parasitic loading of each circuit through a wideband power combiner. The bidirectional transceiver circuit is implemented in 90-nm SiGe BiCMOS process. In TX mode, the bidirectional transceiver transmits a maximum saturated power of 11 dBm at 78 GHz with a 3-dB bandwidth from 71 to 86 GHz. In RX mode, the maximum 30.6-dB conversion gain and the minimum 6.6-dB noise figure are measured at 73 GHz. The whole RF frontend chip consumes 350.2- and 137.7-mW dc power in TX and RX modes, respectively, including all the RF, IF, and local oscillator amplifiers. The overall chip size is mm including pads.
Autors: Po-Yi Wu;Tissana Kijsanayotin;James F. Buckwalter;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2016, volume: 64, issue:12, pages: 4262 - 4273
Publisher: IEEE
 
» A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS
Abstract:
This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC in 28 nm CMOS. The MASH ADC uses a first-order front-end stage to digitize the input signal and a second-order back-end stage to digitize the quantization noise of the coarse flash ADC inside the front-end. An RC lattice filter and a current-steering DAC are utilized to extract the front-end coarse quantization residue. The prototype MASH ADC chip built in a 28 nm CMOS process is clocked at 8 GHz with an OSR of 8.6, providing a signal bandwidth of 465 MHz. The ADC achieves a DR of 72 dB and an average small-signal NSD of −160 dBFS/Hz. The peak SNR is 68 dB and the peak SNDR is 67 dB. The IM3 is −88 dBFS with two −9 dBFS tones at the band edge. The ADC consumes 890 mW of power from +1.8/1.0/-1.0 V supplies and achieves a thermal noise FOM of 159 dB.
Autors: Yunzhi Dong;Jialin Zhao;Wenhua William Yang;Trevor Caldwell;Hajime Shibata;Zhao Li;Richard Schreier;Qingdong Meng;Jose B. Silva;Donald Paterson;Jeffrey C. Gealow;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 2917 - 2927
Publisher: IEEE
 
» A 750–1000 GHz $H$ -Plane Dielectric Horn Based on Silicon Technology
Abstract:
A wideband THz H-plane dielectric horn antenna based on silicon (Si) technology is proposed in this paper. The antenna can be integrated with the planar structure circuit and the dielectric ridge waveguide. To fabricate the proposed antenna, the deep reactive ion etching high-resistivity Si fabrication process is used. The size of the proposed antenna is mm3. The operating frequency of the antenna ranges from 750 to 1000 GHz, which corresponds to a fractional impedance bandwidth of 28.6%. The antenna has a narrow beamwidth in the H-plane and a high gain. To test this antenna, the characterization of the metal waveguide diagonal horn for measurement is analyzed. Then the non-contact measurement method is applied to measure the designed dielectric horn. The simulated radiation efficiency of the antenna is higher than 80% while the measured gain of the antenna is larger than 8 dBi. Measured H-plane radiation patterns from the proposed antenna are presented and show reasonable agreement with the simulated results.
Autors: Hao-Tian Zhu;Quan Xue;Jia-Nan Hui;Stella W. Pang;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2016, volume: 64, issue:12, pages: 5074 - 5083
Publisher: IEEE
 
» A 915 MHz 175 $mu text{W}$ Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference Tolerance
Abstract:
Improving interference robustness in ultralow power (ULP) receivers (RXs) is a big challenge due to their low power budget. This paper presents an envelope detector based 915 MHz 10 kb/s ULP RX, which is fabricated in 65 nm CMOS process for wireless sensor networks and Internet of Things. Two power-efficient techniques, transmitted-reference and shifted limiter, are proposed to improve the interference robustness. The RX sensitivity is between −61 and −76 dBm. The maximum in-band signal-to-interference ratio at ±1 MHz offset is up to −50 dB while just consuming 175 power from a 1 V supply.
Autors: Dawei Ye;Ronan van der Zee;Bram Nauta;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3114 - 3124
Publisher: IEEE
 
» A Bayesian Perspective on Early Stage Event Prediction in Longitudinal Data
Abstract:
Predicting event occurrence at the early stage of a longitudinal study is an important and challenging problem which has high practical value in many real-world applications. As opposed to the standard classification and regression problems where a domain expert can provide labels for the data in a reasonably short period of time, training data in such longitudinal studies must be obtained only by waiting for the occurrence of a sufficient number of events. Survival analysis aims at directly predicting the time to an event of interest using the data collected in the past for a certain duration. However, it cannot give an answer to the open question of “how to forecast whether a subject will experience an event by end of a longitudinal study using event occurrence information of other subjects at the early stage of the study?”. The goal of this work is to predict the event occurrence at a future time point using only the information about a limited number of events that occurred at the initial stages of a longitudinal study. This problem exhibits two major challenges: (1) absence of complete information about event occurrence (censoring) and (2) availability of only a partial set of events that occurred during the initial phase of the study. We propose a novel Early Stage Prediction (ESP) framework for building event prediction models which are trained at the early stages of longitudinal studies. First, we develop a novel approach to address the first challenge by introducing a new method for handling censored data using Kaplan-Meier estimator. We then extend the Naive Bayes, Tree-Augmented Naive Bayes (TAN), and Bayesian Network methods based on the proposed framework, and develop three algorithms, namely, ESP-NB, ESP-TAN, and ESP-BN, to effectively predict event occurrence using training data obtained at an early stage of the study. More specifically, our approach effectively integrates Bayesian methods with a- Accelerated Failure Time (AFT) model by adapting the prior probability of the event occurrence for future time points. The proposed framework is evaluated using a wide range of synthetic and real-world benchmark datasets. Our extensive set of experiments show that the proposed ESP framework is, on an average, 20 percent more accurate compared to existing schemes when using only limited event information in the training data.
Autors: Mahtab Jahanbani Fard;Ping Wang;Sanjay Chawla;Chandan K. Reddy;
Appeared in: IEEE Transactions on Knowledge and Data Engineering
Publication date: Dec 2016, volume: 28, issue:12, pages: 3126 - 3139
Publisher: IEEE
 
» A Big Bang–Big Crunch Type-2 Fuzzy Logic System for Machine-Vision-Based Event Detection and Summarization in Real-World Ambient-Assisted Living
Abstract:
The area of ambient-assisted living (AAL) focuses on developing new technologies, which can improve the quality of life and care provided to elderly and disabled people. In this paper, we propose a novel system based on 3-D RGB-D vision sensors and interval type-2 fuzzy-logic-based systems (IT2FLSs) employing the big bang–big crunch algorithm for the real-time automatic detection and summarization of important events and human behaviors from the large-scale data. We will present several real-world experiments, which were conducted for AAL-related behaviors with various users. It will be shown that the proposed BB-BC IT2FLSs outperform the type-1 fuzzy logic system counterparts as well as other conventional nonfuzzy methods, and the performance improves when the number of subjects increases.
Autors: Bo Yao;Hani Hagras;Daniyal Alghazzawi;Mohammed J. Alhaddad;
Appeared in: IEEE Transactions on Fuzzy Systems
Publication date: Dec 2016, volume: 24, issue:6, pages: 1307 - 1319
Publisher: IEEE
 
» A Bilevel Scale-Sets Model for Hierarchical Representation of Large Remote Sensing Images
Abstract:
Due to the diversity of geographical objects, it makes great sense to introduce multiscale segmentation/representation into the analysis and interpretation of high-spatial-resolution remote sensing images. However, with the increasing use of high-resolution images, traditional multiscale segmentation methods gradually show their lack in efficiency, particularly when handling large-scale images. In this paper, a novel bilevel scale-sets model (BSM) is proposed for multiscale region-based representation of large-scale remote sensing images. In the BSM, first, an image is divided into blocks with overlapped margins, and a low-level scale-sets model is blockwisely implemented. Second, a segmentation result is obtained by retrieving and mosaicking the blockwise segmentation results, based on which a high-level scale-sets model is implemented covering the whole image. To further improve the efficiency of the BSM, a parallel implementation is presented for the blockwise scale-sets model. In the experiments, first, the effectiveness of the BSM is validated using a WorldView2 image covering a coastal area of Shenzhen, where the BSM obtains accurate multiscale representation results without any mosaic artifacts. Then, the efficiency of the BSM is demonstrated by comparing with the state-of-the-art multiscale segmentation method, i.e., the one integrated in the commercial software eCognition v9.2, where the proposed BSM takes about 7 min to process a 24 000 × 24 000 multispectral ZY3 image and is two to three times faster than the competing method.
Autors: Zhongwen Hu;Qingquan Li;Qin Zou;Qian Zhang;Guofeng Wu;
Appeared in: IEEE Transactions on Geoscience and Remote Sensing
Publication date: Dec 2016, volume: 54, issue:12, pages: 7366 - 7377
Publisher: IEEE
 
» A blockchain currency that beat s bitcoin on privacy [News]
Abstract:
In October, I was in a van in Denver with Zooko Wilcox, the CEO of Zcash, a company that was soon to launch a new blockchain-based digital currency of the same name. On the floor next to me was a bunch of recently purchased computer equipment. I knew we were going to a hotel but didn’t know which one. I only knew that I’d be there for the next two days straight and that it would be my job to watch, ask questions, stave off sleep, and document as much as I possibly could.
Autors: Morgen Peck;
Appeared in: IEEE Spectrum
Publication date: Dec 2016, volume: 53, issue:12, pages: 11 - 13
Publisher: IEEE
 
» A Bright Future for IEEE Intelligent Systems
Abstract:
Editor-in-chief Daniel Zeng says his farewell as his term ends at the end of 2016.
Autors: Daniel Zeng;
Appeared in: IEEE Intelligent Systems
Publication date: Dec 2016, volume: 31, issue:6, pages: 3 - 4
Publisher: IEEE
 
» A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring
Abstract:
This brief presents a built-in self-calibration (BISC) technique for minimization of the total jitter in bang-bang all-digital phase-locked loops (ADPLLs). It is based on the addition of a monitoring phase-frequency detector (PFD) with tunable delay cells for the reference clock and the divider clock and a counter for this PFD output signal. This allows for on-chip binary comparison of the jitter distribution widths at the ADPLL PFD input, when ADPLL filter parameters are altered. Since only a relative comparison is performed, no accurate delay calibration is required. The statistical properties of this comparison of two random distributions are analyzed theoretically, and guidelines for circuit dimensioning are derived. The proposed method is used for BISC by adaption of the ADPLL filter coefficients. This allows for jitter minimization under process, voltage and temperature variations as well as gain and period jitter of the digitally controlled oscillator. The proposed calibration technique is verified by system simulations and measurements of a silicon prototype implementation in 28-nm CMOS technology.
Autors: Sebastian Höppner;Johannes Partzsch;Johannes Neumann;René Schüffny;Christian Mayr;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2016, volume: 24, issue:12, pages: 3548 - 3552
Publisher: IEEE
 
» A Centrifugal Force-Based Configuration-Independent High-Torque-Density Passive Brake for Human-Friendly Robots
Abstract:
Safe actuation is one of the most important requirements for human-robot collaboration. Although a variety of passive brakes have been developed in order to safely regulate joint velocities, their performances are significantly subjective to gravity direction and mounting position, and thus are not suitable for multi-degrees of freedom (DoF) robotic applications. Addressing these issues, we developed a centrifugal force-based configuration-independent high-torque-density passive brake. The brake is rapidly and bidirectionally activated at the desired velocity limit in any orientation relative to the direction of gravity. A design optimization methodology is proposed for high-torque density and low-reflected inertia, which allows for inherent safe actuation in the event of a system failure. Experimental results demonstrate that the proposed brake is an effective solution for limiting velocity in multi-DoF human-friendly robots.
Autors: Dongjun Shin;Akichika Tanaka;Namho Kim;Oussama Khatib;
Appeared in: IEEE/ASME Transactions on Mechatronics
Publication date: Dec 2016, volume: 21, issue:6, pages: 2827 - 2835
Publisher: IEEE
 
» A Circuit Model of Human Whole Blood in a Microfluidic Dielectric Sensor
Abstract:
This brief reports on the analysis of a circuit model for human whole blood in a microfluidic dielectric sensor. The sensor employs a novel, 3-D, parallel-plate, capacitive sensing structure with a floating electrode integrated onto a microfluidic channel with 9 of sample volume. A circuit model is developed that accurately captures the characteristics of the capacitive double-layer formed due to the ionic content of blood, as well as the characteristics of the dispersion region attributed to interfacial polarization of the red blood cells. The sensor-measured permittivity of human whole blood and blood samples with hematocrit levels of 0.2, 0.4, and 0.6 show an excellent agreement to simulated data from the circuit model, with rms errors less than 2.14% and 1.17% for the real and imaginary parts of permittivity, respectively, for all samples and over the full measurement frequency range of 10 kHz–100 MHz.
Autors: Michael A. Suster;Nicholas H. Vitale;Debnath Maji;Pedram Mohseni;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2016, volume: 63, issue:12, pages: 1156 - 1160
Publisher: IEEE
 
» A Classic Power Plant: Early Electric Power at Pratt Institute [History]
Abstract:
In April of 2000, I had the pleasure of visiting a truly beautiful artifact of electric power history, and of meeting Conrad Milster, its long-time caretaker. This is the power plant of the Pratt Institute, located in the Clinton Hill neighborhood of Brooklyn, New York City. This unique installation still exists today (along with Milster) and, hopefully, both will continue so for a very long time.
Autors: Thomas J. Blalock;
Appeared in: IEEE Power and Energy Magazine
Publication date: Dec 2016, volume: 14, issue:6, pages: 84 - 92
Publisher: IEEE
 
» A Cloud to the Ground: The New Frontier of Intelligent and Autonomous Networks of Things
Abstract:
Autors: Cesare Alippi;Romano Fantacci;Dania Marabissi;Manuel Roveri;
Appeared in: IEEE Communications Magazine
Publication date: Dec 2016, volume: 54, issue:12, pages: 14 - 20
Publisher: IEEE
 
» A CMOS Image Sensor-Based Stereo Matching Accelerator With Focal-Plane Sparse Rectification and Analog Census Transform
Abstract:
A low-latency and low-power stereo matching accelerator is monolithically integrated with a CMOS image sensor (CIS) for mobile applications. To reduce the overall latency, focal-plane processing is adopted by using the proposed analog census transform circuit (ACTC), and the image readout is pipelined with the following stereo matching process. In addition, a novel focal-plane rectification pixel array (FRPA) merges the rectification with the image readout without any additional processing latency. For area-efficient pixel design, sparse rectification is proposed, and the image rectification is implemented with only two additional switches in each pixel. A stereo matching digital processor (SMDP) is integrated with the CIS for cost aggregation. We present the full design including the layout with a 65 nm CMOS process, and the FRPA, the ACTC, and the SMDP achieve 11.0 ms latency with complete stereo matching stages, which is suitable for a smooth user interface. As a result, the 2-chip stereo matching system dissipates /frame and achieves 17% energy reduction compared to a previous stereo matching SoC.
Autors: Changhyeon Kim;Kyeongryeol Bong;Sungpill Choi;Kyuho Jason Lee;Hoi-Jun Yoo;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2016, volume: 63, issue:12, pages: 2180 - 2188
Publisher: IEEE
 
» A Co-Training Strategy for Multiple View Clustering in Process Mining
Abstract:
Process mining refers to the discovery, conformance, and enhancement of process models from event logs currently produced by several information systems (e.g. workflow management systems). By tightly coupling event logs and process models, process mining makes it possible to detect deviations, predict delays, support decision making, and recommend process redesigns.Event logs are data sets containing the executions (called traces) of a business process. Several process mining algorithms have been defined to mine event logs and deliver valuable models (e.g. Petri nets) of how logged processes are being executed. However, they often generate spaghetti-like process models, which can be hard to understand. This is caused by the inherent complexity of real-life processes, which tend to be less structured and more flexible than what the stakeholders typically expect. In particular, spaghetti-like process models are discovered when all possible behaviors are shown in a single model as a result of considering the set of traces in the event log all at once.To minimize this problem, trace clustering can be used as a preprocessing step. It splits up an event log into clusters of similar traces, so as to handle variability in the recorded behavior and facilitate process model discovery. In this paper, we investigate a multiple view aware approach to trace clustering, based on a co-training strategy. In an assessment, using benchmark event logs, we show that the presented algorithm is able to discover a clustering pattern of the log, such that related traces result appropriately clustered. We evaluate the significance of the formed clusters using established machine learning and process mining metrics.
Autors: Annalisa Appice;Donato Malerba;
Appeared in: IEEE Transactions on Services Computing
Publication date: Dec 2016, volume: 9, issue:6, pages: 832 - 845
Publisher: IEEE
 
» A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration
Abstract:
Large-scale workloads often show parallelism of different levels. which offers acceleration potential for clusters and parallel processors. Although processors such as GPGPUs and FPGAs show good performance of speedup, there is still vacancy for a low power, high efficiency and dynamically reconfigurable one, and coarse-grained reconfigurable architecture (CGRA) seems to be one possible choice. In this paper, we introduce how we use our CGRA fabric Chameleon to realize a dynamically reconfigurable acceleration to MapReduce-based (MR-based) applications. A FPGA-shell-CGRA-core (FSCC) architecture is designed for the acceleration PCI-Express board, and a programming model with compilation flow for CGRA is presented. With the supports above, a small evaluation cluster with Hadoop framework is set up, and experiments on compute-intensive applications show that the programming process is significantly simplified, with an 30-60 speedup offered under low power.
Autors: Shuang Liang;Shouyi Yin;Leibo Liu;Yike Guo;Shaojun Wei;
Appeared in: Computer Architecture Letters
Publication date: Dec 2016, volume: 15, issue:2, pages: 69 - 72
Publisher: IEEE
 
» A Coarse-to-Fine Method for Building Reconstruction From HR SAR Layover Map Using Restricted Parametric Geometrical Models
Abstract:
Layover in slant range synthetic aperture radar (SAR) images contains rich 3-D information of building geometry. In this letter, a coarse-to-fine method for building reconstruction from high-resolution (HR) SAR layover map using restricted parametric geometrical models is presented. First, we propose a new restricted parametric geometrical model for building layover and for corner line, respectively. Under the guidance of these models, a hierarchical coarse-to-fine layover estimation scheme is designed. Owning to the coarse-to-fine scheme, this method is resistant to various flaws of layover. At last, the building is reconstructed from the well-estimated layover. Experiments on HR TanDEM-X data demonstrate the effectiveness and precision of our method.
Autors: Kun Fu;Yue Zhang;Xian Sun;Feng Li;Hongqi Wang;Fangzheng Dou;
Appeared in: IEEE Geoscience and Remote Sensing Letters
Publication date: Dec 2016, volume: 13, issue:12, pages: 2004 - 2008
Publisher: IEEE
 
» A Collaboration Incentive Exploiting the Primary-Secondary Systems’ Cross Interference for PHY Security Enhancement
Abstract:
We investigate the spectrum sharing possibility as an incentive to enhance the physical layer security. The concept behind is that a legitimate source-destination pair, communicating in the presence of a passive eavesdropper, stimulates the help of another source-destination nodes looking for transmission opportunities, referred to as secondary network (SN). We thus propose a cooperative scheme, whereby the secondary transmitter (ST) will act as a friendly jammer to confound the eavesdropper and be granted to share the spectrum of the legitimate pair, referred to as primary network (PN), as a reward. Meanwhile, the ST has to secure its own secrecy communication and thus exploit the impact of the induced interference by the PN. To evaluate the performance of our cooperative scheme, we derive the closed-form expressions of the secrecy outage probability (SOP) for both cooperative networks. However, to assess its usefulness, we introduce the mutual outage probability (MOP) and we carry out analysis to derive its expression. We show that a satisfactory SOP is a necessary condition for triggering the cooperation, whereas a satisfactory MOP is a sufficient condition to guarantee that the PN-SN collaboration leads to a win-win situation. Furthermore, an asymptotic analysis is also carried out to derive the generalized secrecy diversity for the scheme under investigation, where it has been shown that the primary system achieves its full secrecy diversity order, equal to the number of antenna at the primary transmitter. Such results present useful insights for practical design and setups.
Autors: Kamel Tourki;Mazen O. Hasna;
Appeared in: IEEE Journal of Selected Topics in Signal Processing
Publication date: Dec 2016, volume: 10, issue:8, pages: 1346 - 1358
Publisher: IEEE
 
» A Colorful Blackout: The Havoc Caused by Auroral Electrojet Generated Magnetic Field Variations in 1989
Abstract:
The Hydro-Québec system is a winter-peaking system whose all-time record peak load of 39,240 MW was recorded in January 2014. Hydro-Québec exports to neighboring systems in Canada and the United States, with an annual transaction volume of approximately 30 TWh. The current system configuration is based on the major development projects of the 1960s and 1970s. In 1965, as part of the development of the Manic-Outardes hydroelectric complex, Hydro-Québec commissioned the world's first 735-kV lines, which had a much greater capacity than the existing 315-kV lines put into service in the late 1950s with the development of the Bersimis hydroelectric complex. In 1971, Hydro-Québec launched what was then dubbed the "project of the century": the development of the La Grande River complex in the James Bay region at the southern end of Hudson Bay. In 1996, when the final generating station, Laforge-2, was commissioned at the end of the second phase of the project, La Grande became the largest hydroelectric facility in the world, a title it retained for a number of years.
Autors: Sebastien Guillon;Patrick Toner;Louis Gibson;David Boteler;
Appeared in: IEEE Power and Energy Magazine
Publication date: Dec 2016, volume: 14, issue:6, pages: 59 - 71
Publisher: IEEE
 
» A Combined Rotational Raman–Rayleigh Lidar for Atmospheric Temperature Measurements Over 5–80 km With Self-Calibration
Abstract:
A combined lidar system on the basis of conventional Rayleigh lidar has been extended by two rotational Raman (RR) channels for nocturnal atmospheric temperature measurements from 5 to 80 km over Wuhan, China (30.5°N, 114.5°E). An overlapping altitude range of about 10 km is obtained with the RR-technique temperatures reaching upward to 40 km and the Rayleigh-integration-technique temperatures above 30 km. Temperature values obtained by two different mechanisms match nicely in the overlapping area. By using a data-merge method, complete temperature profiles covering widely from 5 to 80 km are obtained for the observation of the thermal structure and perturbations from the troposphere up to the mesosphere. Based on the overlapping-region (30-40 km) data obtained from this combined RR-Rayleigh lidar system and Rayleigh-integration-technique temperatures initialized with model data at an upper height (90 km), we develop a self-calibration method for the determination of the system-dependent constants for RR temperature retrieval. Compared with the conventional radiosonde calibration method, the self-calibration obtained in the overlap region of both lidar temperature measurement techniques can be extrapolated to the lower temperatures in the tropopause region by using the simpler two-constant calibration function. With this new calibration method, the combined lidar system can perform independent and accurate atmospheric temperature measurements when a coincident (in time and space) radiosonde is not available, as it is often the case. This combined RR-Rayleigh lidar thus has the potential for long-term studies of atmospheric thermal structure and associate perturbations.
Autors: Yajuan Li;Xin Lin;Shalei Song;Yong Yang;Xuewu Cheng;Zhenwei Chen;Linmei Liu;Yuan Xia;Jun Xiong;Shunsheng Gong;Faquan Li;
Appeared in: IEEE Transactions on Geoscience and Remote Sensing
Publication date: Dec 2016, volume: 54, issue:12, pages: 7055 - 7065
Publisher: IEEE
 
» A Compact Directional Slot Antenna and Its Application in MIMO Array
Abstract:
In this communication, a new design for the microstrip-fed slot antenna with a directive radiation pattern for WLAN/WiMAX application is presented. By utilizing a two-element array topology, a unidirectional radiation pattern is obtained. Without any directors and reflectors, the proposed slot antenna shows advantages in terms of compact size and high front-to-back gain ratio in the azimuthal plane. Four directional slot antennas are then placed in a square loop array to obtain nearly orthogonal patterns. Thus, a compact multiple input multiple output array with high isolation among those four elements is achieved. Simulated and measured results are presented to validate the practicality of the proposed antenna structures.
Autors: Hao-Tao Hu;Fu-Chang Chen;Qing-Xin Chu;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2016, volume: 64, issue:12, pages: 5513 - 5517
Publisher: IEEE
 
» A Compact Microstrip-Fed Patch Antenna With Enhanced Bandwidth and Harmonic Suppression
Abstract:
A single-layer microstrip-fed patch antenna with capabilities of both bandwidth enhancement and harmonic suppression is proposed. For this purpose, a pair of /4 microstrip-line resonators is introduced and coupled in proximity to a rectangular patch. The wideband property can be obtained by making effective use of the two resonances introduced by the radiating patch and nonradiating /4 resonators. Different from other reported dual-resonance patch antennas, the proposed antenna does not require the electrically thick substrate, so it has attractive low-profile property. Thanks to the good features of /4 resonators and capacitive feeding scheme, harmonic radiating modes of the patch antenna can be significantly suppressed as highly demanded in modern highly integrated communication systems. The working principle, equivalent circuit, and design procedure are extensively described. Finally, a prototype antenna operating at 4.9 GHz is designed and fabricated. The measured results show that its bandwidth is 2.7 times wider than that of the traditional insert-fed patch counterpart, and the harmful spurious radiation from other higher order radiating modes has been effectively suppressed.
Autors: Jin-Dong Zhang;Lei Zhu;Qiong-Sen Wu;Neng-Wu Liu;Wen Wu;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2016, volume: 64, issue:12, pages: 5030 - 5037
Publisher: IEEE
 
» A Compact Mixer-First Receiver With >24 dB Self-Interference Cancellation for Full-Duplex Radios
Abstract:
This letter presents a single-channel full-duplex receiver with tunable self-interference (SI) cancelling capability through LO phase shifting. The receiver takes advantage of high linearity of the passive mixer-first architecture to eliminate SI without degrading sensitivity due to inter-modulation distortion. The proposed receiver exhibits a DSB noise figure of 8.6–12.5 dB over an operating frequency range of 800 MHz–1.7 GHz. It achieves >70.5 dB SINDR in 16.25 MHz RF signal bandwidth at −18 dBm input SI power. The receiver is implemented in a 130 nm CMOS process and occupies an area of 0.63 mm2.
Autors: Gaurav Agrawal;Sankaran Aniruddhan;Radha Krishna Ganti;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2016, volume: 26, issue:12, pages: 1005 - 1007
Publisher: IEEE
 
» A Comparative Study That Measures Ball Mill Load Parameters Through Different Single-Scale and Multiscale Frequency Spectra-Based Approaches
Abstract:
Data-driven modeling based on the shell vibration and acoustic signals of ball mills is normally applied to overcome the subjective errors of human inference. Many previously proposed selective ensemble (SEN) modeling approaches are based on “the manipulation of input features” from the multiinformation fusion perspective, which cannot selectively and jointly fuse the information hidden in multiscale spectral features and under several operating conditions (training samples). Therefore, this study suggests a new soft measuring procedure based on ensemble empirical mode decomposition (EEMD) and SEN. An improved kernel partial least-squares algorithm for SEN that is based on “subsample training samples” is utilized to construct a soft measuring model with the selected features and training samples. This study compares such data-driven soft measuring methods. The comparative results of bootstrap-based prediction performance estimation show that different methods have specific advantages in terms of simplicity, prediction accuracy, and interpretability. The industrial application of the EEMD-SEN method is discussed in this paper, and a new virtual sample generation method is proposed to address the modeling problem based on small sample spectral data.
Autors: Jian Tang;Tianyou Chai;Wen Yu;Zhuo Liu;Xiaojie Zhou;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Dec 2016, volume: 12, issue:6, pages: 2008 - 2019
Publisher: IEEE
 
» A Comparison of the Performance of Different Multiline Transmit Setups for Fast Volumetric Cardiac Ultrasound
Abstract:
It was previously demonstrated in 2-D echocardiography that a proper multiline transmit (MLT) implementation can be used to increase frame rate while preserving image quality. Initial findings for extending MLT to 3-D showed that it might address the low spatiotemporal resolution of current volumetric ultrasound systems. However, to date, it remains unclear how much transmit/receive parallelization would be possible using a 3-D MLT system. Therefore, the aim of this paper was to contrast different MLT setups for 3-D imaging by computer simulation in order to determine an optimal tradeoff between the amount of parallelization of an MLT system and the corresponding signal-to-noise ratio of the resulting images. Hereto, the image quality of several MLT setups was estimated by quantifying their crosstalk energy level. The results showed that for the tested setups, 4MLT broad beams and 9MLT narrow beams with Tukey () apodization in transmit and receive give the highest frame rate gain while maintaining an acceptable interbeam interference level. Moreover, although 16MLT narrow beams with Tukey/Tukey () apodization did show more pronounced interbeam interference, its gain in frame rate might outweigh its predicted loss in image quality. As such both 9MLT and 16MLT narrow beams were tested experimentally. For both systems, four receive lines were reconstructed from each transmit beam. The contrast-to-noise ratio of these imaging strategies was quantified and compared with the image quality obtained with line-by-line scanning. Despite some expected loss in image quality, the resulting images of the parallelized systems were very competitive to the benchmark, while speeding up the acquisition process by a factor of 36 and 64, respectively.
Autors: Alejandra Ortega;Jean Provost;Ling Tong;Pedro Santos;Brecht Heyde;Mathieu Pernot;Jan D’hooge;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Dec 2016, volume: 63, issue:12, pages: 2082 - 2091
Publisher: IEEE
 
» A Conical Patch Antenna Array for Agile Point-to-Point Communications in the 5.2-GHz Band
Abstract:
We study here a 12-element conical antenna array made of four linear subarrays angularly spaced by 90 ° and with three probe-fed radiating elements per subarray. A prototype has been designed and manufactured. The measured radiation characteristics of the elementary radiating element (active pattern) and of the subarray are found in good agreement with the simulation results. The proposed array configuration is considered as a promising solution to rotate and steer the antenna beam for ensuring point-to-point communication at 5.2 GHz.
Autors: V. Jaeck;L. Bernard;K. Mahdjoubi;R. Sauleau;S. Collardey;P. Pouliguen;P. Potier;
Appeared in: IEEE Antennas and Wireless Propagation Letters
Publication date: Dec 2016, volume: 15, issue: , pages: 1230 - 1233
Publisher: IEEE
 
» A Consensus Model for Motion Segmentation in Dynamic Scenes
Abstract:
The study of phenomena segmentation in natural scenes has attracted growing attention and is a popular research topic. While there are many studies detailing algorithms for motion segmentation in dynamic scenes, an important question arising from these studies is how to combine these algorithms. How can the label correspondence problem be resolved? Answering this question is difficult, because there are no labeled training data available in clustering to guide the search. Also, different algorithms produce incompatible data labels resulting in intractable correspondence problems. This paper presents a new consensus model for motion segmentation in dynamic scenes, which aims to combine several unsupervised methods to achieve a more reliable and accurate result. The advantage of our method is that it is intuitively appealing. Numerical experiments on various phenomena are conducted. The performance of the proposed model is compared with the best state-of-the-art motion segmentation methods recently proposed in the literature, demonstrating the robustness and accuracy of our method.
Autors: Thanh Minh Nguyen;Qingming Jonathan Wu;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Dec 2016, volume: 26, issue:12, pages: 2240 - 2249
Publisher: IEEE
 
» A Constellation Design Methodology Based on QoS and User Demand in High-Altitude Platform Broadband Networks
Abstract:
An investigation into the constellation design methodology of high-altitude platform (HAP) broadband networks is presented. The quality of service (QoS) metrics and user demand model are established in the HAP broadband networks. Each HAP is seen as a mobile base station, and a methodology of mobile base station placement is proposed with QoS and user demand guarantee for the first time. The multiple HAP coverage is analyzed with link geometry based on the single HAP coverage model. Besides, a cost-efficient optimization design framework for the HAP constellation is established by optimizing the design vector to maximize the network capacity per cost under the constraints of QoS metrics. In addition, the optimization model and improved artificial immune algorithm based on immune review are designed, and performance of the proposed method is demonstrated through in-depth numerical simulations. Simulation results show that the proposed constellation design method can effectively solve the problem of the mobile base station layout in the HAP broadband networks.
Autors: Feihong Dong;Han Han;Xiangwu Gong;Jingchao Wang;Hongjun Li;
Appeared in: IEEE Transactions on Multimedia
Publication date: Dec 2016, volume: 18, issue:12, pages: 2384 - 2397
Publisher: IEEE
 
» A Content-Aware Video Encoding Scheme Based on Single-Pass Consistent Quality Control
Abstract:
In real-time video streaming applications based on battery-powered camera systems, it is crucial to capture and transmit critical information satisfying the storage capacity and channel bandwidth requirement. In this paper, we propose a single-pass content-aware video encoding scheme for such applications to achieve a consistent video quality while satisfying the bit-rate constraints. To achieve the objective we developed: 1) scene descriptor based on the discrete cosine transformation coefficients obtained from the video encoder; 2) a parameterized analytic distortion model for video encoding using the scene descriptor; 3) scene change detection based on the encoded MB mode ratio; and 4) a single-pass consistent video quality control scheme which exploits 1), 2), and 3). Experimental results show that the proposed method results in less deviation from the target distortion and less distortion variance than the up-to-date best result by up to 65.25% and 75.88%, respectively, while satisfying the given rate constraints. The computing time overhead in the proposed method was 0.560% and 0.571% for the variable and constrained variable bit-rate mode, respectively, which is negligible in nearly all embedded applications.
Autors: Giwon Kim;Kang Yi;Chong-Min Kyung;
Appeared in: IEEE Transactions on Broadcasting
Publication date: Dec 2016, volume: 62, issue:4, pages: 800 - 816
Publisher: IEEE
 
» A Coupled Memcapacitor Emulator-Based Relaxation Oscillator
Abstract:
This brief proposes a floating emulator circuit for mimicking the dynamic behaviors of flux coupled memcapacitors (MCs) by making use of common off-the-shelf active devices. The equivalent constitutive relation of the coupled MC emulators is theoretically presented in details. The coupled MCs are then utilized to structure new relaxation oscillators (ROs) with the purpose of achieving controllable oscillation frequency and duty cycle. In consideration of different parameter configuration cases, an experimental investigation is carried out using a practical circuit emulating the dual coupled MCs and the ROs. Good agreement between experimental and theoretical results confirms that dual coupled MCs can be utilized to structure ROs with controllability.
Autors: Dongsheng Yu;Zhi Zhou;Herbert Ho-Ching Iu;Tyrone Fernando;YiHua Hu;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2016, volume: 63, issue:12, pages: 1101 - 1105
Publisher: IEEE
 
» A Current Control Scheme With Back EMF Cancellation and Tracking Error Adapted Commutation Shift for Switched-Reluctance Motor Drive
Abstract:
In this paper, an improved winding current control scheme for switched-reluctance motor drive is developed and evaluated. The current feedback controller (CFBC) is augmented with an observed back electromotive force (EMF) current feedforward controller (CFFC) and a current tracking error adapted dynamic commutation shift controller (DCSC). In the proposed DCSC, the rising winding current tracking errors of all phases are extracted, synthesized, and processed to generate the suitable advanced commutation shift angle. The effects of motor back EMF and nonlinear winding inductance can be reduced to yield improved winding current tracking waveforms under a wide operation range. The gradual improvements in current responses and efficiencies by augmenting the CFBC with the CFFC and then the DCSC are verified experimentally. Then, the robust speed control scheme is properly designed to achieve good acceleration/deceleration, reversible running, and dynamic characteristics.
Autors: Hsin-Ning Huang;Kai-Wei Hu;Yu-Wei Wu;Tai-Lang Jong;Chang-Ming Liaw;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Dec 2016, volume: 63, issue:12, pages: 7381 - 7392
Publisher: IEEE
 
» A Cybersecurity Detection Framework for Supervisory Control and Data Acquisition Systems
Abstract:
This paper presents a distributed intrusion detection system (DIDS) for supervisory control and data acquisition (SCADA) industrial control systems, which was developed for the CockpitCI project. Its architecture was designed to address the specific characteristics and requirements for SCADA cybersecurity that cannot be adequately fulfilled by techniques from the information technology world, thus requiring a domain-specific approach. DIDS components are described in terms of their functionality, operation, integration, and management. Moreover, system evaluation and validation are undertaken within an especially designed hybrid testbed emulating the SCADA system for an electrical distribution grid.
Autors: Tiago Cruz;Luis Rosa;Jorge Proença;Leandros Maglaras;Matthieu Aubigny;Leonid Lev;Jianmin Jiang;Paulo Simões;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Dec 2016, volume: 12, issue:6, pages: 2236 - 2246
Publisher: IEEE
 
» A Deep Neural Network-Driven Feature Learning Method for Multi-view Facial Expression Recognition
Abstract:
In this paper, a novel deep neural network (DNN)-driven feature learning method is proposed and applied to multi-view facial expression recognition (FER). In this method, scale invariant feature transform (SIFT) features corresponding to a set of landmark points are first extracted from each facial image. Then, a feature matrix consisting of the extracted SIFT feature vectors is used as input data and sent to a well-designed DNN model for learning optimal discriminative features for expression classification. The proposed DNN model employs several layers to characterize the corresponding relationship between the SIFT feature vectors and their corresponding high-level semantic information. By training the DNN model, we are able to learn a set of optimal features that are well suitable for classifying the facial expressions across different facial views. To evaluate the effectiveness of the proposed method, two nonfrontal facial expression databases, namely BU-3DFE and Multi-PIE, are respectively used to testify our method and the experimental results show that our algorithm outperforms the state-of-the-art methods.
Autors: Tong Zhang;Wenming Zheng;Zhen Cui;Yuan Zong;Jingwei Yan;Keyu Yan;
Appeared in: IEEE Transactions on Multimedia
Publication date: Dec 2016, volume: 18, issue:12, pages: 2528 - 2536
Publisher: IEEE
 
» A Differential ML Combiner for Differential Amplify-and-Forward System in Time-Selective Fading Channels
Abstract:
We propose a new differential maximum-likelihood (DML) combiner for noncoherent detection of the differential amplify-and-forward (D-AF) relaying system in the time-selective channel. The weights are computed based on both the average channel quality and the correlation coefficient of the direct and relay channels. Moreover, we derive a closed-form approximate expression for the average bit error rate (BER), which is applicable to any single-relay D-AF system with fixed weights. Both theoretical and simulated results are presented to show that the time-selective nature of the underlying channels tends to reduce the diversity gains at the low-signal-to-noise-ratio (SNR) region, resulting in an asymptotic BER floor at the high-SNR region. Moreover, the proposed DML combiner is capable of providing significant BER improvements compared with the conventional differential detection (CDD) and selection-combining (SC) schemes.
Autors: Yi Lou;Yong-Kui Ma;Qi-Yue Yu;Hong-Lin Zhao;Wei Xiang;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Dec 2016, volume: 65, issue:12, pages: 10157 - 10163
Publisher: IEEE
 
» A Differential Oscillator Injection Locking Technique for an 8 GHz Outphasing Modulator With 22.7% Modulation Efficiency
Abstract:
A wideband technique for outphasing modulation is introduced that efficiently generates outphasing modulation using differential injection locking between oscillators without requiring digital signal processing. Complex modulation with outphasing signals is demonstrated with two edge oscillators generating outphasing signals locked to a central master oscillator. The coupled-oscillator outphasing modulator circuit is implemented in 45 nm SOI CMOS and delivers 9.2 dBm to a 50 external load at 8 GHz while consuming only 36.5 mW to achieve a 22.7% overall system efficiency. The modulator provides 30 dB of dynamic range and the measurements demonstrate complex waveforms such as 64-quadrature amplitude modulation with 2.1% error vector magnitude at 60 Mb/s.
Autors: Mohammad S. Mehrjoo;James F. Buckwalter;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3093 - 3102
Publisher: IEEE
 
» A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <–73 dBc Fractional Spur and <–110 dBc Reference Spur in 65 nm CMOS
Abstract:
This paper proposes a fractional-N digital phase-locked loop (DPLL) architecture with feedforward multi-tone spur cancellation scheme. The proposed cancellation loop is capable of suppressing both internal spur, i.e., fractional-N spur, and externally coupled spur from input paths. It can be further extended for multi-stage operation for mitigating multiple spur sources. Both theoretical analysis and simulation results are provided in this paper to explore the design tradeoffs of the proposed technique. A proof-of-concept prototype is implemented in 65 nm CMOS. It measures external spur reduction of 15 to 35 dB and the worst-case fractional spur of 73.66 to 117 dBc with 20–50 dB improvement after enabling the cancellation loop. The measured reference spur ranges from 110.1 to 116.1 dBc across the entire DPLL operation range (3.2–4.8 GHz) thanks to design techniques. The measured in-band phase noise achieves 103 dBc at 100 kHz frequency offset and out-of-band phase noise of 122 dBc at 3 MHz frequency offset with integrated phase noise of 38.1 dBc from 10 kHz to 40 MHz.
Autors: Cheng-Ru Ho;Mike Shuo-Wei Chen;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2016, volume: 51, issue:12, pages: 3216 - 3230
Publisher: IEEE
 
» A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces
Abstract:
A transceiver (TRX) architecture employing a spectrum shaping signaling scheme is proposed, which can significantly reduce intersymbol interference and crosstalk in multidrop interfaces. The proposed TRX architecture relies on digital implementation rather than an analog/multitone approach, which can offer a power-efficient and versatile silicon implementation. Moreover, the crosstalk-induced noise can be reduced by applying the spectrum shaping signaling, and the whole TRX can be customized to the communication link by digital calibration while the aggregate data rate is kept fixed.
Autors: Gain Kim;Kiarash Gharibdoust;Armin Tajalli;Yusuf Leblebici com;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2016, volume: 63, issue:12, pages: 1126 - 1130
Publisher: IEEE
 

Publication archives by date

  2017:   January     February     March     April     May     June     July     August     September     October     November     December    

  2016:   January     February     March     April     May     June     July     August     September     October     November     December    

  2015:   January     February     March     April     May     June     July     August     September     October     November     December    

  2014:   January     February     March     April     May     June     July     August     September     October     November     December    

  2013:   January     February     March     April     May     June     July     August     September     October     November     December    

  2012:   January     February     March     April     May     June     July     August     September     October     November     December    

  2011:   January     February     March     April     May     June     July     August     September     October     November     December    

  2010:   January     February     March     April     May     June     July     August     September     October     November     December    

  2009:   January     February     March     April     May     June     July     August     September     October     November     December    

 
0-C     D-L     M-R     S-Z