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Electrical and Electronics Engineering publications abstract of: 12-2015 sorted by title, page: 0

» "Found" in Space - Helical Resonator Filters for Satellite Communication [Book/Software Reviews]
Abstract:
This book's main objective is to offer a contemporary, comprehensive approach to the design of RF and microwave filters for satellite applications with an emphasis on helical resonator technology. By exploiting the synergies among available data, information fusion can reduce data traffic, filter noisy measurements, and make predictions and inferences about a monitored entity. The book examines the state of the art in information fusion. It presents the known methods, algorithms, architectures, and models of information fusion and discusses their applicability in the context of wireless sensor networks (WSNs). Paying particular attention to the wide range of topics that have been covered in recent literature, the text presents the results of a number of typical case studies. Complete with research-supported elements and comprehensive references, this teaching-oriented volume uses standard scientific terminology, conventions, and notations throughout. It applies recently developed convex-optimization theory and highly efficient algorithms in estimation fusion to open up discussion and provide researchers with an ideal starting point for further research on distributed estimation and fusion for WSNs. The book supplies a cohesive overview of the key results of theory and applications of information-fusion-related problems in networked systems in a unified framework. Providing advanced mathematical treatment of fundamental problems with information fusion, it will help readers broaden their understanding of prospective applications and how to address such problems in practice. After reading the book, readers will gain the understanding required to model parts of dynamic systems and use those models to develop distributed fusion control algorithms that are based on feedback control theory.
Autors: Chu, J.;
Appeared in: IEEE Microwave Magazine
Publication date: Dec 2015, volume: 16, issue:11, pages: 80 - 82
Publisher: IEEE
 
» 2-Additive Capacity Identification Methods From Multicriteria Correlation Preference Information
Abstract:
The essential role of the particular families of capacities and the capacity identification methods is to help the decision maker to deal with the exponential complexity inherent in the construction process of the capacity. The 2-additive capacities appear to be the most popular among the particular families of capacities since they permit to model interactions between criteria while preserving simplicity. Besides the preference with respect to the decision criteria, most of the capacity identification methods also need to provide the desired overall evaluations of the decision alternatives in the learning set, which is a time-consuming task for the decision maker. In this paper, we propose some models to identify 2-additive capacities only from a kind of refined preference information with respect to the decision criteria called the multicriteria correlation preference information (MCCPI). The MCCPI is a group of 2-D preference information which can be described and obtained by the refined diamond diagram. The common principle of the proposed models is to minimize the different kinds of deviations between the MCCPI and the most desired 2-additive capacity(ies). A multicriteria decision making example is presented to show the feasibility of the proposed methods, and a 2-D scale of the MCCPI is also introduced in the further discussion of the illustrative example.
Autors: Wu, J.;Yang, S.;Zhang, Q.;Ding, S.;
Appeared in: IEEE Transactions on Fuzzy Systems
Publication date: Dec 2015, volume: 23, issue:6, pages: 2094 - 2106
Publisher: IEEE
 
» 2-D Write/Read Channel Model for Bit-Patterned Media Recording With Large Media Noise
Abstract:
A 2-D write/read channel model, which can accurately capture the media, writer, and reader characteristics, is proposed and investigated for very-high-density bit-patterned media recording (BPMR) system with large media noise. For the write process, a 2-D data-dependent write channel combined with a micromagnetic model of the writer is investigated for BPMR. In order to better understand the proposed channel model, several 2-D patterns are investigated, and the corresponding write failure events are studied. It is observed that the write error rates (WERs) are different for different 2-D patterns due to the 2-D data-dependent nature of the write-in errors, even though the write failure rates are the same for these different 2-D patterns. For the readback process, a read channel, including media noise, is combined with the write channel, and the bit error rates (BERs) are studied for various 2-D patterns as a function of media jitter and write clock phase drift. It is observed that the 2-D pattern corresponding to four identical bits in a square pattern provides the best performance at a target BER of , because it can provide adequate tolerance to media noise and interference in down-track and cross-track (CT) directions. The difference between the WER and the BER after readback is studied for various 2-D patterns, and the pattern corresponding to 4 bits with transitions in the CT direction is found to exhibit the largest difference among the studied patterns due to the fact that inter-track interference is more severe than the inter-symbol interference. These results motivate possible inclusion of 2-D modulation codes in BPMR channel to avoid certain bit patterns.
Autors: Wang, Y.;Yao, J.;Kumar, B.V.K.V.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Dec 2015, volume: 51, issue:12, pages: 1 - 11
Publisher: IEEE
 
» 20 Gb/s Mobile Indoor Visible Light Communication System Employing Beam Steering and Computer Generated Holograms
Abstract:
Visible light communication (VLC) systems have typically operated at data rates below 10 Gb/s and operation at this data rate was shown to be feasible by using laser diodes (LDs), imaging receivers and delay adaptation techniques (DAT imaging LDs-VLC). However, higher data rates, beyond 10 Gb/s, are challenging due to the low signal to noise ratio (SNR) and inter symbol interference (ISI). In this paper, for the first time, to the best of our knowledge, we propose, design, and evaluate a VLC system that employs beam steering (of part of the VLC beam) using adaptive finite vocabulary of holograms in conjunction with an imaging receiver and a DAT to enhance SNR and to mitigate the impact of ISI at high data rates (20 Gb/s). An algorithm was used to estimate the receiver location, so that part of the white light can be directed towards a desired target (receiver) using beam steering to improve SNR. Simulation results of our location estimation algorithm (LEA) indicated that the required time to estimate the position of the VLC receiver is typically within 224 ms in our system and environment. A finite vocabulary of stored holograms is introduced to reduce the computation time required by LEA to identify the best location to steer the beam to the receiver location. The beam steering approach improved the SNR of the fully adaptive VLC system by 15 dB at high data rates (20 Gb/s) over the DAT imaging LDs-VLC system in the worst-case scenario. In addition, we examined our new proposed system in a very harsh environment with mobility. The results showed that our proposed VLC system has strong robustness against shadowing, signal blockage, and mobility.
Autors: Hussein, A.T.;Alresheedi, M.T.;Elmirghani, J.M.H.;
Appeared in: Journal of Lightwave Technology
Publication date: Dec 2015, volume: 33, issue:24, pages: 5242 - 5260
Publisher: IEEE
 
» 2015 MTT-S Awards [MTT-S Society News]
Abstract:
Presents the recipients of various MTT-S society awards.
Autors: Jackson, C.;
Appeared in: IEEE Microwave Magazine
Publication date: Dec 2015, volume: 16, issue:11, pages: 90 - 99
Publisher: IEEE
 
» 2015 Scott Helt Memorial Award for the Best Paper Published in the IEEE Transactions on Broadcasting
Abstract:
The 2015 Scott Helt Memorial Award was awarded to Wenbo Ding, Fang Yang, Changyong Pan, Lingling Dai and Jian Song for their paper, “Compressive Sensing Based Channel Estimation for OFDM Systems Under Long Delay Channels.” This paper appeared in the IEEE TRANSACTIONS ON BROADCASTING, vol. 60, no. 2, pp. 313–321, Jun. 2014. The purpose of the IEEE Scott Helt Memorial Award is to recognize exceptional publications in the field and to stimulate interest in and encourage contributions to the fields of interest of the society.
Autors: Song, J.;Ding, W.;Yang, F.;Pan, C.;Dai, L.;
Appeared in: IEEE Transactions on Broadcasting
Publication date: Dec 2015, volume: 61, issue:4, pages: 555 - 556
Publisher: IEEE
 
» 2015 Tech Women Leadership Summit Helps Women Become Successful Leaders [WIE from Around the World]
Abstract:
Connect. Inspire. Lead. The 2015 Tech Women Leadership Summit held on 25 June 2015, in Guadalajara, Mexico, at the Intel Zapopan Site encouraged women to do just that. Hosted for the first time by IEEE Women in Engineering (WIE) and the Women at Intel Network affinity groups, the summit connected women leaders from the local technology industry, inspired them with ideas about leadership, and provided them with professional development skills to help them lead from their current positions. The summit, the first of its kind for women leaders in technology, focused on leadership, career development, and work-life balance. We spoke to three particiopants, and we're happy to share with you their stories and their advice on how to find success in the workplace no matter your age or experience level.
Autors: Salim, N.;
Appeared in: IEEE Women in Engineering Magazine
Publication date: Dec 2015, volume: 9, issue:2, pages: 58 - 62
Publisher: IEEE
 
» 3-D Hybrid Analytical Modeling: 3-D Fourier Modeling Combined With Mesh-Based 3-D Magnetic Equivalent Circuits
Abstract:
This paper presents a novel 3-D hybrid analytical modeling (HAM) method that integrates a mesh-based 3-D magnetic equivalent circuit model into 3-D Fourier modeling. This HAM is capable of predicting the electromagnetic field distributions for Cartesian 3-D structures. A generalized approach of the hybrid-modeling concept is presented. The modeling technique is applicable to a wide range of electromagnetic devices, such as linear and planar actuators. In only a fraction of the calculation times of 3-D finite-element approaches, the 3-D HAM calculates the magnet field distributions and forces with approximately 90% accuracy.
Autors: Pluk, K.J.W.;Jansen, J.W.;Lomonova, E.A.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Dec 2015, volume: 51, issue:12, pages: 1 - 14
Publisher: IEEE
 
» 3-D Model-Based Multi-Camera Deployment: A Recursive Convex Optimization Approach
Abstract:
Based on a convex optimization approach, we propose a new method of multi-camera deployment for visual coverage of a 3-D object surface. In particular, the optimal placement of a single camera is first formulated as translation and rotation convex optimization problems, respectively, over a set of covered triangle pieces on the target object. The convex optimization is recursively applied to expand the covered area of the single camera, with the initially covered triangle pieces being chosen along the object boundary for the first trial through a selection criterion. Then, the same optimization procedures are applied to place the next camera and thereafter. It is pointed out that our optimization approach guarantees that each camera is placed at the optimal pose in some sense for a group of triangles instead of a single piece. This feature, together with the selection criterion for initially covered triangles, reduces the number of operating cameras while still satisfying various constraint requirements such as resolution, field of view, blur, and occlusion. Both simulation and experimental results are presented to show superior performance of the proposed approach, comparing with the results from other existing methods.
Autors: Xuebo Zhang;Xiang Chen;Alarcon-Herrera, J.L.;Yongchun Fang;
Appeared in: IEEE/ASME Transactions on Mechatronics
Publication date: Dec 2015, volume: 20, issue:6, pages: 3157 - 3169
Publisher: IEEE
 
» 3-D Non-UV Digital Printing of Hydrogel Microstructures by Optically Controlled Digital Electropolymerization
Abstract:
A technique using digital masks without ultraviolet light to rapidly print 3-D biopolymer structures with complex microarchitectures in a microfluidic chip has been demonstrated. In this approach, a customized system is used to project light images on a photoconductive substrate in order to create localized virtual electrodes when an alternating electric field is applied across the fluidic medium in an optically controlled digital electropolymerization chip. Upon these virtual electrodes, the localized electric fields are generated, which could activate the polymerization of acrylate-based molecules, such as poly(ethylene glycol) diacrylate (PEGDA), to form microstructures with the same shapes as the projected light images. We have demonstrated that the 3-D PEGDA microstructures with the customized shapes could be fabricated rapidly through a layer-by-layer process by applying a series of digital masks (projected light images). With our current projection and microscopy system, the fabrication of microhydrogel structures with a lateral resolution of 3 and an adjustable thickness ranging from tens of nanometers to hundreds of micrometers has been demonstrated. In summary, this novel technique provides an efficient process for the rapid printing of the 3-D biopolymer-based microstructures, and could enable many future applications in a mechanoanalysis of cancer cells, tissue engineering, and drug screening. [2015-0110]
Autors: Liu, N.;Li, P.;Liu, L.;Yu, H.;Wang, Y.;Lee, G.;Li, W.J.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Dec 2015, volume: 24, issue:6, pages: 2128 - 2135
Publisher: IEEE
 
» 3-Gbit/s Indoor Visible Light Communications Using Optical Diversity Schemes
Abstract:
A 3-Gb/s high-speed indoor visible light communication system using optical diversity schemes is presented. A double optical diversity (DOD) scheme in time and frequency is employed with selection combining (SC) on the basis of red, green, and blue (RGB) light-emitting diodes (LEDs). In the proposed scheme, the original data and the delayed versions of this data are transmitted simultaneously by multiplying with orthogonal frequency in order to create diversity effect over the transmission. In addition, RGB LEDs are used for parallel transmission of data, thus resulting in an increase in the data speed. At the receiver, color filters are used to filter out for the desired signal, and SC is performed to obtain the most probable bits. Simulation results demonstrate that the proposed scheme is robust and efficient to overcome the effect of multiple reflections with a link margin of approximately 10 dB, as compared with a conventional on-off keying (OOK) modulation scheme at a bit error rate (BER) of 10-6. Moreover, the scheme achieves a data rate of 3 Gb/s with a BER of 10-6 at a signal-to-noise ratio (SNR) value of 3.6 dB over most locations in an indoor visible light communication (VLC) environment.
Autors: Sewaiwar, A.;Phyu Phyu Han;Yeon Ho Chung;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2015, volume: 7, issue:6, pages: 1 - 9
Publisher: IEEE
 
» 340-GHz SIW Cavity-Backed Magnetic Rectangular Slot Loop Antennas and Arrays in Silicon Technology
Abstract:
A 340-GHz on-chip antenna (OCA) with high-gain and high-radiation efficiency is designed using a standard SiGe BiCMOS technology without any postprocesses. In the proposed OCA structure, a rectangular slot loop is etched in the upper wall of a substrate integrated waveguide (SIW) to form a magnetic current loop radiator. The SIW structure forms a back cavity to suppress the surface waves and separate the radiation aperture from the low-resistivity substrate. Furthermore, the side wall of the SIW cavity and the edge of the slot form a resonator to reflect the power back to the slot loop. As a result, the radiation efficiency is improved. By etching a slot properly in the SIW upper wall, another resonating point is constructed and hence, the bandwidth is broadened. Single antenna element and a array are both designed and fabricated with- and without- the slot structure; a maximum gain of 7.9 dBi with the radiation efficiency of 48% at 340 GHz is achieved for the proposed SIW cavity-backed antenna structure.
Autors: Deng, X.;Li, Y.;Wu, W.;Xiong, Y.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2015, volume: 63, issue:12, pages: 5272 - 5279
Publisher: IEEE
 
» 3D Massive MIMO Systems: Modeling and Performance Analysis
Abstract:
Multiple-input-multiple-output (MIMO) systems of current LTE releases are capable of adaptation in the azimuth only. Recently, the trend is to enhance system performance by exploiting the channel's degrees of freedom in the elevation, which necessitates the characterization of 3D channels. We present an information-theoretic channel model for MIMO systems that supports the elevation dimension. The model is based on the principle of maximum entropy, which enables us to determine the distribution of the channel matrix consistent with the prior information on the angles. Based on this model, we provide analytical expression for the cumulative density function (CDF) of the mutual information (MI) for systems with a single receive and finite number of transmit antennas in the general signal-to-interference-plus-noise-ratio (SINR) regime. The result is extended to systems with finite receive antennas in the low SINR regime. A Gaussian approximation to the asymptotic behavior of MI distribution is derived for the large number of transmit antennas and paths regime. We corroborate our analysis with simulations that study the performance gains realizable through meticulous selection of the transmit antenna downtilt angles, confirming the potential of elevation beamforming to enhance system performance. The results are directly applicable to the analysis of 5G 3D-Massive MIMO-systems.
Autors: Nadeem, Q.;Kammoun, A.;Debbah, M.;Alouini, M.;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Dec 2015, volume: 14, issue:12, pages: 6926 - 6939
Publisher: IEEE
 
» 3D Shape Matching via Two Layer Coding
Abstract:
View-based 3D shape retrieval is a popular branch in 3D shape analysis owing to the high discriminative property of 2D views. However, many previous works do not scale up to large 3D shape databases. We propose a two layer coding (TLC) framework to conduct shape matching much more efficiently. The first layer coding is applied to pairs of views represented as depth images. The spatial relationship of each view pair is captured with so-called eigen-angle, which is the planar angle between the two views measured at the center of the 3D shape. Prior to the second layer coding, the view pairs are divided into subsets according to their eigen-angles. Consequently, view pairs that differ significantly in their eigen-angles are encoded with different codewords, which implies that spatial arrangement of views is preserved in the second layer coding. The final feature vector of a 3D shape is the concatenation of all the encoded features from different subsets, which is used for efficient indexing directly. TLC is not limited to encode the local features from 2D views, but can be also applied to encoding 3D features. Exhaustive experimental results confirm that TLC achieves state-of-the-art performance in both retrieval accuracy and efficiency.
Autors: Xiang Bai;Song Bai;Zhuotun Zhu;Latecki, L.J.;
Appeared in: IEEE Transactions on Pattern Analysis and Machine Intelligence
Publication date: Dec 2015, volume: 37, issue:12, pages: 2361 - 2373
Publisher: IEEE
 
» 3D Wideband Non-Stationary Geometry-Based Stochastic Models for Non-Isotropic MIMO Vehicle-to-Vehicle Channels
Abstract:
Actual vehicle-to-vehicle (V2V) channel measurements have shown that the wide-sense stationary (WSS) modeling assumption is valid only for very short time intervals. This fact motivates us to develop non-WSS V2V channel models. In this paper, we propose a novel three-dimensional (3D) theoretical non-WSS regular-shaped geometry-based stochastic model (RS-GBSM) and the corresponding sum-of-sinusoids (SoS) simulation model for non-isotropic scattering wideband multiple-input multiple-output (MIMO) V2V fading channels. The movements of the transmitter (Tx), scatterers, and receiver (Rx) result in the time-varying angles of departure (AoDs) and angles of arrival (AoAs) that make our models non-stationary. The proposed RS-GBSMs, combining line-of-sight (LoS) components, a two-sphere model, and multiple confocal elliptic-cylinder models, have the ability to study the impacts of vehicular traffic density (VTD) and non-stationarity on channel statistics, and jointly consider the azimuth and elevation angles by using the von Mises Fisher (VMF) distribution. The proposed RS-GBSMs are sufficiently generic and adaptable to model various V2V scenarios. Based on the proposed 3D non-WSS RS-GBSMs, important local channel statistical properties are derived and thoroughly investigated. The impacts of VTD and non-stationarity on these channel statistical properties are investigated by comparing them with those of the corresponding WSS model. The proposed non-WSS RS-GBSMs are validated by measurements in terms of the channel stationary time. Finally, numerical and simulation results demonstrate that the 3D non-WSS model is more practical to characterize real V2V channels.
Autors: Yuan, Y.;Wang, C.;He, Y.;Alwakeel, M.M.;Aggoune, e.M.;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Dec 2015, volume: 14, issue:12, pages: 6883 - 6895
Publisher: IEEE
 
» 3D-Printed Origami Packaging With Inkjet-Printed Antennas for RF Harvesting Sensors
Abstract:
Pub DtlThis paper demonstrates the combination of additive manufacturing techniques for realizing complex 3D origami structures for high frequency applications. A 3D-printed compact package for enclosing radio frequency (RF) electronics is built, that features on-package antennas for RF signal reception (for harvesting or communication) at orthogonal orientations. Conventional 3D printing technologies often require significant amounts of time and supporting material to realize certain structures, such as hollow packages. In this work, instead of fabricating the package in its final 3D form, it is 3D-printed as a planar structure with “smart” shape-memory hinges that allow origami folding to a 3D shape after heating. This significantly reduces fabrication time and effectively eliminates the need for supporting material, thus minimizing the overall manufacturing cost. Metallization on the package is performed by directly inkjet printing conductive inks on top of the 3D-printed surface with a modified inkjet-printed process without the need for surface treatment or processing. Inkjet-printed on-package conductive features are successfully fabricated, that are combined with RF energy harvesting electronics to showcase the proof-of-concept of utilizing origami techniques to build fully 3D RF systems. The methodologies presented in this paper will be enabling the manufacturing of numerous real-time shape-changing 3D complex structures for electromagnetic applications.
Autors: Kimionis, J.;Isakov, M.;Koh, B.S.;Georgiadis, A.;Tentzeris, M.M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2015, volume: 63, issue:12, pages: 4521 - 4532
Publisher: IEEE
 
» 5.8-GHz Stacked Differential Rectenna Suitable for Large-Scale Rectenna Arrays With DC Connection
Abstract:
In this communication, a novel stacked differential rectenna is proposed and its characteristics are experimentally investigated. The proposed rectenna can effectively convert RF power to dc due to its differential operation. The conversion efficiency of 44.1% was obtained when the received power density was as low as . The proposed rectenna can easily achieve large-scale rectenna arrays effectively using its simple structure. The rectenna array with DC connection provides almost the same conversion efficiency and incident angle characteristics in comparison with a single rectenna.
Autors: Matsunaga, T.;Nishiyama, E.;Toyoda, I.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2015, volume: 63, issue:12, pages: 5944 - 5949
Publisher: IEEE
 
» 5G internet of things [Editor's Note]
Abstract:
Presents the introductory editorial for the "Communications Standards" issue for this publication.
Autors: Parsons, G.;
Appeared in: IEEE Communications Magazine
Publication date: Dec 2015, volume: 53, issue:12, pages: 2 - 2
Publisher: IEEE
 
» 8-Gb/s RGBY LED-Based WDM VLC System Employing High-Order CAP Modulation and Hybrid Post Equalizer
Abstract:
In this paper, for the first time, we propose the use of a hybrid post equalizer in a high-order carrierless-amplitude-and-phase-modulation-based visible light communication (VLC) system. The hybrid equalizer consists of a linear equalizer, a Volterra-series-based nonlinear equalizer, and a decision-directed least mean squares equalizer to simultaneously mitigate the linear and nonlinear distortions of the VLC system. A commercially available red-blue-green-yellow light-emitting diode (RBGY LED) is utilized for four-wavelength multiplexing. By the hybrid equalizer, an aggregate data rate of 8 Gb/s is experimentally achieved over a 1-m indoor free-space transmission with the bit error rate (BER) below the 7% forward error correction (FEC) limit of 3.8 × 10-3. To the best of our knowledge, this is the highest data rate ever reported in high-speed VLC systems.
Autors: Yiguang Wang;Li Tao;Xingxing Huang;Jianyang Shi;Nan Chi;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2015, volume: 7, issue:6, pages: 1 - 7
Publisher: IEEE
 
» -Constrained Normalized LMS Algorithms for Adaptive Beamforming
Abstract:
We detail in this paper an -norm Linearly constrained normalized least-mean-square ( -CNLMS) algorithm and its weighted version ( -WCNLMS) applied to solve problems whose solutions have some degree of sparsity, such as the beamforming problem in uniform linear arrays, standard hexagonal arrays, and (non-standard) hexagonal antenna arrays. In addition to the linear constraints present in the CNLMS algorithm, the -WCNLMS and the -CNLMS algorithms take into account an -norm penalty on the filter coefficients, which results in sparse solutions producing thinned arrays. The effectiveness of both algorithms is demonstrated via computer simulations. When employing these algorithms to antenna array problems, the resulting effect due to the -norm constraint is perceived as a large aperture array with few active elements. Although this work focuses the algorithm on antenna array synthesis, its application is not limited to them, i.e., the -CNLMS is suitable to solve other problems like sparse system identification and signal reconstruction, where the weighted version, the -WCNLMS algorithm, presents superior performance compared to the -CNLMS algorithm.
Autors: de Andrade, J.F.;de Campos, M.L.R.;Apolinario, J.A.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Dec 2015, volume: 63, issue:24, pages: 6524 - 6539
Publisher: IEEE
 
» Control of Descriptor Systems Possessing Invariant Zeros on the Imaginary Axis and Infinity
Abstract:
We present an algorithm for suboptimal control of descriptor systems possessing invariant zeros on the imaginary axis and infinity. It is proved that the algorithm works also in an optimality case. The algorithm is illustrated by examples.
Autors: Stefanovski, J.D.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Dec 2015, volume: 60, issue:12, pages: 3127 - 3139
Publisher: IEEE
 
» Control of Descriptor Systems Possessing Invariant Zeros on the Imaginary Axis and Infinity
Abstract:
We present an algorithm for suboptimal control of descriptor systems possessing invariant zeros on the imaginary axis and infinity. It is proved that the algorithm works also in an optimality case. The algorithm is illustrated by examples.
Autors: Stefanovski, J.D.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Dec 2015, volume: 60, issue:12, pages: 3127 - 3139
Publisher: IEEE
 
» In Situ Platform for Isothermal Testing of Thin-Film Mechanical Properties Using Thermal Actuators
Abstract:
An in situ tensile test platform has been developed to study the mechanical properties of thin-film metal specimens. The fully integrated on-chip platform loads a specimen using a thermal actuator (TA). TAs conveniently provide high forces and excellent alignment, but generate large heat that can flow to specimens and raise their temperature. In the new design, heat flow to the specimen is negligible. This attribute was achieved by introducing a thermal resistor that limits heat flow to the specimen and a heat sink that shunts the remaining heat. Tensile residual stress in the specimen was eliminated by including preinserted microgrippers. A comprehensive error analysis indicates that the strength accuracy is ±5% (one standard deviation). The platform was used to study the strength-related mechanical properties of Al/0.5 wt% Cu microtensile bars with two different thicknesses. Initial tests indicate that 0.63- -thick tensile bars exhibit higher strength, a larger strain hardening coefficient, and less elongation than 1.03- -thick tensile bars. Transmission electron microscopy indicated that the lower ductility was due to plastic strain localization. When the tensile bar length is decreased from 200 to 70 or 50 , strength increased by 40% for both thickness values. [2015-0082]
Autors: Saleh, M.E.;Beuth, J.L.;Picard, Y.N.;de Boer, M.P.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Dec 2015, volume: 24, issue:6, pages: 2008 - 2018
Publisher: IEEE
 
» In-silico Studies Show Potent Inhibition of HIV-1 Reverse Transcriptase Activity by a Herbal Drug
Abstract:
Acquired immunodeficiency syndrome (AIDS) is a life threatening disease of the human immune system caused by human immunodeficiency virus (HIV). Effective inhibition of reverse transcriptase activity is a prominent, clinically viable approach for the treatment of AIDS. Few non-nucleoside reverse transcriptase inhibitors (NNRTIs) have been approved by the United States Food and Drug Administration (US FDA) as drugs for AIDS. In order to enhance therapeutic options against AIDS we examined novel herbal compounds of 4-thiazolidinone and its derivatives that are known to have remarkable antiviral potency. Our molecular docking and simulation experiments have identified one such herbal molecule known as (5E)-3-(2-aminoethyl)-5-benzylidene-1, 3-thiazolidine-2,4-dione that may bind HIV-1RT with high affinity to cause noncompetitive inhibition. Results are also compared with other US FDA approved drugs. Long de novo simulations and docking study suggest that the ligand (5E)-3-(2-aminoethyl)-5-benzylidene-1, 3-thiazolidine-2,4-dione (CID: 1656714) has strong binding interactions with Asp113, Asp110, Asp185 and Asp186 amino acids, all of which belong to one or the other catalytic pockets of HIV-1RT. It is expected that these interactions could be critical in the inhibitory activity of the HIV-1RT. Therefore, this study provides an evidence for consideration of (5E)-3-(2-aminoethyl)-5-benzylidene-1, 3-thiazolidine-2,4-dione as a valuable natural molecule in the treatment and prevention of HIV- associated disorders.
Autors: Seniya, C.;Yadav, A.;Khan, G.;Sah, N.K.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Dec 2015, volume: 12, issue:6, pages: 1355 - 1364
Publisher: IEEE
 
» PreProPath: An Uncertainty-Aware Algorithm for Identifying Predictable Profitable Pathways in Biochemical Networks
Abstract:
Pathway analysis is a powerful approach to enable rational design or redesign of biochemical networks for optimizing metabolic engineering and synthetic biology objectives such as production of desired chemicals or biomolecules from specific nutrients. While experimental methods can be quite successful, computational approaches can enhance discovery and guide experimentation by efficiently exploring very large design spaces. We present a computational algorithm, Predictably Profitable Path (PreProPath), to identify target pathways best suited for engineering modifications. The algorithm utilizes uncertainties about the metabolic networks operating state inherent in the underdetermined linear equations representing the stoichiometric model. Flux Variability Analysis is used to determine the operational flux range. PreProPath identifies a path that is predictable in behavior, exhibiting small flux ranges, and profitable, containing the least restrictive flux-limiting reaction in the network. The algorithm is computationally efficient because it does not require enumeration of pathways. The results of case studies show that PreProPath can efficiently analyze variances in metabolic states and model uncertainties to suggest pathway engineering strategies that have been previously supported by experimental data.
Autors: Ullah, E.;Walker, M.;Lee, K.;Hassoun, S.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Dec 2015, volume: 12, issue:6, pages: 1405 - 1415
Publisher: IEEE
 
» OnOff Error Control Coding Scheme for Minimizing Tracking Error in Wireless Feedback Control Systems
Abstract:
In wireless feedback control systems, reducing packet loss is critical. The use of channel coding may decrease such packet loss; however, redundancy in channel coding also decreases the packet transmission rate although the bit rate remains the same. Thus, control systems are highly affected by disturbances. To improve control system quality, channel coding should be adaptively employed on the basis of packet loss and disturbances. Herein, an onoff error control coding scheme based on the communication and control layers is proposed. In this scheme, channel coding is adaptively used to minimize tracking errors in a controlled plant. Results demonstrate that the proposed onoff error control coding scheme improves the control system’s reference tracking performance compared with that when using a fixed-rate coding scheme.
Autors: Hattori, S.;Kobayashi, K.;Okada, H.;Katayama, M.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Dec 2015, volume: 11, issue:6, pages: 1411 - 1421
Publisher: IEEE
 
» A 0.009–1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching
Abstract:
This brief presents a 0.009–1.4-GHz frequency synthesizer that is able to compensate for changes in the frequency tuning range, due to temperature variations, by switching voltage-controlled oscillator (VCO) bands with minimal phase and frequency errors, without cycle slipping and without introducing any phase offsets. This is accomplished by a subthreshold capacitor bank switching circuit that causes the gradual addition of capacitance slowly enough to allow the loop to adjust the VCO control voltage to compensate. The additional circuitry uses less than 0.001 mm2 of silicon area and has minimal power consumption and minimal effects on the synthesizer's phase noise when fully switched. The synthesizer used to demonstrate this was implemented in a 0.18- SiGe BiCMOS process and achieves 365-fs integrated jitter at 1.05 GHz, with a total power consumption of 81 mW. Measurements of the capacitor bank switching circuit shows that it prevents cycle slipping during band switching and reduces the maximum frequency deviation by 99.3%.
Autors: Lam, J.;Riley, T.;Filiol, N.M.;Rogers, J.W.M.;Plett, C.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2015, volume: 62, issue:12, pages: 1129 - 1133
Publisher: IEEE
 
» A 0.13- m CMOS Current-Mode All-Pass Filter for Multi-GHz Operation
Abstract:
A CMOS wide-bandwidth first-order current-mode all-pass filter (APF) is discussed. The circuit consists of one transistor, a resistor, a grounded inductor, and a load. When used with a current mirror as the load, the current-mode filter exhibits a high output impedance, which is advantageous from an integration point of view and enables this configuration to be cascaded with current-mode circuits. The operation of the proposed circuit is experimentally validated. The APF implemented in IBM CMOS was measured to have the pole-zero pair located at 8.32 GHz and to achieve a 55 ps group delay while consuming 19 mW from a 1.5-V supply. This paper experimentally demonstrates a CMOS APF that operates at multi-GHz frequencies and achieves the highest delay-bandwidth products of the published CMOS first-order APFs known to the authors.
Autors: Ahmadi, P.;Taghavi, M.H.;Belostotski, L.;Madanayake, A.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2015, volume: 23, issue:12, pages: 2813 - 2818
Publisher: IEEE
 
» A 0.13- m CMOS Current-Mode All-Pass Filter for Multi-GHz Operation
Abstract:
A CMOS wide-bandwidth first-order current-mode all-pass filter (APF) is discussed. The circuit consists of one transistor, a resistor, a grounded inductor, and a load. When used with a current mirror as the load, the current-mode filter exhibits a high output impedance, which is advantageous from an integration point of view and enables this configuration to be cascaded with current-mode circuits. The operation of the proposed circuit is experimentally validated. The APF implemented in IBM 0.13-μm CMOS was measured to have the pole-zero pair located at 8.32 GHz and to achieve a 55 ps group delay while consuming 19 mW from a 1.5-V supply. This paper experimentally demonstrates a CMOS APF that operates at multi-GHz frequencies and achieves the highest delay-bandwidth products of the published CMOS first-order APFs known to the authors.
Autors: Ahmadi, P.;Taghavi, M.H.;Belostotski, L.;Madanayake, A.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2015, volume: 23, issue:12, pages: 2813 - 2818
Publisher: IEEE
 
» A 0.27e Read Noise 220- Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11- CIS Process
Abstract:
A low temporal read noise and high conversion gain reset-gate-less CMOS image sensor (CIS) has been developed and demonstrated for the first time at photoelectron-counting-level imaging. To achieve a high pixel conversion gain without fine or special processes, the proposed pixel has two unique structures: 1) coupling capacitance between the transfer gate and floating diffusion (FD) and 2) coupling capacitance between the reset gate and FD, for removing parasitic capacitances around the FD node. As a result, a CIS with the proposed pixels is able to achieve a high pixel conversion gain of and a low read noise of 0.27e using correlated multiple-sampling-based readout circuitry.
Autors: Seo, M.;Kawahito, S.;Kagawa, K.;Yasutomi, K.;
Appeared in: IEEE Electron Device Letters
Publication date: Dec 2015, volume: 36, issue:12, pages: 1344 - 1347
Publisher: IEEE
 
» A 0.27e Read Noise 220- Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11- CIS Process
Abstract:
A low temporal read noise and high conversion gain reset-gate-less CMOS image sensor (CIS) has been developed and demonstrated for the first time at photoelectron-counting-level imaging. To achieve a high pixel conversion gain without fine or special processes, the proposed pixel has two unique structures: 1) coupling capacitance between the transfer gate and floating diffusion (FD) and 2) coupling capacitance between the reset gate and FD, for removing parasitic capacitances around the FD node. As a result, a CIS with the proposed pixels is able to achieve a high pixel conversion gain of 220 μV/e- and a low read noise of 0.27erms- using correlated multiple-sampling-based readout circuitry.
Autors: Min-Woong Seo;Kawahito, S.;Kagawa, K.;Yasutomi, K.;
Appeared in: IEEE Electron Device Letters
Publication date: Dec 2015, volume: 36, issue:12, pages: 1344 - 1347
Publisher: IEEE
 
» A 0.5 V/1.8 V High Dynamic Range CMOS Imager for Artificial Retina Applications
Abstract:
This paper presents a 0.5 V/1.8 V high dynamic range (HDR) sense-and-stimulus (SAS) CMOS imager with adaptive gain control for artificial retina applications. The proposed dual-supply SAS pixel consists of a 0.5 V HDR pulsewidth modulation image sensor (for sense) and a 1.8 V pulse-to-current stimulator (for stimulus) to achieve a highly integrated and lowpower solution. The 0.5 V operated HDR image sensor is adopted to reduce power consumption with dynamic range extension for in vivo requirement and mimicking the eyesight capability. The 1.8 V operated in-pixel pulse-to-current stimulator provides a biphasic current pulse with sufficient intensity to activate neuron cells for artificial vision recovery applications. The timeto-voltage conversion technique with a programmable gain is employed to achieve a reduced fixed-pattern-noise (FPN) and an adaptive sensitivity. A prototype chip has been implemented and verified with a sensing array of 40 × 40, a pixel size of 30 × 30 μm2, and a fill factor of 33.3%. The maximum driving capability of biphasic stimulation current is ±50 μA with a 7.5 kQ electrode model. The measurement results show an array FPN of 0.63% and a tunable dynamic range of 36 dB. The chip consumes a total power of 2.1 mW with current stimulator at 16.9 frame/s, which achieves an imager figure of merit of 77.7 nW/frame pixel.
Autors: Chih-Lin Lee;Chih-Cheng Hsieh;
Appeared in: IEEE Sensors Journal
Publication date: Dec 2015, volume: 15, issue:12, pages: 6833 - 6838
Publisher: IEEE
 
» A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC
Abstract:
This paper presents a 13 bit 50 MS/s fully differential ring amplifier based SAR-assisted pipeline ADC, implemented in 65 nm CMOS. We introduce a new fully differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of high gain, fast slew based charging and an almost rail-to-rail output swing. We implement a switched-capacitor (SC) inter-stage residue amplifier that uses this new fully differential ring amplifier to give accurate amplification without calibration. In addition, a new floated detect-and-skip (FDAS) capacitive DAC (CDAC) switching method reduces the switching energy and improves linearity of first-stage CDAC. With these techniques, the prototype ADC achieves measured SNDR, SNR, and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, with a Nyquist frequency input. The prototype achieves 13 bit linearity without calibration and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion step and 174.9 dB, respectively.
Autors: Lim, Y.;Flynn, M.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2901 - 2911
Publisher: IEEE
 
» A 10 mW Bluetooth Low-Energy Transceiver With On-Chip Matching
Abstract:
A mass-produced Bluetooth Low-Energy transceiver is presented in classic double frequency VCO architecture fabricated in TSMC 55 nm CMOS. The radio part occupies 2.9 mm while the complete SoC occupies 5.9 mm . The transceiver consumes 11 mW when receiving at 94 dBm and 10 mW when transmitting at 0 dBm. This is roughly a factor 2 lower than benchmark mass-produced designs. The power consumption is higher than recently published experimental sliding-IF designs, but it does not suffer from their inherent susceptibility to blocking and pulling. Easy application is enabled by a fully integrated single-ended 50 RFIO and combined Buck- and Boost-mode DC-DC converter.
Autors: Prummel, J.;Papamichail, M.;Willms, J.;Todi, R.;Aartsen, W.;Kruiskamp, W.;Haanstra, J.;Opbroek, E.;Rievers, S.;Seesink, P.;van Gorsel, J.;Woering, H.;Smit, C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 3077 - 3088
Publisher: IEEE
 
» A 10-Bit Low-Power High-Color-Depth Column Driver With Two-Stage Multi-Channel RDACs for Small-Format TFT-LCD Driver ICs
Abstract:
This study proposes a 10-bit low-power high-color-depth LCD column driver IC with two-stage multi-channel RDACs and switch resistance compensation. The design removes intermediate buffers from two-stage RDACs and uses global reference buffers to isolate the global resistor string and output channels. Because the global resistor string is isolated from output channels, the global resistor string can use a larger resistance value to achieve lower power consumption. This study proposes a class-AB buffer for the global reference buffers to compensate for the errors caused by the voltage drop on switches connected in series with the channel resistor string. The channel resistor strings also reuse the output stage current of the global buffer to reduce power consumption. A prototype of a 200-channel column driver was fabricated using 0.18- m/0.35- m CMOS technology with the worst DNL/INL being 1.2/1.1 LSB. The proposed 10-bit DAC occupies only 66% of the area of a conventional 8-bit RDAC using the same technology. The 200-channel column driver consumes a total static current of only 0.38 mA.
Autors: Yin, P.-Y.;Lu, C.-W.;Chen, Y.-H.;Liang, H.-C.;Tseng, S.-P.;
Appeared in: Journal of Display Technology
Publication date: Dec 2015, volume: 11, issue:12, pages: 1061 - 1068
Publisher: IEEE
 
» A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers
Abstract:
The virtual ground reference buffer (VGRB) technique is introduced as a means to improve the performance of switched-capacitor circuits. The technique enhances the performance by improving the feedback factor of the op-amp without affecting the signal gain. The bootstrapping action of the level-shifting buffers relaxes key op-amp performance requirements including unity-gain bandwidth, noise, open-loop gain and offset compared with conventional circuits. This reduces the design complexity and the power consumption of op-amp based circuits. Based on this technique, a 12 b pipelined ADC is implemented in 65 nm CMOS that achieves 67.0 dB SNDR at 250 MS/s and consumes 49.7 mW of power from a 1.2 V power supply.
Autors: Boo, H.H.;Boning, D.S.;Lee, H.-S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2912 - 2921
Publisher: IEEE
 
» A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS
Abstract:
This paper presents a 14 bit 35 MS/s successive approximation register (SAR) ADC that achieves a nearly constant 74.5 dB peak SNDR up to Nyquist and an SFDR of 90/99 dB for inputs near Nyquist and at low-frequencies, respectively. The ADC employs a loop-embedded input buffer that shields the large sampling capacitor from the input and thereby eases the ADC drive requirements significantly. Since the buffer's nonlinearity is cancelled by the SAR operation, a pair of basic source followers can be used, adding only 12.5 mW (23% of the total power) to the power budget. The ADC includes a bandgap reference and a self-calibrated current steering DAC to close the SAR loop, which eliminates the need for a low-impedance off-chip reference. The design occupies 0.236 mm in 40 nm CMOS and consumes a total power of 54.5 mW from its 1.2/2.5 V supplies, leading to an SNDR-based Schreier FOM of 159.5 dB at Nyquist.
Autors: Kramer, M.J.;Janssen, E.;Doris, K.;Murmann, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2891 - 2900
Publisher: IEEE
 
» A 16–28-W 92.8%-Efficiency Monolithic Quasi-Resonant LED Driver With Constant-Duty-Ratio Frequency Regulator
Abstract:
This brief presents a monolithic high-voltage light-emitting diode (LED) driver for lighting applications. The LED driver is able to operate at high switching frequency because large switching loss is eliminated by zero-voltage switching. Inductor values are therefore reduced. A constant-duty-ratio frequency regulator (CDFR) is proposed to regulate the LED current, and the small signal characteristics of the proposed LED driver with CDFR are analyzed. The proposed design, including the controller and power transistor, was fabricated in MagnaChip 0.35- 700-V bipolar-CMOS- LDMOS process. The LED driver with inductors switches at around 5.4 MHz and powers up 16–28 1-W LEDs. Experimental results show that the LED driver achieves peak efficiency of 92.8% within the input voltage range of 55–120 V.
Autors: Li, L.;Gao, Y.;Mok, P.K.T.;Sun, I.M.;Park, N.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2015, volume: 62, issue:12, pages: 1199 - 1203
Publisher: IEEE
 
» A 2-GHz Bandwidth, Integrated Transimpedance Amplifier for Single-Photon Timing Applications
Abstract:
In recent years, single-photon timing techniques have been employed in a steadily increasing number of applications. Most of these applications require high detector performance in terms of noise, photon detection efficiency, time resolution, and number of pixels operating in parallel. The detectors best fitting these requirements are single-photon avalanche diode (SPAD) arrays built in custom technology, although the systems based on such detectors are limited to a few pixels. In this paper, we present a novel read-out circuit, developed in a 0.18- m high voltage-CMOS technology, for the detection of the SPAD avalanche current: the designed circuit is based on a 2.2-GHz bandwidth integrated transimpedance amplifier, followed by a low-pass filter, to reduce crosstalk, and by an integrated comparator. The pick-up circuit has a total power dissipation of 1.1 mW, occupies an overall area of 15500 and shows a time resolution down to 48 ps and a negligible crosstalk between two different pixels. All these features can open the way to the development of large SPAD arrays, characterized by a performance comparable with that of the single-pixel structures. Moreover, the good agreement between the simulated and the measured resolution (with a 14% maximum error) makes the future improvement of the evaluated performance possible.
Autors: Crotti, M.;Rech, I.;Acconcia, G.;Gulinatti, A.;Ghioni, M.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2015, volume: 23, issue:12, pages: 2819 - 2828
Publisher: IEEE
 
» A 2.45 GHz Phased Array Antenna Unit Cell Fabricated Using 3-D Multi-Layer Direct Digital Manufacturing
Abstract:
This paper reports on the design, fabrication and characterization of a 3-D printed RF front end for a 2.45 GHz phased array unit cell. The printed unit cell, which includes a circularly-polarized dipole antenna, a miniaturized capacitive-loaded open-loop resonator filter and a 4-bit phase shifter, is fabricated using a direct digital manufacturing (DDM) approach that integrates fused deposition of thermoplastic substrates with micro-dispensing for deposition of conductive traces. The individual components are combined in a passive phased array antenna unit cell comprised of seven stacked substrate layers with seven conductor layers. The measured return loss of the unit cell is dB across the 2.45 GHz ISM band and the measured gain is dBi including all components. Experimental and simulation-based characterization is performed to investigate electrical properties of as-printed materials, in particular the inhomogeneity of printed thick-film conductors and substrate surface roughness. The results demonstrate the strong potential for fully-printed RF front ends for light weight, low cost, conformal and readily customized applications.
Autors: Ketterl, T.P.;Vega, Y.;Arnal, N.C.;Stratton, J.W.I.;Rojas-Nastrucci, E.A.;Cordoba-Erazo, M.F.;Abdin, M.M.;Perkowski, C.W.;Deffenbaugh, P.I.;Church, K.H.;Weller, T.M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2015, volume: 63, issue:12, pages: 4382 - 4394
Publisher: IEEE
 
» A 2.45-GHz Energy-Autonomous Wireless Power Relay Node
Abstract:
Pub DtlThis paper describes the design and experimental characterization of a battery-less bidirectional 2.45-GHz circuit operating in oscillator mode as a wireless power transmitter or in rectifier mode as an energy harvester, with a measured efficiency greater than 50% in both operating states. The dc voltage harvested in rectifier mode provides the drain bias for the oscillator. The FET-gate self-bias mechanism is exploited in both functionalities, thus eliminating external gate bias. Bi-directionality is based on the time-reversal properties of a transistor oscillator. Energy autonomy is possible at received RF power levels as low as dBm, by means of a bias-assisting feedback loop, consisting of a single matched low-power diode in shunt configuration. A hybrid prototype is demonstrated with the ability to operate as an energy-autonomous power relay node by switching between transmit and receive power modes.
Autors: Del Prete, M.;Costanzo, A.;Georgiadis, A.;Collado, A.;Masotti, D.;Popovic, Z.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2015, volume: 63, issue:12, pages: 4511 - 4520
Publisher: IEEE
 
» A 200-Mb/s Data Rate 3.1–4.8-GHz IR-UWB All-Digital Pulse Generator With DB-BPSK Modulation
Abstract:
A new all-digital impulse radio ultrawideband pulse generator in a 65-nm CMOS technology for a wireless body area network is presented. The system architecture is a delay-based pulse generator that is designed using only logic gates to minimize the power consumption. The system uses a frequency range of 3.1–4.8 GHz and 3 channels with a 500-MHz bandwidth. The maximum data rate of this system is 100 Mb/s with pulse positioned modulation and 200 Mb/s with on–off keying. Delay-based binary phase-shift keying is used to achieve an efficient spectral line characteristic. The total power consumption of the pulse generator is 30 pJ/pulse at a 1.2-V supply voltage without a static bias current.
Autors: Na, K.;Jang, H.;Ma, H.;Choi, Y.;Bien, F.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2015, volume: 62, issue:12, pages: 1184 - 1188
Publisher: IEEE
 
» A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks
Abstract:
We report a dc-coupled burst-mode (BM) receiver for optical links in a dynamically reconfigurable network. Through the introduction of interlocking search algorithms, a robust 25 Gb/s BM operation is achieved with 31 ns lock time. At the beginning of the burst, the receiver first performs input dc current offset calibration in 12.5 ns, then achieves phase lock in 18.5 ns, and after that tracks data using a phase interpolator (PI) based bang-bang clock and data recovery (CDR). The sensitivity of the receiver is (average power, ) at 25 Gb/s, tested with a single mode 1550 nm reference optical transmitter. There is no significant sensitivity penalty in the presence of frequency offset between the transmitter and the receiver. Measured power efficiency of the receiver at 25 Gb/s is 4.4 pJ/bit. The core of the 32 nm SOI CMOS circuit occupies .
Autors: Rylyakov, A.;Proesel, J.E.;Rylov, S.;Lee, B.G.;Bulzacchelli, J.F.;Ardey, A.;Parker, B.;Beakes, M.;Baks, C.W.;Schow, C.L.;Meghelli, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 3120 - 3132
Publisher: IEEE
 
» A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS
Abstract:
Silicon photonics devices offer promising solution to meet the growing bandwidth demands of next-generation interconnects. This paper presents a 5 × 25 Gb/s carrier-depletion microring-based wavelength-division multiplexing (WDM) transmitter in 65 nm CMOS. An AC-coupled differential driver is proposed to realize 4 × VDD output swing as well as tunable DC-biasing. The proposed transmitter incorporates 2-tap asymmetric pre-emphasis to effectively cancel the optical nonlinearity of the ring modulator. An average-power-based dynamic wavelength stabilization loop is also demonstrated to compensate for thermal induced resonant wavelength drift. At 25 Gb/s operation, each transmitter channel consumes 113.5 mW and maintains 7 dB extinction ratio with a 4.4 V output swing in the presence of thermal fluctuations.
Autors: Li, H.;Xuan, Z.;Titriku, A.;Li, C.;Yu, K.;Wang, B.;Shafik, A.;Qi, N.;Liu, Y.;Ding, R.;Baehr-Jones, T.;Fiorentino, M.;Hochberg, M.;Palermo, S.;Chiang, P.Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 3145 - 3159
Publisher: IEEE
 
» A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS
Abstract:
This paper presents a power- and area-efficient multistandard serial link transceiver designed for backplane application rates of up to 28 Gb/s, such as OIF CEI-25G, CEI-28G, and IEEE 802.3bj 100G-KR4. The receiver features a continuous-time linear equalizer, variable gain amplifier, and a 14-tap decision feedback equalizer, including eight floating taps. The transmitter has a 2:1 multiplexer with a duty cycle distortion corrected half-rate clock and a full-rate source-series terminated driver with a 5-tap feed-forward equalizer. The shared PLL employs a transformer-based LC-VCO that achieves a VCO tuning range of 20G to 29 GHz and 0.23 ps RMS jitter at 28.125 GHz. The transmitter output shows only 50 fs duty-cycle distortion. The transceiver can compensate a 40 dB insertion loss backplane channel (excluding package) at a data rate of 25.78 Gb/s with eight channels running simultaneously. It is fabricated in 28 nm standard CMOS and analog section consumes only 295 mW at 1 V supply with transmitter driver at 1.25 V. Such low power consumption and performance are achieved by combination of advanced 28 nm process, low power and performance driven receiver and transmitter topologies, widely adopted bandwidth extension techniques, built-in analog calibrations and one common PLL with a transformer based VCO for four transceivers.
Autors: Zhang, B.;Khanoyan, K.;Hatamkhani, H.;Tong, H.;Hu, K.;Fallahi, S.;Abdul-Latif, M.;Vakilian, K.;Fujimori, I.;Brewster, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 3089 - 3100
Publisher: IEEE
 
» A 3-D Interface-Enriched Generalized FEM for Electromagnetic Problems With Nonconformal Discretizations
Abstract:
An interface-enriched generalized finite-element method (IGFEM) is introduced for efficient 3-D electromagnetic analysis of heterogeneous materials. Without using meshes that conform to the material microstructures, which greatly lessens the burden of mesh generation, the method assigns generalized degrees of freedom (DOFs) at material interfaces to capture the discontinuities of the field and its derivatives. The generalized DOFs are supported by enriched vector basis functions (VBFs), which are constructed through a linear combination of the VBFs from the subelements. Several verification examples are provided to show that the IGFEM is not sensitive to the quality of the subelements and maintains the same level of solution accuracy and computational complexity as the standard finite-element method (FEM) based on conformal meshes. The potential of the proposed IGFEM is demonstrated by simulating some engineering problems with complex, periodic internal structures, including composite materials with randomly distributed spherical particles and ellipsoidal inclusions and microvascular channels.
Autors: Zhang, K.;Jin, J.;Geubelle, P.H.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2015, volume: 63, issue:12, pages: 5637 - 5649
Publisher: IEEE
 
» A 3-Phase Resonant Switched Capacitor Converter Delivering 7.7 W at 85% Efficiency Using 1.1 nH PCB Trace Inductors
Abstract:
In recent years, there has been a push towards high-density and monolithic DC-DC converters to support applications such as performance and mobile computing, consumer electronics, and renewable energy. Switched capacitor (SC) converters have started to gain traction for a number of these applications, but are still subject to fundamental limitations that drive them towards expensive process options and high switching frequencies. Variable regulation is challenging with the SC approach, and comes at the cost of lower power density and efficiency. This work presents a resonant switched capacitor (ReSC) topology that addresses some of these challenges by introducing a small amount of inductance in series with the flying capacitor, eliminating charge-sharing losses and thus allowing efficient operation in a low-cost process option. The three-phase interleaved topology can deliver up to 7.7 W at 85% efficiency (power density of 0.91 W/mm or 6.4 kW/in ) using a bootstrapped n-channel power train and single-digit nH inductors embedded in a flip-chip assembly. We also present the first implementation of efficient, fully-variable conversion ratios in a silicon ReSC integrated circuit without reconfiguration or gain-hopping .
Autors: Schaef, C.;Stauth, J.T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2861 - 2869
Publisher: IEEE
 
» A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion
Abstract:
A 3.5 GHz digital fractional-N PLL in 65 nm CMOS technology is presented that achieves phase noise and spurious tone performance comparable to those of a high-performance analog PLL. It is enabled by a new second-order frequency-to-digital converter that uses a dual-mode ring oscillator and digital logic instead of a charge pump and ADC. It also incorporates a new technique to reduce excess phase noise that would otherwise be caused by component mismatches when the DCO input is near integer boundaries. The PLL's largest in-band fractional spur is -60 dBc, its worst-case reference spur is -81 dBc, and its phase noise is -93, -126, and -151 dBc/Hz at offsets of 100 kHz, 1 MHz, and 20 MHz, respectively. Its active area is 0.34 mm 2 and it dissipates 15.6 mW from a 1 V supply.
Autors: Weltin-Wu, C.;Zhao, G.;Galton, I.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2988 - 3002
Publisher: IEEE
 
» A 300-V LDMOS Analog-Multiplexed Driver for MEMS Devices
Abstract:
The paper presents a high-voltage integrated-circuit driver capable of producing analog voltages up to 300 V, using Dalsa's 0.8- HV CMOS/DMOS process, suitable for MEMS and medical systems. The IC driver includes a HV operational amplifier (op-amp) with a class-B output stage, and HV analog switches with improved off-isolation performance. In contrast to previous frequency compensation schemes, where only one dominant pole occurs below the unity-gain bandwidth, the HV op-amp employs a novel frequency compensation topology with three poles and two zeros located within the unity-gain bandwidth, and is capable of driving large capacitive loads from 100 pF to 10 nF. Theoretical analysis of off-isolation of the HV analog switches is also reported and confirms the improvement in off-isolation performance.
Autors: Dai, S.;Knepper, R.W.;Horenstein, M.N.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2015, volume: 62, issue:12, pages: 2806 - 2816
Publisher: IEEE
 
» A 4 4 MIMO-OFDM Baseband Receiver With 160 MHz Bandwidth for Indoor Gigabit Wireless Communications
Abstract:
This paper presents the design and implementation of a 4 4 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) baseband receiver for indoor high-throughput wireless communication systems. The receiver uses bandwidths of 40, 80, and 160 MHz that correspond to three operation modes of 128, 256, and 512-point FFT, respectively. Four spatial streams are supported to offer the maximum uncoded data rate of 2.6 Gbps. Channel pre-processing based on sorted QR decomposition and the non-constant K-best soft-output MIMO detector are adopted to enhance the system performance. The addressing scheme for the QR phase memory is proposed to deal with the processing-time discrepancy between the write-in and read-out accesses. The high-throughput pipelined architecture for the non-constant K-best soft-output MIMO detector with selected discard-paths is analyzed to show a balance between performance and complexity. This receiver IC integrates 1.034 M logic gates as well as a total of 835 Kb SRAM in 90 nm CMOS technology and can generate hard output for 64-QAM constellation. The coded system performance is also provided with the soft-output MIMO detection. From the measurement results, the power consumption of the chip is 424 mW, 97 mW, and 26 mW at 1.16 V, 0.8 V and 0.66 V, respectively, for operations in 160 MHz, 80 MHz, and 40 MHz bandwidth modes. Compared to the prior works for 80 MHz channel bandwidth, this work supports wider channel bandwidth and achieves higher throughput.
Autors: Tsai, P.-Y.;Lo, P.-C.;Shih, F.-J.;Jau, W.-J.;Huang, M.-Y.;Huang, Z.-Y.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2015, volume: 62, issue:12, pages: 2929 - 2939
Publisher: IEEE
 
» A 4 4 MIMO-OFDM Baseband Receiver With 160 MHz Bandwidth for Indoor Gigabit Wireless Communications
Abstract:
This paper presents the design and implementation of a 4 4 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) baseband receiver for indoor high-throughput wireless communication systems. The receiver uses bandwidths of 40, 80, and 160 MHz that correspond to three operation modes of 128, 256, and 512-point FFT, respectively. Four spatial streams are supported to offer the maximum uncoded data rate of 2.6 Gbps. Channel pre-processing based on sorted QR decomposition and the non-constant K-best soft-output MIMO detector are adopted to enhance the system performance. The addressing scheme for the QR phase memory is proposed to deal with the processing-time discrepancy between the write-in and read-out accesses. The high-throughput pipelined architecture for the non-constant K-best soft-output MIMO detector with selected discard-paths is analyzed to show a balance between performance and complexity. This receiver IC integrates 1.034 M logic gates as well as a total of 835 Kb SRAM in 90 nm CMOS technology and can generate hard output for 64-QAM constellation. The coded system performance is also provided with the soft-output MIMO detection. From the measurement results, the power consumption of the chip is 424 mW, 97 mW, and 26 mW at 1.16 V, 0.8 V and 0.66 V, respectively, for operations in 160 MHz, 80 MHz, and 40 MHz bandwidth modes. Compared to the prior works for 80 MHz channel bandwidth, this work supports wider channel bandwidth and achieves higher throughput.
Autors: Tsai, P.-Y.;Lo, P.-C.;Shih, F.-J.;Jau, W.-J.;Huang, M.-Y.;Huang, Z.-Y.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2015, volume: 62, issue:12, pages: 2929 - 2939
Publisher: IEEE
 
» A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator
Abstract:
A high switching frequency multi-phase buck converter architecture using a time-based compensator is presented. Efficiency degradation due to mismatch between the phases is mitigated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65 nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32 mm , of which the controller occupies only 0.04 mm . The converter operates over a wide range of switching frequencies (30–70 MHz) and regulates output to any desired voltage in the range of 0.6 V to 1.5 V from 1.8 V input voltage. With a 400 mA step in the load current, the settling time is less than 0.6 s and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3 A/MHz.
Autors: Kim, S.J.;Nandwana, R.K.;Khan, Q.;Pilawa-Podgurski, R.C.N.;Hanumolu, P.K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2814 - 2824
Publisher: IEEE
 
» A 4.5 mW CT Self-Coupled Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation
Abstract:
This paper presents a power-efficient single-loop continuous-time (CT) modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm .
Autors: Ho, C.-Y.;Liu, C.;Lo, C.-L.;Tsai, H.-C.;Wang, T.-C.;Lin, Y.-H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2870 - 2879
Publisher: IEEE
 
» A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS
Abstract:
This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To achieve low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.8 V and 1 V, respectively. A 2.5 b 2-way time-interleaved 2.5 GS/s multiplying digital-to-analog converter (MDAC) is followed by an 8 b 8-way time-interleaved 625 MHz successive-approximation register (SAR). This architecture combines the benefits of both ADC topologies and allows significant power and complexity reduction. The high-speed 2.5 b MDAC front-end simplifies the complexity of time-interleaving (TI) and provides gain for attenuating the 8 b SAR non-idealities, when referred to the ADC input, relaxing its specifications and design. To further reduce power, the 2.5 b MDAC front-end is SHA-less, and an over-range calibration loop that allows operation at multi-GHz input is introduced. A calibration technique is also proposed to align the MDAC and SAR references, whose misalignment would otherwise produce integral non-linearity (INL) degradation. The ADC achieves 61.8 dB THD, 57.1 dB SNR for a 500 MHz input, while for a 2.35 GHz input it achieves 54.7 dB THD, 46.8 dB SNR (55.8 dB SNR excluding the integrated PLL contribution). The time-interleaving spur is 70 dBc. The ADC consumes 150 mW and occupies less than 0.5 mm .
Autors: Brandolini, M.;Shin, Y.J.;Raviprakash, K.;Wang, T.;Wu, R.;Geddada, H.M.;Ko, Y.-J.;Ding, Y.;Huang, C.-S.;Shih, W.-T.;Hsieh, M.-H.;Chou, W.-T.;Li, T.;Shrivastava, A.;Chen, Y.-C.;Hung, B.J.-J.;Cusmai, G.;Wu, J.;Zhang, M.M.;Yao, Y.;Unruh, G.;Venes, A.;Hu
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2922 - 2934
Publisher: IEEE
 
» A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s Advanced Techniques-Based Novel Intrabody Communication Receiver Analog Front End
Abstract:
This paper presents a low power, long-transmission distance, high data rate intrabody communication (IBC) analog receiver front end (RFE). First, to optimize the transmission performance, conventional transmission line analysis scheme is creatively adopted to the IBC design to characterize the body channel. Second, switched-capacitor filters based on sampling rate boosting technique are adopted for higher accuracy and lower power consumption. Third, a novel RFE topology is proposed to further enhance the IBC performance. The new RFE is designed and fabricated in a standard 180-nm CMOS process. Measurement results show that the RFE can successfully transmit data spanning the whole human body, around 180 cm, which is one of the longest transmission distances reported in related literatures. Furthermore, it reaches a maximum data rate of 2.5 Mb/s with a bit error rate less than 1e-7 and consumes 5.4 mW from a 1.8 V supply. The proposed RFE compares favorably to similar reported works.
Autors: Wang, H.;Tang, X.;Choy, C.S.;Leung, K.N.;Pun, K.P.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2015, volume: 23, issue:12, pages: 2829 - 2841
Publisher: IEEE
 
» A 60 V Auto-Zero and Chopper Operational Amplifier With 800 kHz Interleaved Clocks Pub _newline and Input Bias Current Trimming
Abstract:
An auto-zero and chopper operational amplifier with a 4.5–60 V supply voltage range is realized, using a CMOS process augmented by 5 V CMOS and 60 V DMOS transistors. It achieves a maximum offset voltage drift of 0.02 , a minimum CMRR of 145 dB, a noise PSD of , and a 3.1 MHz unity gain bandwidth, while dissipating 840 of current. Up-modulated chopper ripple is suppressed by auto- zeroing.Pub /_nolinebreak Furthermore, glitches from the charge injection of the input switches are mitigated by employing six parallel input stages with 800 kHz interleaved clocks. This moves the majority of the glitch energy up to 4.8 MHz, while leaving little energy at 800 kHz. As a result, the requirements on an external low-pass glitch filter is relaxed, and a wider usable signal bandwidth can be obtained. Maximum input bias current due to charge injection mismatch is reduced from 1.5 nA to 150 pA by post production trimming with an on-chip charge mismatch compensation circuit.
Autors: Kusuda, Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2804 - 2813
Publisher: IEEE
 
» A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links
Abstract:
A rapid-on/off transceiver for embedded clock architecture that enables energy proportional communication over the serial link is presented. In an energy proportional link, energy consumed by serial link is proportional to the amount of data communicated. Energy proportionality can be achieved by scaling the serial link power linearly with the link utilization, and fine grained rapid power state transition (rapid-on/off) is one such technique which can achieve this objective. In this paper, architecture and circuit techniques to achieve rapid-on/off in PLL, transmitter and receiver are discussed. Background phase calibration technique in PLL and CDR phase calibration logic in receiver enable instantaneous lock on power-on. The proposed transceiver demonstrates power scalability with a wide range of link utilization and, therefore, helps in improving overall system efficiency. Fabricated in 65 nm CMOS technology, the 7 Gb/s transceiver achieves power-on-lock in less than 20 ns. Proposed PLL achieves power-on-lock in 1 ns. The transceiver achieves power scaling by 44 (63.7 mW-to-1.43 mW) and energy efficiency degradation by only 2.2 (9.1 pJ/bit-to-20.5 pJ/bit), when the effective data rate (link utilization) changes by 100 (7 Gb/s-to-70 Mb/s). The proposed transceiver occupies an active die area of 0.39 mm .
Autors: Anand, T.;Talegaonkar, M.;Elkholy, A.;Saxena, S.;Elshazly, A.;Hanumolu, P.K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 3101 - 3119
Publisher: IEEE
 
» A m-Scale Computational Model of Magnetic Neural Stimulation in Multifascicular Peripheral Nerves
Abstract:
There has been recurring interest in using magnetic neural stimulation for implantable localized stimulation. However, the large stimulation voltages and energies necessary to evoke neuronal activity have tempered this interest. To investigate the potential of magnetic stimulation as a viable methodology and to provide the ability to investigate novel coil designs that can result in lower stimulation threshold voltages and energies, there is a need for a model that accurately predicts the magnetic field-tissue interaction that results in neuronal stimulation. In this study, we provide a computational framework to accurately estimate the stimulation threshold and have validated the model with in vivo magnetic stimulation experiments. To make such predictions, we developed a micrometer-resolution anatomically driven computational model of rat sciatic nerve and quantified the effect of tissue heterogeneity (i.e., fascicular organization, axon distribution, and density) and axonal membrane capacitance on the resulting threshold. Using the multiresolution impedance method, we computed the spatial-temporal distribution of the induced electric field in the nerve and applied this field to a Frankenhaeuser-Huxley axon model in NEURON to simulate the nonlinear mechanisms of the membrane channels. The computational model developed predicts the stimulation thresholds for four magnetic coil designs with different geometrical parameters within the 95% confidence interval (experiments count = 4) of measured in vivo stimulation thresholds for the rat sciatic nerve.
Autors: RamRakhyani, A.K.;Kagan, Z.B.;Warren, D.J.;Normann, R.A.;Lazzi, G.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Dec 2015, volume: 62, issue:12, pages: 2837 - 2849
Publisher: IEEE
 
» A m-Scale Computational Model of Magnetic Neural Stimulation in Multifascicular Peripheral Nerves
Abstract:
There has been recurring interest in using magnetic neural stimulation for implantable localized stimulation. However, the large stimulation voltages and energies necessary to evoke neuronal activity have tempered this interest. To investigate the potential of magnetic stimulation as a viable methodology and to provide the ability to investigate novel coil designs that can result in lower stimulation threshold voltages and energies, there is a need for a model that accurately predicts the magnetic field–tissue interaction that results in neuronal stimulation. In this study, we provide a computational framework to accurately estimate the stimulation threshold and have validated the model with in vivo magnetic stimulation experiments. To make such predictions, we developed a micrometer-resolution anatomically driven computational model of rat sciatic nerve and quantified the effect of tissue heterogeneity (i.e., fascicular organization, axon distribution, and density) and axonal membrane capacitance on the resulting threshold. Using the multiresolution impedance method, we computed the spatial-temporal distribution of the induced electric field in the nerve and applied this field to a Frankenhaeuser–Huxley axon model in NEURON to simulate the nonlinear mechanisms of the membrane channels. The computational model developed predicts the stimulation thresholds for four magnetic coil designs with different geometrical parameters within the 95% confidence interval (experiments count = 4) of measured in vivo stimulation thresholds for the rat sciatic nerve.
Autors: RamRakhyani, A.K.;Kagan, Z.B.;Warren, D.J.;Normann, R.A.;Lazzi, G.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Dec 2015, volume: 62, issue:12, pages: 2837 - 2849
Publisher: IEEE
 
» A Bayesian Approach for Spherical Harmonic Expansion Identification: Application to Magnetostatic Field Created by a Power Circuitry
Abstract:
This paper deals with the use of the Bayesian approach to inverse an underdetermined magnetostatic problem based on spherical harmonic expansion. Identification of the spherical harmonic coefficients is helped thanks to some a priori information. This information comes from a numerical model statistically studied to define an average-state vector and a covariance matrix. The whole approach is applied for the study of the magnetostatic field inside an electric vehicle, created by its power circuitry. It demonstrates the strength of merging a priori information and measured information in order to obtain an efficient identification of magnetic sources created by a complex set of conductors.
Autors: Pinaud, O.;Chadebec, O.;Rouve, L.;Coulomb, J.;Guichon, J.;Vassilev, A.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Dec 2015, volume: 57, issue:6, pages: 1501 - 1509
Publisher: IEEE
 
» A Bayesian Method for Planning Accelerated Life Testing
Abstract:
In this paper, a Bayesian criterion is proposed based on the expected Kullback-Leibler divergence between the posterior and the prior distributions of the parameters of interest. We call the Bayesian criterion the reference optimality criterion, which is to find an optimal plan to maximize the amount of information from the data. A large-sample approximation is utilized to simplify the formula to obtain optimal plans numerically. Because optimal plans based on reference optimality criterion do not depend on the sample size, a modified reference optimality criterion is proposed. We give numerical examples using the Weibull distribution with type I censoring to illustrate the methods, and to examine the influence of the prior distribution, censoring time, and sample size. We also compare our methods with other criteria through Monte Carlo simulation.
Autors: Xu, A.;Tang, Y.;
Appeared in: IEEE Transactions on Reliability
Publication date: Dec 2015, volume: 64, issue:4, pages: 1383 - 1392
Publisher: IEEE
 
» A Bidirectional Wireless-Over-Fiber Transport System
Abstract:
This study proposes and demonstrates a bidirectional wireless-over-fiber (WoF) transport system based on an optical interleaver, a phase modulator, and an optical bandpass filter (OBPF)-based phase-modulation-to-intensity-modulation converter that can deliver intensity-modulated 60 GHz millimeter-wave (MMW), 30 GHz microwave (MW), and phase-remodulated 15 GHz MW data signals. A broadband light source, comprising an optoelectronic oscillator scheme and an optical signal-to-noise ratio (OSNR) enhancement scheme, is deployed in these bidirectional 60 GHz/30 GHz/15 GHz WoF transport systems. For downlink transmission, light is promoted optically from a 5 Gbps/ 15 GHz MW data signal to 5 Gbps/60 GHz MMW and 5 Gbps/30 GHz MW data signals in fiber-wireless convergence. The downstream light is phase remodulated successfully using a 5 Gbps/15 GHz MW data signal for uplink transmission. Through a thorough examination of such bidirectional 60 GHz/30 GHz/15 GHz WoF transport systems, the bit error rate (BER) is observed to perform well over a 40 km single-mode fiber and a 4 m RF wireless transmission. This bidirectional 60 GHz/30 GHz/15 GHz WoF transport system is a prominent alternative not only because of its advancement in integrating optical fiber and RF wireless networks but because of the benefits of communication links for broader bandwidth and higher transmission rate as well.
Autors: Mochii, T.;Shiva, A.;Hai-Han Lu;Chang-Jen Wu;Ting-Chieh Lu;Chien-An Chu;Peng-Chun Peng;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2015, volume: 7, issue:6, pages: 1 - 9
Publisher: IEEE
 
» A Blocker-Tolerant Inductor-Less Wideband Receiver With Phase and Thermal Noise Cancellation
Abstract:
A wideband receiver architecture with simultaneous phase and thermal noise cancellation greatly relaxes the traditional trade-offs between noise, out-of-band linearity, LO phase noise and power consumption. The architecture employs thermal noise cancelling and avoids voltage gain at blocker frequencies, and exploits the symmetry of phase noise to cancel the reciprocal mixing products in the presence of either single-tone or modulated blockers. The resulting design in 28 nm CMOS has 2 dB noise figure from 100 MHz to 2.8 GHz. Without using any inductors on-chip including the RF VCO, the receiver's NF is below 14 dB under either a 0 dB CW blocker or a -10 dBm WCDMA blocker.
Autors: Wu, H.;Mikhemar, M.;Murphy, D.;Darabi, H.;Chang, M.-C.F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2948 - 2964
Publisher: IEEE
 
» A Boundary Assembling Method for Chinese Entity-Mention Recognition
Abstract:
A boundary assembling (BA) method is presented for Chinese entity-mention recognition. Given a sentence, instead of recognizing entity mentions in a unitary style, the authors' BA method first detects boundaries of entity mentions and then assembles detected boundaries into entity-mention candidates. Each candidate is further assessed by a classifier trained on nonlocal features. This method can make better use of nonlocal features and effectively recognize nested entity mentions. Using the ACE 2005 Chinese corpus, the authors' experimental results show an improvement over state-of-the-art techniques, outperforming existing methods in F-score by 5 percent for entity-mention detection and 4.23 percent for entity-mention recognition.
Autors: Yanping Chen;Qinghua Zheng;Ping Chen;
Appeared in: IEEE Intelligent Systems
Publication date: Dec 2015, volume: 30, issue:6, pages: 50 - 58
Publisher: IEEE
 
» A Brief History of Computing in Mexico
Abstract:
Although Mexico has a common border with the United States, on account of its enduring inequities in distribution of wealth and often rickety economy, Mexico's technological advances have been a step behind. Nevertheless, Mexico has had quite a few interesting high-end technology locations that helped stimulate the acquisition and spread of computing knowledge. This article briefly describes how Mexican computing has evolved-depending significantly on developments in the US and often hindered by the Mexican politics that have led to long periods of economic crisis. In the 1990s, an international treaty helped boost the Mexican computer industry, although this relatively recent event still left Mexico far behind its neighbor to the north. The treaty made it easy to import computers into Mexico and to produce them in Mexico, and the economy became more stable over the following decades. In time, computing developments in Mexico started catching up with the US, coinciding with cheaper consumer electronics products, a good economy, high productivity, and globalization.
Autors: Nava, Jaquelinne Dominguez;Acosta-Guadarrama, Juan C.;Valdovinos-Rosas, Rosa M.;Solis Ramos, Victor H.;Cesar, Nely Plata;Rebollar, Leticia Quintanar;Perez, Rogelio Davila;
Appeared in: IEEE Annals of the History of Computing
Publication date: Dec 2015, volume: 37, issue:4, pages: 76 - 86
Publisher: IEEE
 
» A Brief History of Experiments in Art and Technology
Abstract:
In the 1960s, there was a growing interest among visual artists, dancers, and composers in using new technology and new technical materials generated by rapid technological developments. The magazine Scientific American was some artists? favorite read.
Autors: Martin, J.;
Appeared in: IEEE Potentials
Publication date: Dec 2015, volume: 34, issue:6, pages: 13 - 19
Publisher: IEEE
 
» A Broadband GaN pHEMT Power Amplifier Using Non-Foster Matching
Abstract:
Non-Foster matching is applied to design a multi- octave broadband GaN power amplifier (PA) in this paper. The bandwidth limitation from high-Q interstage matching is overcome through the use of negative capacitor, which is realized with a negative impedance converter (NIC) using the cross-coupled GaN FETs. For high power operation over the entire bandwidth, the natural interstage matching is optimized for the upper subfrequency band and the lower subfrequency band is compensated for by the negative capacitance presented by non-Foster circuit (NFC). Detailed analysis is presented to understand the frequency and power limits of NIC circuits for PA applications. Two negative impedance matched PAs (NMPAs) are fabricated with 0.25- m GaN pHEMT process. The implemented PA with combining shows the output powers of 35.7–37.5 dBm with the power added efficiencies of 13–21% from 6 to 18 GHz. The combining PA achieves over 5 W output power from 7 to 17 GHz. The NFC boosts the efficiencies and power below 12 GHz to achieve broadband performance without using any lossy matching or negative feedback. To our knowledge, this is the first demonstration of NIC-based broadband amplifiers with multi-watt-level output power.
Autors: Lee, S.;Park, H.;Choi, K.;Kwon, Y.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2015, volume: 63, issue:12, pages: 4406 - 4414
Publisher: IEEE
 
» A Circuit to Eliminate Serial Skew in High-Speed Serial Communication Channels
Abstract:
This brief relates to communication established through high-speed serial links. A serial communication channel can be formed by grouping multiple high-speed serial communication lanes to achieve greater serial bandwidth. Such channels require circuitry to eliminate relative skew across multiple lanes to ensure data integrity in the receiver. Channel bonding is a mechanism used to synchronize serial communication channels in larger data rate and bandwidth applications. This brief presents an approach to channel bonding that optimizes area, power, and initialization time and yields better performance. The ideas discussed here use a delay-based model and explore the possibility of performing channel bonding in a centralized way. The methodology is deployed in the Aurora Protocol Solution Suite, and a comparative analysis with another state-of-the-art approach is performed.
Autors: Sarmah, M.J.;Azeemuddin, S.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2015, volume: 62, issue:12, pages: 1179 - 1183
Publisher: IEEE
 
» A Closed-Loop Speed Advisory Model With Driver's Behavior Adaptability for Eco-Driving
Abstract:
Providing drivers with speed advisories is an effective eco-driving method at signalized intersections. However, all current research on speed advisory models has excluded the driver's behavior factor. In this paper, we focus on developing a speed advisory model that is able to adapt to the driver's behavior for eco-driving. First, we propose a closed-loop speed advisory framework, with simulation results to show that the current model could not fit in the closed-loop implementation. Next, the continuous acceleration with explicit high velocity boundary (CAEHV) model is established to address the issues when the existing model is used. However, the simulation results for the CAEHV model are not fully satisfactory due to the existence of oscillations in actual speed trajectories. Third, the CAEHV with coasting (CAEHV-C) model is established, in which the vehicle coasting is applied to supplement cruising to avoid oscillations. Simulation results show that the fuel economy performance of the CAEHV-C model is improved by 4% when compared with the CAEHV model. It also shows that CAEHV-C performs the best in terms of the driver's behavior adaptability.
Autors: Xiang, X.;Zhou, K.;Zhang, W.;Qin, W.;Mao, Q.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Dec 2015, volume: 16, issue:6, pages: 3313 - 3324
Publisher: IEEE
 
» A Compact 2.45-GHz Broadband Rectenna Using Grounded Coplanar Waveguide
Abstract:
This letter presents a compact 2.45 GHz broadband rectenna using the grounded coplanar waveguide (GCPW). A new broadband slot antenna fed by GCPW with a high gain of 10 dBi and a wide half-power beamwidth of 60 ° is designed as the receiving antenna. By designing an input and an output impedance match network, a compact GCPW rectifying circuit based on the voltage doubler principle is proposed, which has broadband performance and is easy to be integrated with the novel GCPW antenna. The receiving antenna and the rectifying circuit are simulated and measured. The measured results of the rectenna agree well with those of the rectifying circuit, which validate the effectiveness of the design. The microwave-direct current (mw-dc) conversion efficiencies of the rectenna keep higher than 50% within the band from 2.2 to 2.6 GHz at 13 dBm received power on a 900Ω load, and the highest efficiency is 72.5%. This rectenna has good performances of broadband, high mw-dc efficiency and compact structure.
Autors: Mei-Juan Nie;Xue-Xia Yang;Guan-Nan Tan;Bing Han;
Appeared in: IEEE Antennas and Wireless Propagation Letters
Publication date: Dec 2015, volume: 14, issue: , pages: 986 - 989
Publisher: IEEE
 
» A Compact Dipole Antenna With Curved Reflector for 1.0–4.2 GHz EMC Measurement
Abstract:
A figure of merit for electromagnetic compatibility (EMC) testing antennas is first introduced and some design considerations are presented. A compact dipole antenna with curved reflector is proposed for 1.0–4.2 GHz EMC measurement. Structure of the curved reflector, defined by a power function, is studied by full-wave simulations and verified by experiments. A comparison between the curved reflector, corner reflector, and pyramidal reflector is presented and discussed. The presented antenna has nearly constant radiation patterns and realized gain. The minimum measurement distance is only 1.0 m for the proposed antenna, which reaches the lower limit recommended by CISPR. For small equipments under test, the measurement distance can be alternated and higher field strength can be provided by the proposed antenna without increasing the input power. In contrast, double-rigided horn antennas do not have the flexibility as they have much larger dimensions.
Autors: Wu, Q.;Ding, X.;Su, D.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Dec 2015, volume: 57, issue:6, pages: 1289 - 1297
Publisher: IEEE
 
» A Compact Dual-Polarized 4-Port Eleven Feed With High Sensitivity for Reflectors Over 0.35–1.05 GHz
Abstract:
We present significant improvements to the circular Eleven feed technology for a dual-reflector system operating over 0.35–1.05 GHz as a backup for the square kilometer array (SKA) project Band 1. In this work, the number of the feed ports is reduced to 4 from the previous 8 for dual polarization using a novel geometry at the center. The design is carried out by optimizing with a social civilization algorithm. The resulting improvements include a reflection coefficient below , an aperture efficiency above 70% at the upper end of the band, a maximum cross-polar level under , and an ohmic loss about 0.05 dB. A prototype based on this design has been manufactured and the design simulations have been verified against measurements. A simulated sensitivity of the dual-reflector receiver system for the SKA project based on the measured data is also presented in this communication.
Autors: Yang, J.;Pantaleev, M.;Billade, B.;Ivashina, M.;Carozzi, T.;Helldner, L.;Dahlgren, M.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2015, volume: 63, issue:12, pages: 5955 - 5960
Publisher: IEEE
 
» A Compact Tri-Band Dual-Polarized Corner-Truncated Sectoral Patch Antenna
Abstract:
A coaxial probe-fed sector shaped patch antenna with the three corners truncated generates a triple band resonance by employing the higher order modes of the patch. A fourth sectoral indentation is used to tune the third band. The antenna is fabricated on an FR4 substrate of size and experimentally investigated. The resonances cover the UMTS (1.92–2.17 GHz), WiMAX (3.3–3.6 GHz), and the ISM 5.2 (5.1–5.3 GHz) bands with 10 dB return loss bandwidths of 11.2%, 5.14%, and 3.9%, respectively, and 3-dB axial ratio bandwidth of 5.8% in the first band. The polarization is circular in the UMTS band and linearly orthogonal in the other two bands. The frequency ratio of the two linearly polarized bands is tunable in the range 1.39–1.51. Area reductions of 6.6% in the patch and 64% in the ground plane with respect to the work on disc sector patch antenna by Hsu et al. are obtained.
Autors: Mathew, S.;Anitha, R.;Deepak, U.;Aanandan, C.K.;Mohanan, P.;Vasudevan, K.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2015, volume: 63, issue:12, pages: 5842 - 5845
Publisher: IEEE
 
» A Compact Wideband Circularly Polarized Antenna Array for -band Applications
Abstract:
In this letter, we present a compact single-layer microstrip antenna array for applications in the C-band. The device is designed and fabricated with an overall volume of 45 mm × 45 mm × 1.6 mm, (0.86 λ0 × 0.86 λ0 × 0.03 λ0 at a frequency of 5.75 GHz), a suitable dimension for compact handhelds. The proposed array is based on a modified sequential phase network, composed of nonuniform curved transmission lines, feeding a set of 2 × 2 disc based patch elements. The proposed network has space-filling properties, and is arranged in the unoccupied area between the elements, minimizing the overall dimensions without sacrificing the operating bandwidth. Adequate agreements between the simulated and measured results validate the proposed design: a 3-dB axial ratio band of 900 MHz, meaning 15.5%, a peak gain of 8.25 dB maintained within 3 dB for 1.2 GHz, and a very wide 10-dB return loss bandwidth of 29%. This performance is unmatched for the given dimensional constraint with a single-layer via-less technology .
Autors: Maddio, S.;
Appeared in: IEEE Antennas and Wireless Propagation Letters
Publication date: Dec 2015, volume: 14, issue: , pages: 1081 - 1084
Publisher: IEEE
 
» A Comparative Analytical Performance of F2DTC and PIDTC of Induction Motor Using DSPACE-1104
Abstract:
This paper presents fuzzy-2 direct torque control (F2DTC) and proportional-integral direct torque control (PIDTC) of an induction motor drive (IMD) using bus-clamped space vector modulation (BCSVM). The PIDTC gives considerable flux and torque ripples with the poor dynamic performance of the IMD. To improve the dynamic performance of IMD, F2DTC is proposed. In F2DTC, proportional-integral controllers are replaced by fuzzy-2 controllers (F2Cs), where the BCSVM duty ratios are independent of the sampling period. The firing strength of the inverter with F2DTC is improved than the PIDTC. In addition, the F2C effectively deals with the huge ambiguous data using Mamdani and Centroid methods with simple IF and THEN rules. A prototype controller is developed in the laboratory, and the control signals for both PIDTC and F2DTC are generated by the DSPACE DS-1104 controller. The F2DTC provides fewer ripples in flux and torque and less current total harmonic distortion than the PIDTC. Moreover, F2DTC has fast dynamic performance of the IMD as compared with PIDTC.
Autors: Venkataramana Naik, N.;Singh, S.P.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Dec 2015, volume: 62, issue:12, pages: 7350 - 7359
Publisher: IEEE
 
» A Competent Memetic Algorithm for Learning Fuzzy Cognitive Maps
Abstract:
Fuzzy cognitive maps (FCMs) form an important class of models for describing and simulating the behavior of dynamic systems through causal reasoning. Owing to their abilities to make the symbolic knowledge processing simple and transparent, FCMs have been successfully used to model the behavior of complex systems originating from numerous application areas, such as economy, politics, medicine, and engineering. However, the design of FCMs necessarily involves domain experts to develop a graph-based model composed of a collection of system's concepts and causal relationships among them. Consequently, since humans exhibit an intrinsic factor of subjectivity and are only able to efficiently develop small-size graph-based models, there is a legitimate need to devise methods capable of automatically learning FCM models from data. This research addresses this need by introducing a competent memetic algorithm to generate FCM models from available historical data, with no human intervention. Extensive benchmarking tests performed on both synthetic and real-world data quantify the performance of the competent memetic method and emphasize its suitability over the models obtained by conventional and noncompetent hybrid evolutionary approaches in terms of accuracy, approximation ability, and convergence speed. Moreover, the proposed approach is shown to be scalable due to its capability to efficiently learn high-dimensional FCM models.
Autors: Acampora, G.;Pedrycz, W.;Vitiello, A.;
Appeared in: IEEE Transactions on Fuzzy Systems
Publication date: Dec 2015, volume: 23, issue:6, pages: 2397 - 2411
Publisher: IEEE
 
» A Computational Approach Using Ratio Statistics for Identifying Housekeeping Genes from cDNA Microarray Data
Abstract:
We predict housekeeping genes from replicate microarray gene expression data of human lymphoblastoid cells and liver tissue with outliers removed using a scoring scheme, by an algorithm based on statistical hypothesis testing, assuming that such genes are constitutively expressed. A few predicted genes were examined and found to be housekeeping.
Autors: Sengupta, T.;Bhushan, M.;Wangikar, P.P.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Dec 2015, volume: 12, issue:6, pages: 1457 - 1463
Publisher: IEEE
 
» A Computationally Efficient Motion Primitive for Quadrocopter Trajectory Generation
Abstract:
A method is presented for the rapid generation and feasibility verification of motion primitives for quadrocopters and similar multirotor vehicles. The motion primitives are defined by the quadrocopter's initial state, the desired motion duration, and any combination of components of the quadrocopter's position, velocity, and acceleration at the motion's end. Closed-form solutions for the primitives are given, which minimize a cost function related to input aggressiveness. Computationally efficient tests are presented to allow for rapid feasibility verification. Conditions are given under which the existence of feasible primitives can be guaranteed a priori . The algorithm may be incorporated in a high-level trajectory generator, which can then rapidly search over a large number of motion primitives which would achieve some given high-level goal. It is shown that a million motion primitives may be evaluated and compared per second on a standard laptop computer. The motion primitive generation algorithm is experimentally demonstrated by tasking a quadrocopter with an attached net to catch a thrown ball, evaluating thousands of different possible motions to catch the ball.
Autors: Mueller, M.W.;Hehn, M.;DAndrea, R.;
Appeared in: IEEE Transactions on Robotics
Publication date: Dec 2015, volume: 31, issue:6, pages: 1294 - 1310
Publisher: IEEE
 
» A Computationally Efficient PM Power Loss Mapping for Brushless AC PM Machines With Surface-Mounted PM Rotor Construction
Abstract:
This paper describes a computationally efficient approach for mapping rotor power loss in permanent magnet (PM) machines. The PM loss mapping methodology discussed here utilizes a small number of time-step finite-element analyses (FEAs) to determine the parameters of a functional representation of loss variation with speed (frequency) and stator current and is intended for a rapid evaluation of machine performance over the entire torque-speed envelope. The research focus is placed on field-oriented-controlled brushless AC PM machines with surface-mounted PM rotor construction, although the method could be adapted for other rotor formats. The loss mapping procedure accounts for the axial segmentation of the PM array through the use of an equivalent electrical resistivity of the segmented PM array, which is obtained from three-dimensional (3-D) FEA. The PM loss can be accurately mapped across the full operational envelope, including the field-weakened mode, through a single 3-D and four two-dimensional time-step FEAs. The proposed methodology is validated on an 18-slot 16-pole surface-mounted brushless AC PM machine design. The loss mapping procedure results closely agree with the computationally demanding alternative of direct 3-D finite-element prediction of the PM power loss undertaken at each of the machine's operating points.
Autors: Xiaopeng Wu;Wrobel, R.;Mellor, P.H.;Chengning Zhang;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Dec 2015, volume: 62, issue:12, pages: 7391 - 7401
Publisher: IEEE
 
» A Constrained Variable Projection Reconstruction Method for Photoacoustic Computed Tomography Without Accurate Knowledge of Transducer Responses
Abstract:
Photoacoustic computed tomography (PACT) is an emerging computed imaging modality that exploits optical contrast and ultrasonic detection principles to form images of the absorbed optical energy density within tissue. When the imaging system employs conventional piezoelectric ultrasonic transducers, the ideal photoacoustic (PA) signals are degraded by the transducers' acousto-electric impulse responses (EIRs) during the measurement process. If unaccounted for, this can degrade the accuracy of the reconstructed image. In principle, the effect of the EIRs on the measured PA signals can be ameliorated via deconvolution; images can be reconstructed subsequently by application of a reconstruction method that assumes an idealized EIR. Alternatively, the effect of the EIR can be incorporated into an imaging model and implicitly compensated for during reconstruction. In either case, the efficacy of the correction can be limited by errors in the assumed EIRs. In this work, a joint optimization approach to PACT image reconstruction is proposed for mitigating errors in reconstructed images that are caused by use of an inaccurate EIR. The method exploits the bi-linear nature of the imaging model and seeks to refine the measured EIR during the process of reconstructing the sought-after absorbed optical energy density. Computer-simulation and experimental studies are conducted to investigate the numerical properties of the method and demonstrate its value for mitigating image distortions and enhancing the visibility of fine structures.
Autors: Sheng, Q.;Wang, K.;Matthews, T.P.;Xia, J.;Zhu, L.;Wang, L.V.;Anastasio, M.A.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Dec 2015, volume: 34, issue:12, pages: 2443 - 2458
Publisher: IEEE
 
» A Continuous-Time Sturdy-MASH Modulator in 28 nm CMOS
Abstract:
This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency.
Autors: Yoon, D.-Y.;Ho, S.;Lee, H.-S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2015, volume: 50, issue:12, pages: 2880 - 2890
Publisher: IEEE
 
» A Convergence and Asymptotic Analysis of the Generalized Symmetric FastICA Algorithm
Abstract:
This contribution deals with the FastICA algorithm in the domain of Independent Component Analysis (ICA). The focus is on the asymptotic behavior of the generalized symmetric variant of the algorithm. The latter has already been shown to possess the potential to achieve the Cramér-Rao Bound (CRB) by allowing the usage of different nonlinearity functions in its implementation. Although the FastICA algorithm along with its variants are among the most extensively studied methods in the domain of ICA, a rigorous study of the asymptotic distribution of the generalized symmetric FastICA algorithm is still missing. In fact, all the existing results exhibit certain limitations. Some ignores the impact of data standardization on the asymptotic statistics; others are only based on heuristic arguments. In this work, we aim at deriving general and rigorous results on the limiting distribution and the asymptotic statistics of the FastICA algorithm. We begin by showing that the generalized symmetric FastICA optimizes a function that is a sum of the contrast functions of traditional one-unit FastICA with a correction of the sign. Based on this characterization, we established the asymptotic normality and derived a closed-form analytic expression of the asymptotic covariance matrix of the generalized symmetric FastICA estimator using the method of estimating equation and M-estimator. Computer simulations are also provided, which support the theoretical results.
Autors: Tianwen Wei;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Dec 2015, volume: 63, issue:24, pages: 6445 - 6458
Publisher: IEEE
 
» A Cookbook for Building a High-Current Dimpled H Magnetron Source for Accelerators
Abstract:
A high-current (>50 mA) dimpled H magnetron source has been built at Fermilab for supplying H beam to the entire accelerator complex. Despite many decades of expertise with slit H magnetron sources at Fermilab, we were faced with many challenges from the dimpled H magnetron source, which needed to be overcome in order to make it operational. Dimpled H sources for high-energy physics are not new: Brookhaven National Laboratory has operated a dimpled H source for more than two decades. However, the transference of that experience to Fermilab took about two years because a cookbook for building this type of source did not exist and seemingly innocuous or undocumented choices had a huge impact on the success or failure for this type of source. Therefore, it is the goal of this paper to document the reasons for these choices and to present a cookbook for building and operating dimpled H magnetron sources.
Autors: Bollinger, D.S.;Karns, P.R.;Tan, C.;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Dec 2015, volume: 43, issue:12, pages: 4110 - 4122
Publisher: IEEE
 
» A Cooperative Co-Evolutionary Genetic Algorithm for Tree Scoring and Ancestral Genome Inference
Abstract:
Recent advances of technology have made it easy to obtain and compare whole genomes. Rearrangements of genomes through operations such as reversals and transpositions are rare events that enable researchers to reconstruct deep evolutionary history among species. Some of the popular methods need to search a large tree space for the best scored tree, thus it is desirable to have a fast and accurate method that can score a given tree efficiently. During the tree scoring procedure, the genomic structures of internal tree nodes are also provided, which provide important information for inferring ancestral genomes and for modeling the evolutionary processes. However, computing tree scores and ancestral genomes are very difficult and a lot of researchers have to rely on heuristic methods which have various disadvantages. In this paper, we describe the first genetic algorithm for tree scoring and ancestor inference, which uses a fitness function considering co-evolution, adopts different initial seeding methods to initialize the first population pool, and utilizes a sorting-based approach to realize evolution. Our extensive experiments show that compared with other existing algorithms, this new method is more accurate and can infer ancestral genomes that are much closer to the true ancestors.
Autors: Gao, N.;Zhang, Y.;Feng, B.;Tang, J.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Dec 2015, volume: 12, issue:6, pages: 1248 - 1254
Publisher: IEEE
 
» A Cooperative Coevolution Framework for Parallel Learning to Rank
Abstract:
We propose CCRank, the first parallel framework for learning to rank based on evolutionary algorithms (EA), aiming to significantly improve learning efficiency while maintaining accuracy. CCRank is based on cooperative coevolution (CC), a divide-and-conquer framework that has demonstrated high promise in function optimization for problems with large search space and complex structures. Moreover, CC naturally allows parallelization of sub-solutions to the decomposed sub-problems, which can substantially boost learning efficiency. With CCRank, we investigate parallel CC in the context of learning to rank. We implement CCRank with three EA-based learning to rank algorithms for demonstration. Extensive experiments on benchmark datasets in comparison with the state-of-the-art algorithms show the performance gains of CCRank in efficiency and accuracy.
Autors: Shuaiqiang Wang;Yun Wu;Gao, B.J.;Ke Wang;Lauw, H.W.;Jun Ma;
Appeared in: IEEE Transactions on Knowledge and Data Engineering
Publication date: Dec 2015, volume: 27, issue:12, pages: 3152 - 3165
Publisher: IEEE
 
» A Cooperative Demand Response Scheme Using Punishment Mechanism and Application to Industrial Refrigerated Warehouses
Abstract:
This paper proposes a cooperative demand response (CDR) scheme for load management in smart grid. The CDR scheme is formulated as a constrained optimization problem that generates a Pareto-optimal response strategy profile for consumers. Comparing with the noncooperative response strategy (i.e., Nash equilibrium) obtained from the one-shot demand management game, the Pareto-optimal response strategy reduces the electricity costs to the consumers. We further develop an incentive-compatible trigger-and-punishment mechanism to avoid the noncooperative behaviors of the selfish consumers. Furthermore, the CDR scheme is applied to achieve load management of industrial refrigerated warehouses. To implement the CDR scheme in large-scale systems, we group the refrigerated warehouses into clusters and utilize the CDR scheme within each cluster. Numerical results demonstrate that the CDR scheme can reduce the electricity costs, drop the electricity prices, and curtail the total energy consumption in comparison with the noncooperative demand response scheme.
Autors: Ma, K.;Hu, G.;Spanos, C.J.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Dec 2015, volume: 11, issue:6, pages: 1520 - 1531
Publisher: IEEE
 

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