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Electrical and Electronics Engineering publications abstract of: 12-2014 sorted by title, page: 0
» "Just Good Enough" Can Be Great [Editorial]
Abstract:
Autors: Martin, L.;
Appeared in: IEEE Potentials
Publication date: Dec 2014, volume: 33, issue:6, pages: 3 - 3
Publisher: IEEE
 
» “U-turn” feature in the efficiency-versus-current curve of GaInN/GaN light-emitting diodes
Abstract:
The onset of the efficiency droop in GaInN/GaN blue light-emitting diodes (LEDs), i.e., the maximum-efficiency point, typically occurs at current densities of 1–10 A/cm2 and the efficiency decreases monotonically beyond the onset. At typical operating current densities (10–100 A/cm2), LEDs are strongly affected by the droop. At cryogenic temperatures, an increase in the efficiency, i.e., a “U-turn” feature, is found in the droop regime of the efficiency-versus-current curve. The occurrence of the U-turn feature coincides with a distinct increase in device conductivity, which is attributed to an enhancement in p-type conductivity that in turn increases the injection efficiency.
Autors: Lin, Guan-Bo;Shan, Qifeng;Wang, Yaqi;Li, Ting;Schubert, E.Fred;
Appeared in: Applied Physics Letters
Publication date: Dec 2014, volume: 105, issue:22, pages: 221116 - 221116-4
Publisher: IEEE
 
» #FluxFlow: Visual Analysis of Anomalous Information Spreading on Social Media
Abstract:
We present FluxFlow, an interactive visual analysis system for revealing and analyzing anomalous information spreading in social media. Everyday, millions of messages are created, commented, and shared by people on social media websites, such as Twitter and Facebook. This provides valuable data for researchers and practitioners in many application domains, such as marketing, to inform decision-making. Distilling valuable social signals from the huge crowd's messages, however, is challenging, due to the heterogeneous and dynamic crowd behaviors. The challenge is rooted in data analysts' capability of discerning the anomalous information behaviors, such as the spreading of rumors or misinformation, from the rest that are more conventional patterns, such as popular topics and newsworthy events, in a timely fashion. FluxFlow incorporates advanced machine learning algorithms to detect anomalies, and offers a set of novel visualization designs for presenting the detected threads for deeper analysis. We evaluated FluxFlow with real datasets containing the Twitter feeds captured during significant events such as Hurricane Sandy. Through quantitative measurements of the algorithmic performance and qualitative interviews with domain experts, the results show that the back-end anomaly detection model is effective in identifying anomalous retweeting threads, and its front-end interactive visualizations are intuitive and useful for analysts to discover insights in data and comprehend the underlying analytical model.
Autors: Zhao, J.;Cao, N.;Wen, Z.;Song, Y.;Lin, Y.;Collins, C.;
Appeared in: IEEE Transactions on Visualization and Computer Graphics
Publication date: Dec 2014, volume: 20, issue:12, pages: 1773 - 1782
Publisher: IEEE
 
» (In,Mn)As multilayer quantum dot structures
Abstract:
(In,Mn)As multilayer quantum dots structures were grown by molecular beam epitaxy using a Mn selective doping of the central parts of quantum dots. The study of the structural and magneto-optical properties of the samples with three and five layers of (In,Mn)As quantum dots has shown that during the quantum dots assembly, the out-diffusion of Mn from the layers with (In,Mn)As quantum dots can occur resulting in the formation of the extended defects. To produce a high quality structures using the elaborated technique of selective doping, the number of (In,Mn)As quantum dot layers should not exceed three.
Autors: Bouravleuv, Alexei;Sapega, Victor;Nevedomskii, Vladimir;Khrebtov, Artem;Samsonenko, Yuriy;Cirlin, George;
Appeared in: Applied Physics Letters
Publication date: Dec 2014, volume: 105, issue:23, pages: 232101 - 232101-3
Publisher: IEEE
 
» 0.7–20-GHz Dual-Polarized Bilateral Tapered Slot Antenna for EMC Measurements
Abstract:
An asymmetric wideband dual-polarized bilateral tapered slot antenna (DBTSA) is proposed in this letter for wireless EMC measurements. The DBTSA is formed by two bilateral tapered slot antennas designed with low cross polarization. With careful design, the achieved DBTSA not only has a wide operating frequency band, but also maintains a single main-beam from 700 MHz to 20 GHz. This is a significant improvement compared to the conventional dual-polarized tapered slot antennas, which suffer from main-beam split in the high-frequency band. The innovative asymmetric configuration of the proposed DBTSA significantly reduces the field coupling between the two antenna elements, so that low cross polarization and high port isolation are obtained across the entire frequency range. All these intriguing characteristics make the proposed DBTSA a good candidate for a dual-polarized sensor antenna for wireless EMC measurements.
Autors: Lin, F.;Qi, Y.;Fan, J.;Jiao, Y.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Dec 2014, volume: 56, issue:6, pages: 1271 - 1275
Publisher: IEEE
 
» 0.88-THz Optical Clock Distribution on Adhesively Bonded Silicon Nanomembrane
Abstract:
Silicon photonics is a promising solution for on-chip optical clock distribution. We developed an adhesive bonding process to integrate silicon nanomembranes onto silicon chips. The single-mode strip waveguide fabricated on this adhesively bonded silicon membrane has a propagation loss of 4.3 dB/cm. A grating-coupled 1-to-32 H-tree optical distribution is experimentally demonstrated. Each branch includes 1.1-cm long strip waveguides, five Y-splitters, and three 90° bends. This optical distribution has a insertion loss of 13.9 dB, uniformity of 0.72 dB, and 3-dB bandwidth of 880 GHz determined by optical autocorrelation.
Autors: Zhang, Y.;Xu, X.;Kwong, D.;Covey, J.;Hosseini, A.;Chen, R.T.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2014, volume: 26, issue:23, pages: 2376 - 2379
Publisher: IEEE
 
» 1-, 1.5-, and 2-μm Fiber Lasers Q-Switched by a Broadband Few-Layer MoS2 Saturable Absorber
Abstract:
We propose and demonstrate 1, 1.5, and 2 μm passively Q-switched fiber lasers by exploiting a few-layer Molybdenum sulfide (MoS2) polymer composite as broadband saturable absorber (SA), respectively. The few-layer MoS2 nanosheets are prepared by the liquid-phase exfoliation method, and are composited with polyvinyl alcohol (PVA). The PVA-MoS2 film is sandwiched between two fiber ferrules to form the fiber-compatible SA. The few-layer MoS2 not only shows good transparency from ultraviolet to mid-infrared spectral region, but also possesses the nonlinear saturable absorption. The modulation depth and saturation optical intensity of the PVA-MoS2 film are measured to be 1.6% and 13 MW/cm2 at 1566 nm by the balanced twin-detector technique, respectively. By further inserting the filmy PVA-MoS2 SA into the cavities of Yb-, Er- and Tm-doped fiber lasers, we achieve stable Q-switching operations at 1.06, 1.56, and 2.03 μm, respectively. The output characteristics of the Q-switched pulses at the three wavelengths have been investigated, respectively. The MoS2-based Q-switching enables the large pulse energy of ∼1 μJ with a pulse width of 1.76 μs. This is, to the best of our knowledge, the first demonstration of MoS2 -based Q-switched fiber lasers in a wide wavelength range (from 1 to 2 μm). Our results experimentally confirm that the new-type 2-D material, few-layer MoS2, is a promising broadband SA to Q-switch fiber lasers covering all major wavelengths from near- to mid-infrared region.
Autors: Luo, Z.;Huang, Y.;Zhong, M.;Li, Y.;Wu, J.;Xu, B.;Xu, H.;Cai, Z.;Peng, J.;Weng, J.;
Appeared in: Journal of Lightwave Technology
Publication date: Dec 2014, volume: 32, issue:24, pages: 4077 - 4084
Publisher: IEEE
 
» 1150-nm Yb-Doped Fiber Laser Pumped Directly by Laser-Diode With an Output Power of 52 W
Abstract:
A high power, diode pumped, all-fiber Yb-doped fiber laser at 1150-nm wavelength by using conventional double clad fiber with output power of 52.6 W and slope efficiency up to 60% is realized. To the best of our knowledge, it is the highest power at this wavelength.
Autors: Miao, Y.;Zhang, H.;Xiao, H.;Zhou, P.;Liu, Z.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2014, volume: 26, issue:23, pages: 2327 - 2329
Publisher: IEEE
 
» 16-Wavelength DFB Laser Array With High Channel-Spacing Uniformity Based on Equivalent Phase-Shift Technique
Abstract:
The high accuracy of lasing wavelength spacing is one of the key requirements of a distributed feedback (DFB) semiconductor laser array. However, the nonuniformity of the wavelength spacing is increasingly deteriorating with the increase in the channel number in the laser array. In this paper, theoretical study was made to investigate the effects of sampling pattern deviation and seed grating, as well as waveguide dispersion on the wavelength-spacing uniformity for multiwavelength DFB semiconductor laser arrays (MLAs) fabricated using the reconstruction equivalent chirp (REC) technique. A simple measurement method of dispersion for DFB semiconductor lasers based on the REC technique is also proposed. With the dispersion compensation being included in the sampling period design and small deviation in the seed grating period being guaranteed, a high-channel-count (16-channel) DFB laser array with precise channel spacing of 0.7944 nm/channel (design value of 0.80 nm/channel) was achieved in our experiment. It shows excellent channel-spacing uniformity, and most wavelength residuals are within 0.10 nm.
Autors: Shi, Y.;Li, L.;Zheng, J.;Zhang, Y.;Qiu, B.;Chen, X.;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2014, volume: 6, issue:6, pages: 1 - 9
Publisher: IEEE
 
» 2-D Analytical Prediction of Eddy Currents, Circuit Model Parameters, and Steady-State Performances in Solid Rotor Induction Motors
Abstract:
This paper presents a 2-D analytical method in the complex domain for the computation of magnetic field distribution, eddy currents, circuit model parameters, and steady-state performances in solid rotor induction motors. The proposed static analytical model considers stator slotting with tooth-tips. The rotor motion is simulated by varying the slip. The analytical magnetic field distribution is computed in polar coordinates from 2-D subdomain method (i.e., based on the formal resolution of Maxwell’s equations applied in subdomain) in each region, i.e., semiclosed stator slots, air gap, solid rotor, and shaft. The electromagnetic torque is obtained from both the electrical equivalent circuit and Maxwell stress tensor that is given by the magnetic field distribution. Analytical results are validated by the static finite-element method.
Autors: Boughrara, K.;Dubas, F.;Ibtiouen, R.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Dec 2014, volume: 50, issue:12, pages: 1 - 14
Publisher: IEEE
 
» 2014 International Symposium on Computer Architecture Influential Paper Award; 2014 Maurice Wilkes Award Given to Ravi Rajwar
Abstract:
This column discusses two awards given in 2014: the International Symposium on Computer Architecture Influential Paper Award, which was given to the authors of the paper "PipeRench: A Coprocessor for Streaming Multimedia Acceleration," and the Maurice Wilkes Award, which was given to Ravi Rajwar.
Autors: Keckler, Stephen W.;Tullsen, Dean;
Appeared in: IEEE Micro
Publication date: Dec 2014, volume: 34, issue:6, pages: 95 - 97
Publisher: IEEE
 
» 220-GHz High-Efficiency InP HBT Power Amplifiers
Abstract:
Pub DtlThis paper reports on two power amplifier (PA) monolithic microwave integrated circuits (MMICs) operating at frequencies around 220 GHz. The PAs use 250-nm InP HBTs and thin-film microstrip technology formed with a benzocyclobutene dielectric. Both PAs utilize a two-emitter-finger HBT unit-cell with each finger having an emitter area of . The single-stage amplifier MMIC has six two-emitter HBTs in parallel for a total emitter area of . This amplifier has of small-signal gain from 210 to 230 GHz. It has demonstrated saturated output power of 90 mW at 210 and power-added efficiency (PAE) of 10%. This is the highest PAE number demonstrated at these frequencies. The two-stage PA uses three single-stage PAs, one as a driver and two in a balanced configuration in the second stage. The total output emitter area is . This PA demonstrated saturated output and PAE from 210 to 225 GHz.
Autors: Radisic, V.;Scott, D.W.;Cavus, A.;Monier, C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2014, volume: 62, issue:12, pages: 3001 - 3005
Publisher: IEEE
 
» 2D Prony-Huang Transform: A New Tool for 2D Spectral Analysis
Abstract:
This paper provides an extension of the 1D Hilbert Huang transform for the analysis of images using recent optimization techniques. The proposed method consists of: 1) adaptively decomposing an image into oscillating parts called intrinsic mode functions (IMFs) using a mode decomposition procedure and 2) providing a local spectral analysis of the obtained IMFs in order to get the local amplitudes, frequencies, and orientations. For the decomposition step, we propose two robust 2D mode decompositions based on nonsmooth convex optimization: 1) a genuine 2D approach, which constrains the local extrema of the IMFs and 2) a pseudo-2D approach, which separately constrains the extrema of lines, columns, and diagonals. The spectral analysis step is an optimization strategy based on Prony annihilation property and applied on small square patches of the IMFs. The resulting 2D Prony–Huang transform is validated on simulated and real data.
Autors: Schmitt, J.;Pustelnik, N.;Borgnat, P.;Flandrin, P.;Condat, L.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Dec 2014, volume: 23, issue:12, pages: 5233 - 5248
Publisher: IEEE
 
» 3-D Discrete Dispersion Relation, Numerical Stability, and Accuracy of the Hybrid FDTD Model for Cold Magnetized Toroidal Plasma
Abstract:
The finite-difference time-domain (FDTD) method in cylindrical coordinates is used to describe electromagnetic wave propagation in a cold magnetized plasma. This enables us to study curvature effects in toroidal plasma. We derive the discrete dispersion relation of this FDTD scheme and compare it with the exact solution. The accuracy analysis of the proposed method is presented. We also provide a stability proof for nonmagnetized uniform plasma, in which case the stability condition is the vacuum Courant condition. For magnetized cold plasma we investigate the stability condition numerically using the von Neumann method. We present some numerical examples which reproduce the dispersion relation, wave field structure and steady state condition for typical plasma modes.
Autors: Surkova, M.;Tierens, W.;Pavlenko, I.;Van Eester, D.;Van Oost, G.;De Zutter, D.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2014, volume: 62, issue:12, pages: 6307 - 6316
Publisher: IEEE
 
» 3-D Printing of Elements in Frequency Selective Arrays
Abstract:
3-D printing is a technology that enables the fabrication of complex objects directly from a digital model. Folding the elements of Frequency Selective arrays in three dimensions gives a significant reduction in the resonant frequency for a given cell dimension, and such structures are candidates for additive manufacture. The aim in this paper is to demonstrate by example the development of novel electromagnetic structures that could be fabricated in parallel and integral with the additive manufacture of buildings, for electromagnetic architecture control. The principle is illustrated with two new geometries based on dipole and loop elements. The cores of these structures were fabricated with a 3-D printer that uses a plaster-based material. Theoretical and experimental results confirm the operation of the surfaces within the UHF frequency band.
Autors: Sanz-Izquierdo, B.;Parker, E.A.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2014, volume: 62, issue:12, pages: 6060 - 6066
Publisher: IEEE
 
» 3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations
Abstract:
Process variation models for variation tolerant designs are developed through expensive silicon characterization. This paper presents a low-cost variation characterization method that takes advantage of correlations between test items. The proposed method is based on compressed sensing (CS), a new innovative theory in signal processing and information theory, and we formulate the problem of accounting for the correlations in the form of standard CS problems, allowing us to leverage advances in CS theory. We consider wafer-level measurement results for multiple test items a 3-D signal and propose the sparsifying transform that combines the 2-D discrete cosine transform and the Karhunen–Loéve transform. Our experimental results show that the proposed method reduces the number of samples required for the same accuracy up to 2X compared to virtual probe when two test items are used.
Autors: Chung, J.;Kim, Y.;Yang, J.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Dec 2014, volume: 33, issue:12, pages: 2005 - 2009
Publisher: IEEE
 
» 3-D Resistance Model for Phase-Change Memory Cell
Abstract:
In this paper, a 3-D resistance model is proposed for phase-change (PC) memory cell based on cell geometry and RESET current. Explicit expression is developed for PC radius in terms of RESET current, cell geometry, and material property. Conformal mappings are used for SET and RESET resistance calculation in 2-D models, which solve the problem of current crowding in structures with complex boundary condition. In the 3-D model development, additional spreading resistance is considered, together with the bulk resistance stemmed from 2-D model to form the eventual complete expression. Models show good consistency with finite element simulation and experimental data.
Autors: Chen, Y.;Kwong, K.C.;Lin, X.;Song, Z.;Chan, M.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2014, volume: 61, issue:12, pages: 4098 - 4104
Publisher: IEEE
 
» 3-D Ultrasound-Guided Robotic Needle Steering in Biological Tissue
Abstract:
Robotic needle steering systems have the potential to greatly improve medical interventions, but they require new methods for medical image guidance. Three-dimensional (3-D) ultrasound is a widely available, low-cost imaging modality that may be used to provide real-time feedback to needle steering robots. Unfortunately, the poor visibility of steerable needles in standard grayscale ultrasound makes automatic segmentation of the needles impractical. A new imaging approach is proposed, in which high-frequency vibration of a steerable needle makes it visible in ultrasound Doppler images. Experiments demonstrate that segmentation from this Doppler data is accurate to within 1–2 mm. An image-guided control algorithm that incorporates the segmentation data as feedback is also described. In experimental tests in ex vivo bovine liver tissue, a robotic needle steering system implementing this control scheme was able to consistently steer a needle tip to a simulated target with an average error of 1.57 mm. Implementation of 3-D ultrasound-guided needle steering in biological tissue represents a significant step toward the clinical application of robotic needle steering.
Autors: Adebar, T.K.;Fletcher, A.E.;Okamura, A.M.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Dec 2014, volume: 61, issue:12, pages: 2899 - 2910
Publisher: IEEE
 
» 3-MV compact very fast transient overvoltage generator for testing ultra-high-voltage gas-insulated switchgear
Abstract:
Gas-insulated switchgear (GIS) is widely used today in electrical power systems because of its reliability, compaction, long maintenance cycle, and small impact on the environment [1]. In its use the normal operation of the disconnector generates very fast transient overvoltages (VFTO) with frequencies ranging from 1 to 100 MHz [2] and amplitudes up to 2.5 p.u. [3]. For systems above 330 kV, the insulation strength of the GIS under VFTO is of concern as insulation failures caused by VFTO have exceeded those caused by lightning impulse (LI) [4]. This characteristic has attracted the attention of researchers worldwide and currently is a hot topic in the field of ultra-high-voltage (UHV) GIS insulation.
Autors: Wen, T.;Zhang, Q.;guo, c.;Liu, X.;Pang, L.;Zhao, J.;Yin, Y.;Shi, W.;Chen, W.;Tan, X.;
Appeared in: IEEE Electrical Insulation Magazine
Publication date: Dec 2014, volume: 30, issue:6, pages: 26 - 33
Publisher: IEEE
 
» 300-GHz InP HBT Oscillators Based on Common-Base Cross-Coupled Topology
Abstract:
Pub DtlTwo fundamental-mode oscillators operating around 300 GHz, a fixed-frequency oscillator and a voltage-controlled oscillator (VCO), have been developed in this work based on a 250-nm InP heterojunction bipolar transistor (HBT) technology. Both oscillators adopted the common-base configuration for the cross-coupled oscillator core, providing higher oscillation frequency compared to the conventional common-emitter cross-coupled topology. The fabricated fixed-frequency oscillator and the VCO exhibited oscillation frequency of 305.8 GHz and 298.1–316.1 GHz (18-GHz tuning range) at dc power dissipation of 87.4 and 88.1 mW, respectively. The phase noise of the fixed-frequency oscillator was measured to be at 10 MHz offset. The peak output power of 5.3 dBm (3.8% dc-to-RF efficiency) and 4.7 dBm (3.2% dc-to-RF efficiency) were respectively achieved for the two oscillators, which are the highest reported power for a transistor-based single oscillator beyond 200 GHz.
Autors: Yun, J.;Yoon, D.;Kim, H.;Rieh, J.-S.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2014, volume: 62, issue:12, pages: 3053 - 3064
Publisher: IEEE
 
» 3D Integrated Optical E-Field Sensor for Lightning Electromagnetic Impulse Measurement
Abstract:
A 3D lithium niobate integrated electro-optical electric field (E-field) sensor utilizing three optical waveguide Mach–Zehnder interferometers has been designed, fabricated, and characterized for the measurement of lightning electromagnetic impulse (EMP). The linear detected E-fields with the sensor are 15–370 kV/m. Experimental results demonstrate that the half wave E-fields of the 3D probe are all more than 4000 kV/m which means the maximal detectable E-field can be exceed 1000 kV/m. Based on the time domain response for applying the nanosecond EMP, the frequency response of the sensor has been calculated up to 500 MHz.
Autors: Zhang, J.;Chen, F.;Sun, B.;Chen, K.;Li, C.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2014, volume: 26, issue:23, pages: 2353 - 2356
Publisher: IEEE
 
» 3D parallel-detection microwave tomography for clinical breast imaging
Abstract:
A biomedical microwave tomography system with 3D-imaging capabilities has been constructed and translated to the clinic. Updates to the hardware and reconfiguration of the electronic-network layouts in a more compartmentalized construct have streamlined system packaging. Upgrades to the data acquisition and microwave components have increased data-acquisition speeds and improved system performance. By incorporating analog-to-digital boards that accommodate the linear amplification and dynamic-range coverage our system requires, a complete set of data (for a fixed array position at a single frequency) is now acquired in 5.8 s. Replacement of key components (e.g., switches and power dividers) by devices with improved operational bandwidths has enhanced system response over a wider frequency range. High-integrity, low-power signals are routinely measured down to −130 dBm for frequencies ranging from 500 to 2300 MHz. Adequate inter-channel isolation has been maintained, and a dynamic range >110 dB has been achieved for the full operating frequency range (500–2900 MHz). For our primary band of interest, the associated measurement deviations are less than 0.33% and 0.5° for signal amplitude and phase values, respectively. A modified monopole antenna array (composed of two interwoven eight-element sub-arrays), in conjunction with an updated motion-control system capable of independently moving the sub-arrays to various in-plane and cross-plane positions within the illumination chamber, has been configured in the new design for full volumetric data acquisition. Signal-to-noise ratios (SNRs) are more than adequate for all transmit/receive antenna pairs over the full frequency range and for the variety of in-plane and cross-plane configurations. For proximal receivers, in-plane SNRs greater than 80 dB are observed up to 2900 MHz, while cross-plane SNRs greater than 80 dB are seen for 6 cm sub-array spacing (for frequencies up to 1500 MHz). We demo- strate accurate recovery of 3D dielectric property distributions for breast-like phantoms with tumor inclusions utilizing both the in-plane and new cross-plane data.
Autors: Epstein, N.R.;Meaney, P.M.;Paulsen, K.D.;
Appeared in: Review of Scientific Instruments
Publication date: Dec 2014, volume: 85, issue:12, pages: 124704 - 124704-12
Publisher: IEEE
 
» 3D Planar Representation of Stereo Depth Images for 3DTV Applications
Abstract:
The depth modality of the multiview video plus depth (MVD) format is an active research area, whose main objective is to develop depth image based rendering friendly efficient compression methods. As a part of this research, a novel 3D planar-based depth representation is proposed. The planar approximation of multiple depth images are formulated as an energy-based co-segmentation problem by a Markov random field model. The energy terms of this problem are designed to mimic the rate-distortion tradeoff for a depth compression application. A novel algorithm is developed for practical utilization of the proposed planar approximations in stereo depth compression. The co-segmented regions are also represented as layered planar structures forming a novel single-reference MVD format. The ability of the proposed layered planar MVD representation in decoupling the texture and geometric distortions make it a promising approach. Proposed 3D planar depth compression approaches are compared against the state-of-the-art image/video coding standards by objective and visual evaluation and yielded competitive performance.
Autors: Ozkalayci, B.O.;Alatan, A.A.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Dec 2014, volume: 23, issue:12, pages: 5222 - 5232
Publisher: IEEE
 
» 5G wireless access: requirements and realization
Abstract:
5G, the mobile communication technology for beyond 2020, will provide access to information and the sharing of data anywhere and anytime for anyone and anything. This paper describes the current status of the processes moving toward 5G, or "IMT for 2020 and beyond," in ITU-R. We also provide a view of 5G opportunities, challenges, requirements and technical solutions.
Autors: Dahlman, E.;Mildh, G.;Parkvall, S.;Peisa, J.;Sachs, J.;Sel??n, Y.;Sk??ld, J.;
Appeared in: IEEE Communications Magazine
Publication date: Dec 2014, volume: 52, issue:12, pages: 42 - 47
Publisher: IEEE
 
» 5G wireless backhaul networks: challenges and research advances
Abstract:
5G networks are expected to achieve gigabit-level throughput in future cellular networks. However, it is a great challenge to treat 5G wireless backhaul traffic in an effective way. In this article, we analyze the wireless backhaul traffic in two typical network architectures adopting small cell and millimeter wave communication technologies. Furthermore, the energy efficiency of wireless backhaul networks is compared for different network architectures and frequency bands. Numerical comparison results provide some guidelines for deploying future 5G wireless backhaul networks in economical and highly energy-efficient ways.
Autors: Ge, X.;Cheng, H.;Guizani, M.;Han, T.;
Appeared in: IEEE Network
Publication date: Dec 2014, volume: 28, issue:6, pages: 6 - 11
Publisher: IEEE
 
» 650-GHz Resonant-Tunneling-Diode VCO With Wide Tuning Range Using Varactor Diode
Abstract:
We fabricated a wide-range varactor-tuned terahertz oscillator using a resonant tunneling diode (RTD). An AlAs/InGaAs double-barrier RTD and a varactor-diode mesa were integrated into a 20- m-long slot antenna. A wide tuning range of % (70 GHz) of the center frequency of 655 GHz was achieved by changing the depletion-layer capacitance of the varactor diode with a dc sweep from −4 to 0.5 V. The dependence of the output power on the varactor-diode bias was also measured. These experimental results agreed well with theory.
Autors: Kitagawa, S.;Suzuki, S.;Asada, M.;
Appeared in: IEEE Electron Device Letters
Publication date: Dec 2014, volume: 35, issue:12, pages: 1215 - 1217
Publisher: IEEE
 
» 6TiSCH: deterministic IP-enabled industrial internet (of things)
Abstract:
Industrial and IP-enabled low-power wireless networking technologies are converging, resulting in the Industrial Internet of Things. On the one hand, low-power wireless solutions are available today that answer the strict reliability and power consumption requirements of industrial applications. These solutions are based on Time- Synchronized Channel Hopping, a medium access control technique at the heart of industrial standards such as the WirelessHART and ISA100.11a, and layer 1 and 2 standards such as IEEE802.15.4e. On the other hand, a range of standards have been published to allow low-power wireless devices to communicate using the Internet Protocol (IP), thereby becoming true ???fingers of the Internet,??? and greatly simplifying their integration into existing networks. This article acknowledges the standardization effort to combine those capabilities. The networks resulting from this convergence exhibit reliability and power consumption performances compatible with demanding industrial applications, while being easy to integrate, and following the end-to-end paradigm of today???s Internet. In particular, this article presents the work being done in 6TiSCH, a newly-formed working group in the Internet Engineering Task Force, which is standardizing the mechanisms making the Industrial Internet of Things a reality.
Autors: Dujovne, D.;Watteyne, T.;Vilajosana, X.;Thubert, P.;
Appeared in: IEEE Communications Magazine
Publication date: Dec 2014, volume: 52, issue:12, pages: 36 - 41
Publisher: IEEE
 
» 802.11ec: Collision Avoidance Without Control Messages
Abstract:
In this paper, we design, implement, and evaluate 802.11ec (Encoded Control), an 802.11-based protocol without control messages: Instead, 802.11ec employs correlatable symbol sequences that, together with the timing the codes are transmitted, encode all control information and change the fundamental design properties of the MAC. The use of correlatable symbol sequences provides two key advantages: 1) efficiency, as it permits a near order of magnitude reduction of the control time; 2) robustness, because codes are short and easily detectable even at low signal-to-interference-plus-noise ratio (SINR) and even while a neighbor is transmitting data. We implement 802.11ec on a field programmable gate array (FPGA)-based software defined radio. We perform a large number of experiments and show that, compared to 802.11 (with and without RTS/CTS), 802.11ec achieves a vast efficiency gain in conveying control information and resolves key throughput and fairness problems in the presence of hidden terminals, asymmetric topologies, and general multihop topologies.
Autors: Magistretti, E.;Gurewitz, O.;Knightly, E.W.;
Appeared in: IEEE/ACM Transactions on Networking
Publication date: Dec 2014, volume: 22, issue:6, pages: 1845 - 1858
Publisher: IEEE
 
» Cupid: Cluster-Based Exploration of Geometry Generators with Parallel Coordinates and Radial Trees
Abstract:
Geometry generators are commonly used in video games and evaluation systems for computer vision to create geometric shapes such as terrains, vegetation or airplanes. The parameters of the generator are often sampled automatically which can lead to many similar or unwanted geometric shapes. In this paper, we propose a novel visual exploration approach that combines the abstract parameter space of the geometry generator with the resulting 3D shapes in a composite visualization. Similar geometric shapes are first grouped using hierarchical clustering and then nested within an illustrative parallel coordinates visualization. This helps the user to study the sensitivity of the generator with respect to its parameter space and to identify invalid parameter settings. Starting from a compact overview representation, the user can iteratively drill-down into local shape differences by clicking on the respective clusters. Additionally, a linked radial tree gives an overview of the cluster hierarchy and enables the user to manually split or merge clusters. We evaluate our approach by exploring the parameter space of a cup generator and provide feedback from domain experts.
Autors: Beham, M.;Herzner, W.;Groller, M.E.;Kehrer, J.;
Appeared in: IEEE Transactions on Visualization and Computer Graphics
Publication date: Dec 2014, volume: 20, issue:12, pages: 1693 - 1702
Publisher: IEEE
 
» TM-Score: A Misuseability Weight Measure for Textual Content
Abstract:
In recent years, data leakage prevention solutions became an inherent component of the organizations' security suite. These solutions focus mainly on the data and its sensitivity level, and on preventing it from reaching an unauthorized entity. They ignore, however, the fact that an insider is gradually exposed to more and more sensitive data to which she is authorized to access. Such data may cause great damage to the organization when leaked or misused. In this research, we propose an extension to the misuseability weight concept. Our main goal is to define a misuseability measure called TM-Score for textual data. Using this measure, the organization can estimate the extent of damage that can be caused by an insider that is continuously and gradually exposed to textual content (e.g., documents and emails). The extent of damage is determined by the amount, type, and quality of information to which the insider was exposed. We present a two-step method for the continuous assignment of a misuseability score to a set of documents and evaluate the proposed method using the Enron email data set.
Autors: Vartanian, A.;Shabtai, A.;
Appeared in: IEEE Transactions on Information Forensics and Security
Publication date: Dec 2014, volume: 9, issue:12, pages: 2205 - 2219
Publisher: IEEE
 
» A 0.002-mm 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver With 59.6% Horizontal Eye Opening Under 23.3-dB Channel Loss at Nyquist Frequency
Abstract:
This paper reports a full-rate direct decision-feedback-equalization (DFE) receiver with circuit techniques to widen the data eye opening with competitive power and area efficiencies. Specifically, a current-reuse active-inductor (AI) linear equalizer is merged into a clocked-one-tap DFE core for joint-elimination of pre-cursor and long-tail post-cursors. Unlike the passive-inductor designs that are bulky and untunable, the AI linear equalizer offers orthogonally tunable low- and high-frequency de-emphasis. The clocked-one-tap DFE resolves the first post-cursor via return-to-zero feedback data patterns for sharper data transition (i.e., horizontal eye opening), and is followed by a D-flip-flop slicer to maximize the data height (i.e., vertical eye opening). A 10-Gb/s DFE receiver was fabricated in 65-nm CMOS. Measured over an 84-cm printed circuit board differential trace with 23.3-dB channel loss at Nyquist frequency (5 GHz), the achieved figure-of-merit is 0.027 pJ/bit/dB (power consumption/date rate/channel loss). At 10 bit error rate under pseudorandom binary sequence, the horizontal and vertical eye opening are 59.6% and 189.3 mV, respectively. The die size is 0.002 mm .
Autors: Chen, Y.;Mak, P.-I.;Zhang, L.;Wang, Y.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2014, volume: 62, issue:12, pages: 3107 - 3117
Publisher: IEEE
 
» A 0.002-mm 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver With 59.6% Horizontal Eye Opening Under 23.3-dB Channel Loss at Nyquist Frequency
Abstract:
This paper reports a full-rate direct decision-feedback-equalization (DFE) receiver with circuit techniques to widen the data eye opening with competitive power and area efficiencies. Specifically, a current-reuse active-inductor (AI) linear equalizer is merged into a clocked-one-tap DFE core for joint-elimination of pre-cursor and long-tail post-cursors. Unlike the passive-inductor designs that are bulky and untunable, the AI linear equalizer offers orthogonally tunable low- and high-frequency de-emphasis. The clocked-one-tap DFE resolves the first post-cursor via return-to-zero feedback data patterns for sharper data transition (i.e., horizontal eye opening), and is followed by a D-flip-flop slicer to maximize the data height (i.e., vertical eye opening). A 10-Gb/s DFE receiver was fabricated in 65-nm CMOS. Measured over an 84-cm printed circuit board differential trace with 23.3-dB channel loss at Nyquist frequency (5 GHz), the achieved figure-of-merit is 0.027 pJ/bit/dB (power consumption/date rate/channel loss). At 10 bit error rate under pseudorandom binary sequence, the horizontal and vertical eye opening are 59.6% and 189.3 mV, respectively. The die size is 0.002 mm .
Autors: Chen, Y.;Mak, P.-I.;Zhang, L.;Wang, Y.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2014, volume: 62, issue:12, pages: 3107 - 3117
Publisher: IEEE
 
» A 0.25-to-2.25 GHz, 27 dBm IIP3, 16-Path Tunable Bandpass Filter
Abstract:
A fully-differential, 16-path bandpass filter (BPF) is demonstrated with wide tuning range, high linearity for and wideband harmonic rejection. The reconfigurable filter and clock generation circuitry is fabricated in IBM 45 nm CMOS SOI. To cover a tuning range of one decade (250 MHz to 2250 MHz), a 16-path scheme eliminates harmonic aliasing component to 15th harmonic of the local oscillator. The BPF has a 3 dB bandwidth greater than 20 MHz and 0.9 dB insertion loss. The BPF also achieves high linearity with an out-of-band and . The BPF tolerates blockers to 9 dBm 1 dB desensitization point (B1dB).
Autors: Luo, C.-K.;Buckwalter, J.F.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2014, volume: 24, issue:12, pages: 866 - 868
Publisher: IEEE
 
» A 0.53 THz Reconfigurable Source Module With Up to 1 mW Radiated Power for Diffuse Illumination in Terahertz Imaging Applications
Abstract:
This paper presents a high-power 0.53 THz source module with programmable diversity to adjust the brightness and the direction of light to obtain the desired diffuse lighting conditions in THz imaging applications. The source module consists of a single SiGe BiCMOS chip which operates an array of 16 source-pixel incoherently. Each source pixel consists of a primary on-chip ring-antenna and two triple-push oscillators locked 180° out-of-phase. The module provides a total radiated power of up to 1 mW (0 dBm) with 62.5 µW (–12 dBm) per source pixel on average and an EIRP per pixel of 25 dBm. The circuit layout is scalable in size and output power. The chip consumes up to 2.5 W from a 2.4 V supply and 3.2 mW from a digital 1.2 V supply respectively. The module includes a secondary silicon lens, is programmable through a CPLD, and supplied from a USB port. The THz radiation can be recorded with a CMOS 1 k-pixel THz video camera and represent an all silicon solution for real-time active THz imaging.
Autors: Pfeiffer, U.R.;Zhao, Y.;Grzyb, J.;Al Hadi, R.;Sarmah, N.;Forster, W.;Rucker, H.;Heinemann, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2938 - 2950
Publisher: IEEE
 
» A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration
Abstract:
This paper presents a time-interleaved (TI) SAR ADC which enables background timing skew calibration without a separate timing reference channel and enhances the conversion speed of each SAR channel. The proposed ADC incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the full-speed flash ADC does not suffer from timing skew errors, the flash ADC output is also used as a timing reference to estimate the timing skew of the TI SAR ADCs. A prototype ADC is designed and fabricated in a 65 nm CMOS process. After background timing skew calibration, 51.4 dB SNDR, 59.1 dB SFDR, and 1.0 LSB INL/DNL are achieved at 1 GS/s with a Nyquist rate input signal. The power consumption is 18.9 mW from a 1.0 V supply, which corresponds to 62.3 fJ/step FoM.
Autors: Lee, S.;Chandrakasan, A.P.;Lee, H.-S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2846 - 2856
Publisher: IEEE
 
» A 1.0 V, 10–22 GHz, 4 mW LNA Utilizing Weakly Saturated SiGe HBTs for Single-Chip, Low-Power, Remote Sensing Applications
Abstract:
A 1 V supply voltage, 10–22 GHz wideband low-power low noise amplifier (LNA) is implemented in a 0.13 SiGe BiCMOS technology, targeting portable single-chip remote sensing radar application. This LNA exhibits a measured gain of 15.5 dB at 16 GHz and a 3 dB bandwidth of 12 GHz, while dissipating only 4 mA from a 1 V supply, with intentionally biasing the HBTs in weak saturation. The LNA has a measured noise figure (NF) of 3.4 dB at 16 GHz and less than 4.4 dB across the operating bandwidth of 10 to 22 GHz. In addition, the LNA design offers a reduced bandwidth operational mode of 10–16 GHz for interference reduction, bringing the power consumption further down to only 3 mW.
Autors: Inanlou, F.;Coen, C.T.;Cressler, J.D.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2014, volume: 24, issue:12, pages: 890 - 892
Publisher: IEEE
 
» A 1.1 nW Energy-Harvesting System with 544 pW Quiescent Power for Next-Generation Implants
Abstract:
This paper presents a nW power management unit (PMU) for an autonomous wireless sensor that sustains itself by harvesting energy from the endocochlear potential (EP), the 70–100 mV electrochemical bio-potential inside the mammalian ear. Due to the anatomical constraints inside the inner ear, the total extractable power from the EP is limited close to 1.1–6.25 nW. A nW boost converter is used to increase the input voltage (30–55 mV) to a higher voltage (0.8–1.1 V) usable by CMOS circuits in the sensor. A pW charge pump circuit is used to minimize the leakage in the boost converter. Furthermore, ultralow-power control circuits consisting of digital implementations of input impedance adjustment circuits and zero current switching circuits along with Timer and Reference circuits keep the quiescent power of the PMU down to 544 pW. The designed boost converter achieves a peak power conversion efficiency of 56%. The PMU can sustain itself, and a duty-cyled ultralow-power load while extracting power from the EP of a live guinea pig. The PMU circuits have been implemented on a 0.18- CMOS process.
Autors: Bandyopadhyay, S.;Mercier, P.P.;Lysaght, A.C.;Stankovic, K.M.;Chandrakasan, A.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2812 - 2824
Publisher: IEEE
 
» A 1.2 nJ/bit 2.4 GHz Receiver With a Sliding-IF Phase-to-Digital Converter for Wireless Personal/Body Area Networks
Abstract:
This paper presents an ultra-low power 2.4 GHz FSK/PSK RX for wireless personal/body area networks. A single-channel phase-tracking RX based on a sliding-IF phase-to-digital conversion (SIF-PDC) loop is proposed to directly demodulate and digitize the frequency/phase-modulated information. The sliding-IF frequency plan reduces the power consumption of the multi-phase LO generation. A phase rotator is adopted in SIF-PDC to guarantee frequency stability, i.e., avoid the frequency pulling by interference or frequency drift. It equivalently transforms the RF signal processing from the I/Q amplitude domain to a digital-phase domain, which saves up to nearly 40% on power consumption and relaxes the digital baseband complexity. A phase-domain linear model of the proposed SIF-PDC is presented to analyze the frequency response. Fabricated in a 90 nm CMOS technology, the presented RX consumes 2.4 mW at 2 Mbps data rate, i.e., 1.2 nJ/b efficiency, and achieves a sensitivity of –92 dBm.
Autors: Liu, Y.-H.;Ba, A.;van den Heuvel, J.H.C.;Philips, K.;Dolmans, G.;de Groot, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 3005 - 3017
Publisher: IEEE
 
» A 1.5 mW 68 dB SNDR 80 Ms/s 2 Interleaved Pipelined SAR ADC in 28 nm CMOS
Abstract:
This paper presents a power-efficient 80 MS/s, 11 bit ENOB ADC. It is realized in 28 nm CMOS and is based on two interleaved pipelined SAR ADCs. It includes an on-chip reference generator and does not require any external components. The total power dissipation is 1.5 mW, resulting in a low-frequency Walden FOM of 9.1 fJ/conv-step and a low-frequency Schreier FOM of 172.2 dB, which is the largest FOM reported to date for sampling frequencies larger than 1 MS/s. The key aspects in achieving this excellent power efficiency include the choice of ADC architecture, integrator-based amplifiers used for noise filtering, the finite settling of the reference voltage during the SAR conversion, and the modified DAC switching scheme to reduce the DAC switching energy.
Autors: van der Goes, F.;Ward, C.M.;Astgimath, S.;Han Yan;Riley, J.;Zeng Zeng;Mulder, J.;Sijia Wang;Bult, K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2835 - 2845
Publisher: IEEE
 
» A 1.5-mW, 2.4 GHz Quasi-Circulator With High Transmitter-to-Receiver Isolation in CMOS Technology
Abstract:
A 2.4 GHz active quasi-circulator is implemented in TSMC CMOS technology. We propose a new architecture using current-reuse and adjustable signal cancellation to achieve a low-power, high-isolation and small-size circulator. The measured isolation from transmitter to receiver, , can be as high as 68 dB, which to our knowledge is the highest value ever reported in integrated circulators. Other isolations, such as receiver-to-transmitter, receiver-to-antenna, and antenna-to-transmitter isolations, are all better than 28 dB. The total power consumption is only 1.5 mW with a chip size of 820 m 750 m including bypass capacitors and pads.
Autors: Hsieh, J.-Y.;Wang, T.;Lu, S.-S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2014, volume: 24, issue:12, pages: 872 - 874
Publisher: IEEE
 
» A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE
Abstract:
A fully integrated envelope elimination and restoration (EER) CMOS power amplifier (PA) has been developed for WCDMA and LTE handsets. EER is a supply modulation technique that first divides modulated RF signal into envelope and phase signals and then restores it at a switching PA output. Supply voltage of the switching PA is modulated by the envelope signal through a high-speed supply modulator. EER PA is highly efficient due to the switching PA and the supply modulation. However, it generally has difficulty, especially for a wide bandwidth baseband application like LTE, achieving a wide bandwidth for phase signal path and highly accurate timing between envelope and phase signals. To overcome these challenges, an envelope/phase generator based on a mixer and a limiter was proposed to generate the wide bandwidth phase signal, and a timing aligner based on a delay locked loop with a variable high-pass filter (HPF) was proposed to compensate for the timing mismatch. The chip was implemented in 90 nm CMOS technology. Measured power-added efficiency (PAE) and adjacent channel leakage ratio (ACLR) were 39% and –41 dBc for WCDMA, and measured PAE and ACLR E-UTRA1 were 32% and –33 dBc for 20 MHz-BW LTE.
Autors: Oishi, K.;Yoshida, E.;Sakai, Y.;Takauchi, H.;Kawano, Y.;Shirai, N.;Kano, H.;Kudo, M.;Murakami, T.;Tamura, T.;Kawai, S.;Suto, K.;Yamazaki, H.;Mori, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2915 - 2924
Publisher: IEEE
 
» A 10 bit SAR ADC With Data-Dependent Energy Reduction Using LSB-First Successive Approximation
Abstract:
This paper presents a successive approximation (SA) algorithm called LSB-first SA and a corresponding 10 bit ADC implementation. The energy per conversion and number of bitcycles per conversion used by this algorithm both scale logarithmically with the activity of the input signal, such that an N-bit conversion uses between 2 and 2N+1 bitcycles, compared to N for conventional binary SA. This algorithm reduces ADC power consumption when sampling signals with low mean activity. The ADC is implemented in a 0.18 μm CMOS process. With a 0.6 V supply, the maximum sample rate, leakage power, and ENOB are 16 kHz, 0.58 nW, and 9.73 b, averaged over 10 test chips. The DNL and INL are bounded at 0.09 and 0.22 LSBs. Given a DC input, the ADC achieves its best-case FoM of 3.5 fJ/conversion-step. Given a fullscale Nyquist sinusoid input, the ADC has its worst-case FoM of 20 fJ/conversion-step. The supply voltage can be increased to 1.0 V to reach a sample rate of 450 kHz, or decreased to 0.5 V to achieve a 2.9–17 fJ/conversion-step FoM range.
Autors: Yaul, F.M.;Chandrakasan, A.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2825 - 2834
Publisher: IEEE
 
» A 10/30 MHz Fast Reference-Tracking Buck Converter With DDA-Based Type-III Compensator
Abstract:
A 10/30 MHz voltage-mode controlled buck converter with a wide duty-cycle range is presented. A high-accuracy delay-compensated ramp generator using only low-speed comparators but can work up to 70 MHz is proposed. By using a differential difference amplifier (DDA), a new Type-III compensator is proposed to reduce the chip area of the compensator by 60%. Moreover, based on the unique structure of the proposed compensator, an end-point prediction (EPP) scheme is also implemented to achieve fast reference-tracking responses. The converter was fabricated in a 0.13 m standard CMOS process. It achieves wide duty-cycle ranges of 0.75 and 0.59 when switching at 10 MHz and 30 MHz with peak efficiencies of 91.8% and 86.6%, respectively. The measured maximum output power is 3.6 W with 2.4 V output voltage and 1.5 A load current. With a constant load current of 500 mA, the up-tracking speeds for switching frequencies of 10 MHz and 30 MHz are 1.67 s/V and 0.67 s/V, respectively. The down-tracking speeds for 10 MHz and 30 MHz are 4.44 s/V and 1.56 s/V, respectively.
Autors: Cheng, L.;Liu, Y.;Ki, W.-H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2788 - 2799
Publisher: IEEE
 
» A 100-Gb/s Multiple-Input Multiple-Output Visible Laser Light Communication System
Abstract:
A 100-Gb/s multiple-input multiple-output (MIMO) visible laser light communication (VLLC) system employing vertical-cavity surface-emitting lasers with 16-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) modulating signals is proposed and experimentally demonstrated. The transmission capacity of systems is significantly increased by space-division-multiplexing scheme. With the aid of low-noise amplifier and equalizer at the receiving site, good bit error rate performance and clear constellation map are obtained for each optical channel. A system of eight 16-QAM-OFDM channels over 5-m free-space links with a total data rate of 100 Gb/s (12.5 Gb/s/channel × 8 channels) is successfully achieved. Such a proposed MIMO VLLC system is shown to be a prominent one not only presents its convenience in free-space optical communication, but also reveals its potential for the real implementation.
Autors: Chang, C.;Li, C.;Lu, H.;Lin, C.;Chen, J.;Wan, Z.;Cheng, C.;
Appeared in: Journal of Lightwave Technology
Publication date: Dec 2014, volume: 32, issue:24, pages: 4121 - 4127
Publisher: IEEE
 
» A 110–134-GHz SiGe Amplifier With Peak Output Power of 100–120 mW
Abstract:
Pub DtlThis paper presents a fully integrated eight-way power-combining amplifier for 110–134-GHz applications in an advanced 90-nm silicon–germanium HBT technology. The eight-way amplifier is implemented using four-stage common-emitter single-ended power amplifiers (PAs) as building blocks, and reactive impedance transformation networks are used for power combining. The single-ended PA breakout has a small-signal gain of 20 dB at 116 GHz, and saturation output power ( ) of 12.5–13.8 dBm at 114–130 GHz. The eight-way power-combining PA achieves a small-signal gain of 15 dB at 116 GHz, and of 20–20.8 dBm at 114–126 GHz with a power-added efficiency of 7.6%–6.3%. The eight-way amplifier occupies 4.95 (including pads) and consumes a maximum current of 980 mA from a 1.6-V supply. To our knowledge, this is the highest power silicon-based D-band amplifier to date.
Autors: Lin, H.-C.;Rebeiz, G.M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2014, volume: 62, issue:12, pages: 2990 - 3000
Publisher: IEEE
 
» A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration
Abstract:
We discuss a 14 bit 1 GS/s RF sampling pipelined ADC that utilizes correlation-based background calibration to correct the inter-stage gain, settling and memory errors. To improve the sampling linearity and RF sampling performance, the ADC employs input distortion cancellation and a digital background calibration technique to compensate for the non-linear charge injection (kick-back) from the sampling capacitors on the input driver. In addition, an effective dithering technique is embedded in the calibration signal to break the dependence of the calibration's convergence on the input signal amplitude. The ADC is fabricated on a 65 nm CMOS process and has an integrated input buffer. With a 140 MHz and 2 Vpp input signal, the SNR is 69 dB, the SFDR is 86 dB, and the power is 1.2 W.
Autors: Ali, A.M.A.;Dinc, H.;Bhoraskar, P.;Dillon, C.;Puckett, S.;Gray, B.;Speir, C.;Lanford, J.;Brunsilius, J.;Derounian, P.R.;Jeffries, B.;Mehta, U.;McShea, M.;Stop, R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2857 - 2867
Publisher: IEEE
 
» A 15 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB
Abstract:
A low power SAR logic-based resistive sensor readout circuit is proposed. A high sensitivity thermistor is used for local temperature measurements. The need for a low-noise front-end voltage amplifier is avoided by employing time-domain operation. In each operation step the sensor resistance is compared with the value of a reference resistive DAC which is implemented on chip. Therefore no stable, temperature compensated reference voltage is needed for operation. Furthermore the chip is operational with supply voltages ranging from 1.2 to 1.8 volts. Detailed analyses of the circuit gain and noise are provided. In addition, the effect of circuit topology on the noise performance is discussed. The effect of 1/f noise on accuracy of the circuit is also negligible due to resetting the charge-integrating capacitor after each comparison. A prototype chip is fabricated in 0.18- μm CMOS. The circuit dissipates 15 μW with 5.5 kS/s conversion rate from a 1.5 V supply. The complete interface circuit has 14 pJ/c-s figure of merit and 7.6 effective number of bits.
Autors: Ghanad, M.A.;Green, M.M.;Dehollain, C.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2014, volume: 61, issue:12, pages: 3321 - 3329
Publisher: IEEE
 
» A 15 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB
Abstract:
A low power SAR logic-based resistive sensor readout circuit is proposed. A high sensitivity thermistor is used for local temperature measurements. The need for a low-noise front-end voltage amplifier is avoided by employing time-domain operation. In each operation step the sensor resistance is compared with the value of a reference resistive DAC which is implemented on chip. Therefore no stable, temperature compensated reference voltage is needed for operation. Furthermore the chip is operational with supply voltages ranging from 1.2 to 1.8 volts. Detailed analyses of the circuit gain and noise are provided. In addition, the effect of circuit topology on the noise performance is discussed. The effect of noise on accuracy of the circuit is also negligible due to resetting the charge-integrating capacitor after each comparison. A prototype chip is fabricated in 0.18- CMOS. The circuit dissipates 15 with 5.5 kS/s conversion rate from a 1.5 V supply. The complete interface circuit has 14 pJ/c-s figure of merit and 7.6 effective number of bits.
Autors: Ghanad, M.A.;Green, M.M.;Dehollain, C.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2014, volume: 61, issue:12, pages: 3321 - 3329
Publisher: IEEE
 
» A 15–22 Gbps Serial Link in 28 nm CMOS With Direct DFE
Abstract:
A half-duplex serial link design that is capable of 22 Gbps operation over PCB channels with up to 20 dB of loss is presented. A current-mode transmitter can be configured either as a pre-cursor or post-cursor 2-tap FIR filter. The receiver consists of a trans-admittance-trans-impedance single-stage linear equalizer that can provide 10 dB of high-frequency gain without the use of peaking inductors. The CTLE is followed by an half-rate 2-tap decision feedback equalizer with direct feedback. To mitigate long-tail intersymbol interference in a power-efficient manner, a third DFE tap employs a single-pole IIR filter. A 15–22 GHz LC-PLL provides quadrature clocks to a 16-lane macro. The 16-lane macro occupies 1.66 mm 1.6 mm in a 28 nm CMOS process and is packaged in a 45 mm 45 mm flip-chip MCM module. The link operates from two power supplies at 1.35 V and 0.9 V with a BER and a power efficiency of 6.5 mW/Gbps at 20 Gbps.
Autors: Balan, V.;Oluwole, O.;Kodani, G.;Zhong, C.;Dadi, R.;Amin, A.;Ragab, A.;Lee, M.-J.E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 3104 - 3115
Publisher: IEEE
 
» A 160 Channel QAM Modulator With 4.6 Gsps 14 Bit DAC
Abstract:
Cable headend systems typically employ multiple QAM modulator signal chains to synthesize the entire TV spectrum for triple-play services resulting in high power, cost, and size. The digital up-converter (DUC) and DAC reported here can directly synthesize 160 DOCSIS 3.0 compliant 6-MHz QAM channels, spanning the entire downstream cable band of 43–1003 MHz. It thereby enables low-cost, low-power headend systems for new cable standards such as the converged cable access platform (CCAP) for triple/quad play services. The DUC (40 nm) and DAC (180 nm) die are co-packaged to form a complete system in package. The DAC offers high dynamic range at an update rate of 4.6 Gsps.
Autors: McMahill, D.R.;Hurta, D.S.;Brandt, B.;Wu, M.;Kalthoff, P.;Ostrem, G.S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2878 - 2890
Publisher: IEEE
 
» A 16TX/16RX 60 GHz 802.11ad Chipset With Single Coaxial Interface and Polarization Diversity
Abstract:
The IEEE 802.11ad standard supports PHY rates up to 6.7 Gbps on four 2 GHz-wide channels from 57 to 64 GHz. A 60 GHz system offers higher throughput than existing 802.11ac solutions but has several challenges for high-volume production including: integration in the host platform, automated test, and high link loss due to blockage and polarization mismatch. This paper presents a 802.11ad radio chipset capable of SC and OFDM modulation using a 16TX-16RX beamforming RF front-end, complete with an antenna array that supports polarization diversity. To aid low-cost integration in PC platforms, a single coaxial cable interface is used between chips. The chipset is capable of maintaining a link of 4.6 Gbps (PHY rate) at 10 m.
Autors: Boers, M.;Afshar, B.;Vassiliou, I.;Sarkar, S.;Nicolson, S.T.;Adabi, E.;Perumana, B.G.;Chalvatzis, T.;Kavvadias, S.;Sen, P.;Chan, W.L.;Yu, A.H.-T.;Parsa, A.;Nariman, M.;Yoon, S.;Besoli, A.G.;Kyriazidou, C.A.;Zochios, G.;Castaneda, J.A.;Sowlati, T.;Rof
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 3031 - 3045
Publisher: IEEE
 
» A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS
Abstract:
This paper presents a direct digital frequency synthesizer (DDFS) based on the nonlinear DAC with a maximum operating frequency of 2 GHz. This work proposes three design methods to enhance the performance of a DDFS. First, a multi-level momentarily activated bias is proposed to reduce power dissipation in the phase accumulator. Second, a coarse phase-based consecutive fine amplitude grouping scheme is presented to reduce hardware complexity and power consumption in the digital decoder. Third, the mixed-wave conversion topology in the nonlinear DAC is proposed to improve the output spectral purity. The DDFS with 9 bit amplitude resolution is capable of producing a minimum spurious-free dynamic range (SFDR) of 55.1 dBc up to Nyquist frequency at the clock frequency of 2 GHz. The prototype DDFS is fabricated in a 55-nm CMOS. It occupies an active area of 0.1 mm 2 with a total power dissipation of 130 mW. The figure of merit of this DDFS is 8944 GHz · 2 (SFDR/6) /W.
Autors: Yoo, T.;Yeoh, H.C.;Jung, Y.-H.;Cho, S.-J.;Kim, Y.S.;Kang, S.-M.;Baek, K.-H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2976 - 2989
Publisher: IEEE
 
» A 2-D Interpolation-Based QRD Processor With Partial Layer Mapping for MIMO-OFDM Systems
Abstract:
The rapid growth of wideband communication devices, such as smart phones and tablets, has dramatically increased the throughput requirements of communication systems. Multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) has been widely recognized as the potential technology to achieve this requirement. The main implementation bottleneck lies in the high-complexity MIMO detections for thousands of subcarrier symbols in the MIMO-OFDM receiver. The QR decomposition processor is an essential preprocessing module for many MIMO decoders because the QR decomposition helps improve the decoding efficiency significantly by providing the tree-search structure for the MIMO detection algorithms. This paper presents a low-complexity 2-D interpolation-based QR decomposition (2-D-IQRD) with a partial layer mapping scheme to reduce computational complexity. The proposed 2-D-IQRD processor also adopts a scaling technique to reduce the signal dynamic-range problem in the traditional IQRD algorithm. These proposed methods successfully address the limitation of the interpolation-based QRD processor caused by successive multiplications in layer mapping and inverse layer mapping. Therefore, the 2-D interpolation can greatly reduce complexity and improve the BER performance of fast-fading MIMO-OFDM systems. This paper designs and implements the proposed architecture using a 90-nm CMOS technology. The implementation results show that the proposed architecture achieves 45.6 MQRD/s.
Autors: Chai, L.;Chiu, P.;Huang, Y.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2014, volume: 22, issue:12, pages: 2689 - 2700
Publisher: IEEE
 
» A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS
Abstract:
This paper presents a 28 Gb/s multistandard SerDes macro which is fabricated in TSMC 28 nm CMOS process. The transimpedance amplifier (TIA) base analog front-end achieved 15 dB high-frequency boost with an on-chip compact passive inductor. The adaptation loop for the boost is decoupled from the decision feedback equalizer (DFE) adaptation by the use of a group delay algorithm. The DFE is a half-rate 1-tap unrolled design with only two total error latches for power and area reduction. A two-stage sense amplifier-based latch achieved sensitivity of 15 mV. The high-speed clock buffer uses a PMOS active inductor circuit with common-mode feedback to optimize the circuit performance. The transceiver achieves error-free operation at 28 Gbps with 34 dB channel loss, consumes the worst case power of 560 mW/lane, and fully complies with multiple standards and applications.
Autors: Kimura, H.;Aziz, P.M.;Jing, T.;Sinha, A.;Kotagiri, S.P.;Narayan, R.;Gao, H.;Jing, P.;Hom, G.;Liang, A.;Zhang, E.;Kadkol, A.;Kothari, R.;Chan, G.;Sun, Y.;Ge, B.;Zeng, J.;Ling, K.;Wang, M.C.;Malipatil, A.;Li, L.;Abel, C.;Zhong, F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 3091 - 3103
Publisher: IEEE
 
» A 2D Ray-Tracing Based Model for Micro- and Millimeter-Wave Propagation Through Vegetation
Abstract:
A novel two dimensional model to characterize the electromagnetic behavior of trees has been developed with the purpose of being used in ray-tracing based simulation platforms. This model uses various point scatterers with specific radiation characteristics to describe the effect of the trees present in the radiowave propagation path. The method to extract the parameters of the point scatterers from measurements is presented. The performance of this novel formulation is assessed in a tree formation scenario against measurements results obtained in a controlled environment, inside an anechoic chamber, at 20 and 62.4 GHz. Additionally, a comparison analysis with a discretized radiative energy transfer (dRET) approach is conducted, where a relatively good agreement has been found. The absence of readily plug-in models considering propagation through and/or around vegetation makes this new tool interesting for radio planning purposes.
Autors: Leonor, N.R.;Caldeirinha, R.F.S.;Fernandes, T.R.;Ferreira, D.;Sanchez, M.G.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2014, volume: 62, issue:12, pages: 6443 - 6453
Publisher: IEEE
 
» A 3.1 Gb/s 8 8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition
Abstract:
This paper presents the VLSI implementation of a lattice-reduction-aided (LRA) detection system. The proposed system includes a QR decomposition, lattice reduction (LR) processor, and sorting-reduced (SR) K-best detector for 8 8 multiple-input multiple-output (MIMO) systems. The bit error rate of the proposed MIMO detection system only incurs approximately 3 dB of implementation loss compared with optimal maximum likelihood detection with 64-quadratic-amplitude modulation. The proposed processor can also support different throughput requirements by adjusting the stage number of LR. The SR K-best detector can achieve 3.1 Gb/s throughput with 0.24-ns latency. The throughput of the system reaches 585 Mb/s if one channel preprocessing can support 72 symbol detections. The corresponding energy per bit is 63 pJ/bit, which is the smallest value achieved to date. This paper presents the first VLSI implementation of a complete LRA K-best detector with an 8 8 dimension.
Autors: Liao, C.;Wang, J.;Huang, Y.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2014, volume: 22, issue:12, pages: 2675 - 2688
Publisher: IEEE
 
» A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS
Abstract:
A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as 21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 .
Autors: Li, C.-H.;Ko, C.-L.;Kuo, C.-N.;Kuo, M.-C.;Chang, D.-C.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2014, volume: 24, issue:12, pages: 863 - 865
Publisher: IEEE
 
» A 38- to 40-GHz Current-Reused Active Phase Shifter Based on the Coupled Resonator
Abstract:
A 38- to 40-GHz current-reused active phase shifter based on a coupled resonator is proposed. The coupled resonator is used to increase the phase-shifting range and reduce the gain variation along with the phase-shifting value. The digital controlled artificial dielectric transmission lines are used instead of varactors to achieve high quality and directly digital control, and a current reuse technique is employed to reduce the power consumption. Implemented in 65-nm CMOS, the phase shifter occupies a chip area of 0.16 without pads and consumes a 6.6 mA current from a 1.0 V power supply. Measured results show that the gain variation of the phase shifter is less than 1 dB over 38–40 GHz while achieving the 90 phase-shifting range.
Autors: Jia, H.;Chi, B.;Kuang, L.;Wang, Z.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2014, volume: 61, issue:12, pages: 917 - 921
Publisher: IEEE
 
» A 3D-Based Pose Invariant Face Recognition at a Distance Framework
Abstract:
Face recognition in the wild can be defined as recognizing individuals unabated by pose, illumination, expression, and uncertainties from the image acquisition. In this paper, we propose a framework recognizing human faces under such uncertainties by focusing on the pose problem while considering the other factors together. The proposed work introduces an automatic front-end stereo-based system, which starts with image acquisition and ends by face recognition. Once an individual is detected by one of the stereo cameras, its facial features are identified using a facial features extraction model. These features are used to steer the second camera to see the same subject. Then, a stereo pair is captured and 3D face is reconstructed. The proposed stereo matching approach carefully handles illumination variance, occlusion, and disparity discontinuity. The reconstructed 3D shape is used to synthesize virtual 2D views in novel poses. All these steps are done off-line in an Enrollment stage. To recognize a face from a 2D image, which is captured under unknown environmental conditions, another fast on-line stage starts by facial features detection. Then, a facial signature is extracted from patches around these facial features. Finally, this probe image is matched against the closest synthesized images. Experiments are conducted on different public databases from where we investigate the effect of each component of the proposed framework on the recognition performance. The results confirm that without training and with automatic features extraction, our proposed face recognition at a distance approach outperforms most of the state-of-the-art approaches.
Autors: Ali, A.M.;
Appeared in: IEEE Transactions on Information Forensics and Security
Publication date: Dec 2014, volume: 9, issue:12, pages: 2158 - 2169
Publisher: IEEE
 
» A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS
Abstract:
This paper details the design of an 8-lane bidirectional link for both within-the-box and external communications in 22 nm CMOS technology. A low profile connector with a high density cable assembly ensure a data rate of up to 32 Gb/s per lane while maintaining channel loss below 25 dB. Channel equalization is performed by a combination of a 3-tap feed-forward equalizer (FFE), single-stage continuous-time linear equalizer (CTLE) and a 6-tap decision-feedback equalizer (DFE). Collaborative timing recovery is used to enable lane characterization without degrading jitter performance. Phase error decimation, with a conditional phase detection scheme, is used to reduce the DFE complexity by 50%. Power consumption over a wide range of data rates from 4 to 32 Gb/s is reduced by using regulated CMOS clocking with lane bundling, low swing transmitter with a source-series terminated (SST) driver and a highly reconfigurable receiver with an active inductor CTLE. At a lane data rate of 32 Gb/s, over a 0.5 m cable with 16 dB of loss, a transceiver lane consumes 205 mW from a 1.07 V supply. The power scales down to 26 mW from a 0.72 V supply at 8 Gb/s, when transmitting over a channel with 8 dB loss. The active silicon area per lane is 0.079 mm .
Autors: Musah, T.;Jaussi, J.;Balamurugan, G.;Hyvonen, S.;Hsueh, T.-C.;Keskin, G.;Shekhar, S.;Kennedy, J.;Sen, S.;Inti, R.;Mansuri, M.;Leddige, M.;Horine, B.;Roberts, C.;Mooney, R.;Casper, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 3079 - 3090
Publisher: IEEE
 
» A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
Abstract:
This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs boosted word-line (WL) for improving both read performance and write-ability. A ripple bit-line (RiBL) structure provides 30%–44% read access performance improvement and 2 –3.5 variation immunity at 0.7 V compared with the conventional hierarchical bit-line (HiBL) schemes. An adaptive data-aware write-assist (ADAWA) with VCS tracking is employed to further enhance the write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An adaptive voltage detector (AVD) with binary boosting control is used to mitigating gate electric over-stress. The design is implemented in UMC 40 nm low-power (40LP) CMOS technology. The 512 kb test chip operates from 1.5 V to 0.65 V, with maximum operation frequency of 800 MHz@1.1 V and 200 MHz@0.65 V. The measured power consumption is 0.5 mW/MHz (active) and 4.4 mW (standby) at 1.1 V, and 0.107 mW/MHz (active) and 0.367 mW (standby) at 0.65 V.
Autors: Lien, N.-C.;Chu, L.-W.;Chen, C.-H.;Yang, H.-I.;Tu, M.-H.;Kan, P.-S.;Hu, Y.-J.;Chuang, C.-T.;Jou, S.-J.;Hwang, W.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2014, volume: 61, issue:12, pages: 3416 - 3425
Publisher: IEEE
 
» A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination
Abstract:
A switched-diode termination (SDT) is proposed to implement a low-power transceiver circuit for on-chip single-ended signaling through a through-silicon via (TSV). The channel signal swing is limited to 40 mV by the SDT to reduce the transmitter (TX) power. An inverter-cascade amplifier is used to reduce the receiver (RX) power. The SDT consists of an nMOS diode and a pMOS diode, which are connected in a series between power rails through the RX input node. Only one of these two diodes is switched on depending on the RX output data, which eliminates the short-circuit current of the center-tap resistor termination. Inverter feedback is applied to the cascade amplifier of the RX to increase the bandwidth from 0.9 to 5.0 GHz. The transceiver in the 65-nm CMOS process combined with an emulated five-stack TSV on the same chip works at 8 Gb/s with 149 fJ/b/pF and a 1.2-V supply.
Autors: Yi, I.;Lee, S.;Bae, S.;Sohn, Y.;Choi, J.;Kim, B.;Sim, J.;Park, H.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2014, volume: 61, issue:12, pages: 987 - 991
Publisher: IEEE
 
» A 44–93- 250–400-mV 0.18- CMOS Starter for DC-Sourced Switched-Inductor Energy Harvesters
Abstract:
Although microsystems can replenish batteries and energize modules with ambient energy without having to store much energy on board, on-chip photovoltaic cells and thermoelectric generators generate 50–400 mV, which is usually not sufficiently high to operate transistors. Although stacking cells is possible, the tradeoff in power is ultimately unfavorable because small transducers output little power. Thankfully, transformers can boost millivolt voltages but not without a significant toll on space. Motion-propelled microelectromechanical system switches can also start a harvester but only in the presence of vibrations. Moreover, although 50–300-mV ring and oscillating networks can charge batteries, initialization requires 1–15 ms. The prototyped 0.18- CMOS oscillating starter presented here draws power from 250–450 mV to charge 100 pF to 0.32–1.55 V in 44–92 . In the steady state, the cost of the starter to the direct-current-sourced harvester it supports is only a 1.8% drop in the power conversion efficiency.
Autors: Blanco, A.A.;Rincon-Mora, G.A.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2014, volume: 61, issue:12, pages: 1002 - 1006
Publisher: IEEE
 
» A 5.8-GHz DSRC Transceiver With a 10- Interference-Aware Wake-Up Receiver for the Chinese ETCS
Abstract:
This paper presents a fully integrated 5.8-GHz dedicated short-range communication transceiver with a 10- interference-aware wake-up receiver (WuRx) for Chinese electronic toll collection system terminals that can operate with a low standby and operating current consumption. To reduce the current consumption, a high-gain RF envelope detector using a voltage-boosting method is proposed for both the WuRx and receiver (Rx) while the proposed high-power ASK modulator extends output dynamic range in low power consumption. Additionally, a delay-based bandpass filter is adopted in the WuRx to filter out interference from automotive applications, thus increasing the battery lifetime by reducing the probability of a false wake-up. The proposed transceiver is fabricated using 0.13- CMOS technology with a chip size of 2.8 for the target frequency range of 5.8 GHz. The measured results demonstrate sensitivities of 44 and 61 dBm for the WuRx and Rx, dissipating currents of 10 and 19 mA from 3.3-V supply voltage, respectively. The transmitter exhibits a normal output power of 5 dBm at an operating current of 46 mA.
Autors: Choi, J.;Lee, I.-Y.;Lee, K.;Yun, S.-O.;Kim, J.;Ko, J.;Yoon, G.;Lee, S.-G.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2014, volume: 62, issue:12, pages: 3146 - 3160
Publisher: IEEE
 
» A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI
Abstract:
A 20 GS/s 6b time-interleaved ADC is implemented in 32 nm CMOS SOI with an embedded time-to-digital converter to sense timing skew, and the randomness of process mismatch is exploited to compensate for the clock misalignment and dynamic offset errors of comparators that occur during high-speed operation. To achieve low-power consumption at high-speed operation with small-size transistors, a low-complexity on-chip calibration reduces gain, offset, and delay mismatches in background. With the timing skew calibration, the spurs due to clock misalignment are reduced by 20 dB. The proposed ADC achieves an SNDR of 30.7 dB at Nyquist frequency and consumes only 69.5 mW with a figure-of-merit of 124 J/conv-step.
Autors: Chen, V.H.-C.;Pileggi, L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2891 - 2901
Publisher: IEEE
 
» A 780 mW 4 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS
Abstract:
This paper describes a reconfigurable 4 × 28 Gb/s transceiver supporting 100 GbE/40 GbE standards. In each lane, the transmitter incorporates a 3-tap FIR with independent output phase adjustment, and the receiver has a half-rate CDR with a dedicated eye-monitor channel. There is a global resonant clock distribution network implemented using programmable distributed on-chip inductors. Implemented in a 40 nm CMOS process, the TX output measures 1.87 pspp DJ and 202 fsrms RJ. The RX jitter tolerance is 0.46 UIpp at 80 MHz with an input sensitivity of 27 mVpp-diff. The transceiver achieves BER on a channel with 20 dB loss at Nyquist, dissipating only 780 mW from a 0.9 V supply for all four lanes at 28 Gb/s operation.
Autors: Singh, U.;Garg, A.;Raghavan, B.;Huang, N.;Heng Zhang;Zhi Huang;Momtaz, A.;Jun Cao;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 3116 - 3129
Publisher: IEEE
 
» A 780 mW 4 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS
Abstract:
This paper describes a reconfigurable 4 28 Gb/s transceiver supporting 100 GbE/40 GbE standards. In each lane, the transmitter incorporates a 3-tap FIR with independent output phase adjustment, and the receiver has a half-rate CDR with a dedicated eye-monitor channel. There is a global resonant clock distribution network implemented using programmable distributed on-chip inductors. Implemented in a 40 nm CMOS process, the TX output measures and . The RX jitter tolerance is at 80 MHz with an input sensitivity of . The transceiver achieves BER on a channel with 20 dB loss at Nyquist, dissipating only 780 mW from a 0.9 V supply for all four lanes at 28 Gb/s operation.
Autors: Singh, U.;Garg, A.;Raghavan, B.;Huang, N.;Zhang, H.;Huang, Z.;Momtaz, A.;Cao, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 3116 - 3129
Publisher: IEEE
 
» A 79 GHz Phase-Modulated 4 GHz-BW CW Radar Transmitter in 28 nm CMOS
Abstract:
Millimeter-wave sensors perform robust and accurate remote motion sensing. We propose a 28 nm CMOS Radar TX that modulates a 79 GHz carrier with a 2 Gsps Pseudo-Noise sequence. The measured modulated output power at 79 GHz in 4 GHz BW is higher than 11 dBm (27 C), while the spurious emissions are below 20 dBc, fully satisfying the spectral mask regulations. The output RF BW where we can lock the injection-locked LO is 13 GHz. Overall, the TX draws 121 mW from a 0.9 V supply resulting in a record efficiency above 10%. More importantly, the TX is functional up to 125 C still providing more than 7 dBm output power over the same RF BW.
Autors: Giannini, V.;Guermandi, D.;Shi, Q.;Medra, A.;Van Thillo, W.;Bourdoux, A.;Wambacq, P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2925 - 2937
Publisher: IEEE
 
» A -Factor Enhanced Optoelectronic Oscillator for 40-Gbit/s Pulsed RZ-OOK Transmission
Abstract:
By using a Mach–Zehnder intensity modulator (MZM)-based -factor enhanced 40-GHz optoelectronic oscillator (OEO) loop, a self-starting pulsed encoder is demonstrated to generate 40-Gbit/s return-to-zero on–off-keying (RZ-OOK) data-stream. By nonlinearly driving the MZM with an OEO circuitry via a proper setting on the intra-loop delay, both the RF and optical output of the OEO at 40 GHz can be extracted to deliver the clock with a -factor of up to , and trigger the synthesizer-free 40-Gbit/s RZ-OOK data-stream. The maximal output power and the carrier-to-noise ratio of the RF output from the OEO are 20 dBm and 62 dB, respectively. Moreover, the single side-band phase noise is suppressed to 120 dBc/Hz at 100-kHz offset frequency by lengthening the single-mode fiber in the OEO loop up to 900 m. In addition, the pulsed RZ carrier with a pulsewidth of 10.5 ps provides a jitter as low as 120 fs and an on/off extinction ratio of 7.7 dB, which is particularly suitable for the RZ-OOK transmission at 40 Gbit/s. The back-to-back transmitted synthesizer-free 40-Gbit/s RZ-OOK data with a pattern length of reveals a receiving power sensitivity of 15.2 dBm at the requested bit error rate of .
Autors: Chi, Y.-C.;Lin, G.-R.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2014, volume: 62, issue:12, pages: 3216 - 3223
Publisher: IEEE
 
» A -Band Divide-by-Five Injection-Locked Frequency Divider Using a Near-Threshold VCO
Abstract:
This letter presents a divide-by-five injection-locked frequency divider (ILFD) using a near-threshold (NT) VCO. The input frequency is injected in the proposed ILFD by a VCO employing a noise-cancelling technique. Both the proposed ILFD and VCO are based on a single compact coil which consists of a distributed and center-tapped inductor for an enhanced ILFD locking range of 20.2 to 21.9 GHz without varactors. The proposed VCO and ILFD are fabricated in a 0.13 CMOS process and consume 0.3 and 0.55 mW, respectively, from a 0.45 V supply.
Autors: Jalalifar, M.;Byun, G.-S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2014, volume: 24, issue:12, pages: 881 - 883
Publisher: IEEE
 
» A -Factor Enhanced Optoelectronic Oscillator for 40-Gbit/s Pulsed RZ-OOK Transmission
Abstract:
By using a Mach–Zehnder intensity modulator (MZM)-based -factor enhanced 40-GHz optoelectronic oscillator (OEO) loop, a self-starting pulsed encoder is demonstrated to generate 40-Gbit/s return-to-zero on–off-keying (RZ-OOK) data-stream. By nonlinearly driving the MZM with an OEO circuitry via a proper setting on the intra-loop delay, both the RF and optical output of the OEO at 40 GHz can be extracted to deliver the clock with a -factor of up to , and trigger the synthesizer-free 40-Gbit/s RZ-OOK data-stream. The maximal output power and the carrier-to-noise ratio of the RF output from the OEO are 20 dBm and 62 dB, respectively. Moreover, the single side-band phase noise is suppressed to 120 dBc/Hz at 100-kHz offset frequency by lengthening the single-mode fiber in the OEO loop up to 900 m. In addition, the pulsed RZ carrier with a pulsewidth of 10.5 ps provides a jitter as low as 120 fs and an on/off extinction ratio of 7.7 dB, which is particularly suitable for the RZ-OOK transmission at 40 Gbit/s. The back-to-back transmitted synthesizer-free 40-Gbit/s RZ-OOK data with a pattern length of reveals a receiving power sensitivity of 15.2 dBm at the requested bit error rate of .
Autors: Chi, Y.-C.;Lin, G.-R.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2014, volume: 62, issue:12, pages: 3216 - 3223
Publisher: IEEE
 
» A -TDC-Based Beamforming Method for Vital Sign Detection Radar Systems
Abstract:
This brief describes a time-to-digital converter (TDC)-based digital-intensive beamforming method that is insensitive to analog delay mismatches. For vital sign detection, the proposed architecture can perform either vector summation (beamforming) or scalar summation (beamsumming) in the digital domain by simply weighting or removing the direct-current term for each channel, thus not requiring analog delay circuits. A prototype four-channel radar receiver that utilizes a digital phase tracking circuit and a 1-bit delta–sigma TDC is implemented in the 0.18- CMOS. The digital-intensive receiver consumes 33.2 mW/channel from a 1.8-V supply and successfully demonstrates spatial selectivity and signal-to-noise-ratio enhancement.
Autors: Chen, X.;Zhang, W.;Rhee, W.;Wang, Z.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2014, volume: 61, issue:12, pages: 932 - 936
Publisher: IEEE
 
» A Banzhaf Function for a Fuzzy Game
Abstract:
In this paper, another important solution for fuzzy games, called the Banzhaf function, is investigated. First, a simplified expression for the Banzhaf function for games with fuzzy coalition is proposed. The relationship between this simplified expression and two kinds of particular Banzhaf functions are discussed in detail. Furthermore, in the framework of games with fuzzy coalitions, we give a definition of the potential function of fuzzy games, and prove that the marginal values of the potential function are the components of the Banzhaf function. Furthermore, a new axiomatic characterization of the Banzhaf function for games with fuzzy coalitions is provided.
Autors: Tan, C.;Jiang, Z.-Z.;Chen, X.;Ip, W.H.;
Appeared in: IEEE Transactions on Fuzzy Systems
Publication date: Dec 2014, volume: 22, issue:6, pages: 1489 - 1502
Publisher: IEEE
 
» A Basic Protein Comparative Three-Dimensional Modeling Methodological Workflow Theory and Practice
Abstract:
When working with proteins and studying its properties, it is crucial to have access to the three-dimensional structure of the molecule. If experimentally solved structures are not available, comparative modeling techniques can be used to generate useful protein models to subsidize structure-based research projects. In recent years, with Bioinformatics becoming the basis for the study of protein structures, there is a crescent need for the exposure of details about the algorithms behind the softwares and servers, as well as a need for protocols to guide in silico predictive experiments. In this article, we explore different steps of the comparative modeling technique, such as template identification, sequence alignment, generation of candidate structures and quality assessment, its peculiarities and theoretical description. We then present a practical step-by-step workflow, to support the Biologist on the in silico generation of protein structures. Finally, we explore further steps on comparative modeling, presenting perspectives to the study of protein structures through Bioinformatics. We trust that this is a thorough guide for beginners that wish to work on the comparative modeling of proteins.
Autors: Bitar, M.;Franco, G.R.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Dec 2014, volume: 11, issue:6, pages: 1052 - 1065
Publisher: IEEE
 
» A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs
Abstract:
This paper proposes a built-in self-test (BIST) scheme with syndrome-compression ability for random access memories (RAMs) with static (SF) and dynamic faults (DFs). A March-element-based (MEB) compression scheme is proposed to reduce the volume of diagnostic data. The MEB compression scheme can efficiently compress the diagnostic data of a RAM tested by a March test for detecting SFs and DFs. Simulation results show that the compression ratio (the ratio of the number bits of the compressed diagnostic data to that of the original diagnostic data) is about 50.79% for an 8K -bit memory. The area overhead of the BIST with the MEB compressor is about 2.73% for an 8K -bit RAM using TSMC 0.18 cell library.
Autors: Hou, C.;Li, J.;Fu, T.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Dec 2014, volume: 33, issue:12, pages: 2020 - 2024
Publisher: IEEE
 
» A Bulk Queue Model for the Evaluation of Impact of Headway Variations and Passenger Waiting Behavior on Public Transit Performance
Abstract:
This paper demonstrates a model developed using the Markov chain technique, to ascertain the performance of public transit systems and examine the effects of stochastic variations in passenger arrival, waiting, boarding, and alighting behaviors on the regularity of headway along the route. The model addresses situations in which passengers abandon the system after a certain amount of waiting time. This accounts for the existence of a finite allowance of waiting time from the viewpoint of the passengers. The numerical examples included offer insights into factors that affect the reliability of public transit systems and presented analysis of the system performance measures such as mean counts of passengers served by transit systems, abandoned passengers, and unused space on vehicles. The impact of variability of departure headway on the utilization of public transit systems is illustrated. This model can be used as an analysis tool by transit planners to evaluate selection of system attributes.
Autors: Islam, M.K.;Vandebona, U.;Dixit, V.V.;Sharma, A.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Dec 2014, volume: 15, issue:6, pages: 2432 - 2442
Publisher: IEEE
 
» A Cantor multilayer traveling wave applicator for microwave heating: Numerical analysis and design
Abstract:
A traveling wave applicator particularly suitable for heating low loss materials is described. The applicator consists of a dielectric Cantor multilayer inserted in a single-mode rectangular metallic waveguide. Field localization phenomenon occurring in the multilayer allows high field amplitude (several times the amplitude of the incident field) to be obtained in a load placed at the center of the applicator. Design examples and numerical characterization of an applicator in WR-284 waveguide operating at 2.45 GHz are presented for cylindrical and planar loads. Results show that the proposed applicator can significantly enhance the effectiveness of the heating process.
Autors: Chiadini, F.;Diovisalvi, A.;Fiumara, V.;Scaglione, A.;
Appeared in: Journal of Applied Physics
Publication date: Dec 2014, volume: 116, issue:21, pages: 214503 - 214503-9
Publisher: IEEE
 
» A Cavity Green's Function Boundary Element Method With Spectral Domain Acceleration for Modeling of Reverberation Chambers
Abstract:
A novel boundary element method approach with the rectangular cavity Green's function is presented and utilized to model reverberation chambers. Different from all other approaches that employ rectangular cavity Green's functions, the computationally expensive part of the matrix-vector product is evaluated in the spectral domain. A drastic acceleration is achieved even though the algorithm operates with excellent accuracy. The approach is validated and compared against the boundary element method with free-space Green's function. Examples demonstrate the usability of the proposed approach.
Autors: Gruber, M.E.;Eibert, T.F.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Dec 2014, volume: 56, issue:6, pages: 1466 - 1473
Publisher: IEEE
 
» A Chiral Plasmonic Metasurface Circular Polarization Filter
Abstract:
Here, we demonstrate a proof of principle circular polarization filter based on a far-field interference effect using an array of pairs of simple nanoapertures. We demonstrate computationally and experimentally device performance which show good agreement and close to a 10% difference in transmission through the structure for left- and right-circularly polarized light. This ultracompact device could prove useful for remote sensing and advanced telecommunication applications.
Autors: Cadusch, J.J.;James, T.D.;Djalalian-Assl, A.;Davis, T.J.;Roberts, A.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2014, volume: 26, issue:23, pages: 2357 - 2360
Publisher: IEEE
 
» A Class of de Bruijn Sequences
Abstract:
In this paper, a class of linear feedback shift registers (LFSRs) with characteristic polynomial is discussed, where is a primitive polynomial of degree . The cycle structure and adjacency graphs of the LFSRs are determined. A new class of de Bruijn sequences is constructed from these LFSRs, and the number of de Bruijn sequences in the class is also considered. To illustrate the efficiency of constructing de Bruijn sequences from these LFSRs, an algorithm for producing some corresponding maximum-length nonlinear feedback shift registers with time and memory complexity is also proposed.
Autors: Li, C.;Zeng, X.;Li, C.;Helleseth, T.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Dec 2014, volume: 60, issue:12, pages: 7955 - 7969
Publisher: IEEE
 
» A Cluster-Based Distributed Active Current Sensing Circuit for Hardware Trojan Detection
Abstract:
The globalization of integrated circuits (ICs) design and fabrication has given rise to severe concerns on the devastating impact of subverted chip supply. Hardware Trojan (HT) is among the most dangerous threats to defend. The dormant circuit inserted stealthily into the chip by the advisory could steal the confidential information or paralyze the system connected to the subverted chip upon the HT activation. This paper presents a transient power supply current sensor to facilitate the screening of an IC for HT infection. Based on the power gating scheme, it converts the current activity on local power grid into a timing pulse from which the timing and power-related side channel signals can be externally monitored by the existing scan test architecture. Its current comparator threshold can be calibrated against the quiescent current noise floor to reduce the impacts of process variations. Postlayout statistical simulations of process variations are performed on the ISCAS’85 benchmark circuits to demonstrate the effectiveness of the proposed technique for the detection of delay-invariant and rarely switched HTs. Compared with the detection error rate of a 4-bit counter-based HT reported by an existing HT detection method using the path delay fingerprint, our method shows an order of magnitude improvement in the detection accuracy.
Autors: Cao, Y.;Chang, C.;Chen, S.;
Appeared in: IEEE Transactions on Information Forensics and Security
Publication date: Dec 2014, volume: 9, issue:12, pages: 2220 - 2231
Publisher: IEEE
 
» A Collaborative Fuzzy Clustering Algorithm in Distributed Network Environments
Abstract:
Due to privacy and security requirements or technical constraints, traditional centralized approaches to data clustering in a large dynamic distributed peer-to-peer network are difficult to perform. In this paper, a novel collaborative fuzzy clustering algorithm is proposed, in which the centralized clustering solution is approximated by performing distributed clustering at each peer with the collaboration of other peers. The required communication links are established at the level of cluster prototype and attribute weight. The information exchange only exists between topological neighboring peers. The attribute-weight-entropy regularization technique is applied in the distributed clustering method to achieve an ideal distribution of attribute weights, which ensures good clustering results. And the important features are successfully extracted for the high-dimensional data clustering. The kernelization of the proposed algorithm is also realized as a practical tool for clustering the data with “nonspherical”-shaped clusters. Experiments on synthetic and real-world datasets have demonstrated the efficiency and superiority of the proposed algorithms.
Autors: Zhou, J.;Philip Chen, C.L.;Chen, L.;Li, H.-X.;
Appeared in: IEEE Transactions on Fuzzy Systems
Publication date: Dec 2014, volume: 22, issue:6, pages: 1443 - 1456
Publisher: IEEE
 
» A Compact Circularly Polarized Slotted Patch Antenna for GNSS Applications
Abstract:
A compact circularly polarized (CP) square-ring slotted patch antenna with vias is proposed for global navigation satellite systems (GNSS). Four square-ring-shaped slots are cut symmetrically onto a square patch radiator along its diagonals for wide-angle CP radiation and miniaturization. The antenna size is further reduced by grounding the central patches surrounded by the square-ring-shaped slots. An antenna prototype with an overall size of 60 mm 60 mm 5 mm shows a measured 10-dB return loss bandwidth of 90.0 MHz (1.565–1.655 GHz) with a maximum gain of 4.65 dBic. The measured 3-dB axial ratio (AR) bandwidth is 35.0 MHz (1.57–1.605 GHz) with a 3-dB AR beamwidth of more than 140 across the bandwidth.
Autors: Nasimuddin;Qing, X.;Chen, Z.N.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2014, volume: 62, issue:12, pages: 6506 - 6509
Publisher: IEEE
 
» A Compact Current–Voltage Model for 2D Semiconductor Based Field-Effect Transistors Considering Interface Traps, Mobility Degradation, and Inefficient Doping Effect
Abstract:
This paper presents an analytical current–voltage model specifically formulated for 2-dimensional (2D) transition metal dichalcogenide (TMD) semiconductor based field-effect transistors (FETs). The model is derived from the fundamentals considering the physics of 2D TMD crystals, and covers all regions of the FET operation (linear, saturation, and subthreshold) under a continuous function. Moreover, three issues of great importance in the emerging 2D FET arena: interface traps, mobility degradation, and inefficient doping have been carefully considered. The compact models are verified against 2-D device simulations as well as experimental results for state-of-the-art top-gated monolayer TMD FETs, and can be easily employed for efficient exploration of circuits based on 2D FETs as well as for evaluation and optimization of 2D TMD-channel FET design and performance.
Autors: Cao, W.;Kang, J.;Liu, W.;Banerjee, K.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2014, volume: 61, issue:12, pages: 4282 - 4290
Publisher: IEEE
 
» A Compact Dipole Antenna for DTV Applications by Utilizing L-Shaped Stub and Coupling Strip
Abstract:
In this study, a small dipole antenna for digital television (DTV) reception band (470–862 MHz) is developed. The antenna is composed of a pair of bent dipoles, which are coupling fed by a coaxial cable. The resultant antenna has compact size of . Two parasitically coupling strips are added to excite one additional resonance mode. Bent dipole antennas and feeding structures are fabricated on the different planes of the substrate to embed two L-shaped stubs, thus resulting in improvement of the impedance matching condition. After careful optimization of the geometrical parameters of the antenna, the resonances are merged and thus, a wide impedance bandwidth is obtained. The measured 6-dB bandwidth of the antenna in free space is 615 MHz (80.4%).
Autors: Wang, C.-J.;Lee, Y.-L.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2014, volume: 62, issue:12, pages: 6515 - 6519
Publisher: IEEE
 
» A Comparative Study of Radiation-Tolerant Fiber Optic Sensors for Relative Humidity Monitoring in High-Radiation Environments at CERN
Abstract:
In this paper, we report a comparative study of fiber optic sensors for applications of relative humidity (RH) monitoring in high-radiation environments. In particular, we present investigations carried out since 2011 by our multidisciplinary research group, in collaboration with the European Organization for Nuclear Research (CERN) in Geneva. Our research has been first focused on the development of polyimide-coated fiber Bragg grating (FBG) sensors, and recently, it has been extended to nanoscale metal oxide-coated long-period gratings (LPGs). Experimental tests in the [0–70] %RH range at different temperatures, before and after -ionizing radiation exposures, have been carried out to assess the sensors' performances in conditions required in experiments running at CERN. The advantages and disadvantages of the two proposed technologies are discussed in this paper in light of their possible application in high-energy physics environments. In particular, reported results suggest that LPG-based sensors can be preferred in some applications (particularly in presence of very low humidity levels) mainly because they are able to provide very high RH sensitivity (up to 1.4 nm/%RH), which is up to three orders of magnitude higher than that exhibited by FBG-based hygrometers. On the other side, compared with FBGs, LPGs are more difficult to multiplex due to limitations in terms of available bandwidth.
Autors: Berruti, G.;Consales, M.;Borriello, A.;Giordano, M.;Buontempo, S.;Makovec, A.;Breglio, G.;Petagna, P.;Cusano, A.;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2014, volume: 6, issue:6, pages: 1 - 15
Publisher: IEEE
 
» A Comparison of Algorithms for Detecting Synchronous Digital Devices Using Their Unintended Electromagnetic Emissions
Abstract:
Electronically initiated explosives can have unintended electromagnetic emissions, which propagate through walls and unshielded containers. These emissions, if properly characterized, can be used to quickly detect explosive threats. In this paper, an analytic model is developed for the unintended emissions of clocked digital devices, such as microcontrollers, which can be used as initiators. It is demonstrated that these emissions are clock-dependent, periodic train of impulses. An autoregressive model of these clock emissions is developed, and the model is validated using measurements of an 8051 microcontroller. Existing algorithms, including pitch-estimation and the epoch-folding algorithm, are surveyed for detecting generic digital devices with unknown clock frequencies and emissions characteristics. A novel detection algorithm, which uses pitch estimation, is proposed. The model is used, in a simulated environment, to evaluate the noise performance of the proposed algorithms. Results indicate that the pitch-estimation techniques are robust against jitter and have a 4-dB sensitivity improvement over epoch-folding algorithms.
Autors: Stagner, C.;Beetner, D.G.;Grant, S.L.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Dec 2014, volume: 56, issue:6, pages: 1304 - 1312
Publisher: IEEE
 
» A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology
Abstract:
In this paper, we present for the first time a direct measurement procedure to characterize the bias temperature instability (BTI)-induced dynamic variability in static random access memory (SRAM) cells. This measurement procedure is based on the supply read retention voltage metric. The variability results obtained with this technique are explained by means of Monte Carlo SPICE simulations. The analytical model is then proposed to extrapolate this BTI-induced variability at different stress conditions. Finally, the impact of this variability on a large SRAM array is investigated. A semianalytical method is first developed to calculate the fresh read failure probability for different operating voltages . The model is then extended to address the effect of BTI stress on the SRAM array. Results show that under SRAM cells operating conditions the bitcell read stability is barely impacted by BTI stress even after 10 years of work.
Autors: El Husseini, J.;Garros, X.;Cluzel, J.;Subirats, A.;Makosiej, A.;Weber, O.;Thomas, O.;Huard, V.;Federspiel, X.;Reimbold, G.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2014, volume: 61, issue:12, pages: 3991 - 3999
Publisher: IEEE
 
» A Complex Network Approach to Topology Control Problem in Underwater Acoustic Sensor Networks
Abstract:
Underwater acoustic sensor networks (UASNs) have been developed for a set of underwater applications, including resource exploration, pollution monitoring, and tactical surveillance. Topology control techniques of UASNs are significantly different from those of terrestrial wireless sensor networks, due to the properties of underwater environments and acoustic communications. This research begins with a scale-free network model for calculating edge probability, which is used to generate initial topology randomly. Subsequently, a topology control strategy based on complex network theory (TCSCN) is put forward to construct a double clustering structure, where there are two kinds of cluster-heads to ensure connectivity and coverage, respectively. The performance of TCSCN is analyzed through simulation experiments that indicate a well-constructed topology, where (1, )-Coverage and (1, )-Connectivity can be achieved while optimizing energy consumption and propagation delay as much as possible.
Autors: Liu, L.;Liu, Y.;Zhang, N.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Dec 2014, volume: 25, issue:12, pages: 3046 - 3055
Publisher: IEEE
 
» A Computational Model of the Hybrid Bio-Machine MPMS for Ratbots Navigation
Abstract:
As a typical cyborg intelligent system, ratbots possess not only their own biological brain but machine visual sensation, memory, and computation. Electrodes implanted in the medial forebrain bundle (MFB) connect the rat's biological brain with the computer, which presents a hybrid bio-machine parallel memory system in the ratbot. For the novel multiple parallel memory system (MPMS) with real-time MFB stimuli, a computational model is proposed to explain the learning and memory processes underlying the enhanced performance of the ratbots in maze navigation tasks. It's shown that the proposed computational model can predict the finish trial number of the maze learning task, which matches well with behavioral experiments. This work will be helpful to understand the memory and learning mechanisms of cyborg intelligent systems and has the potential significance of optimizing the cognitive performance of these systems as well.
Autors: Su, Lijuan;Zhang, Nenggan;Yao, Min;Wu, Zhaohui;
Appeared in: IEEE Intelligent Systems
Publication date: Dec 2014, volume: 29, issue:6, pages: 5 - 13
Publisher: IEEE
 
» A Context-Aware M2M-Based Middleware for Service Selection in Mobile Ad-Hoc Networks
Abstract:
This paper proposes a novel middleware for service selection in mobile ad-hoc networks with a particular focus on scenarios immediately and subsequently afterwards an emergency. The proposed middleware, operating on a mobile user’s hand-held device and collecting the user’s contexts through machine-to-machine connectivity, has three major contributions as compared to the current literature. The middleware, based on the collected contexts, firstly classifies a service request, e.g., safety-related or comfort service. Then, it initiates the required network connectivity for service discovery, i.e., the ad-hoc connectivity when an infrastructure-based network is inaccessible. Finally, the middleware selects the service based on a method specifically proposed for that service category, including pre-defined realistic user contexts, to access it. The simulation results show that the middleware achieves up to 12 percent higher success rate compared to the minimum hop count service selection method. Compared with the same method, it has a response time up to 50 percent lower for the safety-related but 80 percent higher for the comfort services. Yet, the middleware attains up to 96 percent user satisfaction rate for both service classes.
Autors: Surobhi, N.A.;Jamalipour, A.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Dec 2014, volume: 25, issue:12, pages: 3056 - 3065
Publisher: IEEE
 
» A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS
Abstract:
We present design and measurement details for a 0–3 multi-stage noise-shaping (MASH) ADC that achieves a dynamic range of 88 dB over 53 MHz signal bandwidth. The ADC utilizes a zeroth-order front-end, i.e., a 17-level flash ADC, to perform a coarse quantization and a third-order 7-level continuous-time ΔΣ back-end to digitize the residue error of the front-end. The ADC achieves the high thermal noise power efficiency of a continuous-time feedforward ΔΣ modulator and the flat signal transfer function of a flash ADC. The test chip, implemented in a 28 nm CMOS process, clocks at 3.2 GHz. The average noise spectral density with small input signals is –167 dBFS/Hz and the dynamic range is 88 dB. The test chip ADC consumes a total power of 235 mW from triple power supplies of 0.9/1.8/–1.0 V. The thermal-noise figure-of-merit, defined as FOM = DR + 10log 10 (BW/P) is 171.6 dB.
Autors: Dong, Y.;Yang, W.;Schreier, R.;Sheikholeslami, A.;Korrapati, S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2014, volume: 49, issue:12, pages: 2868 - 2877
Publisher: IEEE
 
» A Correction to Algorithm A2 in “Asynchronous Distributed Averaging on Communication Networks”
Abstract:
This paper discusses Algorithm A2 in “Asynchronous Distributed Averaging on Communication Networks” (IEEE Trans. Netw., vol. 15, no. 3, pp. 512–520, Jun. 2007), which claims to solve the distributed averaging problem provided that the parameters to the algorithm meet certain constraints. Specifically, the states of each node in the network are claimed to converge to the average of the initial values associated with the nodes under these constraints. This paper points out a flaw in the proof of the algorithm and in addition provides a specific example of a network, satisfying the assumptions, for which the algorithm does not converge.
Autors: Kriegleder, M.;
Appeared in: IEEE/ACM Transactions on Networking
Publication date: Dec 2014, volume: 22, issue:6, pages: 2026 - 2027
Publisher: IEEE
 
» A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking
Abstract:
Interpolation is an important and distinguished method popularly applied to recent synthesis and verification research topics. Existing approaches generate interpolants by analyzing unsatisfiability (UNSAT) proofs from satisfiable (SAT) solvers. Unfortunately, the interpolant is predestinedly determined by how the UNSAT proof is logged. This particularly weakens the abstraction of interpolation-based model checking procedure. In this paper, a new approach to generate a variety of functionally different interpolants using simulation and SAT solving is proposed. We further seamlessly integrated the novel interpolant generation algorithm into a reinterpreted interpolation-based model checking procedure. Moreover, spurious counterexamples from the model checker further guide the generation of interpolants to refute excessive refinements. As an extra benefit, proof logging is not required for SAT solvers. Experiments show promising results of our interpolation-based model checker NewITP on solving a large set of HWMCC benchmarks.
Autors: Wu, C.;Wu, C.;Lai, C.;Haung, C.R.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Dec 2014, volume: 33, issue:12, pages: 1846 - 1858
Publisher: IEEE
 

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