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Electrical and Electronics Engineering publications abstract of: 12-2013 sorted by title, page: 0
» "I Saw Three Ships?" [From the Editor's Desk]
Abstract:
Autors: Wood, J.;
Appeared in: IEEE Microwave Magazine
Publication date: Dec 2013, volume: 14, issue:7, pages: 6 - 10
Publisher: IEEE
 
» "Carrying a Bag"?: Memoirs of an IBM Salesman, 1974-1981
Abstract:
This article is the memoir of an IBM salesman working in the Data Processing Division, 1974-1981. This was a Golden Age for account management, sales of mainframes, all during the period of IBM's antitrust suit. The author provides insights into the operations and culture of IBM's sales history.
Autors: Cortada, James W.;
Appeared in: IEEE Annals of the History of Computing
Publication date: Dec 2013, volume: 35, issue:4, pages: 32 - 47
Publisher: IEEE
 
» "Carrying a Bag"?: Memoirs of an IBM Salesman, 1974-1981
Abstract:
This article is the memoir of an IBM salesman working in the Data Processing Division, 1974-1981. This was a Golden Age for account management, sales of mainframes, all during the period of IBM's antitrust suit. The author provides insights into the operations and culture of IBM's sales history.
Autors: Cortada, J.W.;
Appeared in: IEEE Annals of the History of Computing
Publication date: Dec 2013, volume: 35, issue:4, pages: 32 - 47
Publisher: IEEE
 
» (IPC) A Photonic Correlation Scheme Using FWM With Phase Management to Achieve Optical Subtraction
Abstract:
In this paper, a photonic correlation scheme that allows accumulation of negative signals is presented. The scheme uses four-wave mixing of pairs of signal and pump wavelengths, which are chosen such that they create idler wavelengths at a common wavelength. The total optical power at this target idler wavelength depends on the relative phase of each pump and signal wavelength. This concept has been applied to form a correlator where signal wavelengths are modulated by an input bit stream and mixed with pump wavelengths representing a reference bit pattern. This approach provides a correlation function with smaller unwanted noise peaks due to cancelation in the subtraction process. Simulation of the proposed correlation technique has been used to verify the concept using both intensity and phase modulation of the signal wavelengths.
Autors: Kibria, R.;Bui, L.A.;Mitchell, A.;Austin, M.W.;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2013, volume: 5, issue:6, pages: 5502209 - 5502209
Publisher: IEEE
 
» (IPC) Multigigabit Relay Link Using Millimeter-Wave Radio-Over-Fiber Technologies
Abstract:
A multigigabit relay transceiver system based on analog radio-over-fiber technology is proposed and experimentally evaluated for broadband radio-signal transmission in the millimeter-wave band, particularly at 60 GHz. The combination of a high-speed optical modulator and a photodiode provides signal delivery over an optical fiber. The observed dynamic range and resultant error vector magnitude of a 16-ary quadrature amplitude modulation signal compliant with the IEEE 802.11ad Standard, designated for a wireless local access network at 60 GHz, can be within the limit set by the standard.
Autors: Kanno, A.;Kawanishi, T.;Ogawa, H.;Shibagaki, N.;Hanyu, H.;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2013, volume: 5, issue:6, pages: 7902909 - 7902909
Publisher: IEEE
 
» 120-GHz-Band Fully Integrated Wireless Link Using QSPK for Realtime 10-Gbit/s Transmission
Abstract:
This paper describes a 10-Gbit/s fully integrated wireless link for last-one-mile access in optical fiber networks. The wireless equipment employs quadrature phase-shift keying (QPSK) for modulation. The transmitter (TX) head of the link includes a 120-GHz-band QPSK TX module and an encoder board for generating an in-phase and quadrature signal from a 10-Gbit/s optical signal. The receiver (RX) head consists of an RX module using QPSK differentially coherent detection and a decoder board. To obtain sufficient output power for a link distance of over 1 km, we designed a power amplifier (PA) monolithic microwave integrated circuit (MMIC) using a 0.1- m-gate indium–phosphide HEMT. The MMIC uses a novel RF pad for high isolation between input and output ports. The measured gain of the amplifier is over 15 dB from 110 to 140 GHz. The saturation output power at 128 GHz is 15 dBm. The TX, RX, and PA modules provide sufficient data-transmission performance: a bit error rate of less than and an error vector magnitude of 10%. The integrated TX head exhibits the 99% power bandwidth of 8.4 GHz and the spectral efficiency is 1.32 bit/s/Hz. We demonstrated real-time 10-Gbit/s building-to-building connection using a new QPSK wireless link over the distance of 170 m.
Autors: Takahashi, H.;Kosugi, T.;Hirata, A.;Takeuchi, J.;Murata, K.;Kukutsu, N.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2013, volume: 61, issue:12, pages: 4745 - 4753
Publisher: IEEE
 
» 140 Participate in the Ninth PRIME Conference in Villach, Austria: Program Exclusively for Student Work Co-Organized by SSCS-Austria and Italy Chapters [Chapters]
Abstract:
Autors: Baschirotto, A.;
Appeared in: IEEE Solid-State Circuits Magazine
Publication date: Dec 2013, volume: 5, issue:4, pages: 63 - 65
Publisher: IEEE
 
» 2- Tm-Doped All-Fiber Pulse Laser With Active Mode-Locking and Relaxation Oscillation Modulating
Abstract:
We report on the actively mode-locked and relaxation-oscillation-modulated 2- μm all-fiber laser, using an electronic optical phase modulator with fiber pigtail. Linear-cavity and ring-cavity fiber lasers with Tm-doped fiber were set up with a center wavelength around 1.95 μm. Actively mode-locked stable pulse train was generated with a repetition rate of 11.884 MHz (linear cavity) and 12.099 MHz (ring cavity), and the duration of the pulse was 816 ps and 446 ps, respectively. The stable pulse train with a duration of 5.885 μs and a repetition rate of 4-18 kHz was generated by actively modulating the relaxation oscillation of the linear-cavity fiber laser. Similar results for the ring-cavity fiber laser were 1.554 μs and 6-26 kHz, respectively. All the stable pulse trains' energy fluctuations were less than 7%.
Autors: Xiong Wang;Pu Zhou;Xiaolin Wang;Rumao Tao;Lei Si;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2013, volume: 5, issue:6, pages: 1502206 - 1502206
Publisher: IEEE
 
» 2-D Direct-Coupled Standing-Wave Oscillator Arrays
Abstract:
A direct-coupled technique for standing wave oscillator (SWO) arrays is presented in this paper. The oscillation currents of a unit cell in the SWO array directly inject to adjacent cells through the resonator. Two 2-D SWO arrays based on the technique are reported. The first SWO array can provide synchronous signals with identical frequencies, amplitudes, and phases at multiple locations over a chip. It is implemented in a 90-nm CMOS technology with 61.5-GHz oscillation frequency. Millimeter-wave radiators that consists of the proposed SWO array, an RF driver array, and an on-chip loop antenna array are implemented in a single chip to verify the synchronicity of the reported 2-D SWO via wireless measurement. The indirect evidence of synchronicity is provided from the correlation between the wireless measured effective isotropic radiated power (EIRP) and phase noise of 1 1, 2 2, and 3 3 arrays. The EIRP in the normal direction of the array is increasing by a factor of and the phase noise is reducing by a factor of over that of a single cell, where is the number of unit cells in the array. The second SWO array can provide synchronous signals with identical frequencies, amplitudes, and multiple phases at multiple locations over a chip. It is implemented in a 65-nm CMOS technology with 132.5-GHz fundamental frequency. The SWO array is designed for a 2-D second-harmonic (265 GHz) spatial power radiating and combining array. The EIRPs of the fundamental frequency and second harmonic in the normal directio- of the array are and dBm, respectively. The phase noise of the fundamental frequency and second harmonic at 1-MHz offset from the carrier frequency are and dBc/Hz, respectively.
Autors: Chen, Y.-J.;Chu, T.-S.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2013, volume: 61, issue:12, pages: 4472 - 4482
Publisher: IEEE
 
» 2013 Scott Helt Memorial Award for the Best Paper Published in the IEEE Transactions on Broadcasting
Abstract:
Reports on the recipient of the 2013 Scott Helt Memorial Award for the Best Paper.
Autors: null;
Appeared in: IEEE Transactions on Broadcasting
Publication date: Dec 2013, volume: 59, issue:4, pages: 565 - 566
Publisher: IEEE
 
» 2013 Special NSREC Issue of the IEEE Transactions on Nuclear Science Comments by the Editors
Abstract:
The papers in this special issue were originally presented at the 50th annual IEEE International Nuclear and Space Radiation Effects Conference (NSREC), held July 8-12, 2013, in San Francisco, CA, USA.
Autors: Fleetwood, D.;Brown, D.;Girard, S.;Gouker, P.;Gerardin, S.;Quinn, H.;Barnaby, H.;
Appeared in: IEEE Transactions on Nuclear Science
Publication date: Dec 2013, volume: 60, issue:6, pages: 4042 - 4042
Publisher: IEEE
 
» 2013 Student Activities Committee E-mail Addresses
Abstract:
Autors: Causer, C.;
Appeared in: IEEE Potentials
Publication date: Dec 2013, volume: 32, issue:6, pages: 46 - 46
Publisher: IEEE
 
» 2014 Donald O. Pederson Award in Solid-State Circuits Bestowed Upon IEEE Life Fellow Robert G. Meyer: SSCS Distinguished Lecturer Gabriel M. Rebeiz Receives the 2014 IEEE Daniel E. Noble Award for Emerging Technologies [People]
Abstract:
The 2014 Donald O. Pederson Award in Solid-State Circuits was presented to Robert G. Meyer and Gabriel M. Rebeiz received the 2014 IEEE Daniel E. Noble Award for Emerging Technologies.
Autors: Olstein, K.;
Appeared in: IEEE Solid-State Circuits Magazine
Publication date: Dec 2013, volume: 5, issue:4, pages: 41 - 43
Publisher: IEEE
 
» 240 GHz and 272 GHz Fundamental VCOs Using 32 nm CMOS Technology
Abstract:
Two fundamental oscillators, a 240 GHz and a 272 GHz are demonstrated using the IBM CMOS 32 nm process. The design of both oscillators was based on a Colpitts differential topology, where parasitic capacitances of the device are used as a part of the inductor-capacitor tank. The design process and consideration is discussed, as well as the measurement procedures. A simplified model predicting the output power of the voltage-controlled oscillator (VCO) and its phase noise is presented, and comparison to the measured results is discussed. An output power level of 0.2 mW ( 7 dBm) was realized for the 240 GHz oscillator, with total power consumption of 13.3 mW and a total tuning range of 13.5 GHz achieved by changing both the gate and drain bias. The 272 GHz oscillator achieved a lower power level of about 22 dBm, with a total power consumption of only 7 mW.
Autors: Landsberg, N.;Socher, E.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2013, volume: 61, issue:12, pages: 4461 - 4471
Publisher: IEEE
 
» 3-D Statistical Simulation Comparison of Oxide Reliability of Planar MOSFETs and FinFET
Abstract:
New transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, and results are compared with those obtained from conventional bulk MOSFETs. Not only the impact of static trapped charges is investigated, but also the charge trapping dynamics are studied to allow device lifetime and failure rate predictions. Our results show that device-to-device variability is barely increased by progressive oxide charge trapping in bulk devices. On the contrary, oxide degradation determines the SV of SoI and FinFET devices. However, the SoI and multigate transistor architectures are shown to be significantly more robust in terms of immunity to time-dependent SV when compared with the conventional bulk device. The comparative study here presented could be of significant importance for reliability resistant CMOS circuits and systems design.
Autors: Gerrer, L.;Amoroso, S.M.;Markov, S.;Adamu-Lema, F.;Asenov, A.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2013, volume: 60, issue:12, pages: 4008 - 4013
Publisher: IEEE
 
» 3-Dimensional Blow Torch-Molding of Fused Silica Microstructures
Abstract:
This paper presents a new and simple microfabrication process for creating various 3-D microstructures with high-aspect ratios . The key feature of this process is the use of a blow torch, which provides very intense localized heat for a short amount of time . The flame temperature can be up to 2500 for a propane-oxygen torch, above the melting temperatures of many high- materials. We demonstrate the fabrication of hemispherical and half-toroid (birdbath) shells from 100- -thick fused silica substrates. The structures have an rms surface roughness of 5.3 , which is crucial for achieving both high mechanical and optical . We create microbirdbath resonators by batch-level releasing the birdbath shells. We verify the resonance mode shapes of the degenerate modes using laser vibrometry and measure the frequency and of these modes using laser vibrometry and a capacitive measurement method. We demonstrate one of the best mechanical and smallest frequency split between the modes among existing micromechanical resonators. The birdbath resonator is promising for emerging applications such as the mi- rorate-integrating gyroscope.
Autors: Cho, J.Y.;Yan, J.;Gregory, J.A.;Eberhart, H.W.;Peterson, R.L.;Najafi, K.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Dec 2013, volume: 22, issue:6, pages: 1276 - 1284
Publisher: IEEE
 
» 30??50 GHz high-gain CMOS UWB LNA
Abstract:
A 30??50 GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) with a flat high power gain (S21), along with a flat low-noise figure (NF) is demonstrated for the Atacama large millimetre array (ALMA) band-1 (31.3??45 GHz) system applications. The high S21 and low NF are achieved because the triple-well transistors are utilised with their respective source and body terminals connected together. Furthermore, the bandwidth extension and gain flatness is achieved due to the careful design of the inductive-peaking networks. The LNA has a measured S21 of 21.5 ± 1.5 dB, a minimum NF (NFmin) of 3.8 dB at 32.5 GHz, an average NF (NFavg) of 4.67 dB over the range of 30??50 GHz and an input third-order intercept point (IIP3) of 0 dBm, with a DC power consumption of 20.4 mW at 1.2 V supply. The proposed LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain bandwidth product and highest IIP3 suitable for the ALMA band-1 system applications.
Autors: null;null;null;null;
Appeared in: Electronics Letters
Publication date: Dec 2013, volume: 49, issue:25
Publisher: IEEE
 
» 32 & 16 Years Ago
Abstract:
A summary of articles published in Computer 32 and 16 years ago.
Autors: Holmes, Neville;
Appeared in: Computer
Publication date: Dec 2013, volume: 46, issue:12, pages: 14 - 15
Publisher: IEEE
 
» 3D Vascular Decomposition and Classification for Computer-Aided Detection
Abstract:
In this study, we propose a weighted approximate convex decomposition (WACD) and classification methodology for computer-aided detection (CADe) and analysis. We start by addressing the problem of vascular decomposition as a cluster optimization problem and introduce a methodology for compact geometric decomposition. The classification of decomposed vessel sections is performed using the most relevant eigenvalues obtained through feature selection. The method was validated using presegmented sections of vasculature archived for 98 aneurysms in 112 patients. We test first for vascular decomposition and next for classification. The proposed method produced promising results with an estimated 81.5% of the vessel sections correctly decomposed. Recursive feature elimination was performed to find the most compact and informative set of features. We showed that the selected subset of eigenvalues produces minimum error and improved classifier precision. The method was also validated on a longitudinal study of four cases having internal cerebral aneurysms. Volumetric and surface area comparisons were made between expert-segmented sections and WACD classified sections containing aneurysms. Results suggest that the approach is able to classify and detect changes in aneurysm volumes and surface areas close to that segmented by an expert.
Autors: Chowriappa, A.;Salunke, S.;Mokin, M.;Kan, P.;Scott, P.D.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Dec 2013, volume: 60, issue:12, pages: 3514 - 3523
Publisher: IEEE
 
» 3D-Printing Spatially Varying BRDFs
Abstract:
A new method fabricates custom surface reflectance and spatially varying bidirectional reflectance distribution functions (svBRDFs). Researchers optimize a microgeometry for a range of normal distribution functions and simulate the resulting surface's effective reflectance. Using the simulation's results, they reproduce an input svBRDF's appearance by distributing the microgeometry on the printed material's surface. This method lets people print svBRDFs on planar samples with current 3D printing technology, even with a limited set of printing materials. It extends naturally to printing svBRDFs on arbitrary shapes.
Autors: Rouiller, Olivier;Bickel, Bernd;Kautz, Jan;Matusik, Wojciech;Alexa, Marc;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Dec 2013, volume: 33, issue:6, pages: 48 - 57
Publisher: IEEE
 
» 40 Gb/s NRZ-DQPSK Data All-Optical Wavelength Conversion Using Four Wave Mixing in a Bulk SOA
Abstract:
Differential quadrature phase shift keying (DQPSK) modulation has become particularly attractive in high-speed optical communications because of its resistance to fiber nonlinearities and its more efficient use of fiber bandwidth. Because of its wavelength conversion ability, semiconductor optical amplifier (SOA) four wave mixing effect has attracted much attention. We experimentally study the FWM wavelength conversion of 40 Gb/s (20 GBd) NRZ-DQPSK data. A bulk SOA with 21 dB gain and 10 dBm output saturation power is used. The -factors of the input and wavelength converted signal are measured. Some signal regeneration properties are shown. A -factor improvement up to 1.7 dB is observed.
Autors: Krzczanowicz, L.;Connelly, M.J.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2013, volume: 25, issue:24, pages: 2439 - 2441
Publisher: IEEE
 
» 4 4-Element Corporate-Feed Waveguide Slot Array Antenna With Cavities for the 120 GHz-Band
Abstract:
We propose a 4 4-element corporate-feed waveguide slot array antenna with outer cavities for the 120 GHz band. To adjust the mutual coupling effects in a small sized array antenna, an outer cavity structure is employed for each radiating slot. The outer cavity in this antenna structure provides adequate mutual coupling effects for each radiating element. As a result, high antenna efficiency is achieved over a broad bandwidth. A 4 4-element array with the outer cavities was fabricated by diffusion bonding of laminated thin copper plates, which has the advantages of high precision and low loss characteristics even in a high frequency region such as the 120 GHz band. The antenna gain of 21.1 dBi and the antenna efficiency of 80.0% are measured at the center frequency. The measured 1 dB-down gain bandwidth is 22 GHz (from 118 to 140 GHz) which is corresponding to 17.6%.
Autors: Kim, D.;Hirokawa, J.;Ando, M.;Takeuchi, J.;Hirata, A.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2013, volume: 61, issue:12, pages: 5968 - 5975
Publisher: IEEE
 
» 4 4-Element Corporate-Feed Waveguide Slot Array Antenna With Cavities for the 120 GHz-Band
Abstract:
We propose a 4 4-element corporate-feed waveguide slot array antenna with outer cavities for the 120 GHz band. To adjust the mutual coupling effects in a small sized array antenna, an outer cavity structure is employed for each radiating slot. The outer cavity in this antenna structure provides adequate mutual coupling effects for each radiating element. As a result, high antenna efficiency is achieved over a broad bandwidth. A 4 4-element array with the outer cavities was fabricated by diffusion bonding of laminated thin copper plates, which has the advantages of high precision and low loss characteristics even in a high frequency region such as the 120 GHz band. The antenna gain of 21.1 dBi and the antenna efficiency of 80.0% are measured at the center frequency. The measured 1 dB-down gain bandwidth is 22 GHz (from 118 to 140 GHz) which is corresponding to 17.6%.
Autors: Kim, D.;Hirokawa, J.;Ando, M.;Takeuchi, J.;Hirata, A.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2013, volume: 61, issue:12, pages: 5968 - 5975
Publisher: IEEE
 
» 60-GHz LTCC Miniaturized Substrate Integrated Multibeam Array Antenna With Multiple Polarizations
Abstract:
In this paper, miniaturized substrate integrated multibeam array antennas are proposed and designed at 60 GHz. Owing to the design flexibility of the low temperature cofired ceramic (LTCC) technology, the entire multibeam antenna size is only equal to the size of radiating aperture by carefully embedding the complicated substrate integrated waveguide (SIW) feeding network underneath the radiating array. After introducing design procedures for the folded Butler matrix and the corresponding radiating array, a dual linear-polarization (LP) and a dual circular-polarization (CP) substrate integrated multibeam array antennas are designed and fabricated, respectively. Here, each multibeam antenna has four switchable beams with different pointing directions. Each beam direction has two orthogonal LP or CP modes, therefore allowing the polarization diversity. Measured results validate our design and demonstrate good performances of our proposed structures.
Autors: Cheng, Y.J.;Bao, X.Y.;Guo, Y.X.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2013, volume: 61, issue:12, pages: 5958 - 5967
Publisher: IEEE
 
» 93% of the -Conjecture Is Already Verified
Abstract:
One of the most important challenges in the context of fix-free codes is proving the -conjecture, which guarantees the existence of fix-free codewords of lengths if . Although this conjecture has not become a theorem yet, some researchers have proved the problem with some extra constraints on the codelengths. One of those, we call it Yekhanin's constraint, is , where . In this paper, it is shown that such a constraint is not so restrictive. We prove that almost 93.8% of the -tuple codelength vectors with Kraft sum do satisfy Yekhanin's constraint. One can optimistically interpret this result as almost 93.8% of the road of proving the -conjecture is paved.
Autors: Aghajan, A.;Khosravifard, M.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Dec 2013, volume: 59, issue:12, pages: 8182 - 8194
Publisher: IEEE
 
» 93% of the -Conjecture Is Already Verified
Abstract:
One of the most important challenges in the context of fix-free codes is proving the 3/4-conjecture, which guarantees the existence of fix-free codewords of lengths ℓ1,ℓ2,..., ℓN if Σi=1N2-ℓi ≤ 3/4. Although this conjecture has not become a theorem yet, some researchers have proved the problem with some extra constraints on the codelengths. One of those, we call it Yekhanin's constraint, is Σi:ℓi-λ ≤1 2-ℓi ≥ 1/2, where λ = minklk. In this paper, it is shown that such a constraint is not so restrictive. We prove that almost 93.8% of the N-tuple codelength vectors with Kraft sum 3/4 do satisfy Yekhanin's constraint. One can optimistically interpret this result as almost 93.8% of the road of proving the 3/4-conjecture is paved.
Autors: Aghajan, A.;Khosravifard, M.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Dec 2013, volume: 59, issue:12, pages: 8182 - 8194
Publisher: IEEE
 
» -Optimal Decentralized Control Over Posets: A State-Space Solution for State-Feedback
Abstract:
Pub DtlWe develop a complete state-space solution to -optimal decentralized control of poset-causal systems with state-feedback. Our solution is based on the exploitation of a key separability property of the problem that enables an efficient computation of the optimal controller by solving a small number of uncoupled standard Riccati equations. Our approach gives important insight into the structure of optimal controllers, such as controller degree bounds that depend on the structure of the poset. A novel element in our state-space characterization of the controller is an intuitive description of the controller as an aggregation of local control laws.
Autors: Shah, P.;Parrilo, P.A.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Dec 2013, volume: 58, issue:12, pages: 3084 - 3096
Publisher: IEEE
 
» -Optimal Decentralized Control Over Posets: A State-Space Solution for State-Feedback
Abstract:
We develop a complete state-space solution to H2-optimal decentralized control of poset-causal systems with state-feedback. Our solution is based on the exploitation of a key separability property of the problem that enables an efficient computation of the optimal controller by solving a small number of uncoupled standard Riccati equations. Our approach gives important insight into the structure of optimal controllers, such as controller degree bounds that depend on the structure of the poset. A novel element in our state-space characterization of the controller is an intuitive description of the controller as an aggregation of local control laws.
Autors: Shah, P.;Parrilo, P.A.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Dec 2013, volume: 58, issue:12, pages: 3084 - 3096
Publisher: IEEE
 
» Quantum-Well Tunnel-FETs With Tunable Backward Diode Characteristics
Abstract:
Vertical quantum-well (QW) tunnel-FETs are fabricated based on an ultrathin In0.53Ga0.47As/GaAs0.5Sb0.5 staggered gap (type-II) heterostructure lattice matched to InP. Area-dependent QW-to-QW tunneling current is demonstrated. Devices with HfO2 high- k gate dielectric (EOT ~ 1.3 nm) exhibit minimum subthreshold swings of 140 mV/decade at 300 K, with an ON-current density of 0.5 μA/μm2 at VDD=0.5 V. Sharp negative differential resistance is observed in the output characteristics. For the first time, gate-tunable backward diode characteristics are demonstrated in this material system, with peak curvature coefficient of 30 V-1 near VDS=0 V. These results show the potential of vertical TFETs in hybrid IC applications.
Autors: Tao Yu;Teherani, J.T.;Antoniadis, D.A.;Hoyt, J.L.;
Appeared in: IEEE Electron Device Letters
Publication date: Dec 2013, volume: 34, issue:12, pages: 1503 - 1505
Publisher: IEEE
 
» A 0.13- m CMOS Interface Circuit for a MEMS Resonator-Based Vacuum Measurement System
Abstract:
This paper presents the design of the interface circuit for a novel MEMS-based vacuum measurement system topology. The system is designed to target a vacuum range from 10 to 1200 mbar , providing a theoretical pressure resolution of 2 mbar over the temperature range from C to 60 C. The proposed circuit is designed and fabricated in an IBM 0.13- m CMOS process. Measurements show the circuit consumes 62 W from a 1.2-V supply, and has a maximum response time of 2 ms. This work is a critical step towards the goal of building a low-power, monolithic, integrated MEMS-based temperature-compensated vacuum measurement system.
Autors: Ali Taghvaei, M.;Cicek, P.-V.;Allidina, K.;Nabki, F.;El-Gamal, M.N.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2013, volume: 60, issue:12, pages: 3136 - 3144
Publisher: IEEE
 
» A 0.13- m CMOS Interface Circuit for a MEMS Resonator-Based Vacuum Measurement System
Abstract:
This paper presents the design of the interface circuit for a novel MEMS-based vacuum measurement system topology. The system is designed to target a vacuum range from 10 to 1200 mbar , providing a theoretical pressure resolution of 2 mbar over the temperature range from -10°C to 60°C. The proposed circuit is designed and fabricated in an IBM 0.13- μm CMOS process. Measurements show the circuit consumes 62 μW from a 1.2-V supply, and has a maximum response time of 2 ms. This work is a critical step towards the goal of building a low-power, monolithic, integrated MEMS-based temperature-compensated vacuum measurement system.
Autors: Taghvaei, M.A.;Cicek, P.-V.;Allidina, K.;Nabki, F.;El-Gamal, M.N.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2013, volume: 60, issue:12, pages: 3136 - 3144
Publisher: IEEE
 
» A 0.39–0.44 THz 2x4 Amplifier-Quadrupler Array With Peak EIRP of 3–4 dBm
Abstract:
This paper presents a CMOS amplifier-multiplier-antenna array capable of generating an EIRP of 3–4 dBm at 420 GHz. The chip is built using a 45-nm CMOS SOI process, and efficient on-chip antennas are used to extract the power out of the chip. The design is based on a 90–110 GHz distribution network with splitters and amplifiers, and a balanced quadrupler capable of delivering up of power at 370–430 GHz. The amplifier–multiplier concept is proven on a 2 4 array, and it can be also scaled to any array using additional W-band splitters and amplifiers.
Autors: Golcuk, F.;Gurbuz, O.D.;Rebeiz, G.M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2013, volume: 61, issue:12, pages: 4483 - 4491
Publisher: IEEE
 
» A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications
Abstract:
High-speed signaling over high density interconnect on organic package substrates or silicon interposers offers an attractive solution to the off-chip bandwidth limitation problem faced in modern digital systems. In this paper, we describe a signaling system co-designed with the interconnect to take advantage of the characteristics of this environment to enable a high-speed, low area, and low-power die to die link. Ground-Referenced Signaling (GRS) is a single-ended signaling system that eliminates the major problems traditionally associated with single-ended design by using the ground plane as the reference and signaling above and below ground. This design employs a novel charge pump driver that additionally eliminates the issue of simultaneous switching noise with data independent current consumption. Silicon measurements from a test chip implementing two 16-lane links, with forwarded clocks, in a standard 28 nm process demonstrate 20 Gb/s operation at 0.54 pJ/bit over 4.5 mm organic substrate channels at a nominal 0.9 V power supply voltage. Timing margins at the receiver are 0.3 UI at a BER of 10 . We estimate BER 10 at the eye center.
Autors: Poulton, J.W.;Dally, W.J.;Chen, X.;Eyles, J.G.;Greer, T.H.;Tell, S.G.;Wilson, J.M.;Gray, C.T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3206 - 3218
Publisher: IEEE
 
» A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS
Abstract:
Tomlinson–Harashima (TH) precoding is a transmitter equalization technique in which the post-cursor intersymbol interference (ISI) is canceled by means of an infinite impulse response (IIR) filter with modulo (MOD)-based amplitude limitation. TH equalizers are suited for asymmetric links, such as DRAM interfaces, where the transmitter contains the equalization complexity and the receiver is kept simple. To increase the data rate, we propose the application of pipelining and half-rate operation to the ISI subtraction in the equalizer's feedback path. A TH equalizer with 8 taps, 6 bit resolution, and 2-PAM/4-PAM support has been implemented in 22-nm silicon-on-insulator (SOI) CMOS technology. In measurements, the feedback delay reduction techniques allow us to equalize 34-cm-long PCB traces having 12-dB loss with 7 ISI reduction for 5.0-Gb/s 2-PAM signaling, and in 10.0-Gb/s 4-PAM mode completely closed eye diagrams are opened. The measured efficiency of the 145 transmitter is 1.2 pJ/bit in 4-PAM mode at 5.0 Gbaud with disabled equalization and increases linearly with 14 per 1% increase of the equalization tap weights.
Autors: Kossel, M.;Toifl, T.;Francese, P.A.;Brandli, M.;Menolfi, C.;Buchmann, P.;Kull, L.;Andersen, T.M.;Morf, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3268 - 3284
Publisher: IEEE
 
» A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications
Abstract:
This paper presents the design of a 40-nm CMOS 10.3-GS/s 6-bit Flash ADC used as the analog frontend of a universal DSP-based receiver that meets the requirements for all the NRZ 10G Ethernet (10GE) standards, for both fiber and copper channels. The 4-way interleaved ADC consists of a pair of frontend variable gain amplifiers (VGAs) driving four sets of track-and-hold (T/H) switches, followed by fine VGAs that drive 6-bit comparator arrays. A Wallace-tree adder is utilized as the thermometer-to-binary encoder allowing comparator re-ordering and redundancy. Also integrated is an 8-bit calibration DAC that is used as a reference to nullify the accumulated offset of the entire signal path, as well as to compensate for the nominal nonlinearity of the fine VGA and the resistor ladder. After calibration, the peak SNDR of the ADC is about 34 dB with bandwidth ranging from 3.5 to 6 GHz over all VGA gain settings. The ADC, along with its entire clock path, occupies 0.27 mm and consumes 242 mW from a 0.9-V supply.
Autors: Varzaghani, A.;Kasapi, A.;Loizos, D.N.;Paik, S.-H.;Verma, S.;Zogopoulos, S.;Sidiropoulos, S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3038 - 3048
Publisher: IEEE
 
» A 100 MHz 82.4% Efficiency Package-Bondwire Based Four-Phase Fully-Integrated Buck Converter With Flying Capacitor for Area Reduction
Abstract:
In today's fully-integrated converters, the integrated LC components dominate the chip-area and have become the major limitation of reducing the cost and increasing the current density. This paper presents a 100 MHz four-phase fully-integrated buck converter with standard package bondwire inductors and a flying capacitor (C ) topology for chip-area reduction, occupying 1.25 mm² effective area in 0.13-µm CMOS technology. A four-phase operation is introduced for chip-area reduction with the cost penalty minimized by utilizing standard package bondwire inductance as power inductors. Meanwhile, an extra more than 40% chip-area saving is achieved by the simple but effective C topology to take advantage of the parasitic bondwire inductance at the input for ripple attenuation. A maximum output current of 1.2 A is obtained by the four-phase operation, while only 3.73 nF overall integrated capacitors are required. Also, with the chip-area hungry integrated spiral metal inductors eliminated, the current density is significantly increased. 0.96 A/mm² current density and 82.4% efficiency is obtained with 1.2 V to 0.9 V voltage conversion without using any off-chip inductors or advanced processes. The reliability is also verified by measurement with various bondwire inductances and configurations.
Autors: Huang, C.;Mok, P.K.T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 2977 - 2988
Publisher: IEEE
 
» A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step
Abstract:
This paper presents a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications. It supports resolutions of 10 and 12 bit and sample rates from DC up to 40 kS/s to accommodate a variety of sensor applications. A Data-Driven Noise-Reduction method is introduced to selectively enhance the comparator noise performance. In this way, a higher ADC resolution can be achieved with a small increase of the power consumption. A self-oscillating comparator is used to generate the bit-cycling clock internally. In this way, the ADC only requires an external clock at the sample-rate frequency. A segmented capacitive DAC with 250 aF unit elements is applied to save power and to reduce DNL errors at the same time. The implemented prototype in 65 nm CMOS occupies an area of 0.076 mm . For the two supported resolutions (10/12 bit), the ADC achieves an ENOB of 9.4 and 10.1 bit while consuming 72 and 97 nW from a 0.6 V supply at 40 kS/s. This leads to power efficiencies of 2.7 and 2.2 fJ/conversion-step for 10 bit and 12 bit resolution, respectively. Furthermore, the leakage power, which is below 0.4 nW, ensures that the efficiency can be maintained down to very low sample rates.
Autors: Harpe, P.;Cantatore, E.;van Roermund, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3011 - 3018
Publisher: IEEE
 
» A 12.4-mW 4.5-Gb/s Receiver With Majority-Voting 1-Tap Speculative DFE in 0.13- CMOS
Abstract:
This brief presents a majority-voting 1-tap speculative decision-feedback equalization (DFE) architecture wherein the current-mode-logic (CML) selector after the slicers is replaced with a CML majority voter with two instead of three transistors in the stack, thereby resulting in improved speed and increased voltage headroom (or lower supply voltage operation). Compared with the traditional CML selector, the majority voter shows around 50% delay reduction at the same bias conditions and 25% reduction in supply. A receiver with the proposed majority-voting DFE is implemented in 0.13- CMOS process. With the DFE enabled, the receiver is able to equalize a 20-in channel over an FR4 board with 22-dB Nyquist loss at 4.5 Gb/s. The whole receiver core occupies 0.14 and consumes 12.4 mW.
Autors: Chen, J.;Bashirullah, R.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2013, volume: 60, issue:12, pages: 867 - 871
Publisher: IEEE
 
» A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS
Abstract:
A 14-bit SAR ADC is presented that achieves 73.6 dB SNDR at 80 MSPS while using a 1.2-V-only supply. In order to overcome throughput limitations common to conventional SAR ADCs, several techniques are proposed. First, a flash sub-ADC is utilized to resolve the 5 MSBs quickly prior to SAR sequential decisions of the LSBs. Second, the DAC operation is time-interleaved by a factor of 2, increasing speed while allowing a single comparator to be shared between all DACs. Third, fully on-chip DAC charge redistribution allows the DAC settling time to be improved by more than an order of magnitude compared to conventional techniques. Finally, the ADC is fully self-timed through the use of a replica timer circuit in order to take full advantage of the fast DAC settling and comparator decisions. Despite the increased speed, the ADC consumes only 31.1 mW and occupies a core area of 0.55 mm².
Autors: Kapusta, R.;Shen, J.;Decker, S.;Li, H.;Ibaragi, E.;Zhu, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3059 - 3066
Publisher: IEEE
 
» A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC
Abstract:
An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13- CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 consumes 12 mA and its measured jitter is 4 at 2.4 GHz.
Autors: Song, M.;Jung, I.;Pamarti, S.;Kim, C.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2013, volume: 60, issue:12, pages: 3145 - 3151
Publisher: IEEE
 
» A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability
Abstract:
This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes INL from CMOS switch resistance. The DAC is implemented in a 0.6 µm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/√Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 µs. Current consumption is 4.2 mA from 30 V supplies, excluding power required for external reference buffers.
Autors: McLachlan, R.C.;Gillespie, A.;Coln, M.C.W.;Chisholm, D.;Lee, D.T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3028 - 3037
Publisher: IEEE
 
» A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
Abstract:
An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alternate comparators clocked asynchronously and a redundant capacitive DAC with constant common mode to improve the accuracy of the comparator. A low-power, clocked capacitive reference buffer is used, and fractional reference voltages are provided to reduce the number of unit capacitors in the capacitive DAC (CDAC). The ADC stacks the CDAC with the reference capacitor to reduce the area and enhance the settling speed. Background calibration of comparator offset is implemented. The ADC consumes 3.1 mW from a 1 V supply and occupies 0.0015 mm².
Autors: Kull, L.;Toifl, T.;Schmatz, M.;Francese, P.A.;Menolfi, C.;Brandli, M.;Kossel, M.;Morf, T.;Andersen, T.M.;Leblebici, Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3049 - 3058
Publisher: IEEE
 
» A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process
Abstract:
A 32-Gb/s data-interpolator receiver for electrical chip-to-chip communications is introduced. The receiver front-end samples incoming data by using a blind clock signal, which has a plesiochronous frequency-phase relation with the data. Phase alignment between the data and decision timing is achieved by interpolating the input-signal samples in the analog domain. The receiver has a continuous-time linear equalizer and a two-tap loop unrolled DFE using adjustable-threshold comparators. The receiver occupies 0.24 mm² and consumes 308.4 mW from a 0.9-V supply when it is implemented with a 28-nm CMOS process.
Autors: Doi, Y.;Shibasaki, T.;Danjo, T.;Chaivipas, W.;Hashida, T.;Miyaoka, H.;Hoshino, M.;Koyanagi, Y.;Yamamoto, T.;Tsukamoto, S.;Tamura, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3258 - 3267
Publisher: IEEE
 
» A 38 Gb/s to 43 Gb/s Monolithic Optical Receiver in 65 nm CMOS Technology
Abstract:
A scaled 40 Gb/s optical receiver incorporating a transimpedance amplifier (TIA), a limiting amplifier (LA), a clock and data recovery (CDR), and a 1:4 demultiplexer was proposed in 65 nm CMOS technology. The TIA employs a regulated cascode structure to achieve low input resistance and a stable dc operating point, whereas the LA adopts the third-order interleaving active feedback technique to obtain greater bandwidth and flatter frequency response. A 10 GHz LC-based voltage controlled oscillator with a ring structure that generates eight phases is presented. A quarter-rate phase detector in the CDR samples the 40 Gb/s input data, which are retimed and demultiplexed into four sets of 10 Gb/s output data. Experimental results show that the recovered clock exhibits a phase noise of 112.39 dBc/Hz@10 MHz from a carrier frequency of 10 GHz, in response to 2 1 PRBS input. The retimed and demultiplexed data exhibit a peak-peak jitter of 4.46 ps and an RMS jitter of 1.18 ps. The core circuit of the receiver consumes 160 mW from a 1.2 V supply.
Autors: Chen, Y.;Wang, Z.;Fan, X.;Wang, H.;Li, W.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2013, volume: 60, issue:12, pages: 3173 - 3181
Publisher: IEEE
 
» A 4Ω 2.65W Class-D Audio Amplifier With Embedded DC-DC Boost Converter, Current Sensing ADC and DSP for Adaptive Speaker Protection
Abstract:
In this paper a class-D smart speaker driver is presented that can deliver 2.65 W at 1% THD into a 4Ω load. Maximal output power is maintained at low battery voltage by supplying the class-D amplifier from a DC-DC boost converter. Speaker damage is avoided by a speaker protection algorithm that runs on an embedded DSP. The protection algorithm estimates the membrane excursion and voice coil temperature using a speaker model that tracks the speaker impedance which is determined by measuring the speaker current with less than 2% relative error. A sample & hold technique is presented that rejects the load current ripple by sampling at the moments where the instantaneous load current equals the average current. At full output power the combined efficiency of the class-D amplifier and DC-DC boost converter is higher than 80%. The complete system is implemented on a single chip that measures 6.6 mm² and is fabricated in a 0.14 µm CMOS technology with a 5 V gate-oxide option.
Autors: Berkhout, M.;Dooper, L.;Krabbenborg, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 2952 - 2961
Publisher: IEEE
 
» A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13- CMOS
Abstract:
This paper presents a between-pair skew (BPS) compensator for parallel data communications. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a wide-bandwidth voltage controlled data delay line. A 5-Gb/s sub-bit BPS compensator in 0.13- μm CMOS occupies approximately 0.038- mm2 active die area and dissipates 22.5 mW.
Autors: Yuxiang Zheng;Jin Liu;Payne, R.;Morgan, M.;Hoi Lee;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2013, volume: 21, issue:12, pages: 2274 - 2285
Publisher: IEEE
 
» A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset
Abstract:
A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 µV offset in a conversion time of 40 ms, while drawing only 3.5 µA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm² chip was fabricated in a standard 0.16 µm CMOS process.
Autors: Chae, Y.;Souri, K.;Makinwa, K.A.A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3019 - 3027
Publisher: IEEE
 
» A 60-GHz Circularly-Polarized Array Antenna-in-Package in LTCC Technology
Abstract:
This communication presents a 60-GHz circularly-polarized antenna-in-package in a low-temperature co-fired ceramic technology. It integrates 4 4 aperture-coupled corner-truncated microstrip patch antenna elements and their stripline feeding network as well as signal and ground traces for interconnection with the chip and board. The fabricated sample has a dimension of 13 13 0.9 mm Simulated and measured results confirm its sufficient gain and matching bandwidth for broadband 60-GHz applications (57–66 GHz).
Autors: Zhang, W.;Zhang, Y.P.;Sun, M.;Luxey, C.;Titz, D.;Ferrero, F.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2013, volume: 61, issue:12, pages: 6228 - 6232
Publisher: IEEE
 
» A 650-pJ/bit MedRadio Transmitter With an FIR-Embedded Phase Modulator for Medical Micro-Power Networks (MMNs)
Abstract:
This paper presents a 400-MHz energy-efficient Medical Micro-power Networks transmitter for neural-muscular signal sensing and stimulation applications. The transmitter can fulfill the transmission requirements defined in the MedRadio band, including the recently added 413-MHz to 457-MHz channels. The half-sine shaped offset-QPSK modulation is adopted to meet the transmission mask requirement while supporting a maximum data rate of 4 Mbps within the 6-MHz channel bandwidth. The signal modulation is performed by the proposed FIR-embedded phase modulator which employs a phase-domain FIR filter to suppress the unwanted side-lobe energy. Fabricated in a 0.18-µm CMOS process, the presented transmitter consumes only 2.6 mW from a 1-V supply, resulting in an energy efficiency of 650 pJ/bit. The measured error vector magnitude is 2.5%.
Autors: Liu, Y.-H.;Chen, L.-G.;Lin, C.-Y.;Lin, T.-H.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2013, volume: 60, issue:12, pages: 3279 - 3288
Publisher: IEEE
 
» A 70–90-GHz High-Linearity Multi-Band Quadrature Receiver in SiGe Technology
Abstract:
An integrated frequency agile quadrature -band receiver is presented in this paper. The complete receiver is realized in a commercial SiGe:C technology with an of 170/250 GHz. The receiver covers the two point-to-point communication bands from 71 to 76 GHz and from 81 to 86 GHz and the automotive radar band at 77 GHz. A wide tuning range modified Colpitts oscillator provides a local oscillator (LO) tuning range . A two-stage constant phase RC polyphase network is implemented to provide wideband in-phase quadrature LO signals. The measured phase imbalance of the network stays below over the receiver's frequency range. In addition the chip includes a wideband low-noise amplifier, Wilkinson power divider, down conversion mixers, and frequency prescaler. Each of the chip's receiver I/Q paths shows a measured conversion gain above 19 dB and an input referred 1-dB compression point of . The receiver's measured noise figure stays below 11 dB over the complete frequency range. Furthermore, the receiver has a measured IF bandwidth of 6 GHz. The complete chip including prescaler draws a current of 230 mA from a 3.3-V supply, and consumes a chip area of .
Autors: Nasr, I.;Laemmle, B.;Aufinger, K.;Fischer, G.;Weigel, R.;Kissinger, D.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2013, volume: 61, issue:12, pages: 4600 - 4612
Publisher: IEEE
 
» A 77-GHz CMOS Automotive Radar Transceiver With Anti-Interference Function
Abstract:
Pub DtlThis paper presents a 77-GHz long-range automotive radar transceiver with the function of reducing mutual interference. The proposed frequency-hopping random chirp FMCW technique reconfigures the chirp sweep frequency and time every cycle to result in noise-like frequency response for mutual interference after the received signal is down-converted and demodulated. Thus, the false alarm rate can be reduced significantly. The transceiver IC is fully integrated in TSMC 1P9M 65-nm digital CMOS technology. The chip including pads occupies a silicon area of 1.03 mm 0.94 mm. The transceiver consumes totally 275 mW of power, and the measured transmitting power and receiver noise figure are 6.4 dBm and 14.8 dB, respectively. To the authors' knowledge, this is the first integrated 77-GHz automotive radar transceiver with the feature of anti-interference.
Autors: Luo, T.-N.;Wu, C.-H.E.;Chen, Y.-J.E.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2013, volume: 60, issue:12, pages: 3247 - 3255
Publisher: IEEE
 
» A Lossless Adaptive Optical Power Splitter Employing an Opto-VLSI Processor
Abstract:
We propose and demonstrate the concept of a novel 1 × N lossless adaptive optical power splitter (OPS) structure integrating a software-driven Opto-VLSI processor, optical amplifiers, and an array of 4-f imaging systems. The active area of the Opto-VLSI processor is divided into M pixel blocks driven by multicasting phase holograms and aligned with an M-element lens array and a fiber array, thus forming an array of 4-f imaging systems. Each 4-f imaging system is capable of collimating and adaptively splitting an input optical beam emerging from an optical fiber and then coupling the split beams into different output fiber ports, thus realizing dynamic optical power splitting. The Opto-VLSI processor is driven by optimized multicasting phase holograms that adaptively split an incident laser beam along different angles; thus, user-defined splitting ratios can be achieved. Experimental results show that the optical amplifiers compensate for the splitting and the insertion losses, making the adaptive OPS lossless.
Autors: Mustafa, H.A.B.;Feng Xiao;Alameh, K.;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2013, volume: 5, issue:6, pages: 7902410 - 7902410
Publisher: IEEE
 
» A Bag of Systems Representation for Music Auto-Tagging
Abstract:
We present a content-based automatic tagging system for music that relies on a high-level, concise “Bag of Systems” (BoS) representation of the characteristics of a musical piece. The BoS representation leverages a rich dictionary of musical codewords, where each codeword is a generative model that captures timbral and temporal characteristics of music. Songs are represented as a BoS histogram over codewords, which allows for the use of traditional algorithms for text document retrieval to perform auto-tagging. Compared to estimating a single generative model to directly capture the musical characteristics of songs associated with a tag, the BoS approach offers the flexibility to combine different generative models at various time resolutions through the selection of the BoS codewords. Additionally, decoupling the modeling of audio characteristics from the modeling of tag-specific patterns makes BoS a more robust and rich representation of music. Experiments show that this leads to superior auto-tagging performance.
Autors: Ellis, K.;Coviello, E.;Chan, A.B.;Lanckriet, G.;
Appeared in: IEEE Transactions on Audio, Speech, and Language Processing
Publication date: Dec 2013, volume: 21, issue:12, pages: 2554 - 2569
Publisher: IEEE
 
» A Battery Management System Using an Active Charge Equalization Technique Based on a DC/DC Converter Topology
Abstract:
An active charge equalization technique based on a dc/dc converter topology is proposed in this paper. The technique achieves cell balancing of batteries in a stack in terms of both voltage and charge as the pack is being charged/discharged and in idle periods to maximize the energy and reliability of stack operation. A set of MOSFET switches controlled by a voltage monitoring circuit ensures that each battery module has the same output voltage by transferring charge from an individual battery module with the highest voltage to a weak module. An overvoltage and overdischarge protection circuit is presented to reduce the degradation of battery life and to operate each battery within the voltage limits.
Autors: Yarlagadda, S.;Hartley, T.T.;Husain, I.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Dec 2013, volume: 49, issue:6, pages: 2720 - 2729
Publisher: IEEE
 
» A Beam Steering Horn Antenna Using Active Frequency Selective Surface
Abstract:
In this communication, a novel filtering antenna is proposed by utilizing active frequency selective surface (FSS), which can simultaneously achieve filtering and beam steering function. The FSS unit is composed of a metallic rectangular ring and a patch, with a pair of microwave varactor diodes inserted in between along incident electric field polarization direction. Transmission phase of the emitted wave can be tuned by changing the bias voltage applied to the varactor diodes. Through different configurations of the bias voltages, we can obtain the gradient phase distribution of the emitted wave along E- and H-plane. This active FSS is then fabricated and utilized as a radome above a conventional horn antenna to demonstrate its ability of steering the beam radiated from the horn. The experimental results agree well with the simulated ones, which show that the horn antenna with the active FSS can realize beam steering in both E- and H-plane in a range of at 5.3 GHz with a bandwidth of 180 MHz.
Autors: Pan, W.;Huang, C.;Chen, P.;Pu, M.;Ma, X.;Luo, X.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2013, volume: 61, issue:12, pages: 6218 - 6223
Publisher: IEEE
 
» A Biomedical Engineering Story: Rutherford Inspires Young Adults [Women to Watch]
Abstract:
A biomedical engineer, Kathleen Rutherford is associate director of regulatory affairs at Zimmer Trabecular Metal Technology.
Autors: Salim, N.;
Appeared in: IEEE Women in Engineering Magazine
Publication date: Dec 2013, volume: 7, issue:2, pages: 8 - 9
Publisher: IEEE
 
» A Bivariate Maintenance Policy for Multi-State Repairable Systems With Monotone Process
Abstract:
This paper proposes a sequential failure limit maintenance policy for a repairable system. The objective system is assumed to have states, including one working state and failure states, and the multiple failure states are classified potentially by features such as failure severity or failure cause. The system deteriorates over time and will be replaced upon the th failure. Corrective maintenance is performed immediately upon each of the first failures. To avoid the costly failure, preventive maintenance actions will be performed as soon as the system's reliability drops to a critical threshold . Both preventive maintenance and corrective maintenance are assumed to be imperfect. Increasing and decreasing geometric processes are introduced to characterize the efficiency of preventive maintenance and corrective maintenance. The objective is to derive an optimal maintenance policy such that the long-run expected cost per unit time is minimized. The analytical expression of the cost rate function is derived, and the corresponding optimal maintenance policy can be determined numerically. A numerical example is given to illustrate the theoretical results and the maintaining procedure. The decision model shows its adaptability to different possible characteristics of the maintained system.
Autors: Zhang, M.;Xie, M.;Gaudoin, O.;
Appeared in: IEEE Transactions on Reliability
Publication date: Dec 2013, volume: 62, issue:4, pages: 876 - 886
Publisher: IEEE
 
» A Bivariate Normalization Approach for Characterizing Reverberation Chambers
Abstract:
We suggest a novel bivariate normalization (BN) approach to evaluate distributions of electromagnetic fields in reverberation chambers. The BN approach is simpler and more cost effective than the conventional marginal probability density functions (MPDF) method. In our approach, we transform the complicated MPDF into simplified probability density functions using a normalization technique. In addition, we can also present cumulative distribution functions as simple closed forms with no help of any numerical integration. According to the experiment and the goodness-of-fit test, the BN method shows good agreement with the conventional one, which proves accuracy and validity of our proposal.
Autors: Choi, S.;Park, S.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Dec 2013, volume: 55, issue:6, pages: 1350 - 1353
Publisher: IEEE
 
» A Blind Baud-Rate ADC-Based CDR
Abstract:
This paper proposes a 10-Gb/s blind baud-rate ADC-based CDR. The blind baud-rate operation is made possible by using a 2UI integrate-and-dump filter, which creates intentional ISI in adjacent bit periods. The blind samples are interpolated to recover center-of-the-eye samples for a speculative Mueller–Muller PD and a 2-tap DFE operation. A test chip, fabricated in 65-nm CMOS, implements a 10-Gb/s CDR with a measured high-frequency jitter tolerance of 0.19 and of frequency offset.
Autors: Ting, C.;Liang, J.;Sheikholeslami, A.;Kibune, M.;Tamura, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3285 - 3295
Publisher: IEEE
 
» A Builder and Teacher: Danowski Espouses the Benefits of Communities
Abstract:
Meredith Danowski was interested in engineering before she even knew exactly what engineering was. Growing up, her favorite toys were LEGOs and toy cars, and she loved to watch her grandfather at his workbench fixing things and putting new things together. In grade school, she realized she had a serious love for space and decided she wanted to be an astronaut. She hasn?t looked back since.
Autors: Salim, N.;
Appeared in: IEEE Women in Engineering Magazine
Publication date: Dec 2013, volume: 7, issue:2, pages: 31 - 33
Publisher: IEEE
 
» A Burst Effort Broadcasting Approach of MPEG-4 Video Transmission for Intervehicle Communication
Abstract:
Efficient and real-time video broadcasting helps to improve driving safety and to make traveling fun for drivers. However, it is hard to structure vehicles into permanent network topologies and schedules to broadcast video streaming real-time in intervehicle communication (IVC) in a high-mobility vehicular environment. In order to achieve this, we have designed a burst effort broadcasting (BEB) approach for IVC, which considers the challenges of high mobility and multihop broadcast, as well as the features of MPEG-4 video streams to adapt to highway scenarios. The BEB approach is distributed in real time without protocol overhead and comprises a queuing procedure and a scheduling scheme. The queuing procedure consists of the preprocess of video transmission, including the video shaping of groups of pictures and sequential reordering video frames. Based on the queuing procedure, a mobility-adaptive scheduler is applied to handle the broadcast and rebroadcast of the video stream. The concept of macroscopic broadcast is utilized to increase the broadcast performance and the video perceived quality of service (PQoS), and to reduce the number of unnecessary redundant broadcasts. As an evaluation, the real MPEG-4 video was conducted in simulation and the broadcast performance was compared with another protocol by the metrics of peak-signal-to-noise ratio (PSNR) and loss of video frames in different broadcasting scenarios. Then, the results were analyzed. The simulation proved that this approach is an efficient multihop broadcast solution that does indeed provide a realistic solution to promote a higher degree of video PQoS on highways.
Autors: Chu, Y.-C.;Huang, N.-F.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Dec 2013, volume: 14, issue:4, pages: 1839 - 1848
Publisher: IEEE
 
» A Calibration Technique for Multibit Stage Pipelined A/D Converters via Least-Squares Method
Abstract:
This brief presents a foreground calibration method for correcting linear and memoryless errors in multibit stage pipelined A/D converters (ADCs). Using a least-squares minimization, the method extends the radix-based pipelined ADC calibration to multibit stage architectures by adopting one-of- n encoding with a radix vector expansion, thereby correcting both nonideal stage gain and random code-boundary transitions in a globally optimal sense. Numerical experiments via Monte Carlo simulation of 400 ADCs show that the proposed calibration method can improve the effective number of bits from 9.5 b to 14.4 b for a hypothetical 15-b 200-MS/s pipelined ADC design in 90-nm CMOS process.
Autors: Jintae Kim;Park, C.S.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Dec 2013, volume: 62, issue:12, pages: 3390 - 3392
Publisher: IEEE
 
» A Cancellation Technique for Reciprocal-Mixing Caused by Phase Noise and Spurs
Abstract:
A phase noise and spur filtering technique suppresses the phase-noise contribution to the receiver noise figure in the presence of a –15 dBm blocker by 25 dB consuming only 8 mA, bridging the performance gap between ring oscillators and LC-oscillators. The technique breaks the conventional trade-off between power and phase-noise in oscillators. It makes use of the symmetry of phase noise around the carrier by using the image of the reciprocal-mixing at double the blocker beat frequency to cancel noise in the receive-band.
Autors: Mikhemar, M.;Murphy, D.;Mirzaei, A.;Darabi, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3080 - 3089
Publisher: IEEE
 
» A Class of Optimal Rectangular Filtering Matrices for Single-Channel Signal Enhancement in the Time Domain
Abstract:
In this paper, we introduce a new class of optimal rectangular filtering matrices for single-channel speech enhancement. The new class of filters exploits the fact that the dimension of the signal subspace is lower than that of the full space. By doing this, extra degrees of freedom in the filters, that are otherwise reserved for preserving the signal subspace, can be used for achieving an improved output signal-to-noise ratio (SNR). Moreover, the filters allow for explicit control of the tradeoff between noise reduction and speech distortion via the chosen rank of the signal subspace. An interesting aspect is that the framework in which the filters are derived unifies the ideas of optimal filtering and subspace methods. A number of different optimal filter designs are derived in this framework, and the properties and performance of these are studied using both synthetic, periodic signals and real signals. The results show a number of interesting things. Firstly, they show how speech distortion can be traded for noise reduction and vice versa in a seamless manner. Moreover, the introduced filter designs are capable of achieving both the upper and lower bounds for the output SNR via the choice of a single parameter.
Autors: Jensen, J.R.;Benesty, J.;Christensen, M.G.;Jingdong Chen;
Appeared in: IEEE Transactions on Audio, Speech, and Language Processing
Publication date: Dec 2013, volume: 21, issue:12, pages: 2595 - 2606
Publisher: IEEE
 
» A Class-F CMOS Oscillator
Abstract:
An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators' structures shows the proposed class-F exhibits the lowest phase noise at the same tank's quality factor and supply voltage. The prototype of the class-F oscillator is implemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of 136 dBc/Hz at 3 MHz offset from the carrier over 5.9–7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm while drawing 12 mA from 1.25 V supply.
Autors: Babaie, M.;Staszewski, R.B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3120 - 3133
Publisher: IEEE
 
» A CMOS High-Power Broadband 260-GHz Radiator Array for Spectroscopy
Abstract:
A high-power broadband 260-GHz radiation source using 65-nm bulk CMOS technology is reported. The source is an array of eight harmonic oscillators with mutual coupling through four 130-GHz quadrature oscillators. Based on a novel self-feeding structure, the harmonic oscillator simultaneously achieves the optimum conditions for the fundamental oscillation and the 2nd-harmonic generation. The signals at 260 GHz radiate through eight on-chip slot antennas, and are in-phase combined inside a hemispheric silicon lens attached at the backside of the chip. Similar to the laser pulse-driven photoconductive emitter in many THz spectrometers, the radiation of this source can also be modulated by narrow pulses generated on chip, which achieves broad radiation bandwidth. Without modulation, the chip achieves a measured continuous-wave radiated power of 1.1 mW, and an EIRP of 15.7 dBm. Under modulation, the measured bandwidth of the source is 24.7 GHz. This radiator array consumes 0.8-W DC power from a 1.2-V supply.
Autors: Han, R.;Afshari, E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2013, volume: 48, issue:12, pages: 3090 - 3104
Publisher: IEEE
 
» A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation
Abstract:
This paper proposes a simple and effective modification of the conventional divide-by-two injection locked frequency divider (ILFD) with direct-injection aimed at allowing both the divide-by-two and the divide-by-three modes of operation. The proposed circuit does not employ additional inductors as usual in divide-by-three ILFDs, but exploits the combined effect of two independent injection techniques. The resulting locking range for the divide-by-three mode is comparable in size to that for the divide-by-two. Thus, the proposed circuit can be an optimum alternative to existing dividers, due to the flexibility of two division ratios and due to the absence of additional inductors. An intuitive explanation of the locking mechanism underlying this ILFD and a quantitative analysis are provided, allowing one to predict the amplitude and phase of oscillation in the locked mode, as well as the locking range, with approximate closed-form expressions. Measurements on a circuit prototype and results from SPICE simulations demonstrate the effectiveness of the circuit and validate the theoretical model and the resulting formulas.
Autors: Buonomo, A.;Lo Schiavo, A.;Awan, M.A.;Asghar, M.S.;Kennedy, M.P.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2013, volume: 60, issue:12, pages: 3126 - 3135
Publisher: IEEE
 

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