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Electrical and Electronics Engineering publications abstract of: 12-2011 sorted by title, page: 0
» "How long is it, really?" [History of Physical Standards]
Abstract:
In the Systeme Internationale (SI), the accepted unit of length is the metre, known in the United States as the meter [1]. SI units are universally accepted to express scientific results, and even with that, scientists who specialize often employ other units to describe the fruits of their labor: Astronomers speak of a trip to Alpha Centauri as covering 4.39 light years of distance; biologists measure their paramecia in microns; physicists measure interatomic distance in atomic units.
Autors: Schooley Sr, J.F.;
Appeared in: IEEE Instrumentation & Measurement Magazine
Publication date: Dec 2011, volume: 14, issue:6, pages: 50 - 53
Publisher: IEEE
 
» (Electro)mechanical behavior of selectively solvated diblock/triblock copolymer blends
Abstract:
Thermoplastic elastomeric triblock copolymers swollen with a midblock-selective solvent form a highly elastic physical network that can exhibit remarkable electromechanical properties (high actuation strains and electromechanical efficiency with low hysteresis upon cycling) as dielectric elastomers. One unexplored means of controllably altering the midblock network and the corresponding (electro)mechanical properties at constant copolymer concentration is to substitute non-network-forming diblock for triblock copolymer molecules. In this study, we demonstrate that the incorporation of composition-matched diblock molecules into selectively solvated triblock systems results in softer materials that are less physically crosslinked and thus capable of undergoing electroactuation at reduced electric fields.
Autors: Vargantwar, Pruthesh H.;Brelander, Sarah M.;Krishnan, Arjun S.;Ghosh, Tushar K.;Spontak, Richard J.;
Appeared in: Applied Physics Letters
Publication date: Dec 2011, volume: 99, issue:24, pages: 242901 - 242901-3
Publisher: IEEE
 
» 0.84 ps Resolution Clock Skew Measurement via Subsampling
Abstract:
An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes are subsampled with a near-frequency asynchronous sampling clock to result in beat signals which are themselves skewed in the same proportion but on a larger time scale. The beat signals are then suitably masked to extract only the skews of the rising edges of the clock signals. We propose a histogram of the arithmetic difference of the beat signals which decouples the relationship of clock jitter to the minimum measurable skew, and allows skews arbitrarily close to zero to be measured with a precision limited largely by measurement time, unlike the conventional XOR based histogram approach. We also analytically show that the proposed approach leads to an unbiased estimate of skew. The measured results from a 65 nm delay measurement front-end indicate that for an input skew range of ±1 fan-out-of-4 (FO4) delay, ±3σ resolution of 0.84 ps can be obtained with an integral error of 0.65 ps. We also experimentally demonstrate that a frequency modulation on a sampling clock maintains precision, indicating the robustness of the technique to jitter. We also show how FM modulation helps in restoring precision in case of rationally related clocks.
Autors: Amrutur, B.;Das, P.K.;Vasudevamurthy, R.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2011, volume: 19, issue:12, pages: 2267 - 2275
Publisher: IEEE
 
» 1-50-MHz VHF electromagnetic sensor-interface power-attenuation detector circuit
Abstract:
The natural but unwelcome byproduct of modern telecommunication systems is electromagnetic interference (EMI). These communication networks are dynamic and produce unpredictable position- and time-varying electromagnetic fields that interfere with sensitive high-performance electronics, for which shielding is often a necessity. The shield's ability to suppress electromagnetic noise, however, may change not only over time but also across environmental conditions. EMI sensors, as a result, play a critical role because arbitrarily over-sizing a shield to accommodate worst-case conditions is not an option in many portable and mobile applications. This paper presents a logarithmically compressed peak-detection EMI sensor-interface circuit that combines the complementary functional strengths of state-of-the-art power detectors to monitor and sense 1-50 MHz of EMI with 5-bit accuracy across 16 dB of dynamic range and under -40 to 40 °C. The proposed circuit and printed-circuit-board (PCB) embodiment compensate for temperature variations as well as diode-induced errors to maintain and improve accuracy across a wide operating range.
Autors: Orlando Lazaro, Gabriel A. Rincón-Mora, Justin P. Vogt
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» 10 MLOC in Your Office Copier
Abstract:
Amid the obvious volume of digital copiers and multifunction printers, the system size is in the millions of lines of code with functionality creep into several overlapping areas-a theme of many modern systems.
Autors: Tsuchitoi, Y.;Sugiura, H.;
Appeared in: IEEE Software
Publication date: Dec 2011, volume: 28, issue:6, pages: 93 - 95
Publisher: IEEE
 
» 11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications
Abstract:
In this paper, an 11.3 Gbps CMOS SONET compliant transceiver designed to work in both RZ and NRZ data formats is presented. Using a configurable high-speed transmit path utilizing an AND gate and a duty cycle adjustment circuit, the transmitter can switch output format between RZ and NRZ. The TX driver exhibits 17 ps rise/fall times, 0.25 ps RJ, and 2 ps DJ. In RZ mode, TX output duty cycle can be adjusted within 40–60% range. To improve input sensitivity in both RZ and NRZ reception, the receiver incorporates a limiting amplifier with a distributed threshold adjustment circuit. It achieves 5 mVpp-diff RX input sensitivity with 0.54 UI high-frequency jitter tolerance. An adaptation scheme based on nested linear search is implemented to control the distributed threshold adjustment circuit. While demonstrating the integration of RZ/NRZ functionality into a single-chip solution using 65 nm CMOS technology, the transceiver core occupies 1.36 mm and consumes 214 mW.
Autors: Kocaman, N.;Garg, A.;Raghavan, B.;Cui, D.;Vasani, A.;Tang, K.;Pi, D.;Tong, H.;Fallahi, S.;Zhang, W.;Singh, U.;Cao, J.;Zhang, B.;Momtaz, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 3089 - 3100
Publisher: IEEE
 
» 1220–1280-nm Optically Pumped InAs Quantum Dot-Based Vertical External-Cavity Surface-Emitting Laser
Abstract:
We report an InAs quantum dot-based optically pumped vertical external-cavity surface-emitting laser (VECSEL), with a continuously variable emission wavelength from 1220 to 1280 nm through the use of epitaxial gradient across the wafer. We demonstrate the performance of two designs of this VECSEL. The first design, 4 × 3, makes use of a resonant periodic gain structure where three dot-in-a-well (DWELL) layers are located at the antinode of the E-field standing wave, with a total of four sets being used. The second design, 12 × 1, makes use of a single DWELL layer per antinode which is repeated 12 times for the same total of 12 DWELL layers. We demonstrate the lasing performance of the two structures as a function of distance from the center of the wafer and use known radial composition gradients in the molecular beam epitaxy reactor to achieve 50 nm continuous wavelength variation in the 4 × 3 structure and 60 nm in the 12 × 1 structure. We also demonstrate that the performance of the 12 × 1 structure is significantly improved compared to the 4 × 3 structure for all measured laser parameters, possibly due to increased pump absorption in the former structure's thicker barriers.
Autors: Albrecht, A. R.;Stintz, A.;Jaeckel, F. T.;Rotter, T. J.;Ahirwar, P.;Patel, V. J.;Hains, C. P.;Lester, L. F.;Malloy, K. J.;Balakrishnan, G.;
Appeared in: IEEE Journal of Selected Topics in Quantum Electronics
Publication date: Dec 2011, volume: 17, issue:6, pages: 1787 - 1793
Publisher: IEEE
 
» 19-Gb/s adaptively modulated optical OFDM transmission by separated I/Q baseband delivery using 1 GHz RSOAs
Abstract:

Highlights

? We have demonstrated 19-Gb/s optical OFDM signal transmission over 23-km SMF. ? This system based on separated I/Q baseband delivery using 1 GHz RSOAs. ? This transmission technique is applied to halve the sampling speed requirements. ? Adaptive modulation with pre-emphasis and compensation are used to optimize. ? The proposed technique would be useful to colorless ONU based on 1 GHz RSOAs.


Autors: 19-Gb/s transmission over 23-km SMF is demonstrated based on 1-GHz bandwidth limited RSOAs with adaptively modulated optical OFDM. A novel baseband transmission technique is applied to halve the sampling speed requirements compared to traditional OFD
Appeared in: Optical Fiber Technology
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» 20 A to 100 mA DC–DC Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm CMOS
Abstract:
Pub DtlA DC-DC buck converter capable of handling loads from 20 A to 100 mA and operating off a 2.8–4.2 V battery is implemented in a 45 nm CMOS process. In order to handle high battery voltages in this deeply scaled technology, multiple transistors are stacked in the power train. Switched-Capacitor DC–DC converters are used for internal rail generation for stacking and supplies for control circuits. An DAC pulse width modulator with sleep mode control is proposed which is both area and power-efficient as compared with previously published pulse width modulator schemes. Both pulse frequency modulation (PFM) and pulse width modulation (PWM) modes of control are employed for the wide load range. The converter achieves a peak efficiency of 75% at 20 A, 87.4% at 12 mA in PFM, and 87.2% at 53 mA in PWM.
Autors: Bandyopadhyay, S.;Ramadass, Y. K.;Chandrakasan, A. P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 2807 - 2820
Publisher: IEEE
 
» 20% Efficient Passivated Large-Area Metal Wrap Through Solar Cells on Boron-Doped Cz Silicon
Abstract:
We present metal wrap through passivated emitter and rear solar cells (MWT-PERC) on monocrystalline p-type silicon featuring laser-doped selective emitter structures in combination with either screen-printed (SP) or more advanced dispensed front side contacts. Thermally grown silicon oxide layers serve as emitter and rear surface passivation. Laser-fired contacts connect the SP aluminum rear contact to the silicon base. The rear side features solder contacts for both polarities. Conversion efficiency values of 20.6% for float-zone and 20.1% for Czochralski-grown silicon (not stabilized) are achieved on large-area cells with 149 wafer size. These are within the highest values reported for large-area p-type silicon solar cells to date. Analytical modeling enables a consistent description of the devices and allows for determining the dominating loss mechanisms.
Autors: Lohmuller, E.;Thaidigsmann, B.;Pospischil, M.;Jager, U.;Mack, S.;Specht, J.;Nekarda, J.;Retzlaff, M.;Krieg, A.;Clement, F.;Wolf, A.;Biro, D.;Preu, R.;
Appeared in: IEEE Electron Device Letters
Publication date: Dec 2011, volume: 32, issue:12, pages: 1719 - 1721
Publisher: IEEE
 
» 20 nm Gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2source/drain
Abstract:

Highlights

? 20 nm Gate length SB-MOSFETs with NiSi and epitaxial-NiSi2S/Dcontacts were compared. ? Simulations and experimental show limited scaling behavior of MOSFETs. ? Implantation into silicide process improves the device performance. ? Low contact resistivity of epitaxial NiSi2enhances the on-current.


Autors: Schottky barrier (SB)-MOSFETs with NiSi and epitaxial NiSi2S/Dcontacts with gate lengths as small as 20 nm are presented. Epitaxial NiSi2FETs show higher on-currents than corresponding NiSi devices due to its lower SB height. A striking observation i
Appeared in: Solid-State Electronics
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» 24 GHz Balanced Doppler Radar Front-End With Tx Leakage Canceller for Antenna Impedance Variation and Mutual Coupling
Abstract:
A new balanced Doppler radar front-end architecture with Tx leakage canceller for antenna impedance variation and antenna mutual coupling is proposed. Consisting of two quadrature hybrids, two ring hybrids and 4-port feed antenna system, the proposed balanced structure achieves high transmit/receive (Tx/Rx) isolation stable to antenna impedance variation and antenna mutual coupling. The proposed 4-port feed antenna is configured by dual fed 2 1 patch array having 6.97 dBi and 5.65 dBi of measured Tx and Rx peak gain, respectively. In addition, the proposed architecture undergoes no power loss in both transmit and receive paths, and obtains the measured Tx/Rx isolation of more than 45 dB stable at 24 GHz regardless of the load variation. The proposed architecture that can determine the speed as low as 0.5 mm/s (0.078 Hz Doppler shift) is theoretically and experimentally analyzed for high isolation despite of antenna mismatch.
Autors: Lee, H. L.;Lim, W.-G.;Oh, K.-S.;Yu, J.-W.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2011, volume: 59, issue:12, pages: 4497 - 4504
Publisher: IEEE
 
» 2DPCA-based method for place classification using range scan
Abstract:
A method for place classification from a range scan is proposed, where the range scan is characterised with a 2D histogram of pairwise angular distance. The proposed method uses two-dimensional principal component analysis (2DPCA), a feature extraction and data representation technique, to train a set of classifiers with 2D histograms of range scans.
Autors: S. Park;S.-K. Park;
Appeared in: Electronics Letters
Publication date: Dec 2011, volume: 47, issue:25, pages: 1364 - 1366
Publisher: IEEE
 
» 3-D Space Modulation With Voltage Balancing Capability for a Cascaded Seven-Level Converter in a Solid-State Transformer
Abstract:
The solid-state transformer (SST) is an alternative for existing power transformer due to its advantage in low volume, bidirectional power flow, power factor control, and fault management capability. In this paper, a three-stage cascaded-type SST, which utilizes the cascaded seven-level rectifier as the interface with a 7.2 kV distribution system, is presented. In the described system, dc voltage balancing of the cascaded seven-level rectifier is a necessity for stable operation. Previous PI-based voltage balancing control has intrinsic disadvantage in compromise between fast regulation and PI saturation. Besides, the addition of a voltage balancing controller may also change the system loop and bring unexpected performance. This paper aims at giving an alternative view of voltage balancing mechanism in a cascaded multilevel converter. A novel 3-D space modulation technique with voltage balancing capability is proposed for a cascaded seven-level rectifier stage of SST. By choosing the most suitable switching pairs for dc voltage balance, this method has a very good voltage balancing capability that can realize fast regulation of dc voltages in all operation modes, including unity power factor operation, capacitive operation, and inductive operation. Simulation and experimental results in a scaled-down system are provided to verify the effectiveness of the proposed method.
Autors: She, X.;Huang, A. Q.;Wang, G.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Dec 2011, volume: 26, issue:12, pages: 3778 - 3789
Publisher: IEEE
 
» 3.15 dB NF, 7.2 mW 3–9 GHz CMOS ultra-wideband receiver front-end
Abstract:
A 3–9 GHz receiver front-end (RFE) with excellent stop-band rejection by 0.18 μm CMOS technology is demonstrated. A pre-filter is used to achieve high stop-band rejection and good RF-port input matching. An output buffer with a lowpass filter is used to enhance the conversion gain and to suppress the high-frequency noise and leakage. In the low-noise mode, the RFE consumes 7.2 mW and achieves conversion gain (CG) of 20.21± 1.97 dB, a minimum noise figure (NF) of 3.15 dB, and input 1 dB compression point (P1dB) of – 16.3 dBm. It is believed that this is the lowest NF ever reported for a CMOS UWB RFE with power consumption lower than 10 mW. In the high-gain mode, the RFE consumes 19.35 mW and achieves a high and flat CG of 32.63 ± 1.55 dB.
Autors: Chang, J.-F.;Lin, Y.-S.;
Appeared in: Electronics Letters
Publication date: Dec 2011, volume: 47, issue:25, pages: 1401 - 1402
Publisher: IEEE
 
» 3D Rotations
Abstract:
The author describes four methods to achieve rotations using elementary concepts from algebra, analytic geometry, and calculus.
Autors: Taubin, G.;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Dec 2011, volume: 31, issue:6, pages: 84 - 89
Publisher: IEEE
 
» 4–8 GHz Near-Field Probe for Scanning of Apertures and Multimode Waveguides
Abstract:
In this letter, a high-resolution 4-to-8 GHz-matched dipole probe for near-field mapping of apertures and oversized waveguides is presented. Thanks to its high selectivity, the proposed structure is able to measure with high precision a single linear component of the -field in the reactive near-field zone. Simulations and measurements of the reflection coefficient and of the field patterns of a horn antenna and an oversized waveguide are reported in the last section.
Autors: Russo, I.;Menzel, W.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2011, volume: 21, issue:12, pages: 688 - 690
Publisher: IEEE
 
» Characterization of AlGaN/GaN HFET With p-Type Body Layer
Abstract:
We fabricated AlGaN/GaN heterostructure field-effect transistors (HFETs) with p-GaN substrate layers and p-type ohmic contacts (p-sub HFETs) and measured the substrate-bias -dependent threshold voltage variation. From this characteristic, the acceptor concentration in the buffer layer was determined. This method for doping profile measurement has been widely used for Si MOSFETs. By applying this method to AlGaN/GaN HFETs stressed by negative substrate bias or UV light irradiation, buffer layer deep traps were specifically investigated. The deep traps in the buffer layer were determined to be hole traps with a concentration of . The energy level was estimated to be approximately 0.71–0.95 eV above the valence band.
Autors: Hu, C.-Y.;Kikuta, D.;Sugimoto, M.;Ao, J.-P.;Ohno, Y.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2011, volume: 58, issue:12, pages: 4265 - 4271
Publisher: IEEE
 
» Control of an Atomic Force Microscope Microcantilever: A Sensorless Approach
Abstract:
The scan rate and image resolution of the atomic force microscope (AFM) operating in tapping-mode may be improved by modifying the quality factor of the AFM microcantilever according to the sample type and imaging environment. Piezoelectric shunt control is a new method of controlling the factor of a piezoelectric self-actuating AFM microcantilever. The mechanical damping of the microcantilever is controlled by an electrical impedance placed in series with the tip oscillation circuit. A synthetic impedance was designed to allow easy modification of the control parameters which may vary with environmental conditions. The proposed techniques are experimentally demonstrated to reduce the factor of an AFM microcantilever from 297.6 to 35.5. AFM images obtained using this method show significant improvement in both scan rate and image quality. [2011-0123]
Autors: Fairbairn, M. W.;Moheimani, S. O. R.;Fleming, A. J.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Dec 2011, volume: 20, issue:6, pages: 1372 - 1381
Publisher: IEEE
 
» -Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology
Abstract:
This paper presents two fully integrated binary phase-shift keying (BPSK) and quadrature phase-shift keying (QPSK) transceivers operating at -band [ (BPSK), and 87 GHz (QPSK)]. Including RF front-end, Costas-loop-based carrier and data recovery, and antenna assembly technique, the BPSK transceiver prototype achieves a 2.5-Gb/s data link with while consuming 202 mW (Tx) and 125 mW (Rx) from a 1.2-V supply. The QPSK TRx achieves a 2.5-Gb/s data link with while consuming 212 mW (Tx) and 166 mW (Rx) from a 1.2-V supply. Both cases are measured with link distance of 1 m and antenna gain of 24 dBi.
Autors: Huang, S.-J.;Yeh, Y.-C.;Wang, H.;Chen, P.-N.;Lee, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 3033 - 3046
Publisher: IEEE
 
» Double-Heterostructure Detector With Three Ultraviolet Spectral Band Responses
Abstract:
In this paper, an double-heterostructure (DH) p-p-i-n ultraviolet (UV) detector is designed based on the influence of the polarization effect on the AlGaN/GaN heterostructure. The influences of doping concentration and Al composition in AlGaN on the photoelectric response of the UV detector are calculated and discussed by selfconsistent solving of the Schrödinger–Poisson equation and solving the carriers' continuity equation. The calculation results show that the DH p-p-i-n UV detector presents a three-UV-response wavelength region with increasing bias voltage, and the three-UV-response wavelength region can be abnormally adjusted from 200 to 365 nm by changing the Al composition in the and layers. The calculation results are verified by the Korona's experimental testing results at the end of this paper.
Autors: Gao, B.;Liu, H.;Fan, J.;Wang, S.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2011, volume: 58, issue:12, pages: 4290 - 4296
Publisher: IEEE
 
» -Band Bismuth-Doped Fiber Amplifier With Double-Pass Configuration
Abstract:
A Bismuth-doped fiber amplifier (BDFA) in a double-pass configuration is proposed and demonstrated. The BDFA consists of a Bismuth-doped phosphogermanosilicate (BiPGeSiO2) fiber pumped by a Titanium–Sapphire source at 810 nm. The BDFA has an amplified spontaneous emission (ASE) spectrum with a 3-dB bandwidth from 1220 to 1490 nm. The maximum gain of the proposed BDFA is 2.0 dB at an input signal wavelength of 1340 nm and is a gain enhancement of 100% over a similarly configured single-pass BDFA. The proposed BDFA has a higher gain enhancement of 1.7 dB at low input signal powers but decreases to as low as 0.5 dB as the input signal power increases.Pub _bookmark Command="[Quick Mark]"
Autors: Norizan, S. F.;Chong, W. Y.;Harun, S. W.;Ahmad, H.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2011, volume: 23, issue:24, pages: 1860 - 1862
Publisher: IEEE
 
» Filtering for Discrete-Time State-Delayed Systems With Finite Frequency Specifications
Abstract:
This article researches the problem of finite frequency (FF) filtering for linear discrete-time state-delayed systems. The disturbance is assumed to reside in low/middle/high frequency ranges. To reduce the conservatism of the results, delay-partitioning idea is used to derive a new FF bounded real lemma (BRL). By applying the generalized Kalman-Yakubovich-Popov lemma, two equivalent approaches to the proof of the proposed FF BRL are given, respectively, starting from transfer function and Lyapunov-Krasovskii functional. A new FF filter design method is proposed in terms of solving a set of linear matrix inequalities. Finally, a numerical example clearly demonstrates the merits and effectiveness of the proposed method.
Autors: Gao, H.;Li, X.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Dec 2011, volume: 56, issue:12, pages: 2935 - 2941
Publisher: IEEE
 
» A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration
Abstract:
A digital phase-locked loop (DPLL) employs noise cancellation to mitigate performance degradation due to noise on the ring oscillator supply voltage. A deterministic test signal-based digital background calibration is used to accurately set the cancellation gain and thus achieve accurate cancellation under different process, voltage, temperature, and operating frequency conditions. A hybrid, linear proportional control and bang–bang digital integral control, is used to obviate the need for a high-resolution time-to-digital converter and reduce jitter due to frequency quantization error. Fabricated in 0.13 m CMOS technology, the DPLL operates from a 1.0 V supply and achieves an operating range of 0.4-to-3 GHz. At 1.5 GHz, the DPLL consumes 2.65 mW power wherein the cancellation circuitry consumes about 280 W. The proposed noise cancellation scheme reduces the DPLL's peak-to-peak jitter from 330 to 50 ps in the presence of a 30 mV 10 MHz supply noise tone, and the DPLL peak-to-peak jitter is 50 ps in the absence of any supply noise. The DPLL occupies an active die area of 0.08 mm , of which the calibration logic and cancellation circuitry occupy only 12.5%.
Autors: Elshazly, A.;Inti, R.;Yin, W.;Young, B.;Hanumolu, P. K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 2759 - 2771
Publisher: IEEE
 
» A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
Abstract:
Pub DtlA reference-less highly digital half-rate clock and data recovery (CDR) circuit with improved tolerance to input duty cycle error is presented. Using a chain of frequency dividers, the proposed frequency detector produces a known sub-harmonic tone from the incoming random data. A digital frequency-locked loop uses the extracted tone, and drives the oscillator to any sub-rate of the input data frequency. The early/late outputs of a conventional half-rate bang-bang phase detector are used to determine the duty-cycle error in the incoming random data and adjust the oscillator clock phases to maximize receiver timing margins. Fabricated in 0.13 m CMOS technology, the prototype digital CDR operates without any errors from 0.5 Gb/s to 2.5 Gb/s. At 2 Gb/s, the prototype consumes 6.1 mW power from a 1.2 V supply. The proposed clock-phase calibration is capable of correcting upto 20% of input data duty-cycle error.
Autors: Inti, R.;Yin, W.;Elshazly, A.;Sasidhar, N.;Hanumolu, P. K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 3150 - 3162
Publisher: IEEE
 
» A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta–Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation
Abstract:
A second-order continuous-time delta–sigma modulator incorporating a proposed 4-bit asynchronous sequential quantizer and a digital excess-loop-delay (ELD) compensation technique is presented. The sequential operation of the proposed quantizer facilitates low power consumption while the hardware-efficient digital compensation technique allows the modulator to accommodate ELD. With a 1-MHz bandwidth and a 60-MHz sampling rate, the measured peak signal-to-noise-and-distortion ratio and dynamic range are 62 and 67 dB, respectively. Fabricated in a 90-nm CMOS, this chip consumes only 0.89 mW from a 1.2-V supply.
Autors: Weng, C.-H.;Lin, C.-C.;Chang, Y.-C.;Lin, T.-H.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2011, volume: 58, issue:12, pages: 867 - 871
Publisher: IEEE
 
» A 1.0625 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS
Abstract:
A 14.025 Gb/s multi-media transceiver employs on-die Rx AC coupling with baseline wander correction and equalizes up to 26 dB insertion loss at 14.025 Gb/s with a linear equalizer, 10-tap DFE, and 4-tap Tx FIR filter in SST driver. The proposed techniques enable direct feedback for 1st-tap ISI cancellation, and positions of four DFE taps to be adapted over the range of 7 to 38 UI. The prototype is realized in 40 nm CMOS, consumes 410 mW at worst case, and has passed 16GFC compliance tests at 14.025 Gb/s.
Autors: Zhong, F.;Quan, S.;Liu, W.;Aziz, P.;Jing, T.;Dong, J.;Desai, C.;Gao, H.;Garcia, M.;Hom, G.;Huynh, T.;Kimura, H.;Kothari, R.;Li, L.;Liu, C.;Lowrie, S.;Ling, K.;Malipatil, A.;Narayan, R.;Prokop, T.;Palusa, C.;Rajashekara, A.;Sinha, A.;Zhong, C.;Zhang,
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 3126 - 3139
Publisher: IEEE
 
» A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique
Abstract:
This paper presents circuit techniques to improve the efficiency of high-current LED drivers. An error-averaged, senseFET-based current sensing technique is used to regulate the LED current accurately. Because the proposed scheme eliminates the series current-regulation element present in all conventional LED drivers, it greatly improves efficiency and reduces cost. The converter operates in three different operating modes, namely buck, buck-boost, and boost modes, and achieves high efficiency over the entire Li-Ion battery range (3–5.5 V). Fabricated in 0.5- CMOS process, the prototype occupies an active area of 5 . At 1.2-A LED current, the driver achieves an efficiency improvement of over 13% compared to current-regulation-element-based LED drivers. Measured LED current accuracy is better than 2.8% over the entire range of the battery and its standard deviation measured across seven devices is less than 1.6%. The peak efficiencies are 90.7% and 86% at 600- and 1200-mA currents, respectively.
Autors: Rao, S.;Khan, Q.;Bang, S.;Swank, D.;Rao, A.;McIntyre, W.;Hanumolu, P. K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 2772 - 2783
Publisher: IEEE
 
» A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS
Abstract:
A 7-bit 1.5-GS/s analog-to-digital converter (ADC) incorporates redundancy, reassignment, and digital correction to reduce the complexity of analog functions and the required accuracy compared to traditional Flash ADCs. Deliberate and random mismatch is used to set the desired trip points, achieving a 600-mVpp differential input signal range. The need for a low-impedance high-precision resistor reference ladder is eliminated, and comparator performance is decoupled from matching requirements, so that small and fast dynamic comparators can be used. New analysis discusses the optimum combination of random and deliberate comparator offset to achieve a target effective number of bits (ENOB). This prototype ADC has the highest ENOB and highest sampling frequency of any reported Flash ADC utilizing redundancy. A proof-of-concept prototype achieves no missing codes, 46.6-dB spurious-free dynamic range, and 6.05-bit ENOB at Nyquist input frequency. Fabricated in 90-nm digital CMOS, with a core area of 1.2 , the device consumes 204 mW from a 1.2-V/0.9-V analog/digital supply.
Autors: Pernillo, J.;Flynn, M. P.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2011, volume: 58, issue:12, pages: 837 - 841
Publisher: IEEE
 
» A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link
Abstract:
The first CMOS “gearbox LSI” based on 65-nm CMOS technology—namely, a 2-W 100-Gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer—was developed. Its power dissipation is 75% lower than that of a conventional SiGe-based gearbox LSI. To develop this low-power gearbox LSI, the power dissipation of its 25-Gb/s interface is decreased to 14 mW/Gb/s by three circuit schemes: maximizing the use of CMOS circuits, adopting a low-power circuit architecture for a current-mode-logic (CML) circuit, and minimizing clock distribution by using a flip-flop with a single-clock operation and a PLL with phase rotation for each channel. The 25-Gb/s interface in the LSI provides a transmitter output with sufficient eye opening and achieved minimum input sensitivity of 34.4-mV (peak-to-peak).
Autors: Ono, G.;Watanabe, K.;Muto, T.;Yamashita, H.;Fukuda, K.;Masuda, N.;Nemoto, R.;Suzuki, E.;Takemoto, T.;Yuki, F.;Yagyu, M.;Toyoda, H.;Kono, M.;Kambe, A.;Umai, S.;Saito, T.;Nishimura, S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 3101 - 3112
Publisher: IEEE
 
» A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With 70 dB SFDR up to 500 MHz
Abstract:
A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 750 . It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply.
Autors: Tseng, W.-H.;Fan, C.-W.;Wu, J.-T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 2845 - 2856
Publisher: IEEE
 
» A 12.5+12.5 Gb/s Full-Duplex Plastic Waveguide Interconnect
Abstract:
A new interconnect solution with plastic waveguide is demonstrated. The system consists of a pair of transceivers and a plastic waveguide. Millimeter wave signal is transmitted in a low-cost long piece of solid plastic dielectric acting as a waveguide. The plastic waveguide medium offers a large bandwidth for data communication using mm-wave carrier frequencies. Plastic waveguide interconnects do not require costly electrical-to-optical and optical-to-electrical conversion devices or precise alignment and offer longer transmission distances than wireless solutions due to better field confinement and lower path loss. Multiple plastic waveguides can be used in parallel and the modulated data at different frequencies can be multiplexed to increase the data rate. The demonstrated transceiver chips operate at carrier frequencies of 57 GHz and 80 GHz, and are fabricated in 40 nm low-power logic CMOS. The total area and power consumption of two transceivers are 0.41 mm and 140 mW, respectively. The fabricated demonstrator with Yagi-couplers achieves full-duplex transmission of 12.5 Gb/s ASK modulated signal in each direction over the 120 mm polystyrene waveguide with no equalization. The observed bit error rates for both channels are less than 10 for a PRBS length of 2 1 at the total data rate of 25 Gb/s. This paper shows the feasibility of the plastic waveguide interconnect as a promising alternative to electrical, optical, and wireless interconnects.
Autors: Fukuda, S.;Hino, Y.;Ohashi, S.;Takeda, T.;Yamagishi, H.;Shinke, S.;Komori, K.;Uno, M.;Akiyama, Y.;Kawasaki, K.;Hajimiri, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 3113 - 3125
Publisher: IEEE
 
» A 122 GHz Sub-Harmonic Mixer With a Modified APDP Topology for IC Integration
Abstract:
This letter presents a modified passive subharmonic mixer (SHM) topology based on an anti-parallel-diode-pair (APDP). It features a differential intermediate frequency output facilitating IC integration and improving common-mode noise rejection. An example 122 GHz SHM has been designed and tested in a 0.13 SiGe BiCMOS technology for a 122 GHz radar IC. SiGe HBT transistors have been diode-connected to form the APDP. The example SHM exhibits a conversion loss of 8 dB with a 5 dBm LO pumping power. The measured bandwidth extends from 117 to 124 GHz, adequately covering the 122–123 GHz ISM band, while the input 1 dB compression point and noise figure were measured to be 5 dBm and 8.5 dB respectively. Due to its superior 1/f noise performance and high linearity, the mixer is especially well suited to zero intermediate frequency radars.
Autors: Sun, Y.;Scheytt, C. J.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2011, volume: 21, issue:12, pages: 679 - 681
Publisher: IEEE
 
» A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- Integrated Jitter at 4.5-mW Power
Abstract:
This paper introduces a fractional-N digital PLL based on a single-bit TDC. A digital-to-time converter, placed in the feedback path, cancels out the quantization noise introduced by the dithering of the frequency divider modulus and permits to achieve low noise at low power. The PLL is implemented in a standard 65-nm CMOS process. It achieves 102-dBc/Hz phase noise at 50-kHz offset and a total absolute jitter below 560 (integrated from 3 kHz to 30 MHz), even in the worst-case of a 42-dBc in-band fractional spur. The synthesizer tuning range spans from 2.92 GHz to 4.05 GHz with 70-Hz resolution. The total power consumption is 4.5 mW, which leads to the best jitter-power trade-off obtained with a fractional-N synthesizer. The synthesizer demonstrates the capability of frequency modulation up to 1.25-Mb/s data rate.
Autors: Tasca, D.;Zanuso, M.;Marzin, G.;Levantino, S.;Samori, C.;Lacaita, A. L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 2745 - 2758
Publisher: IEEE
 
» A 3D Printed Dry Electrode for ECG/EEG Recording
Abstract:

Highlights

? 3D printed dry electrodes are functional for both ECG and EEG recordings. ? 3D printed dry electrodes do not require skin preparation nor gel application. ? 3D printed dry electrodes are suitable for mass production. ? No skin penetration is needed for a correct bio-signal recording. ? No micro-machinery or silicon processes are needed.p


Autors: In this paper, the design, fabrication and testing of a 3D printed dry electrode is proposed. 3D printing represents an authentic breakthrough for the development and mass production of dry medical electrodes. In fact, it allows a fast and low cost p
Appeared in: Sensors and Actuators A: Physical
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» A 4 GHz Continuous-Time ADC With 70 dB DR and 74 dBFS THD in 125 MHz BW
Abstract:
A 4 GHz third-order continuous-time ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and 74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 including the modulator, clock circuitry and decimation filter.
Autors: Bolatkale, M.;Breems, L. J.;Rutten, R.;Makinwa, K. A. A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 2857 - 2868
Publisher: IEEE
 
» A 40-mm High-Temperature Superconducting Surface Resonator in a 3-T MRI System: Simulations and Measurements
Abstract:
In this paper, the Ansoft high-frequency structure simulation (HFSS) was adapted to investigate the unloaded quality-factor value of the radio-frequency (RF) receiving resonator. This paper focused on the materials aspects, and a comparison between electromagnetic stimulations and measurement was conducted. A 40 mm in diameter (Bi-2223) tape high- superconducting RF resonator in 3 T was stimulated and built. The simulation models were established according to the experimental dimension of the Bi-2223 surface resonator. Measurements show that the Bi-2223 surface resonator at 77 K provides a gain of 3.84-fold signal-to-noise ratio on phantom images over that of the homemade copper resonator at 300 K. Measuring results were in accordance with predicted ones, and the difference between the predicted SNR gains and measured SNR gains is 1%. This paper suggests that using a Bi-2223 surface resonator at 77 K could be more useful for magnetic resonance imaging coils than a copper surface resonator at 300 K.
Autors: Lin, I.-T.;Yang, H.-C.;Chen, J.-H.;
Appeared in: IEEE Transactions on Applied Superconductivity
Publication date: Dec 2011, volume: 21, issue:6, pages: 3574 - 3580
Publisher: IEEE
 
» A 46- Self-Calibrated Gigahertz VCO for Low-Power Radios
Abstract:
This brief presents a 46 0.8-2 GHz tunable oscillator with built-in self-calibrated process, supply voltage, and temperature compensation for applications in low-power radios. With single-point current calibration at room temperature, the proposed voltage-controlled oscillator (VCO) achieves 2.24% frequency accuracy against process variation, 1.6% frequency shift over 0.85- to 1.15-V supply voltage, and 167- temperature sensitivity between and 76 . The sub-135-pJ on-chip self-calibration is based on a successive approximation scheme. Our design shows improved process variation tolerance, improved supply sensitivity, and improved temperature sensitivity, as compared with the free-running VCO without self-calibration. Measurements are taken from 94 chips fabricated in two different lots in Taiwan Semiconductor Manufacturing Company 65-nm CMOS process.
Autors: Zhang, X.;Mukhopadhyay, I.;Dokania, R.;Apsel, A. B.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2011, volume: 58, issue:12, pages: 847 - 851
Publisher: IEEE
 
» A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS
Abstract:
This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register (SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The sampling front-end consists of four interleaved T/Hs at 650 MS/s that are optimized for timing accuracy and sampling linearity, while the back-end consists of four ADC arrays, each consisting of 16 10b current-mode non-binary SAR ADCs. The interleaving hierarchy allows for many ADCs to be used per T/H and eliminates distortion stemming from open loop buffers interfacing between the front-end and back-end. Startup on-chip calibration deals with offset and gain mismatches as well as DAC linearity. Measurements show that the prototype ADC achieves an SNDR of 48.5 dB and a THD of less than 58 dB at Nyquist with an input signal of 1.4 . An estimated sampling clock skew spread of 400 fs is achieved by careful design and layout. Up to 4 GHz an SNR of more than 49 dB has been measured, enabled by the less than 110 fs rms clock jitter. The ADC consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm .
Autors: Doris, K.;Janssen, E.;Nani, C.;Zanikopoulos, A.;van der Weide, G.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 2821 - 2833
Publisher: IEEE
 
» A 60 GHz Antenna-Referenced Frequency-Locked Loop in 0.13 m CMOS for Wireless Sensor Networks
Abstract:
This paper presents a 60 GHz frequency-locked loop (FLL) for wireless sensor network applications. The FLL incorporates an on-chip patch antenna as both a radiator and a frequency reference, realizing a compact and low-cost solution for non-coherent energy detection radios. To further reduce the size of a wireless sensor node, the area beneath the patch antenna ground plane is utilized for analog and digital baseband circuitry integration. A sensor array was implemented beneath the antenna ground plane to measure the spatial coupling from the antenna to the circuitry beneath it. The FLL is fabricated in a 0.13 m CMOS technology. The operating frequency is locked to the maximum-efficiency point of the antenna with a mean of 59.34 GHz and standard deviation of 195 MHz over process variation. The circuit and antenna occupies 2.85 mm and consumes 29.6 mW.
Autors: Huang, K.-K.;Wentzloff, D. D.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 2956 - 2965
Publisher: IEEE
 
» A 60 GHz CMOS Power Amplifier With Built-in Pre-Distortion Linearizer
Abstract:
A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a of 10.72 dBm and of 7.3 dBm from 1.2 V supply. After linearization, the has been doubled from 7.3 to 10.2 dBm and the operating PAE at consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.
Autors: Tsai, J.-H.;Wu, C.-H.;Yang, H.-Y.;Huang, T.-W.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2011, volume: 21, issue:12, pages: 676 - 678
Publisher: IEEE
 
» A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c
Abstract:
This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The transceiver has been fabricated in a standard 65-nm CMOS process. It includes a receiver with a 17.3-dB conversion gain and less than 8.0-dB noise figure, a transmitter with a 18.3-dB conversion gain, a 9.5-dBm output 1 dB compression point, a 10.9-dBm saturation output power and 8.8-% power added efficiency. The 60-GHz frequency synthesizer is implemented by a combination of a 20-GHz PLL and a 60-GHz quadrature injection-locked oscillator, which achieves a phase noise of 95 dBc/Hz@1 MHz-offset at 60 GHz. The transceiver realizes IEEE802.15.3c full-rate wireless communication for all 16QAM/8PSK/QPSK/BPSK modes, and the communication distances with the full data rate using 2.16-GHz bandwidth, measured with an antenna built in the package, are 2.7-m (BPSK/QPSK) and 0.2-m (8PSK/16QAM). The measured maximum data rates are 8 Gb/s in QPSK mode and 11 Gb/s in 16QAM mode over a 5 cm wireless link within a bit error rate (BER) of 10 . The transceiver consumes 186 mW from a 1.2-V supply voltage while transmitting and 106 mW from 1.0-V supply voltage while receiving. Both transmitter and receiver are driven by a 20-GHz PLL, which consumes 66 mW, including output buffer, from a 1.2-V supply voltage.
Autors: Okada, K.;Li, N.;Matsushita, K.;Bunsen, K.;Murakami, R.;Musa, A.;Sato, T.;Asada, H.;Takayama, N.;Ito, S.;Chaivipas, W.;Minami, R.;Yamaguchi, T.;Takeuchi, Y.;Yamagishi, H.;Noda, M.;Matsuzawa, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 2988 - 3004
Publisher: IEEE
 
» A 65 nm CMOS 4-Element Sub-34 mW/Element 60 GHz Phased-Array Transceiver
Abstract:
Pub DtlThis paper describes a low power and element-scalable 60 GHz 4-element phased array transceiver implemented in a standard 65 nm CMOS process. Using a 1.2 V supply, the array consumes 34 mW/element including LO synthesis and distribution. Energy and area efficiency are achieved by utilizing a baseband phase shifting architecture, holistic impedance optimization, and lumped-element based design. Each receiver (RX) element provides 24 dB of gain with an average noise figure (NF) of 6.8 dB while the total saturated output power of the transmitter (TX) is 4.5 dBm. The array achieves 360 of phase shifting range with a worst-case measured phase resolution of 6 bits (TX)/ 5 bits (RX) while maintaining amplitude variations less than 0.5 dB.
Autors: Tabesh, M.;Chen, J.;Marcu, C.;Kong, L.;Kang, S.;Niknejad, A. M.;Alon, E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 3018 - 3032
Publisher: IEEE
 
» A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications
Abstract:
A fully integrated WirelessHD compatible 60-GHz transceiver module in 65-nm CMOS process is presented, covering the four standard channels. The silicon die is flip-chipped on top of a low-cost HTCC module which also includes an external 65-nm CMOS PA and large beamwidth antennas targeting industrial manufacturability. The module achieves a 16QAM OFDM modulation wireless link with 3.8 Gbps over 1 m. The transceiver consumption is 454 mW in RX mode (including PLL) and 1090 mW in TX mode (including PLL and external PA).
Autors: Siligaris, A.;Richard, O.;Martineau, B.;Mounet, C.;Chaix, F.;Ferragut, R.;Dehos, C.;Lanteri, J.;Dussopt, L.;Yamamoto, S. D.;Pilard, R.;Busson, P.;Cathelin, A.;Belot, D.;Vincent, P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 3005 - 3017
Publisher: IEEE
 
» A Behavior-Authoring Framework for Multiactor Simulations
Abstract:
Interest has been growing in the behavioral animation of autonomous actors in virtual worlds. However, authoring complicated interactions between multiple actors in a way that balances control flexibility and automation remains a considerable challenge. A proposed behavior-authoring framework gives users complete control over the domain of the system: the state space, action space, and cost of executing actions. To specialize actors, the framework uses effect and cost modifiers, which modify existing action definitions, and constraints, which prune action choices in a state-dependent manner. The framework groups actors with common or conflicting goals to form a composite domain, and a multiagent planner generates complicated interactions between multiple actors. The Web extra is a video that shows how multiactor simulations should aim to strike a happy medium between the automation of generation and the flexibility of specification.
Autors: Kapadia, M.;Singh, S.;Reinman, G.;Faloutsos, P.;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Dec 2011, volume: 31, issue:6, pages: 45 - 55
Publisher: IEEE
 
» A bi-axial magnetoelectric vibration energy harvester
Abstract:
This article reports on a vibration energy harvesting approach that uses a magnetoelectric (ME) transducer to harvest energy from bi-axial vibrations. A bi-axial oscillator is created using a permanent-magnet/ball-bearing arrangement, which has the added benefit of permitting a relatively compact design. The magnet produces a bi-axial restoring force on the bearing, and as the bearing oscillates it steers magnetic field through the transducer thereby producing an oscillating charge that can be harvested. A simple laboratory demonstrator of a bi-axial ME harvester was created using a magnetostrictive/piezoelectric laminate transducer, and was shown to produce a peak rms power of 121 ?W from an rms acceleration of 61 mG at 9.8 Hz.
Autors: Scott D. Moss, Joshua E. McLeod, Ian J. Powlesland, Steve C. Galea
Appeared in: Sensors and Actuators A: Physical
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» A Bilateral Ankle Manipulator to Investigate Human Balance Control
Abstract:
The ankles play an important role in human balance. In most studies investigating balance control the contribution of the left and right leg is not separated. However, in certain pathologies such as stroke and Parkinson's disease, balance control can be asymmetric. Here, a bilateral ankle perturbator (BAP) is presented, which applies support surface rotations to both ankles independently. The device consists of two small foot-size support surfaces, which are independently actuated. The BAP device can operate in either angle or torque control mode. The device is able to apply support surface rotations up to 8.6 with a bandwidth of 42 Hz. Additionally the platforms can be replaced by 6-DoF force plates to measure the center of pressure underneath each foot. With the optional force plates the bandwidth decreases to 16 Hz as a result of the additional weight. Two possible applications of the device to investigate human balance control are demonstrated: ankle stiffness by applying minimum jerk profiles and sensory reweighting of the proprioceptive information. In conclusion, we developed a bilateral ankle perturbator which is able to apply support surface rotations to both ankles independently. The major application of the device will be to investigate the contribution of both ankles to human balance control, and the interactions in balance control between both legs.
Autors: Schouten, A. C.;Boonstra, T. A.;Nieuwenhuis, F.;Campfens, S. F.;van der Kooij, H.;
Appeared in: IEEE Transactions on Neural Systems and Rehabilitation Engineering
Publication date: Dec 2011, volume: 19, issue:6, pages: 660 - 669
Publisher: IEEE
 
» A Bio-Inspired Swarming Algorithm for Decentralized Access in Cognitive Radio
Abstract:
The goal of this paper is to propose a bio-inspired radio access mechanism for cognitive networks mimicking the behavior of a flock of birds swarming in search for food in a cohesive fashion without colliding with each other. The equivalence between swarming and radio resource allocation is established by modeling the interference distribution in the resource domain, e.g., frequency and time, as the spatial distribution of food, while the position of the single bird represents the radio resource chosen by each radio node. The swarming mechanism is enforced by letting every node allocate its resources (power/bits) in the time-frequency regions where the interference is minimum (the food density is maximum), avoiding collisions with other nodes (birds), yet limiting the spread in the time-frequency domain (i.e., maintaining the swarm cohesion). The solution is given as the distributed minimization of a functional, borrowed from social foraging swarming models, containing the average interference plus repulsion and attraction terms that help to avoid conflicts and maintain cohesiveness, respectively.
Autors: Di Lorenzo, P.;Barbarossa, S.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Dec 2011, volume: 59, issue:12, pages: 6160 - 6174
Publisher: IEEE
 
» A Blast of Activity
Abstract:
The growth of wind power activities within the IEEE power & energy Society (PES) has been nothing short of phenomenal. Those who thought electric power was a mature industry have learned that it is far from that. Wind power has changed the face of the industry and has instigated fundamental changes in the ways power systems are designed and operated. Wind power blurs the traditional distinction between generating resources, which produce power according to dispatch commands from operators, and system load, which is variable and uncertain but predictable by means of forecasts. A lot has been learned, but as wind power penetration continues to increase, the challenges do too. PES has responded with a greatly increased level of wind-related activities.
Autors: Piwko, R.;Bradt, M.;Camm, E.;Ellis, A.;Walling, R.;O'Malley, M.;
Appeared in: IEEE Power and Energy Magazine
Publication date: Dec 2011, volume: 9, issue:6, pages: 26 - 35
Publisher: IEEE
 
» A blind watermarking algorithm based on fractional fourier transform and visual cryptography
Abstract:

Highlights

? A blind watermarking scheme based on FrFT and VC is proposed in this paper. ? The scheme is lossless in nature, i.e. original image is not modified. ? The transform orders of the fractional Fourier transform are used as secret keys. ? Without knowing the correct keys no attacker can extract the correct data. ? The proposed scheme is highly robust and secure.


Autors: This paper presents a robust copyright protection scheme based on fractional Fourier transform (FrFT) and visual cryptography (VC). Unlike the traditional schemes, in our scheme, the original image is not modified by embedding the watermark into the
Appeared in: Signal Processing
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» A Bridgeless Single-Stage Half-Bridge AC/DC Converter
Abstract:
This paper proposes a new bridgeless single-stage half-bridge ac–dc converter for power factor correction. The proposed converter integrates the bridgeless boost rectifier with the asymmetrical pulse-width modulation half-bridge dc–dc converter. The proposed converter provides an isolated dc output voltage without using any full-bridge diode rectifier. Conduction losses are lowered by eliminating the full-bridge diode rectifier. Zero-voltage switching of the power switches reduces the switching power losses. The proposed converter gives a high efficiency, high power factor, and low cost. The effectiveness of the proposed converter is verified on a 250 W (48 V/5.2 A) experimental prototype. The proposed converter achieves a high efficiency of 93.0% and an almost unity power factor for 250 W output power at 90 V line voltage.
Autors: Choi, W.;Yoo, J.-S.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Dec 2011, volume: 26, issue:12, pages: 3884 - 3895
Publisher: IEEE
 
» A broadband and compact asymmetrical backward coupled-line coupler with high coupling level
Abstract:
A new wideband asymmetric microstrip coupled-line coupler with 3 dB coupling value and quadrature phase difference is presented. Compared with the conventional edge-coupled couplers, this structure, consisting of two different transmission lines (interdigital and conventional microstrip transmission lines) as coupled lines, achieves wider operating bandwidth and larger coupling level. The coupled-line length of the proposed structure is approximately?g/4. To characterize the structure, an equivalent circuit model has been established. A 3 dB designed and fabricated coupler with 0.2 mm spacing between coupled lines exhibits an amplitude balance of 2 dB from 2.2 GHz to 4.2 GHz. Good agreements between the full-wave simulation and equivalent circuit model results has been achieved and verified the effectiveness of the proposed circuit model. Also, measurement results have been presented.
Autors: Rasool Keshavarz, Masoud Movahhedi, Abdolali Abdipour
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» A Broadband mm-Wave and Terahertz Traveling-Wave Frequency Multiplier on CMOS
Abstract:
A wideband frequency multiplier that effectively generates and combines the even harmonics from multiple transistors is proposed. It takes advantage of standing-wave formation and loss cancellation in a distributed structure to generate high amplitude signals resulting in high harmonic power. Wide bandwidth operation and odd harmonic cancellation around the center frequency are the inherent properties of this frequency multiplier. Using this methodology, we implemented a frequency doubler that operates from 220 GHz to 275 GHz in a standard 65 nm CMOS process. Output power of 6.6 dBm (0.22 mW) and conversion loss of 11.4 dB are measured at 244 GHz.
Autors: Momeni, O.;Afshari, E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2011, volume: 46, issue:12, pages: 2966 - 2976
Publisher: IEEE
 
» A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories
Abstract:
With the advent of deep-submicrometer VLSI technology, the capacity and performance of semiconductor memory chips is increasing drastically. This advantage also makes it harder to maintain good yield. Diagnostics and redundancy repair methodologies thus are getting more and more important for memories, including embedded ones that are popular in system chips. In this paper, we propose an efficient memory diagnosis and repair scheme based on fail-pattern identification. The proposed diagnosis scheme can distinguish among row, column, and word faults, and subsequently apply the Huffman compression method for fault syndrome compression. This approach reduces the amount of data that need to be transmitted from the chip under test to the automatic test equipment (ATE) without losing fault information. It also simplifies the analysis that has to be performed on the ATE. The proposed redundancy repair scheme is assisted by fail-pattern identification approach and a flexible redundancy structure. The area overhead for our built-in self-repair (BISR) design is reasonable. Our repair scheme uses less redundancy than other redundancy schemes under the same repair rate requirement. Experimental results show that the area overhead of the BISR design is only 4.1% for an 8 K × 64 memory and is in inverse proportion to the memory size.
Autors: Chin-Lung Su;Rei-Fu Huang;Cheng-Wen Wu;Kun-Lun Luo;Wen-Ching Wu;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2011, volume: 19, issue:12, pages: 2184 - 2194
Publisher: IEEE
 
» A Calderón Multiplicative Preconditioner for the PMCHWT Integral Equation
Abstract:
Electromagnetic scattering by penetrable bodies often is modelled by the Poggio-Miller-Chan-Harrington-Wu-Tsai (PMCHWT) integral equation. Unfortunately the spectrum of the operator involved in this equation is bounded neither from above or below. This implies that the equation suffers from dense discretization breakdown; that is, the condition numbers of the matrix resulting upon discretizing the equation rise with the mesh density. The electric field integral equation, often used to model scattering by perfect electrically conducting bodies, is susceptible to a similar breakdown phenomenon. Recently, this breakdown was cured by leveraging the Calderón identities. In this paper, a Calderón preconditioned PMCHWT integral equation is introduced. By constructing a Calderón identity for the PMCHWT operator, it is shown that the new equation does not suffer from dense discretization breakdown. A consistent discretization scheme involving both Rao-Wilton-Glisson and Buffa-Christiansen functions is introduced. This scheme amounts to the application of a multiplicative matrix preconditioner to the classical PMCHWT system, and therefore is compatible with existing boundary element codes and acceleration schemes. The efficiency and accuracy of the algorithm are corroborated by numerical examples.
Autors: Cools, K.;Andriulli, F. P.;Michielssen, E.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2011, volume: 59, issue:12, pages: 4579 - 4587
Publisher: IEEE
 
» A Canonical Piecewise-Linear Representation Theorem: Geometrical Structures Determine Representation Capability
Abstract:
This brief proposes a general piecewise-linear (GPWL) representation theorem based on geometrical structure analysis of continuous PWL functions. A constructive algorithm is developed to represent a continuous PWL function with the weighted sum of GPWL basis functions. The GPWL basis functions are defined over a domain partition with pairwise directly adjacent regions. The GPWL representation theorem unifies many known PWL models into a common theoretical framework. The GPWL representation is promising to find applications in nonlinear circuit synthesis, dynamic system identification, and control.
Autors: Wen, C.;Ma, X.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2011, volume: 58, issue:12, pages: 936 - 940
Publisher: IEEE
 
» A Cascaded Photovoltaic System Integrating Segmented Energy Storages With Self-Regulating Power Allocation Control and Wide Range Reactive Power Compensation
Abstract:
This paper presents a single-phase photovoltaic (PV) system integrating segmented energy storages (SES) using cascaded multilevel inverter. The system is designed to coordinate power allocation among PV, SES, and utility grid, mitigate the overvoltage at the point of common coupling (PCC), and achieve wide range reactive power compensation. The power allocation principle between PV and SES is described by a vector diagram. Accordingly, a sophisticated power allocation strategy is developed to allocate power between PV and SES based on a novel discrete Fourier transform (DFT) phase-locked loop (PLL) method. An appropriate reactive power allocation coefficient (RPAC) is designed to avoid duty cycle saturation and overmodulation so that wide range reactive power compensation and good power quality can be achieved simultaneously. The self-regulating power allocation control system integrating the preferred RPAC and an advanced active power control algorithm is developed to achieve the aforesaid objective. A 3.5-kW single-phase grid-connected cascaded PV system was built and tested at 1.6 kW in the laboratory. Simulation and experimental results are provided to demonstrate the effectiveness of the proposed cascaded PV system integrating SES.
Autors: Liu, L.;Li, H.;Wu, Z.;Zhou, Y.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Dec 2011, volume: 26, issue:12, pages: 3545 - 3559
Publisher: IEEE
 
» A Case Study of Evaluating Traffic Signal Control Systems Using Computational Experiments
Abstract:
A new traffic signal control system (TSCS) evaluation method that uses computational experiments based on artificial transportation systems (ATSs) is proposed in this paper. Some basic ideas of the method are discussed, i.e., generating reasonable travel demand, modeling the influence of environment, and designing communication interface. Using a 30-day computational experiment on ATSs, a case study is carried out to evaluate three TSCSs, which are implemented using fixed-time (FT), queue-based responsive (QBR), and adaptive dynamic program (ADP) algorithms, respectively. Aside from normal weather, three types of adverse weather, i.e., rain, wind, and fog, are modeled in the computational experiment. After analyzing aggregate data and detailed operating record, reliable evaluation results are obtained from this case study. Furthermore, several interesting phenomena are observed in this case study, which have yet to be noticed by previous work.
Autors: Zhu, F.;Li, G.;Li, Z.;Chen, C.;Wen, D.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Dec 2011, volume: 12, issue:4, pages: 1220 - 1226
Publisher: IEEE
 
» A Case Study of Intelligence-Driven Defense
Abstract:
We can mitigate the threat of mass malware by understanding the techniques, tactics, and procedures unique to this threat. An analysis of empirical attacker data indicates that basic, generic defenses, such as minor reductions of the attack surface and the use of available platform memory protection, are effective against mass malware.
Autors: Guido, Dan;
Appeared in: IEEE Security & Privacy
Publication date: Dec 2011, volume: 9, issue:6, pages: 67 - 70
Publisher: IEEE
 
» A CFD greenhouse night-time condensation model
Abstract:

Highlights

? A CFD night-time condensation model for a greenhouse was developed. ? Model applied to a four-span plastic covered greenhouse and validated against experimental data. ? For a wide range of boundary conditions the condensation rate modelled by a single logistic function. ? To correctly predict the greenhouse climate through a step-change in the water vapour source value.


Autors: A computational fluid dynamics (CFD) model for simulating greenhouse night-time climate and condensation is presented. The model was applied to a four-span plastic covered greenhouse. Film condensation was simulated by applying a user defined functio
Appeared in: Biosystems Engineering
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» A channel model proposal for indoor power line communications
Abstract:
In this article, a channel model for broadband indoor Power Line Communications (PLC) is presented and discussed. The modeling approach is based on the physical structure of the electrical networks inside homes and small offices. The structure has been simplified to derive a parametric model that still preserves the essential behavior of these channels in the HF band (up to 30 MHz). The model provides realistic channels by setting values to a reduced number of physical parameters. In addition, statistical distributions for such parameters that allow generating ensembles of random channels are suggested. The validity of the generated channels is assessed by comparing their behavior to the one of channels measured at several indoor power networks. Hence, this model can be employed to estimate the performance of transmission techniques on PLC channels, to aid in the design of PLC systems or to make prototype conformance tests.
Autors: Canete, F.J.;Cort??s, J.A.;D??ez, L.;Entrambasaguas, J.T.;
Appeared in: IEEE Communications Magazine
Publication date: Dec 2011, volume: 49, issue:12, pages: 166 - 174
Publisher: IEEE
 
» A cloud you can trust
Abstract:
How to ensure that cloud computing's problems– data breaches, leaks, service outages– don't obscure its virtues - This past April, Amazon's Elastic Compute Cloud service crashed during a system upgrade, knocking customers' websites off-line for anywhere from several hours to several days. That same month, hackers broke into the Sony PlayStation Network, exposing the personal information of 77 million people around the world. And in June a software glitch at cloud-storage provider Dropbox temporarily allowed visitors to log in to any of its 25 million customers' accounts using any password–or none at all. As a company blogger drily noted: "This should never have happened." And yet it did, and it does, with astonishing regularity. The Privacy Rights Clearinghouse has logged 175 data breaches this year in the United States alone, involving more than 13 million records.
Autors: Cachin, C.;Schunter, M.;
Appeared in: IEEE Spectrum
Publication date: Dec 2011, volume: 48, issue:12, pages: 28 - 51
Publisher: IEEE
 
» A clustering algorithm based on energy information and cluster heads expectation for wireless sensor networks
Abstract:
image

Highlights

? A sliding window is set up to adjust the electing probability and manage to keep stable the expected number of the cluster heads. ? The number of cluster heads is modified to be a variable according to the number of the living nodes. ? The expected number of cluster heads per round in LEACH-SWDN algorithm isk. ? This method can balance the energy consumption and extend the network lifetime better.

Autors:

Graphical abstract

Appeared in: Computers & Electrical Engineering
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» A Co-Saliency Model of Image Pairs
Abstract:
In this paper, we introduce a method to detect co-saliency from an image pair that may have some objects in common. The co-saliency is modeled as a linear combination of the single-image saliency map (SISM) and the multi-image saliency map (MISM). The first term is designed to describe the local attention, which is computed by using three saliency detection techniques available in literature. To compute the MISM, a co-multilayer graph is constructed by dividing the image pair into a spatial pyramid representation. Each node in the graph is described by two types of visual descriptors, which are extracted from a representation of some aspects of local appearance, e.g., color and texture properties. In order to evaluate the similarity between two nodes, we employ a normalized single-pair SimRank algorithm to compute the similarity score. Experimental evaluation on a number of image pairs demonstrates the good performance of the proposed method on the co-saliency detection task.
Autors: Li, H.;Ngan, K. N.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Dec 2011, volume: 20, issue:12, pages: 3365 - 3375
Publisher: IEEE
 
» A Combined Manifold Learning Analysis of Shape and Appearance to Characterize Neonatal Brain Development
Abstract:
Large medical image datasets form a rich source of anatomical descriptions for research into pathology and clinical biomarkers. Many features may be extracted from data such as MR images to provide, through manifold learning methods, new representations of the population's anatomy. However, the ability of any individual feature to fully capture all aspects morphology is limited. We propose a framework for deriving a representation from multiple features or measures which can be chosen to suit the application and are processed using separate manifold-learning steps. The results are then combined to give a single set of embedding coordinates for the data. We illustrate the framework in a population study of neonatal brain MR images and show how consistent representations, correlating well with clinical data, are given by measures of shape and of appearance. These particular measures were chosen as the developing neonatal brain undergoes rapid changes in shape and MR appearance and were derived from extracted cortical surfaces, nonrigid deformations, and image similarities. Combined single embeddings show improved correlations demonstrating their benefit for further studies such as identifying patterns in the trajectories of brain development. The results also suggest a lasting effect of age at birth on brain morphology, coinciding with previous clinical studies.
Autors: Aljabar, P.;Wolz, R.;Srinivasan, L.;Counsell, S. J.;Rutherford, M. A.;Edwards, A. D.;Hajnal, J. V.;Rueckert, D.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Dec 2011, volume: 30, issue:12, pages: 2072 - 2086
Publisher: IEEE
 
» A combined reactive and reinforcement learning controller for an autonomous tracked vehicle
Abstract:
Unmanned ground vehicles currently exhibit simple autonomous behaviors. This paper presents a control algorithm developed for a tracked vehicle to autonomously climb obstacles by varying its front and back track orientations. A reactive controller computes a desired geometric configuration based on terrain information. A reinforcement learning algorithm enhances vehicle mobility by finding effective exit strategies in deadlock situations. It is capable of incorporating complex information including terrain and vehicle dynamics through learned experiences. Experiments illustrate the effectiveness of the proposed approach for climbing various obstacles.
Autors: Isabelle Vincent, Qiao Sun
Appeared in: Robotics and Autonomous Systems
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» A Comment on the Karpovsky–Taubin Code
Abstract:
This paper presents generalizations of the Karpovsky–Taubin nonlinear code. The generalizations lead to robust and partially robust single error detecting codes and single error correcting codes.
Autors: Engelberg, S.;Keren, O.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Dec 2011, volume: 57, issue:12, pages: 8007 - 8010
Publisher: IEEE
 
» A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers
Abstract:
An area-efficient 9-bit digital-to-analog converter (DAC) for application in current-mode active-matrix organic light-emitting diode mobile display drivers is presented. To reduce the chip size, the proposed DAC is realized with a novel switched-current architecture, which periodically receives digital bits one by one in series to perform single bit conversion. A high-performance current-mode S/H circuit is also suggested in order to increase the sampling speed and linearity of the DAC. The prototype 9-bit DAC occupies only 0.014 per channel in a 0.35- CMOS process and achieves a 100-kS/s conversion rate at a static current of 10 under a 3.3-V supply. The measured maximum integral and differential nonlinearities are 1.6 and 0.8 LSB, respectively. Measured maximum interchannel current output deviations in the best and the worst chips are 15 and 35 nA, respectively.
Autors: Kim, H.-S.;Jeon, J.-Y.;Lee, S.-W.;Yang, J.-H.;Ryu, S.-T.;Cho, G.-H.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2011, volume: 58, issue:12, pages: 887 - 891
Publisher: IEEE
 
» A comparative assessment of surface microstructure and electrical conductivity dependence on co-solvent addition in spin coated and inkjet printed poly(3,4-ethylenedioxythiophene):polystyrene sulphonate (PEDOT:PSS)
Abstract:
image

Highlights

? AFM and XPS studies: DMSO coarsens PEDOT grains and reduces surface roughness. ? This supports the huge reduction of PEDOT:PSS sheet resistance by adding DMSO. ? Inkjet printed films have lower sheet resistance than the spin coated films. ? 1% Surfynol surfactant halves the surface tension of the PEDOT:PSS solution. ? Raises the film surface roughness but has little effect on the sheet resistance.

Autors:

Graphical abstract

Appeared in: Organic Electronics
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» A comparative study of hardware architectures for lightweight block ciphers
Abstract:
image

Highlights

? We have implemented eight lightweight block ciphers for the security of RFID. ? We have use a loop architecture in order to reduce the hardware resources. ? Comparisons in term of implementations characteristics with other ciphers are given. ? We examined that CURUPIRA family ciphers are the worse choices for RFID security. ? We examined that PRESENT cipher is the best choice for RFID security.

Autors:

Graphical abstract

Appeared in: Computers & Electrical Engineering
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» A Competition for Innovation [Education Department News]
Abstract:
Autors: Sottile, J.;
Appeared in: IEEE Industry Applications Magazine
Publication date: Dec 2011, volume: 17, issue:6, pages: 70 - 70
Publisher: IEEE
 
» A Complementary Modularized Ramp Metering Approach Based on Iterative Learning Control and ALINEA
Abstract:
Ramp metering is an effective tool for traffic management on freeway networks. In this paper, we apply iterative learning control (ILC) to address ramp metering in a macroscopic-level freeway environment. By formulating the original ramp metering problem as an output regulating and disturbance rejection problem, ILC has been applied to control the traffic response. The learning mechanism is further combined with Asservissement Linéaire d'Entrée Autoroutière (ALINEA) in a complementary manner to achieve the desired control performance. The ILC-based ramp metering strategy and the modified modularized ramp metering approach based on ILC and ALINEA in the presence of input constraints are also analyzed to highlight the advantages and the robustness of the proposed methods. Extensive simulations are given to verify the effectiveness of the proposed approaches.
Autors: Hou, Z.;Xu, X.;Yan, J.;Xu, J.-X.;Xiong, G.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Dec 2011, volume: 12, issue:4, pages: 1305 - 1318
Publisher: IEEE
 
» A complex adaptive notch filter using modified gradient algorithm
Abstract:
A modified gradient algorithm is developed for improving the convergence speed of a first-order complex adaptive IIR notch filter, which is used for estimating an unknown frequency of a complex sinusoidal signal embedded in white Gaussian noise. The new cost function using new error criterion is presented and analyzed theoretically. The proposed technique can significantly improve the convergence speed as compared with a complex notch filter using plain gradient algorithm. The computer simulations are conducted to demonstrate the validity of the proposed complex adaptive notch filter.
Autors: A. Nosan, R. Punchalard
Appeared in: Signal Processing
Publication date: Dec 2011
Publisher: Elsevier B.V.
 
» A Computational Method for Assessment of the Charge Collection Efficiency in Self-Reciprocating Radioisotope Power Generators
Abstract:
According to static model balancing, the electrostatic and mechanical forces from an equivalent circuit one can have an analytical solution useful for characterization of a self-reciprocating radioisotope-fueled micro power generator. Charge collection efficiency (CCE) , an empirical coefficient describing the portion of the total emitted current that gets collected by the cantilever, is an important parameter to gauge the usefulness of the cantilever. In this paper, based on MCNP Monte Carlo calculations, an applicable computational method has been proposed for assessment of the CCE in self-reciprocating radioisotope-powered cantilevers. Validity of the proposed method has been confirmed via comparison of the simulation results on CCE with the experimental value for this parameter, namely, 13.59% and 14.2%, respectively, in a previously demonstrated prototype cantilever device. The relative difference between computational and experimental results is within 4%, which confirms that the order of magnitude of the results is very close. Furthermore, suggestions have been proposed and investigated for the enhancement of the CCE in self-reciprocating radioisotope-fueled power generators. Effect of cantilever geometry and material on CCE has been investigated for some material and geometry specifications. The obtained results are indicative of the fact that this method can be used to investigate optimized design parameters in order to improve the total efficiency of the device. [2010-0094]
Autors: Houshmand, R.;Feghhi, S. A. H.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Dec 2011, volume: 20, issue:6, pages: 1234 - 1240
Publisher: IEEE
 

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