Electrical and Electronics Engineering publications abstract of: 11-2016 sorted by title, page: 0

» "Intelligent" Software-Defined Radio ( [Book/Software Reviews]
Abstract:
The book reviewed is, Cognitive Radio: Interoperability through Waveform Reconfiguration (Lechowicz, L. and Kokar, M.M.; 2015) contains ten chapters and three appendices. Cognitive radio, which combines a software-defined radio (SDR) with an intelligent agent, promises to deliver a new level of functionality. The two authors started this study while in graduate school and continued through their doctoral research. Chapter 1 opens the text by describing the interoperability of communicating systems, with a focus on the physical layer of the protocol stack of dynamic interoperability, in which the rules that define the replies to particular types of messages are introduced during the system’s operation. Also addresses some of the following topics: fundamentals of sampling and digital signal processing; software defined radio; cognitive radio; interoperability and reconfiguration; AND ontology-based cognitive radio reconfiguration. The final chapter includes a summary of the main intent of the book: reconfiguration of waveforms on the fly, which also applies to emergency response cases. This book adeptly gathers all the research and development work done in the past few years and paves the way for future research. For radio engineers who wish to pursue cognitive radio design or research, this book can serve as a guiding resource.
Autors: James Chu;
Appeared in: IEEE Microwave Magazine
Publication date: Nov 2016, volume: 17, issue:11, pages: 82 - 98
Publisher: IEEE
 
» #Communication [From the Editor's Desk]
Abstract:
Autors: Alfy Riddle;
Appeared in: IEEE Microwave Magazine
Publication date: Nov 2016, volume: 17, issue:11, pages: 6 - 8
Publisher: IEEE
 
» $E^{2}$ -MAC: Energy Efficient Medium Access for Massive M2M Communications
Abstract:
In this paper, we investigate energy-efficient clustering and medium access control for cellular-based machine-to-machine (M2M) networks to minimize device energy consumption and prolong network battery lifetime. First, we present an accurate energy consumption model that considers both static and dynamic energy consumptions, and utilize this model to derive the network lifetime. Second, we find the cluster size to maximize the network lifetime and develop an energy-efficient cluster-head selection scheme. Furthermore, we find feasible regions where clustering is beneficial in enhancing network lifetime. We further investigate communications protocols for both intra- and inter-cluster communications. While inter-cluster communications use conventional cellular access schemes, we develop an energy-efficient and load-adaptive multiple access scheme, called -phase carrier sense multiple access with collision avoidance (CSMA/CA), which provides a tunable tradeoff between energy efficiency, delay, and spectral efficiency of the network. The simulation results show that the proposed clustering, cluster-head selection, and communications protocol design outperform the others in energy saving and significantly prolong the lifetimes of both individual nodes and the whole M2M network.
Autors: Guowang Miao;Amin Azari;Taewon Hwang;
Appeared in: IEEE Transactions on Communications
Publication date: Nov 2016, volume: 64, issue:11, pages: 4720 - 4735
Publisher: IEEE
 
» $f$ -Divergence Inequalities
Abstract:
This paper develops systematic approaches to obtain -divergence inequalities, dealing with pairs of probability measures defined on arbitrary alphabets. Functional domination is one such approach, where special emphasis is placed on finding the best possible constant upper bounding a ratio of -divergences. Another approach used for the derivation of bounds among -divergences relies on moment inequalities and the logarithmic-convexity property, which results in tight bounds on the relative entropy and Bhattacharyya distance in terms of divergences. A rich variety of bounds are shown to hold under boundedness assumptions on the relative information. Special attention is devoted to the total variation distance and its relation to the relative information and relative entropy, including “reverse Pinsker inequalities,” as well as on the divergence, which generalizes the total variation distance. Pinsker’s inequality is extended for this type of -divergence, a result which leads to an inequality linking the relative entropy and relative information spectrum. Integral expressions of the Rényi divergence in terms of the relative information spectrum are derived, leading to bounds on the Rényi divergence in terms of either the variational distance or relative entropy.
Autors: Igal Sason;Sergio Verdú;
Appeared in: IEEE Transactions on Information Theory
Publication date: Nov 2016, volume: 62, issue:11, pages: 5973 - 6006
Publisher: IEEE
 
» $text{M}^{3}$ -STEP: Matching-Based Multi-Radio Multi-Channel Spectrum Trading With Evolving Preferences
Abstract:
Spectrum trading not only improves spectrum utilization but also benefits both secondary users (SUs) with more accessing opportunities and primary users (PUs) with monetary gains. Although the existing centralized designs consider the special features of spectrum trading (e.g., frequency reuse, interference mitigation, multi-radio multi-channel transmissions, and so on), they still have to face many practical but challenging issues, such as the new infrastructure deployment, the extra control overhead, and the scalability issues. To address those issues, in this paper, we propose a novel matching-based multi-radio multi-channel spectrum trading (-STEP) scheme in cognitive radio (CR) networks. We employ conflict graph to characterize the interference relationship among SUs with multiple CR radios, and formulate the centralized PUs’ revenue maximization problem under multiple constrains. In view of the NP-hardness of solving the problem and no existence of centralized entity, we develop the -STEP algorithms based on conflict graph observed by PUs, solve the problem via dynamic matching with evolving preferences, and prove its pairwise stability. Simulation results show that the proposed -STEP algorithm achieves close to optimal performance and outperforms other distributed algorithms without considering spectrum reuse.
Autors: Jingyi Wang;Wenbo Ding;Yuanxiong Guo;Chi Zhang;Miao Pan;Jian Song;
Appeared in: IEEE Journal on Selected Areas in Communications
Publication date: Nov 2016, volume: 34, issue:11, pages: 3014 - 3024
Publisher: IEEE
 
» ${mathbb {Z}}_{2}{mathbb {Z}}_{4}$ -Additive Cyclic Codes, Generator Polynomials, and Dual Codes
Abstract:
A -additive code is called cyclic if the set of coordinates can be partitioned into two subsets, the set of and the set of coordinates, such that any cyclic shift of the coordinates of both subsets leaves the code invariant. These codes can be identified as submodules of the -module . The parameters of a -additive cyclic code are stated in terms of the degrees of the generator polynomials of the code. The generator polynomials of the dual code of a -additive cyclic code are determined in terms of the generator polynomials of the code .
Autors: Joaquim Borges;Cristina Fernández-Córdoba;Roger Ten-Valls;
Appeared in: IEEE Transactions on Information Theory
Publication date: Nov 2016, volume: 62, issue:11, pages: 6348 - 6354
Publisher: IEEE
 
» "I'm Not a Computer Scientist, but ..."
Abstract:
Computing is opaque to some scientists, and science is opaque to software engineers.
Autors: David Alan Grier;
Appeared in: Computer
Publication date: Nov 2016, volume: 49, issue:11, pages: 104 - 104
Publisher: IEEE
 
» “Big Data Assimilation” Toward Post-Petascale Severe Weather Prediction: An Overview and Progress
Abstract:
Following the invention of the telegraph, electronic computer, and remote sensing, “big data” is bringing another revolution to weather prediction. As sensor and computer technologies advance, orders of magnitude bigger data are produced by new sensors and high-precision computer simulation or “big simulation.” Data assimilation (DA) is a key to numerical weather prediction (NWP) by integrating the real-world sensor data into simulation. However, the current DA and NWP systems are not designed to handle the “big data” from next-generation sensors and big simulation. Therefore, we propose “big data assimilation” (BDA) innovation to fully utilize the big data. Since October 2013, the Japan’s BDA project has been exploring revolutionary NWP at 100-m mesh refreshed every 30 s, orders of magnitude finer and faster than the current typical NWP systems, by taking advantage of the fortunate combination of next-generation technologies: the 10-petaflops K computer, phased array weather radar, and geostationary satellite Himawari-8. So far, a BDA prototype system was developed and tested with real-world retrospective local rainstorm cases. This paper summarizes the activities and progress of the BDA project, and concludes with perspectives toward the post-petascale supercomputing era.
Autors: Takemasa Miyoshi;Guo-Yuan Lien;Shinsuke Satoh;Tomoo Ushio;Kotaro Bessho;Hirofumi Tomita;Seiya Nishizawa;Ryuji Yoshida;Sachiho A. Adachi;Jianwei Liao;Balazs Gerofi;Yutaka Ishikawa;Masaru Kunii;Juan Ruiz;Yasumitsu Maejima;Shigenori Otsuka;Michiko Otsuk
Appeared in: Proceedings of the IEEE
Publication date: Nov 2016, volume: 104, issue:11, pages: 2155 - 2179
Publisher: IEEE
 
» 0.5-V 70-nW Rail-to-Rail Operational Amplifier Using a Cross-Coupled Output Stage
Abstract:
We develop and fabricate a 0.5-V rail-to-rail operational amplifier (op-amp) with ultralow-power operation in a 0.18- standard complementary metal-oxide-semiconductor process. The op-amp has a two-stage structure that comprises a complementary input stage and a novel cross-coupled output stage. The cross-coupled output stage increases the transconductances of the metal-oxide-semiconductor field-effect transistors of the output stage without requiring an additional chip area. Hence, it increases the gain of the op-amp and drivability for a capacitive load. Our experimental results showed that the dc gain was 77 dB at the common-mode input voltage of 0.25 V with a supply voltage of 0.5 V. DC gains of more than 40 dB were obtained for common-mode input voltages ranging 50–450 mV. Furthermore, the unity-gain frequency was 4.0 kHz and the phase margin was 56°, with a capacitive load of 40 pF. The power consumption was 70 nW, including all bias circuits.
Autors: Zhigang Qin;Akihiro Tanaka;Naomi Takaya;Hirokazu Yoshizawa;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2016, volume: 63, issue:11, pages: 1009 - 1013
Publisher: IEEE
 
» 0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier
Abstract:
A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies an area of and is powered from 0.7 V with a standby current consumption of around 36 . DC gain and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of 20 pF. Overall good large-signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.
Autors: Elena Cabrera-Bernal;Salvatore Pennisi;Alfio Dario Grasso;Antonio Torralba;Ramón Gonzalez Carvajal;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2016, volume: 63, issue:11, pages: 1807 - 1815
Publisher: IEEE
 
» 1-D Periodic Green’s Function for Leaky and Complex Waves Using the Ewald Method
Abstract:
The Ewald method for evaluating the free-space 1-D periodic Green’s function is extended to leaky waves by allowing for complex wavenumbers. It is shown that care must be taken when choosing the path of integration in the complex plane in the derivation of the Ewald method in order to obtain solutions that correspond to physical leaky-wave solutions. The use of different paths results in an evaluation of the Ewald method using an analytical continuation of the exponential integral function previously used when the wavenumber is real. The extension of the Ewald method to complex wavenumbers allows for the treatment of practical periodic leaky-wave antennas and periodic guiding structures with losses, as well as metamaterials, including 1-D chains of plasmonic nanoparticles.
Autors: Varada Rajan Komanduri;David R. Jackson;Filippo Capolino;Donald R. Wilton;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2016, volume: 64, issue:11, pages: 4703 - 4712
Publisher: IEEE
 
» 1-kb FinFET Dielectric Resistive Random Access Memory Array in $1times $ nm CMOS Logic Technology for Embedded Nonvolatile Memory Applications
Abstract:
A new two-transistor logic resistive random-access memory (RRAM) cell with a 16-nm standard FinFET CMOS logic platform that is fully compatible with the CMOS process is proposed and demonstrated in a 1-kb FinFET dielectric RRAM (FIND RRAM) array. The new 16-nm FIND RRAM comprises two logic standard FinFET transistors with a HfO2-based composite resistive gate dielectric film as the storage node in a cell. The set and reset characteristics of the FIND RRAM are largely improved by the locally enhanced field at fin corners, which results in low set voltage and low reset current in array operations. Due to adoption of a FinFET CMOS logic process without any additional masks or processing steps, FIND RRAM can be scaled aggressively with a cell size of nm. Low-voltage operation, excellent reliability, and stable low-resistance state/high-resistance state window are realized with the set and reset procedures based on the incremental step pulse programming algorithm, making FIND RRAM a promising embedded nonvolatile memory in the FinFET era.
Autors: Kai Ping Huang;Hsin Wei Pan;Shih Yu Chen;Ping Chun Peng;Cheng-Hsiung Kuo;Yue-Der Chih;Chrong Jung Lin;Ya-Chin King;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2016, volume: 63, issue:11, pages: 4273 - 4278
Publisher: IEEE
 
» 20-Gb/s 5- and 25-Gb/s 3.8- Area-Efficient Modulator Drivers in 65-nm CMOS
Abstract:
This brief presents two area-efficient drivers for a 50- terminated optical modulator. Driver 1 adopts a double cascode with dynamic biasing that enables sufficient high-speed operation owing to the high transition frequency of the thin-oxide transistor. Therefore, it does not require area-consuming additional peaking inductors. A custom-designed shared inductor is used in Driver 2 for bandwidth enhancement with a small area penalty; the required total inductance is only 13.3% of the conventional shunt peaking case. The prototypes are fabricated in a 65-nm complementary metal–oxide–semiconductor process. Electrical measurement results show that Driver 1 exhibits a differential output swing of 5 , a data rate of 20 Gb/s, and a power consumption of 534 mW. The measured performance of Driver 2 is 3.8 and 348 mW at 25 Gb/s. The active areas of the proposed modulator drivers are only 0.068 mm2 and 0.038 mm2.
Autors: Yoonsoo Kim;Gyu-Seob Jeong;Jun-Eun Park;Joonbae Park;Gyungock Kim;Deog-Kyoon Jeong;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2016, volume: 63, issue:11, pages: 1034 - 1038
Publisher: IEEE
 
» 20-Gb/s 5- and 25-Gb/s 3.8- Area-Efficient Modulator Drivers in 65-nm CMOS
Abstract:
This brief presents two area-efficient drivers for a 50- terminated optical modulator. Driver 1 adopts a double cascode with dynamic biasing that enables sufficient high-speed operation owing to the high transition frequency of the thin-oxide transistor. Therefore, it does not require area-consuming additional peaking inductors. A custom-designed shared inductor is used in Driver 2 for bandwidth enhancement with a small area penalty; the required total inductance is only 13.3% of the conventional shunt peaking case. The prototypes are fabricated in a 65-nm complementary metal–oxide–semiconductor process. Electrical measurement results show that Driver 1 exhibits a differential output swing of 5 , a data rate of 20 Gb/s, and a power consumption of 534 mW. The measured performance of Driver 2 is 3.8 and 348 mW at 25 Gb/s. The active areas of the proposed modulator drivers are only 0.068 mm2 and 0.038 mm2.
Autors: Yoonsoo Kim;Gyu-Seob Jeong;Jun-Eun Park;Joonbae Park;Gyungock Kim;Deog-Kyoon Jeong;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2016, volume: 63, issue:11, pages: 1034 - 1038
Publisher: IEEE
 
» 3-D Magnetohydrodynamic Modeling of DC Arc in Power System
Abstract:
With the rise of large-scale photovoltaic arrays and dc buses in power systems, dc-arc hazards have raised great concerns. Currently, the IEEE Std. 1584-2002 pertains to arc flashes originating in only ac systems. Little research has been conducted to investigate the theoretical or semiempirical methods to estimate dc arcs. The theoretical method, based on the maximum power transfer theorem, overall produces the estimations on the conservative side; the semiempirical methods are limited by the experiment scale, which cannot provide the comprehensive dc-arc prediction to the industry. This paper presents a magnetohydrodynamic (MHD) model of dc arcs. The MHD equations are solved by using computational fluid dynamic (CFD) software Code Saturne, which is based on collocated finite volume. The simulation results are compatible with the lab testing. The proposed MHD modeling provides an innovative approach to study dc-arc phenomena.
Autors: Shiuan-Hau Rau;Zhenyuan Zhang;Wei-Jen Lee;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Nov 2016, volume: 52, issue:6, pages: 4549 - 4555
Publisher: IEEE
 
» 3-D Ultrasonic Fingerprint Sensor-on-a-Chip
Abstract:
A fully integrated 3-D ultrasonic fingerprint sensor-on-a-chip is presented. The device consists of a piezoelectric micromachined ultrasonic transducer (PMUT) array bonded at the wafer level to custom readout electronics fabricated in a 180-nm CMOS process with a HV (24 V) transistor option. With the 24 V driving signal strength, the sensor consumes 280 to image a 4.73 mm mm section of a fingerprint at a rate of 380 fps. A wakeup mode that detects the presence of a finger at 4 fps and dissipates 10 allows the proposed sensor to double as a power switch. The sensor is capable of imaging both the surface epidermal and subsurface dermal fingerprints and is insensitive to contaminations, including perspiration or oil. The 3-D imaging capability combined with the sensor’s sensitivity to the acoustic properties of the tissue translates into excellent robustness against spoofing attacks.
Autors: Hao-Yen Tang;Yipeng Lu;Xiaoyue Jiang;Eldwin J. Ng;Julius M. Tsai;David A. Horsley;Bernhard E. Boser;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2522 - 2533
Publisher: IEEE
 
» 3-D Vector Flow Estimation With Row–Column-Addressed Arrays
Abstract:
Simulation and experimental results from 3-D vector flow estimations for a 62 + 62 2-D row–column (RC) array with integrated apodization are presented. A method for implementing a 3-D transverse oscillation (TO) velocity estimator on a 3-MHz RC array is developed and validated. First, a parametric simulation study is conducted, where flow direction, ensemble length, number of pulse cycles, steering angles, transmit/receive apodization, and TO apodization profiles and spacing are varied, to find the optimal parameter configuration. The performance of the estimator is evaluated with respect to relative mean bias and mean standard deviation . Second, the optimal parameter configuration is implemented on the prototype RC probe connected to the experimental ultrasound scanner SARUS. Results from measurements conducted in a flow-rig system containing a constant laminar flow and a straight-vessel phantom with a pulsating flow are presented. Both an M-mode and a steered transmit sequence are applied. The 3-D vector flow is estimated in the flow rig for four representative flow directions. In the setup with 90° beam-to-flow angle, the relative mean bias across the entire velocity profile is (−4.7, −0.9, 0.4)% with a relative standard deviation of (8.7, 5.1, 0.8)% for (). The estimated peak velocity is 48.5 ± 3 cm/s giving a −3% bias. The out-of-plane velocity component perpendicular to the cross section is used to estimate volumetric flow rates in the flow rig at a 90° beam-to-flow angle. The estima- ed mean flow rate in this setup is 91.2 ± 3.1 L/h corresponding to a bias of −11.1%. In a pulsating flow setup, flow rate measured during five cycles is 2.3 ± 0.1 mL/stroke giving a negative 9.7% bias. It is concluded that accurate 3-D vector flow estimation can be obtained using a 2-D RC-addressed array.
Autors: Simon Holbek;Thomas Lehrmann Christiansen;Matthias Bo Stuart;Christopher Beers;Erik Vilain Thomsen;Jørgen Arendt Jensen;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Nov 2016, volume: 63, issue:11, pages: 1799 - 1814
Publisher: IEEE
 
» 360 Degree Crosstalk-Free Viewable 3D Display Based on Multiplexed Light Field: Theory and Experiments
Abstract:
A 360° three-dimensional (3D) display is one of the most attractive displays for full parallax in horizontal direction. In this paper, we proposed two 360° crosstalk-free 3D autostereoscopic display methods based on pyramidal mirrors-based 3D light field multiplexing and diaphragms. Display performances of proposed displays were analyzed. We fabricated two 360° display prototypes based on the n-gonal pyramidal mirrors assemblage and flat 3D displays. Moreover, we evaluated our proposed methods by simulations and experiments. Experimental results as well as simulation results were consistent with theoretical analysis based on the geometric optics. Furthermore, the proposed schemes and theories may provide a guideline for light field multiplexing and wide viewing angle augmented reality.
Autors: Guowen Chen;Cong Ma;Dong Zhao;Zhencheng Fan;Hongen Liao;
Appeared in: Journal of Display Technology
Publication date: Nov 2016, volume: 12, issue:11, pages: 1309 - 1318
Publisher: IEEE
 
» 3D Human Model Reconstruction from Sparse Uncalibrated Views
Abstract:
Using a two-stage algorithm, the proposed technique can tackle the challenges of reconstructing high-quality 3D models of humans wearing regular clothes from sparse uncalibrated cameras. The proposed algorithm based on nonrigid dense correspondences (NRDC) requires fewer images than previous methods because it does not require an initial sparse matching. The authors validated the proposed algorithm using images from an existing dataset and images captured by a cell phone camera.
Autors: Xiaoguang Han;Kwan-Yee K. Wong;Yizhou Yu;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Nov 2016, volume: 36, issue:6, pages: 46 - 56
Publisher: IEEE
 
» 3D Interactive System Using Integral Photography by Embedded Optical Sensors for Portable Devices
Abstract:
An air-touch interactive system for portable devices is presented. An embedded optical sensor based on this approach was developed to realize a lightweight and thin-form-factor three-dimensional (3-D) interactive system. Using integral photography, the 3-D coordinates of an object are calculated. Moreover, the micro-lens array is implemented to improve the working range to 80 mm and achieve a position error of less than 5 mm. The spatial resolution in x-y and z domains is 1 and 5 mm, respectively. In addition, this system can also support a gesture vector sensing function in the far field up to 150 mm.
Autors: Chun-Ho Chen;Chih-Hung Ting;Yi-Pai Huang;
Appeared in: Journal of Display Technology
Publication date: Nov 2016, volume: 12, issue:11, pages: 1329 - 1334
Publisher: IEEE
 
» 3D Pose Tracking With Multitemplate Warping and SIFT Correspondences
Abstract:
Template warping is a popular technique in vision-based 3D motion tracking and 3D pose estimation due to its flexibility of being applicable to monocular video sequences. However, the method suffers from two major limitations that hamper its successful use in practice. First, it requires the camera to be calibrated prior to applying the method. Second, it may fail to provide good results if the inter-frame displacements are too large. To overcome the first problem, we propose to estimate the unknown focal length of the camera from several initial frames by an iterative optimization process. To alleviate the second problem, we propose a tracking method based on combining complementary information provided by dense optical flow and tracked scale-invariant feature transform (SIFT) features. While optical flow is good for small displacements and provides accurate local information, tracked SIFT features are better at handling larger displacements or global transformations. To combine these two pieces of complementary information, we introduce a forgetting factor to bootstrap the 3D pose estimates provided by SIFT features, and refine the final results using optical flow. Experiments are performed on three public databases, i.e., the Biwi Head Pose dataset, the BU dataset, and the McGill Faces datasets. The results illustrate that the proposed solution provides more accurate results than baseline methods that rely solely on either template warping or SIFT features. In addition, the approach can be applied in a larger variety of scenarios, due to circumventing the need for camera calibration, thus providing a more flexible solution to the problem than existing methods.
Autors: Shu Chen;Luming Liang;Wenzhang Liang;Hassan Foroosh;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Nov 2016, volume: 26, issue:11, pages: 2043 - 2055
Publisher: IEEE
 
» 4 Steps to dust-size neural implants [News]
Abstract:
Mainstream medicine is making increasing use of electronics inside the body, deploying implanted gadgets both to measure internal conditions and to provide stimulating jolts of electricity to nerves and muscles. But turning a human into a proper cyborg will require many minuscule devices that can be scattered throughout the body. As a step toward that goal, a team of bioengineers has built speck-size wireless electrodes that can be affixed directly to nerves–and that may one day be nestled inside the brain.
Autors: Eliza Strickland;
Appeared in: IEEE Spectrum
Publication date: Nov 2016, volume: 53, issue:11, pages: 14 - 15
Publisher: IEEE
 
» 450 mm SEMI Physical Interface Standards: Architecture, Efficiency, and Validation
Abstract:
Similar to the 300 mm standards, the 450 mm physical interface standards define the multitude of parameters that are essential to factory automation and interoperability. In addition, 450 mm standards drive factory efficiency much farther than the 300 mm standards did. This paper will review the standards architecture and critical parameters defined by the standards with a focus on the efficiency improvements that were incorporated into the 450 mm standards using the learning that the industry has acquired over the last 15 years. We will also outline the steps taken in the industry to test and validate the new 450 mm standards, as well as the preliminary test results.
Autors: Angelo Alaestante;Mutaz Haddadin;Shoji Komatsu;Stefan Radloff;
Appeared in: IEEE Transactions on Semiconductor Manufacturing
Publication date: Nov 2016, volume: 29, issue:4, pages: 306 - 313
Publisher: IEEE
 
» 5/60 GHz $0.18~mu m$ CMOS Dual-Mode Dual- Conversion Receiver Using a Tunable Active Filter for 5-GHz Channel Selection
Abstract:
A dual-mode dual-conversion receiver with two far-apart carrier frequencies, 5 and 60 GHz, and two very different channel bandwidths, tens-MHz and GHz, is demonstrated in a standard CMOS technology. The dual conversion architecture receives 60-GHz mode using Schottky diodes at the first conversion stage and merges 5-GHz mode at the second conversion stage. The 5-GHz RF channel selection is achieved by inserting a 20-MHz bandwidth tunable active filter after a 5-GHz low-noise amplifier for the noise concern and before the second down-conversion mixer to relax the linearity requirement of subsequent stages. A tunable active filter with improved linearity using a transformer-coupled scheme is employed. As a result, the narrow 20 MHz channel bandwidth selection at 5-GHz mode shows a 500 MHz tuning range with noise figure of 9 dB and conversion gain of 28 dB. For 60-GHz operation, the 3-dB IF bandwidth is 1 GHz with noise figure of about 20 dB and conversion gain of −3 dB.
Autors: Yu-Chih Hsiao;ChinChun Meng;Shih-Te Yang;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2016, volume: 26, issue:11, pages: 951 - 953
Publisher: IEEE
 
» 50th Anniversary of the Journal
Abstract:
The flagship journal of our community, the IEEE Journal of Solid-State Circuits (JSSC), also known as the “red rag” by many, has reached half a century of age. For those who don’t believe this, you can look up the old issues on IEEE Xplore; it is a quite fun thing to do, especially for those of us who were not yet born in 1966.
Autors: Jan Craninckx;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2519 - 2519
Publisher: IEEE
 
» 5G Radio Access Architecture and Technologies [Guest editor introduction]
Abstract:
The articles in this special section focus on 5G mobile communication, its network architecture, and technologies that support these services.
Autors: David Soldani;Periklis Chatzimisios;Abbas Jamalipour;Bernard Barani;Simone Redana;Sundeep Rangan;
Appeared in: IEEE Communications Magazine
Publication date: Nov 2016, volume: 54, issue:11, pages: 14 - 15
Publisher: IEEE
 
» 5G Radio Access Network Architecture: Design Guidelines and Key Considerations
Abstract:
Autors: Patrick Marsch;Icaro Da Silva;Omer Bulakci;Milos Tesanovic;Salah Eddine El Ayoubi;Thomas Rosowski;Alexandros Kaloxylos;Mauro Boldi;
Appeared in: IEEE Communications Magazine
Publication date: Nov 2016, volume: 54, issue:11, pages: 24 - 32
Publisher: IEEE
 
» 600 V/ $1.7~Omega$ Normally-Off GaN Vertical Trench Metal–Oxide–Semiconductor Field-Effect Transistor
Abstract:
This letter reports a GaN vertical trench metal–oxide–semiconductor field-effect transistor (MOSFET) with normally-off operation. Selective area regrowth of n+-GaN source layer was performed to avoid plasma etch damage to the p-GaN body contact region. A metal-organic-chemical-vapor-deposition (MOCVD) grown AlN/SiN dielectric stack was employed as the gate “oxide”. This unique process yielded a 0.5-mm2-active-area transistor with threshold voltage of 4.8 V, blocking voltage of 600 V at gate bias of 0 V, and on-resistance of at gate bias of 10 V.
Autors: Ray Li;Yu Cao;Mary Chen;Rongming Chu;
Appeared in: IEEE Electron Device Letters
Publication date: Nov 2016, volume: 37, issue:11, pages: 1466 - 1469
Publisher: IEEE
 
» 8-GHz, 6.6-mW LC-VCO with Small Die Area and FOM of 204 dBc/Hz at 1-MHz Offset
Abstract:
This letter discusses the design of an 8-GHz LC-tank voltage-controlled oscillator (VCO) for use in a receiver chain developed for the Cerro Chajnantor Atacama Telescope Heterodyne Array Instrument. A VCO-optimization approach is proposed that reduces the phase noise (PN) and minimizes the VCO die area. An LC-VCO is realized in a 0.13- CMOS technology to validate the design methodology experimentally. The VCO achieves a worst-case PN, within the whole tuning range of 850 MHz, of -131 dBc/Hz at a 1-MHz offset. At 8 GHz the oscillator PN is measured to be -134.3 dBc/Hz at a 1-MHz offset achieving a figure of merit (FOM) of 204 dBc/Hz.
Autors: Eugene Zailer;Leonid Belostotski;Réne Plume;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2016, volume: 26, issue:11, pages: 936 - 938
Publisher: IEEE
 
» A $K$ -Band Frequency Doubler With 35-dB Fundamental Rejection Based on Novel Transformer Balun in 0.13- $mu text{m}$ SiGe Technology
Abstract:
A compact balanced frequency doubler with more than 35 dB odd-harmonic rejection and fractional bandwidth of 73% is presented in this letter. Wide bandwidth and high odd-harmonic suppression is achieved by adopting a new technique for the transformer balun design, resulting in a very low magnitude imbalance of 0.13 dB and a phase imbalance of 0.4° over 7–15 GHz. The balun performance is improved by offsetting the radius of the primary and secondary coils, which reduces the parasitic coupling capacitance. The input and output frequency ranges for the doubler are 7–15 GHz and 14–30 GHz respectively. The circuit was fabricated in 0.13- SiGe technology. The chip size is 0.6 mm mm.
Autors: Sudipta Chakraborty;Leigh E. Milner;Xi Zhu;Leonard T. Hall;Oya Sevimli;Michael C. Heimlich;
Appeared in: IEEE Electron Device Letters
Publication date: Nov 2016, volume: 37, issue:11, pages: 1375 - 1378
Publisher: IEEE
 
» A − 137 dBm/Hz Noise, 82% Efficiency AC-Coupled Hybrid Supply Modulator With Integrated Buck-Boost Converter
Abstract:
This paper presents a hybrid supply modulator (SM) with a comprehensive analysis of receiver (RX) band noise in an envelope tracking power amplifier (ET-PA). The designed SM supports both ET mode and average power tracking (APT) mode depending on the PA output power level. In the APT mode, an integrated buck-boost (BB) converter with hysteretic control generates dc supply voltage and its average switching frequency ranges from 1 to 2 MHz. In the ET mode, the bandwidth of SM is determined by a linear amplifier, which has about 30 MHz of signal bandwidth. To improve the ET efficiency, an ac coupling capacitor, with an adaptive offset control, and scaled linear supply are used. The scaled linear supply is provided by the BB converter. To lower the output noise of the SM, a parallel class-AB output buffer and resonance frequency tuning schemes are applied in this paper. For long term evolution 10 MHz with quadrature phase shift keying modulation and 5.8 dB peak-to-average power ratio, the designed SM achieves 82% efficiency at 800 mW output power with a fixed 8 resistor. Adapting the proposed SM to a PA, a 10 dB ET operation dynamic range is achieved while achieving a power added efficiency of 42.6% at 27 dBm PA output power. The measured SM output noise is −137 dBm/Hz at 95 MHz offset with the PA load, and the PA RX band noise is −124 dBm/Hz, which is dominated by the stand-alone PA itself. The chip is implemented with a 130 nm CMOS process and the die size is 5.0 mm2.
Autors: Ji-Seon Paek;Seung-Chul Lee;Yong-Sik Youn;Dongsu Kim;Jeong-Hyun Choi;Junhee Jung;Young-Hwan Choo;Sung-Jun Lee;Jae-Yeol Han;Thomas Byunghak Cho;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2757 - 2768
Publisher: IEEE
 
» A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication
Abstract:
A high-density low-power parallel I/O for die-to-die communication is presented. The proposed interface includes a low-power transceiver and a high-density low-cost silicon interposer. The link architecture exploits single-sided and capacitive termination, passive equalization in the transmitter, and CMOS logic-style circuits to reduce the power consumption. To achieve a high bump/wire efficiency, single-ended signaling is used. A 4-layer Aluminum silicon interposer is fabricated providing 2.5 mm and 3.5 mm links between prototype transceivers. The transceiver prototype includes 3 transmitters and 3 receivers fabricated in 28 nm STM FD-SOI CMOS technology. The parallel interface operates at 20 Gb/s/wire and 18 Gb/s/wire data rates over the 2.5 mm and 3.5 mm channels with 5.9 and 7.7 dB of loss relative to DC (10.7 and 13.5 dB total loss) at while consuming 0.30 and 0.32 pJ/bit excluding clocking circuits, respectively.
Autors: Behzad Dehlaghi;Anthony Chan Carusone;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2690 - 2701
Publisher: IEEE
 
» A 0.5 V 55 $mu text{W}$ 64 $times $ 2 Channel Binaural Silicon Cochlea for Event-Driven Stereo-Audio Sensing
Abstract:
This paper presents a channel stereo-audio sensing front end with parallel asynchronous event output inspired by the biological cochlea. Each binaural channel performs feature extraction by analog bandpass filtering, and the filtered signal is encoded into events via asynchronous delta modulation (ADM). The channel central frequencies are geometrically scaled across the human hearing range. Two design techniques are highlighted to achieve the high system power efficiency: source-follower-based bandpass filters (BPFs) and asynchronous delta modulation (ADM) with adaptive self-oscillating comparison. The chip was fabricated in 0.18 1P6M CMOS, and occupies an area of mm2. The core cochlea system operating under a 0.5 V power supply consumes 55 at an output rate of 100k event/s. The measured range of is from 8 Hz to 20 kHz, and the BPF quality factor can be tuned from 1 to almost 40. The 1 mismatch of and between two ears is 3.3% and 15%, respectively, across all channels at 10. Reconstruction of speech input from he event output of the chip is performed to validate the information integrity in event-domain representation, and vowel discrimination is demonstrated as a simple application using histograms of the output events. This type of silicon cochlea front end targets integration with embedded event-driven processors for low-power smart audio sensing with classification capabilities, such as voice activity detection and speaker identification.
Autors: Minhao Yang;Chen-Han Chien;Tobi Delbruck;Shih-Chii Liu;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2554 - 2569
Publisher: IEEE
 
» A 1 V 103 dB 3rd-Order Audio Continuous-Time $Delta Sigma $ ADC With Enhanced Noise Shaping in 65 nm CMOS
Abstract:
As technology scales, integrating high resolution ADCs into high fidelity mixed signal systems becomes challenging in advanced CMOS processes. Cascading integrators to achieve high-order filter structures limits the modulation index and compromises on stability at the expense of added hardware and power consumption. To optimize the maximum stable amplitude (MSA) to accommodate a larger input dynamic range, the supply rails have to be expanded, which limited technology choices to those of a larger feature size. This work proposes a 25 kHz 3rd-order continuous-time modulator (CT) utilizing a 5-bit SAR quantizer, enabling noise coupling (NC) to be possible in a typical nanoscale CMOS 65 nm technology with VDD of 1 V. Mismatches in SAR comparator and DAC array are mitigated with a proposed calibration scheme while CM mismatches are solved by a floating differential charge storage capacitor (FDCSC) coupling method. To allow sufficient time for SAR bit cycling and noise charge feedback settling, 1 Ts excess loop delay (ELD) is compensated with digital differentiation that minimizes both the power and complexity of the auxiliary feedback DAC. The prototype obtained DR/SNR/SNDR of 103.1 dB/100.1 dB/95.2 dB while dissipating 0.8 mW, hence achieving a FoMSNDR and FoMschreier of 0.34 pJ/level and 177.9 dB, respectively.
Autors: Yoon Hwee Leow;Howard Tang;Zhuo Chao Sun;Liter Siek;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2625 - 2638
Publisher: IEEE
 
» A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators
Abstract:
In this paper, we propose a method to reduce a flicker (1/f) noise upconversion in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest impedance path. The asymmetric oscillation waveform results in an effective impulse sensitivity function of a nonzero dc value, which facilitates the 1/f noise upconversion into the oscillator’s 1/f3 phase noise. We demonstrate that if the tank exhibits an auxiliary resonance at 2, thereby forcing this current harmonic to flow into the equivalent resistance of the 2 resonance, then the oscillation waveform would be symmetric and the flicker noise upconversion would be largely suppressed. The auxiliary resonance is realized at no extra silicon area in both inductor- and transformer-based tanks by exploiting different behaviors of inductors and transformers in differential- and common-mode excitations. These tanks are ultimately employed in designing modified class-D and class-F oscillators in 40 nm CMOS technology. They exhibit an average flicker noise corner of less than 100 kHz.
Autors: Mina Shahmohammadi;Masoud Babaie;Robert Bogdan Staszewski;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2610 - 2624
Publisher: IEEE
 
» A 10 dBm Output Power D-Band Power Source With 5 dB Conversion Gain in BiCMOS 55nm
Abstract:
A D-Band power source implemented in the STMicroelectronics BiCMOS 55 nm technology and dedicated to on wafer characterization in millimeter-wave band frequency is presented. The circuit consists in multiplying by four a low frequency signal by cascading two frequency doublers. Two intermediate power amplifiers optimized at the second and fourth harmonics respectively are implemented after each doubler. A high-pass filter implemented before the second amplifier performs the rejection of the first and second harmonics to obtain a pure fourth harmonic output frequency. The measured peak output power is 10 dBm at 140 GHz with a −3 dB bandwidth of 24 GHz and a DC power consumption of 0.61 W. The total chip area is mm2.
Autors: Alice Bossuet;Thomas Quémerais;Christophe Gaquière;Estelle Lauga-Larroze;Jean-Michel Fournier;Sylvie Lepilliet;Daniel Gloria;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2016, volume: 26, issue:11, pages: 930 - 932
Publisher: IEEE
 
» A 10 mm3 Inductive Coupling Radio for Syringe-Implantable Smart Sensor Nodes
Abstract:
We present a near-field radio system for a millimeter-scale wireless smart sensor node that is implantable through a 14-gauge syringe needle. The proposed system integrates a radio system on chip and a magnetic antenna on a glass substrate within a total dimension of mm3. We demonstrate energy-efficient active near-field wireless communication between the millimeter-scale sensor node and a base station device through an RF energy-absorbing tissue. The wireless transceiver, digital baseband controller, wakeup controller, on-chip baseband timer, sleep timer, and MBUS controller are all integrated on the SoC to form a millimeter-scale sensor node, together with a mm2 magnetic antenna fabricated with a 1.5- -thickness gold on a 100 -thickness glass substrate. An asymmetric link is established pairing the sensor antenna with a codesigned cm2 base station antenna to achieve a link distance of up to 50 cm for sensor transmission and 20 cm for sensor reception. The transmitter consumes a 43.5 average power at 2 kb/s, while the receiver power consumption is 36 with a −54 dBm sensitivity at 100 kb/s. When powered by a mm2 thin-film battery (2 \mu
Autors: Yao Shi;Myungjoon Choi;Ziyun Li;Zhihong Luo;Gyouho Kim;Zhiyoong Foo;Hun-Seok Kim;David D. Wentzloff;David Blaauw;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2570 - 2583
Publisher: IEEE
 
» A 10-kV/400-V 500-kVA Electronic Power Transformer
Abstract:
This paper presents the design and development of a three-phase 10-kV/400-V 500-kVA electronic power transformer (EPT). The power circuit is designed in a modular fashion, i.e., the main circuit consists of many identical ac-dc-dc-ac modules (abbreviated as power modules). Each power module consists of a high-voltage power cell, a low-voltage power cell (LVPC), a medium-frequency isolation transformer, and a filter. The corresponding control and protection system is developed. A special three-stage startup strategy is designed to shorten the startup time and reduce the startup inrush current. The negative-sequence current compensation is introduced in the input stage to handle the unbalanced loads. To keep the dc-link voltages balanced, an individual dc voltage balancing controller based on regulating the output power of each parallel LVPC is proposed. The detailed control hardware design and software implementation are discussed. The functions of this 10-kV EPT prototype are verified through the laboratory and field tests. The results are shown in this paper. Currently, the prototype is operating in the industrial power grid.
Autors: Dan Wang;Jie Tian;Chengxiong Mao;Jiming Lu;Yuping Duan;Jun Qiu;Huihong Cai;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Nov 2016, volume: 63, issue:11, pages: 6653 - 6663
Publisher: IEEE
 
» A 12.77-MHz 31 ppm/°C On-Chip RC Relaxation Oscillator With Digital Compensation Technique
Abstract:
The design of a 12.77-MHz on-chip RC relaxation oscillator with digital compensation technique is presented. To maintain the frequency stability versus temperature and supply voltage variations, loop delay tuning by a digital feedback loop is developed in this system. In order to generate an on-chip reference for digital calibration, a replica comparator is added. The on-chip relaxation oscillator is fabricated in 0.18- CMOS process. The measured output frequency variation is 31 ppm/°C across −30 to 120 °C temperature range after compensation. The frequency variation over the supply voltage from 0.6 V to 1.1 V is ±0.5%/V. The measured total power consumption is 56.2 at 0.9-V supply voltage when the digital compensation blocks are enabled. After digital compensation, the compensation blocks can be shutdown for power saving, and the main oscillator consumes only 12.8 .
Autors: Jiacheng Wang;Wang Ling Goh;Xin Liu;Jun Zhou;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2016, volume: 63, issue:11, pages: 1816 - 1824
Publisher: IEEE
 
» A 137 dB Dynamic Range and 0.32 V Self-Powered CMOS Imager With Energy Harvesting Pixels
Abstract:
This work presents an 0.32 V self-powered high dynamic range (DR) CMOS imager in standard CMOS technology with dual-mode operation: imaging (IMG) and optical energy harvesting (OEH) modes. In IMG mode, a dual-exposure extended-counting (DEEC) scheme is proposed and implemented with a 5-bit programmable current-controlled threshold (PCCT) generator. By combining the DR of a short-exposure (88 dB) and an extended long-exposure (49 dB) conversions, the DEEC achieves a high DR of 137 dB. The chip consumes at 6.5 fps with 0.32 V operation and at 16.5 fps with 0.4 V operation, which results in an iFoM of 8.1 f and 9.8 fJ/pixelcode. In OEH mode, the sensing pixels turns into energy harvesting pixels with an additional global micro solar cell and corresponding mode control circuit, which generates 455 mV and at 60 klux (sunny day) and supports a self-powered imaging operation at 4.1 fps.
Autors: Albert Yen-Chih Chiou;Chih-Cheng Hsieh;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2769 - 2776
Publisher: IEEE
 
» A 2-15 GHz VCO With Harmonic Cancellation for Wide-Band Systems
Abstract:
A 2-15 GHz SiGe VCO (voltage controlled oscillator) has been developed with a very low harmonic content. The design is based on the harmonic cancellation concept and uses a multiple-phase ring oscillator together with a wide-band active-weighted summer. The VCO results in an output power of −8 to −6 dBm and < −50 dBc and harmonic level at 2-15 GHz. The active area of the chip is very small ( mm2) due to the lack of inductors, and the power consumption is 88-120 mW from a 2.5 V supply. To our knowledge, this is the first demonstration of a wide-band VCO showing a near-perfect sinewave output over a wide frequency range. The application areas are in built-in-self-test sources for wide-band radios and phased arrays.
Autors: Tumay Kanar;Gabriel M. Rebeiz;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2016, volume: 26, issue:11, pages: 933 - 935
Publisher: IEEE
 
» A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration
Abstract:
This brief presents a two-dimensional (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated ring oscillators (GROs) in the Vernier branches. The already small Vernier quantization noise (∼10.6 ps) is improved by the first-order noise shaping of the GRO. Moreover, since all the delay differences between the and phases can be used (rather than only the diagonal line of the one-dimensional architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65-nm CMOS process and consumes 2.3 mA from 1.0 V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2 ps, whereas the average latency time (within 2 ns) is less than 1/6 of that in a standard Vernier TDC.
Autors: Ping Lu;Ying Wu;Pietro Andreani;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2016, volume: 63, issue:11, pages: 1019 - 1023
Publisher: IEEE
 
» A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE
Abstract:
Implementation of highly integrated optical receivers in CMOS promises low cost, but combining high gain, low noise, high bandwidth, and low power in a CMOS transimpedance amplifier is a challenge. Fortunately, the sensitivity of an optical receiver is improved by limiting its front-end bandwidth far below the symbol rate and using equalization to eliminate the resulting intersymbol interference (ISI). Analysis reveals that when using a decision-feedback equalizer (DFE) to cancel all postcursor ISI, receiver sensitivity is optimized by taking a front-end bandwidth as low as 0.12, depending upon the frequency response and noise spectrum assumed for the front end. This paper presents a 20 Gb/s optical receiver with a front-end bandwidth of 3 GHz. The front end is designed to have an approximately first-order response, ensuring only postcursor ISI, which may be efficiently canceled with a first-order infinite-impulse response DFE (IIR-DFE). An IIR-DFE circuit is also proposed that obviates the need for an explicit full-rate multiplexor. Fabricated in 65 nm CMOS, the receiver achieves 0.705 pJ/b efficiency with the IIR-DFE consuming 150 fJ/b. Using a photodiode with 12 GHz analog bandwidth and responsivity of 0.5 A/W, the receiver has a sensitivity of −5.8 dBm optically modulated amplitude.
Autors: Alireza Sharif-Bakhtiar;Anthony Chan Carusone;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2679 - 2689
Publisher: IEEE
 
» A 24- $mu text{W}$ 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS
Abstract:
This paper presents an energy-efficient 12-bit successive approximation (SA) register analog-to-digital converter (ADC) for high-performance sensor systems. The ADC uses a two-step decision digital-to-analog converter (DAC) switching scheme for improving the DAC linearity with small capacitor arrays. The scheme effectively eliminates the largest binary DAC middle-code transition glitch. The proposed switching scheme also tolerates DAC settling errors during SA. Avoiding unnecessary DAC switching error improves the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR). A reference-scaling binary capacitor DAC is used for improving the ADC energy efficiency without sacrificing production reliability. The implemented prototype in 0.11- CMOS occupies an active area of 0.097 mm2. At 1 MS/s, it consumes a total power of 24 from a 0.9 V supply. The measured differential nonlinearity and the integral nonlinearity are 0.4 least significant bit (LSB) and 0.7 LSB, respectively. Among 50 chips, the peak measured SNDR is 68.3 dB. The peak and the average of SFDR are 89 and 83.5 dB, respectively. The optimal effective number of bits is 11 bit at the Nyquist-rate input, which is equivalent to a figure of merit of 11.7 fJ/conversion-step.
Autors: Yung-Hui Chung;Chia-Wei Yen;Meng-Hsuan Wu;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2016, volume: 24, issue:11, pages: 3334 - 3344
Publisher: IEEE
 
» A 3-D Spatial Model for In-Building Wireless Networks With Correlated Shadowing
Abstract:
Consider orthogonal planes in the 3-D space representing floors and walls in a large building. These planes divide the space into rooms, where a wireless infrastructure is deployed. This paper is focused on the analysis of the correlated shadowing field created by this wireless infrastructure through the set of walls and floors. When the locations of the planes and wireless nodes are governed by Poisson processes, we obtain a simple stochastic model which captures the non-uniform nature of node deployment and room sizes. This model, which we propose to call the Poisson building, captures the complex in-building shadowing correlations, is scalable in the number of dimensions, and can be used for network performance analysis. It allows an exact mathematical characterization of the interference distribution in both infinite and finite buildings, which further leads to closed-form expressions for the coverage probabilities in in-building cellular networks and the success probability of in-building underlay D2D transmissions.
Autors: Junse Lee;Xinchen Zhang;François Baccelli;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Nov 2016, volume: 15, issue:11, pages: 7778 - 7793
Publisher: IEEE
 
» A 300- Audio Modulator With 100.5-dB DR Using Dynamic Bias Inverter
Abstract:
This paper presents a micropower audio delta-sigma modulator for mobile applications. This work employs power-efficient integrators based on the dynamic bias inverter, which consists of a cascode inverter, a floating current source and two offset-storage capacitors. The quiescent current of the inverter is copied from the floating current via offset-storage capacitors and the speed limitation caused by the cascode transistors in the inverter is resolved by using active parasitic compensation. This maximizes both / ratio and slew rate of the inverter-based integrator, while compensating process, voltage, and temperature (PVT) variations. To verify the effectiveness of the proposed technique, a single-bit third-order modulator is implemented in a 0.18 CMOS technology. The prototype modulator achieves 97.7 dB SNDR, 98.6 dB SNR, and 100.5 dB DR in a 20-kHz signal bandwidth, while consuming only 300- from a 1.8 V supply. This corresponds to a state-of-the-art Schreier's FoM of 178.7 dB. The results are fully verified under variable supplies and temperatures.
Autors: Sangwoo Lee;Woojin Jo;Seungwoo Song;Youngcheol Chae;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2016, volume: 63, issue:11, pages: 1866 - 1875
Publisher: IEEE
 
» A 35.7–64.2 GHz low power Miller Divider with Weak Inversion Mixer in 65 nm CMOS
Abstract:
A 60 GHz wide locking range Miller divider is presented in this letter. To enhance the locking range of divider and save power consumption, we proposed a Miller divider based on weak inversion mixer. The proposed Miller divider is implemented in 65 nm CMOS and exhibits 57% locking range from 35.7 to 64.2 GHz at an input power of 0 dBm while consuming 1.6-mW dc power at 0.4 V supply. Compared to the previously reported CMOS millimeter wave frequency dividers, the proposed divider achieves the widest fractional bandwidth without any frequency tuning mechanism.
Autors: Yu-Hsuan Lin;Huei Wang;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2016, volume: 26, issue:11, pages: 948 - 950
Publisher: IEEE
 
» A 40–170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS
Abstract:
A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplifier (PA) is described. A PLL-based architecture is employed, which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used in pulsewidth modulation (PWM) generation. Multilevel signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high peak-to-average power ratios (PAPRs). A differential folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with an additional supply source/sink path compared with the 2-level operation. The PWM driver has been implemented in a 130 nm CMOS process and can operate with a switching frequency of 40–170 MHz. For the 2-/3-/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is −61/−62/−53 dB and the corresponding efficiency is 71%/83%/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2-/3-level PA with a high PAPR signal with 500 kHz bandwidth. While intended as a general-purpose amplifier, the approach is well-suited for applications such as power-line communications.
Autors: Kunhee Cho;Ranjit Gharpurey;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2639 - 2650
Publisher: IEEE
 
» A 5 GHz Fractional- ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM
Abstract:
An ADC-based digital phase-locked loop (DPLL) assisted by a digital-to-time converter (DTC) is proposed for fractional-N frequency synthesis. A successive approximation register (SAR) ADC is adopted to mimic the operation of the timeto-digital converter (TDC) in the conventional DPLL to achieve an equivalent 1-ps time-domain resolution. The superiority of ADC-based TDC is revealed and compared to delay-based TDC. The nonlinearity error induced by both TDC and DTC is also analyzed and discussed. Fabricated in a 40 nm CMOS technology, the proposed DPLL achieves an in-band phase noise -104 dBc/Hz and an integrated phase noise 379 fsrms in the fractional-N mode. The DPLL operates at 5 GHz with 2.92-mW power dissipation from a 0.9-V power supply. The core parts only occupy 0.09-mm2 active area. The FoM of the DPLL can be as good as -243.8 dB.
Autors: Wei-Sung Chang;Tai-Cheng Lee;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2016, volume: 63, issue:11, pages: 1845 - 1853
Publisher: IEEE
 
» A 5 GHz Fractional- ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM
Abstract:
An ADC-based digital phase-locked loop (DPLL) assisted by a digital-to-time converter (DTC) is proposed for fractional- frequency synthesis. A successive approximation register (SAR) ADC is adopted to mimic the operation of the time-to-digital converter (TDC) in the conventional DPLL to achieve an equivalent 1-ps time-domain resolution. The superiority of ADC-based TDC is revealed and compared to delay-based TDC. The nonlinearity error induced by both TDC and DTC is also analyzed and discussed. Fabricated in a 40 nm CMOS technology, the proposed DPLL achieves an in-band phase noise 104 dBc/Hz and an integrated phase noise 379 in the fractional- mode. The DPLL operates at 5 GHz with 2.92-mW power dissipation from a 0.9-V power supply. The core parts only occupy 0.09-mm2 active area. The FoM of the DPLL can be as good as 243.8 dB.
Autors: Wei-Sung Chang;Tai-Cheng Lee;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2016, volume: 63, issue:11, pages: 1845 - 1853
Publisher: IEEE
 
» A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications
Abstract:
Hardware search engine (HSE) plays a major role to speed up the search operation in wireless applications. Ternary content addressable memory (TCAM) is such an engine which performs the search in a single clock cycle but the use of separate content and mask storage, various wordlines for read/mask/write, and decoupled data/search lines require substantial design area and consume relatively high power. This article proposes implementation of a state of the art energy-efficient quasi-static ternary fully associative cache tag for wire speed memory access. A 4-T static content and dynamic mask storage have been used with coupled data and search line for reducing the energy dissipation during search. The proposed 128 32-bit TCAM tag with selective matchline evaluation scheme has been implemented with predictive 45-nm CMOS process and simulated in SPECTRE at the supply voltage of 1.0 V. The design dissipates an energy of 1.72-fJ/bit/search with a reduction of 32% in the cell area compared to the traditional TCAM.
Autors: Sandeep Mishra;Telajala Venkata Mahendra;Anup Dandapat;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2016, volume: 63, issue:11, pages: 1910 - 1920
Publisher: IEEE
 
» A Battery-Assisted Passive EPC Gen-2 RFID Sensor Tag IC With Efficient Battery Power Management and RF Energy Harvesting
Abstract:
Herein, we present a fully integrated electronic product code (EPC) Gen-2 compatible battery-assisted passive (BAP) radio-frequency identification sensor tag integrated circuit (IC) with efficient power management. The key components of the tag IC include an adaptive radio-frequency (RF) energy harvester, a battery access controller (BAC), a storage capacitor charger, and a powergated sensor block. External RF energy is efficiently harvested using dynamically controlled rectifying stages and a threshold-compensation technique. The BAC tightly controls the power path, cutting off leakage current from the battery. The power-gated sensor block supports multiplexed sensing operations in a power efficient manner. The sensor interface includes a chopper amplifier, a programmable gain amplifier, multiplexers, and an 8-bit ADC. For sensing data logging, custom designed nonvolatile memory is employed via one-time programmable memory. The digital control block is based on an EPCglobal Gen-2 standard that is modified to support the sensing operation. The tag chip was fabricated in a 1-poly 6-metal standard 0.18-μm standard CMOS process. The tag IC consumes 1 μA for leakage and active operation (0.1% duty), and the estimated lifespan of the BAP tag IC is about 0.2 year/mA·h.
Autors: Vinh-Hao Duong;Nguyen Xuan Hieu;Hyun-Sik Lee;Jong-Wook Lee;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Nov 2016, volume: 63, issue:11, pages: 7112 - 7123
Publisher: IEEE
 
» A Battery-Less Sensor Concept Outputting Perceivable Signal Demonstrated With an Accelerometer
Abstract:
A stringent battery-less sensor concept stipulating the entire operation of sensing and result indication to be driven solely by the sensing element without any additional power source has been proposed and implemented with a completely self-powered accelerometer as an example. The operation involves energy harnessing of the vibration into electrical charge with a piezoelectric cantilever, accumulating the charge and then releasing it into an indicator device via an ultra-sharp switch. Deemed as an unprecedented accelerometer feature, the acceleration information at a single frequency is quantitatively indicated by the period of the pulsed light or sound from the self-powered indicator device, which is directly perceivable and comprehensible to the user. This letter realizes an energy autonomous sensor system as highly desired by the end users.
Autors: Szu Cheng Lai;Kui Yao;Chin Yaw Tan;
Appeared in: IEEE Sensors Journal
Publication date: Nov 2016, volume: 16, issue:22, pages: 7841 - 7842
Publisher: IEEE
 
» A Bipolar High-Voltage Pulsed-Power Supply Based on Capacitor-Switch Voltage Multiplier
Abstract:
This paper presents a power electronics converter to generate bipolar high-voltage pulses using low-voltage dc source. Converter is designed based on charging of different capacitors by a predetermined switching pattern and their discharging on the load for pulsed power applications. Low number of power electronics devices and bulky transformer elimination are main advantages of the proposed converter. According to new findings, bipolar high-voltage pulses may lead to higher efficiency in many applications, such as food sterilization industry. The proposed pulse generator generates bipolar controllable pulses with a modular circuit structure based on a capacitor-switched network. Experimental results are presented to verify the analysis.
Autors: Ahmad Alijani;Jafar Adabi;Mohammad Rezanejad;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Nov 2016, volume: 44, issue:11, pages: 2880 - 2885
Publisher: IEEE
 
» A Brain–Computer Interface Project Applied in Computer Engineering
Abstract:
Keeping up with novel methods and keeping abreast of new applications are crucial issues in engineering education. In brain research, one of the most significant research areas in recent decades, many developments have application in both modern engineering technology and education. New measurement methods in the observation of brain activity open a new frontier in engineering applications. Electroencephalogram (EEG)-based brain activity observation processes are very promising and have been used in several engineering studies, primarily for the implementation of control tasks. This paper presents the development, implementation, and assessment of an EEG-based engineering education project, in which engineering students applied the theory they had learned and improved their knowledge and skills in the area of observation and evaluation of electrical signals generated by brain activity and measured by biosensors. The main project goal was to develop and test a brain–computer interface that is able to measure the average attention level. The effectiveness of this project-based learning was evaluated by student questionnaire responses and analysis of students' exam results; students who had participated in the project were shown to have higher levels of acquired knowledge.
Autors: Jozsef Katona;Attila Kovari;
Appeared in: IEEE Transactions on Education
Publication date: Nov 2016, volume: 59, issue:4, pages: 319 - 326
Publisher: IEEE
 
» A Bright Future for IEEE Intelligent Systems
Abstract:
Editor-in-chief Daniel Zeng says his farewell as his term ends at the end of 2016.
Autors: Daniel Zeng;
Appeared in: IEEE Intelligent Systems
Publication date: Nov 2016, volume: 31, issue:6, pages: 3 - 4
Publisher: IEEE
 
» A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction
Abstract:
Scratchpad memory (SPM) is widely used in modern embedded processors to overcome the limitations of cache memory. The high vulnerability of SPM to soft errors, however, limits its usage in safety-critical applications. This paper proposes an efficient fault-tolerant scheme, called cache-assisted duplicated SPM (CADS), to protect SPM against soft errors. The main aim of CADS is to utilize cache memory to provide a replica for SPM lines. Using cache memory, CADS is able to guarantee a full duplication of all SPM lines. We also further enhance the proposed scheme by presenting buffered CADS (BCADS) that significantly improves the CADS energy efficiency. BCADS is compared with two well-known duplication schemes as well as single-error correction scheme. The comparison results reveal that: 1) BCADS imposes a 13.6% less energy-delay product (EDP) overhead than the duplication schemes and it does not require to modify the SPM manager and target application and 2) in comparison with the conventional single-error correction double-error detection (SEC-DED) scheme, BCADS provides a significantly higher error correction capability by correcting up to 4-b burst errors using a low-cost 4-b interleaved parity code. Moreover, the area overhead for error correction and the performance overhead of BCADS are negligible (less than 1%), whereas the area and performance overheads are 21.9% and 6.1% for SEC-DED, respectively. Furthermore, BCADS imposes about a 10.7% lower EDP overhead compared with the SEC-DED scheme.
Autors: Hamed Farbeh;Nooshin Sadat Mirzadeh;Nahid Farhady Ghalaty;Seyed-Ghassem Miremadi;Mahdi Fazeli;Hossein Asadi;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2016, volume: 24, issue:11, pages: 3296 - 3309
Publisher: IEEE
 
» A Classic Power Plant: Early Electric Power at Pratt Institute [History]
Abstract:
In April of 2000, I had the pleasure of visiting a truly beautiful artifact of electric power history, and of meeting Conrad Milster, its long-time caretaker. This is the power plant of the Pratt Institute, located in the Clinton Hill neighborhood of Brooklyn, New York City. This unique installation still exists today (along with Milster) and, hopefully, both will continue so for a very long time.
Autors: Thomas J. Blalock;
Appeared in: IEEE Power and Energy Magazine
Publication date: Nov 2016, volume: 14, issue:6, pages: 84 - 92
Publisher: IEEE
 
» A Colored Petri Net Based Frequency Support Scheme Using Fleet of Electric Vehicles in Smart Grid Environment
Abstract:
The ever-growing dependency of modern life on electricity may impose huge burden on smart grids (SGs). This dependency affects the demand-supply gap and may lead to undesirable frequency fluctuations. In the worst case, these fluctuations may result in blackouts. In this direction, fleet of electric vehicles (EVs) may play a crucial role in reducing these fluctuations to a great extent. So, this paper proposes a novel scheme for efficient frequency support in SG environment by utilizing fleet of EVs. These EVs act as controllable loads and work in close coordination with aggregators and charging stations. Aggregators play a crucial role in regulating charging and discharging rates of EVs while meeting their energy requirements with the help of the proposed colored petri net based controller. The proposed scheme has been evaluated with respect to publicly available frequency regulation data acquired from PJM and ERCOT. In addition to this, the scheme has also been compared with an existing approach and results clearly depict that the proposed scheme is more scalable in comparison to the existing schemes in V2G environment.
Autors: Kuljeet Kaur;Rubi Rana;Neeraj Kumar;Mukesh Singh;S. Mishra;
Appeared in: IEEE Transactions on Power Systems
Publication date: Nov 2016, volume: 31, issue:6, pages: 4638 - 4649
Publisher: IEEE
 
» A Colorful Blackout: The Havoc Caused by Auroral Electrojet Generated Magnetic Field Variations in 1989
Abstract:
The Hydro-Québec system is a winter-peaking system whose all-time record peak load of 39,240 MW was recorded in January 2014. Hydro-Québec exports to neighboring systems in Canada and the United States, with an annual transaction volume of approximately 30 TWh. The current system configuration is based on the major development projects of the 1960s and 1970s. In 1965, as part of the development of the Manic-Outardes hydroelectric complex, Hydro-Québec commissioned the world's first 735-kV lines, which had a much greater capacity than the existing 315-kV lines put into service in the late 1950s with the development of the Bersimis hydroelectric complex. In 1971, Hydro-Québec launched what was then dubbed the "project of the century": the development of the La Grande River complex in the James Bay region at the southern end of Hudson Bay. In 1996, when the final generating station, Laforge-2, was commissioned at the end of the second phase of the project, La Grande became the largest hydroelectric facility in the world, a title it retained for a number of years.
Autors: Sebastien Guillon;Patrick Toner;Louis Gibson;David Boteler;
Appeared in: IEEE Power and Energy Magazine
Publication date: Nov 2016, volume: 14, issue:6, pages: 59 - 71
Publisher: IEEE
 
» A Combination of Traditional and Polarimetric Features for Oil Spill Detection Using TerraSAR-X
Abstract:
Synthetic aperture radar (SAR) images are operationally used for the detection of oil spills in the marine environment, as they are independent of sun light and weather-induced phenomena. Exploitation of radar polarimetric features for operational oil spill detection is relatively new and until recently those properties have not been extensively exploited. This paper describes the development of a oil spill detection processing chain using coherent dual-polarimetric (copolarized channels, i.e., HH-VV) TerraSAR-X images. The proposed methodology focuses on offshore platform monitoring and introduces for the first time a combination of traditional and polarimetric features for object-based oil spill detection and look-alike discrimination. A total number of 35 feature parameters were extracted from 225 oil spills and 26 look-alikes and divided into training and validation dataset. Mutual information content among extracted features have been assessed and feature parameters are ranked according to their ability to discriminate between oil spill and look-alike. Extracted features are used for training and validation of a support vector machine-based classifier. Performance estimation was carried out for the proposed methodology on a large dataset with overall classification accuracy of 90% oil spills and 80% for look-alikes. Polarimetric features such as geometric intensity, copolarization power ratio, span proved to be more discriminative than other polarimetric and traditional features.
Autors: Suman Singha;Rudolf Ressel;Domenico Velotto;Susanne Lehner;
Appeared in: IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing
Publication date: Nov 2016, volume: 9, issue:11, pages: 4979 - 4990
Publisher: IEEE
 
» A Compact Broadband Direct Coaxial Line to SIW Transition
Abstract:
In this letter, a novel coaxial line to substrate integrated waveguide (SIW) broadband transition is presented. The transition is designed by connecting the inner conductor of a coaxial line to an open-circuited SIW. The configuration directly transforms the TEM mode of a coaxial line to the fundamental TE10 mode of the SIW. A prototype back-to-back transition is fabricated for X-band operation using a 0.508 mm thick RO 4003C substrate with dielectric constant 3.55. Comparison with other reported transitions shows that the present structure provides lower passband insertion loss, wider bandwidth and most compact. The area of each transition is where is the guided wavelength at passband center frequency of GHz. Measured 15 dB and 20 dB matching bandwidths are over 48% and 20%, respectively, at .
Autors: Arani Ali Khan;Mrinal Kanti Mandal;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2016, volume: 26, issue:11, pages: 894 - 896
Publisher: IEEE
 
» A Compact Dual Circularly Polarized Microstrip Patch Array With Interlaced Sequentially Rotated Feed
Abstract:
This communication presents a microstrip patch array, using sequentially rotated feed networks to achieve dual circular polarization in the same band. By interlacing the microstrip patches of adjacent subarrays, the element spacing is minimized to avoid the challenging grating lobe issue. In this manner, the number of radiating elements is reduced from the conventional 4N to , where is the number of subarrays. The array is implemented on a two-layer substrate, with the upper layer hosting the microstrip patch array and the sequentially rotated networks, and the lower layer hosting the power dividers, sharing a common ground plane in the middle. To validate this novel configuration, a prototype is fabricated and measured. It achieves both dB and axial ratio < 3 dB bandwidth of 12.5% (4.95–5.61 GHz) for right-hand circular polarization and 14.7% (5.05–5.85 GHz) for left-hand circular polarization. The isolation between the orthogonal circularly polarized ports is about 12 dB in band.
Autors: Yizhu Shen;Shi-Gang Zhou;Guan-Long Huang;Tan-Huat Chio;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2016, volume: 64, issue:11, pages: 4933 - 4936
Publisher: IEEE
 
» A Compact Model for Double-Gate Heterojunction Tunnel FETs
Abstract:
A compact model for generic heterojunction tunnel FETs (H-TFET) is developed to simulate H-TFET formed by different source/body material systems. The model is based on the device electrostatic potentials obtained from the solution of Poisson’s equation. After deriving the potential profile, the tunneling distance from the source to the channel is calculated by matching the boundary conditions between the two materials. The drain current, terminal charges, and capacitance are derived based on the electrostatics dictated by the tunneling distance. To improve the accuracy for lightly doped source H-TFET in p-type devices, the effect of source depletion is also included. The model has been implemented in a circuit simulator without convergence program. It has also been extensively verified by TCAD simulations and published data to show its validity.
Autors: Yunpeng Dong;Lining Zhang;Xiangbin Li;Xinnan Lin;Mansun Chan;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2016, volume: 63, issue:11, pages: 4506 - 4513
Publisher: IEEE
 
» A Compact Model of Drain Current for GaN HEMTs Based on 2-DEG Charge Linearization
Abstract:
A physics-based simple and accurate compact model of drain current for GaN-based high electron mobility transistors (HEMTs) is presented. The model is developed using analytical relations for charges in the 2-D electron gas and barrier layer. For the first time, a simple charge linearization approach has been used for GaN-based HEMTs. The access regions are accurately modeled using transistors. The model is rigorously validated over a wide range of geometries and parameters for AlGaN/GaN and AlInN/GaN HEMTs. The model also passes the DC Gummel symmetry test.
Autors: Naveen Karumuri;Gourab Dutta;Nandita DasGupta;Amitava DasGupta;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2016, volume: 63, issue:11, pages: 4226 - 4232
Publisher: IEEE
 
» A Compact Tunable Power Divider With Wide Tuning Frequency Range and Good Reconfigurable Responses
Abstract:
A compact tunable power divider is proposed in this brief. The power divider can achieve a wide frequency tuning range and good matching and isolation performances. Theoretical equations for the characteristic impedance and the electrical length of the power divider are derived. For demonstration, a prototype working at 1.5 GHz as the center frequency is designed and fabricated. The measured results show that the power divider can be effectively tuned within the frequency range of 104% (0.83–2.4 GHz) with a return loss and isolation better than 20 dB and insertion loss varying between −3.3 dB and −3.5 dB.
Autors: Tianyu Zhang;Wenquan Che;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2016, volume: 63, issue:11, pages: 1054 - 1058
Publisher: IEEE
 
» A Compact, Active SiGe Power Divider With Multi-Octave Bandwidth
Abstract:
This letter proposes a wideband active power divider, which realizes multi-octave bandwidth with positive, flat gain, and good isolation. By combining a single stage amplifier with artificial transmission lines and emitter-follower (EF) output stages, a broadband operational bandwidth (2.5-23.0 GHz) and flat gain response (8.8-11.8 dB) with a small chip size are achieved while maintaining good isolation (25 dB) between the output ports. The measured noise figures (NFs) of the two forward paths are lower than 9 dB, the output P1dB (OP1dB) is greater than −9 dBm and the output IP3 (OIP3) is greater than 0 dBm over the 3 dB bandwidth. The maximum amplitude and phase imbalances of the two output ports are 0.2 dB and 1.6 degrees, respectively. The core area of the active power divider is mm. The active power divider consumes 20 mA from a 3.3 V DC supply.
Autors: Moon-Kyu Cho;Ickhyun Song;Inchan Ju;John D. Cressler;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2016, volume: 26, issue:11, pages: 945 - 947
Publisher: IEEE
 
» A Comparison Between Compounding Techniques Using Large Beam-Steered Plane Wave Imaging for Blood Vector Velocity Imaging in a Carotid Artery Model
Abstract:
Conventional color Doppler imaging is limited, since it only provides velocity estimates along the ultrasound beam direction for a restricted field of view at a limited frame rate. High-frame-rate speckle tracking, using plane wave transmits, has shown potential for 2-D blood velocity estimation. However, due to the lack of focusing in transmit, image quality gets reduced, which hampers speckle tracking. Although ultrafast imaging facilitates improved clutter filtering, it still remains a major challenge in blood velocity estimation. Signal dropouts and poor velocity estimates are still present for high beam-to-flow angles and low blood flow velocities. In this paper, ultrafast plane wave imaging was combined with multiscale speckle tracking to assess the 2-D blood velocity vector in a common carotid artery (CCA) flow field. A multiangled plane wave imaging sequence was used to compare the performance of displacement compounding, coherent compounding, and compound speckle tracking. Zero-degree plane wave imaging was also evaluated. The performance of the methods was evaluated before and after clutter filtering for the large range of velocities (0–1.5 m/s) that are normally present in a healthy CCA during the cardiac cycle. An extensive simulation study was performed, based on a sophisticated model of the CCA, to investigate and evaluate the performance of the methods at different pulse repetition frequencies and signal-to-noise levels. In vivo data were acquired of a healthy carotid artery bifurcation to support the simulation results. In general, methods utilizing compounding after speckle tracking, i.e., displacement compounding and compound speckle tracking, were least affected by clutter filtering and provided the most robust and accurate estimates for the entire velocity range. Displacement compounding, which uses solely axial information to estimate the velocity vector, provided most accurate velocity estimates, although it- required sufficiently high pulse repetition frequencies in high blood velocity phases and reliable estimates for all acquisition angles. When this latter requirement was not met, compound speckle tracking was most accurate, because it uses the possibility to discard angular velocity estimates corrupted by clutter filtering. Similar effects were observed for in vivo data obtained at the carotid artery bifurcation. Investigating a combination of these two compounding techniques is recommended for future research.
Autors: Anne E. C. M. Saris;Hendrik H. G. Hansen;Stein Fekkes;Maartje M. Nillesen;Marcel C. M. Rutten;Chris L. de Korte;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Nov 2016, volume: 63, issue:11, pages: 1758 - 1771
Publisher: IEEE
 
» A Comprehensive Computational Modeling Approach for AlGaN/GaN HEMTs
Abstract:
This paper for the first time presents a comprehensive computational modeling approach for AlGaN/GaN high electron mobility transistors. Impact of the polarization charge at different material interfaces on the energy band profile as well as parasitic charge across the epitaxial stack is modeled and studied. Furthermore, impact of surface and bulk traps on two-dimensional electron gas, device characteristics, and gate leakage is accounted in this paper. For the first time, surface states modeled as donor type traps were correlated with gate leakage. Moreover, a new approach to accurately model the forward gate leakage in Schottky gate devices is proposed. Finally, impact of lattice and carrier heating is studied, while highlighting the relevance of carrier heating, lattice heating, and bulk traps over the device characteristics. In addition to this, modeling strategy for other critical aspects like parasitic charges, quantum effects, S/D Schottky contacts, and high field effects is presented.
Autors: Vipin Joshi;Ankit Soni;Shree Prakash Tiwari;Mayank Shrivastava;
Appeared in: IEEE Transactions on Nanotechnology
Publication date: Nov 2016, volume: 15, issue:6, pages: 947 - 955
Publisher: IEEE
 
» A CORDIC Based Digital Hardware For Adaptive Exponential Integrate and Fire Neuron
Abstract:
This paper presents a COordinate Rotation DIgital Computer (CORDIC) based Adaptive Exponential Integrate and Fire (AdEx) neuron for efficient large scale biological neural network implementation. The accuracy of the modified model is investigated by both calculating various errors and bifurcation analysis; both show that the proposed model follows the same signaling, dynamical behavior, and bifurcation pattern as the original model. Network behavior of the original and proposed models are also observed to be very much alike in following the same activity patterns. The model is hardware synthesized and implemented on FPGA as a proof of concept. Measurement results show that the proposed model can reproduce neuronal behaviors similar to the original model. Hardware device utilization and speed also confirm the efficiency of the realized hardware compared with previous works.
Autors: Moslem Heidarpour;Arash Ahmadi;Rashid Rashidzadeh;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2016, volume: 63, issue:11, pages: 1986 - 1996
Publisher: IEEE
 
» A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications
Abstract:
We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh cryogenic environment. The proposed architecture employs time-to-digital converters (TDCs) and phase interpolation techniques to reach a sampling rate, higher than the clock frequency (maximum 400 MHz), up to 1.2 GSa/s. The resulting FPGA ADC can achieve a 6 bit resolution (ENOB) over a 0.9 to 1.6 V input range and an effective resolution bandwidth (ERBW) of 15 MHz. This implies that the ADC has an effective Nyquist rate of 30 MHz, with an oversampling ratio of . The system non-linearities are less than 1 LSB. The main advantages of this architecture are its scalability and reconfigurability, enabling applications with changing demands on one single platform.
Autors: Harald Homulle;Stefan Visser;Edoardo Charbon;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2016, volume: 63, issue:11, pages: 1854 - 1865
Publisher: IEEE
 
» A Customizable Framework for Application Implementation onto 3-D FPGAs
Abstract:
Integrating more functionality in a smaller form factor with higher performance and lower-power consumption is pushing semiconductor technology scaling to its limits. 3-D chip stacking is touted as the silver bullet technology that can keep Moore’s momentum and fuel the next wave of consumer electronic products. Additionally, the complexity of digital designs imposes that computer-aided design algorithms are getting harder and slower. This paper introduces a framework for application implementation onto 3-D reconfigurable architectures. In contrast to existing approaches, the proposed solution is customizable according to constraints posed by the application and the target 3-D device in order to improve performance metrics. Experimental results highlight the effectiveness of our framework, as we achieve average enhancements in terms of maximum operation frequency and power consumption by 35% and 47%, respectively, as compared to state-of-the-art algorithms.
Autors: Kostas Siozios;Dimitrios Soudris;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Nov 2016, volume: 35, issue:11, pages: 1783 - 1796
Publisher: IEEE
 
» A Data-Driven Bidding Model for a Cluster of Price-Responsive Consumers of Electricity
Abstract:
This paper deals with the market-bidding problem of a cluster of price-responsive consumers of electricity. We develop an inverse optimization scheme that, recast as a bilevel programming problem, uses price-consumption data to estimate the complex market bid that best captures the price-response of the cluster. The complex market bid is defined as a series of marginal utility functions plus some constraints on demand, such as maximum pick-up and drop-off rates. The proposed modeling approach also leverages information on exogenous factors that may influence the consumption behavior of the cluster, e.g., weather conditions and calendar effects. We test the proposed methodology for a particular application: forecasting the power consumption of a small aggregation of households that took part in the Olympic Peninsula project. Results show that the price-sensitive consumption of the cluster of flexible loads can be largely captured in the form of a complex market bid, so that this could be ultimately used for the cluster to participate in the wholesale electricity market.
Autors: Javier Saez-Gallego;Juan M. Morales;Marco Zugno;Henrik Madsen;
Appeared in: IEEE Transactions on Power Systems
Publication date: Nov 2016, volume: 31, issue:6, pages: 5001 - 5011
Publisher: IEEE
 
» A DIY Lego controller: A low-cost way to program Lego machines [Resources_Hands On]
Abstract:
If you want to explore coding with Lego bricks, there's one major option: to use a kit from the company's well-known Mindstorms robotics line. Mindstormsbased machines are built around the Intelligent Brick, which can be programmed using Lego's graphical programming environment or one of a number of third-party alternative languages. But Lego also makes a collection of motors, connectors, lights, and infrared receivers collectively sold under the label of Power Functions. In place of a programmable brick, the Power Function line includes a handheld controller for transmitting command signals.
Autors: Diomidis Spinell;
Appeared in: IEEE Spectrum
Publication date: Nov 2016, volume: 53, issue:11, pages: 21 - 22
Publisher: IEEE
 
» A Double-Layer Shaped-Beam Traveling-Wave Slot Array Based on SIW
Abstract:
A double-layer shaped-beam traveling-wave slot array based on substrate integrated waveguide (SIW) at -band is presented. The double-layer SIW longitudinal slot-coupled cavity slot is proposed as the array element, which has an improved bandwidth performance due to the double-resonant feature. By using this kind of slots, a planar nonuniformly spaced shaped-beam traveling-wave array is constructed. To achieve the desired distribution for the shaped-beam pattern, an efficient optimization method, with the mutual coupling effect being considered, is proposed to optimize the array structure parameters. Experimental results show that the array achieves good shaped-beam pattern in a 4.8% frequency band and low-loss characteristic.
Autors: Lei Qiu;Ke Xiao;Shun Lian Chai;Hui Ying Qi;Jun Jie Mao;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2016, volume: 64, issue:11, pages: 4639 - 4647
Publisher: IEEE
 
» A Dual-Wideband Differential Filter on Strip-Loaded Slotline Resonators with Enhanced Coupling Scheme
Abstract:
A dual-wideband differential filter with intrinsic common-mode suppression is presented. The filter is composed of three coupled strip-loaded slotline resonators and strip- loaded coupled slotlines with enhanced coupling strength. Two resonant modes of each resonator are utilized to design the desired dual-wide passbands, whereas the coupling coefficients in two passbands can be independently controlled to achieve dual-band frequency selectivity. The theory and design have been verified experimentally.
Autors: Xin Guo;Lei Zhu;Wen Wu;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2016, volume: 26, issue:11, pages: 882 - 884
Publisher: IEEE
 
» A Family of DC–DC Converters Deduced From Impedance Source DC–DC Converters for High Step-Up Conversion
Abstract:
A family of dc-dc converters based on impedance source dc-dc converters is presented. The scheme of the proposed family is that the switch of impedance source dc-dc converters is moved forward. The derived topologies are suitable for high-voltage step-up ratio. Compared to the typical impedance source dc-dc converters, the presented topology dramatically reduces the voltage stresses on the power semiconductor devices. In addition, the passive lossless clamped circuit is introduced into the proposed family to restrict the peak voltage of the main switch. This paper presents an analysis of the converter and results from a prototype converter to validate the topology's performance.
Autors: Hongchen Liu;Fei Li;Pat Wheeler;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Nov 2016, volume: 63, issue:11, pages: 6856 - 6866
Publisher: IEEE
 
» A Fast Discrete Wavelet Transform Using Hybrid Parallelism on GPUs
Abstract:
Wavelet transform has been widely used in many signal and image processing applications. Due to its wide adoption for time-critical applications, such as streaming and real-time signal processing, many acceleration techniques were developed during the past decade. Recently, the graphics processing unit (GPU) has gained much attention for accelerating computationally-intensive problems and many solutions of GPU-based discrete wavelet transform (DWT) have been introduced, but most of them did not fully leverage the potential of the GPU. In this paper, we present various state-of-the-art GPU optimization strategies in DWT implementation, such as leveraging shared memory, registers, warp shuffling instructions, and thread- and instruction-level parallelism (TLP, ILP), and finally elaborate our hybrid approach to further boost up its performance. In addition, we introduce a novel mixed-band memory layout for Haar DWT, where multi-level transform can be carried out in a single fused kernel launch. As a result, unlike recent GPU DWT methods that focus mainly on maximizing ILP, we show that the optimal GPU DWT performance can be achieved by hybrid parallelism combining both TLP and ILP together in a mixed-band approach. We demonstrate the performance of our proposed method by comparison with other CPU and GPU DWT methods.
Autors: Tran Minh Quan;Won-Ki Jeong;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Nov 2016, volume: 27, issue:11, pages: 3088 - 3100
Publisher: IEEE
 
» A Fast Switching Current Regulator Using Slewing Time Reduction Method for High Dimming Ratio of LED Backlight Drivers
Abstract:
This brief proposes a fast switching current regulator to achieve a high dimming ratio of the light-emitting diode (LED) backlight drivers. The proposed current regulator employs the slewing time reduction method to enhance the dimming ratio by decreasing the rising time of the LED forward current. A six-channel LED backlight driver was fabricated using a 0.35- bipolar-CMOS-DMOS process technology which includes an n-type MOSFET with a low voltage of 5 V and a high-side lateral double diffused MOSFET with a breakdown voltage of 60 V. The measured rising time and minimum pulsewidth of the LED forward current are reduced to 4.8 ns and 12 ns, respectively, at a current transition of 60 mA. Consequently, the dimming ratio of the LED backlight driver using the proposed current regulator is calculated to be 160 000 : 1 at a dimming frequency of 500 Hz, which is more than three times higher than that obtained using the previously reported current regulators. Therefore, the proposed current regulator is suitable for high-end displays which require high image quality.
Autors: Hyun-A Ahn;Seong-Kwan Hong;Oh-Kyong Kwon;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2016, volume: 63, issue:11, pages: 1014 - 1018
Publisher: IEEE
 
» A Fine Day for an Eclipse: It's Never Too Early to Start Planning for One
Abstract:
On 21 August 2017, the United States will experience one of the most amazing phenomena imaginable. A total eclipse of the sun will occur, and essentially everyone in the contiguous 48 states will experience it to some extent. What?s more, the so-called "path of totality" will stretch from coast to coast-Oregon to South Carolina (Figure 1). It's likely that more people will experience this solar eclipse than any in history. The approximately 12 million people who live within the 70-mi-wide path of totality, plus the thousands more who'll travel sometimes very long distances, will see a once-in-a-lifetime event: the disk of the moon completely and exactly blocking the disk of the sun. Assuming they have clear skies, of course!
Autors: George C. Loehr;
Appeared in: IEEE Power and Energy Magazine
Publication date: Nov 2016, volume: 14, issue:6, pages: 72 - 77
Publisher: IEEE
 
» A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems
Abstract:
Runtime attacks on memory, such as buffer overflow based stack smashing and code reuse attacks, are common in embedded systems. Control flow integrity (CFI) has been acknowledged as one promising approach to protect against such runtime attacks. However, previous CFI implementations suffer from coarse granularity (which can be circumvented by an advanced attack model) and high-performance overhead. In this paper, first, we present an approach to enforce fine-grained CFI at a basic block level, named basic block CFI (BB-CFI), which aims to defend against aforesaid attacks. The key idea is to verify the target address (TA) of control flow instructions (CFINs) (e.g., , , and ), which may be modified by the adversary. BB-CFI contains two stages: 1) offline profiling of the program—to extract the control flow information and 2) runtime control flow checking—to verify the TA of CFINs using the extracted information. We also handle the exceptional cases (e.g., multithreading, C++ exception, and longjump) that are found in complex binaries. Second, we propose an architectural design of control flow checker (CFC), which monitors the program execution during runtime to enforce BB-CFI. For proof of concept, we implement the CFC in field-programmable gate array (FPGA). Our method does not require the modification of the source code or the instruction set architecture. The experimental results demonstrate that BB-CFI is effective against runtime attacks, with 100% verification accuracy. The CFC implementation on FPGA shows <1% performance overhead and a small dynamic power consumption of 78 mW, with very small area footprint.
Autors: Sanjeev Das;Wei Zhang;Yang Liu;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2016, volume: 24, issue:11, pages: 3193 - 3207
Publisher: IEEE
 
» A Flexible and Low-Complexity Local Erasure Recovery Scheme
Abstract:
For large-scale distributed storage, besides redundancy, locality in terms of the number of data and parity symbols to access for failure recovery is a critical issue to address in order to ensure data availability, lower network traffic, and reduce recovery latency. A flexible yet low-complexity scheme for local erasure recovery is presented in this letter. Although the proposed scheme is not maximum distance separable, it does not have any constraint on the locality nor the parameters of the code, allows easy tradeoff on the locality and redundancy, and can achieve unequal protection over drives with different reliabilities. More importantly, it enables low-complexity implementation. An efficient hardware architecture for the proposed scheme is developed. It has very small overhead compared with traditional erasure codes when correction capability is not large, such as 2, 3, or 4.
Autors: Xinmiao Zhang;Steven Sprouse;Ishai Ilani;
Appeared in: IEEE Communications Letters
Publication date: Nov 2016, volume: 20, issue:11, pages: 2129 - 2132
Publisher: IEEE
 
» A Flexible DC Voltage Balancing Control Based on the Power Flow Management for Star-Connected Cascaded H-Bridge Converter
Abstract:
This paper presents the flexible dc capacitor voltages balancing control method for star-connected cascaded H-bridge converters. In this paper, the power flows are analyzed by investigating all the converter's control freedoms. Based on the analyses, users can accomplish the dc capacitor voltage balancing with both negative-sequence current and zero-sequence voltage. These two kinds of control options are further integrated together with the defined weighting factor . The low-voltage ride-through operation of a proposed control method is also discussed in this paper. The control method is verified with a 220-V 1-kVA static synchronous compensators based on the star-connected cascaded H-bridge converters, and the experimental test results show that all the dc voltages are well regulated at the commanded value with different weighting factor .
Autors: Hsin-Chih Chen;Ping-Heng Wu;Chia-Tse Lee;Ching-Wei Wang;Ching-Hsiang Yang;Po-Tai Cheng;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Nov 2016, volume: 52, issue:6, pages: 4946 - 4954
Publisher: IEEE
 
» A Fully Integrated 320 GHz Coherent Imaging Transceiver in 130 nm SiGe BiCMOS
Abstract:
A 320 GHz fully integrated terahertz imaging system is reported. The system is composed of a phase-locked high-power transmitter and a coherent high-sensitivity subharmonic-mixing receiver, which are fabricated using a 130 nm SiGe BiCMOS technology (220/280 GHz). To enhance the imaging sensitivity, a heterodyne coherent detection scheme is utilized. To obtain frequency coherency, fully integrated phase-locked loops are implemented on both the transmitter and receiver chips. According to the measurement results, consuming a total dc power of 605 mW, the transmitter chip achieves a peak radiated power of 2 mW and a peak EIRP of 21.1 dBm. The receiver chip achieves an equivalent incoherent responsivity of more than 7.26 MV/W and a sensitivity of 70.1 pW under an integration bandwidth of 1 kHz, with a total dc power consumption of 117 mW. The achieved sensitivity with this proposed coherent imaging transceiver is around ten times better compared with other state-of-the-art incoherent imagers. To the best of our knowledge, this paper demonstrates the first fully integrated coherent terahertz imaging transceiver on silicon.
Autors: Chen Jiang;Ali Mostajeran;Ruonan Han;Mohammad Emadi;Hani Sherry;Andreia Cathelin;Ehsan Afshari;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2596 - 2609
Publisher: IEEE
 
» A Fully Integrated RF CMOS Front-End IC for Connectivity Applications
Abstract:
A fully integrated RF CMOS front-end (FE) IC (FEIC), which is fabricated with a 0.13- bulk RF CMOS process for wireless local area network/Bluetooth (WLAN/BT) applications, is presented. The proposed FEIC includes a dual-mode power amplifier (PA), integrated switches, and a shared low-noise amplifier (LNA) without external matching networks. The proposed compact reconfigurable matching network satisfies the optimum matchings for a multimode PA and a shared LNA. Measurements showed a 16.2-dBm , with a 6.7% power-added efficiency (PAE), at −34-dB error vector magnitude, with an 802.11ac signal source, with a high-power-mode WLAN PA. With a low-power-mode BT PA, it showed a 13.7-dBm , with a 10.9% PAE, with a 2.1+EDR signal. The shared LNA has a 14.8-dB gain and a 3.6-dB noise figure. All the measurements were carried out, including integrated mode-change switches for time-division duplex operation without any digital predistortion.
Autors: Taehwan Joo;Dong-Ho Lee;Songcheol Hong;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2016, volume: 63, issue:11, pages: 1024 - 1028
Publisher: IEEE
 
» A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $SigmaDelta$ ADC
Abstract:
This paper proposes a fully-digital BIST architecture for the dynamic test of ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a test with a higher dynamic range that covers the full scale of the ADC. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNDR. A standard SPI bus provides digital external access to the embedded test instruments. The proposed BIST wrapper has been integrated into a 40 nm CMOS 18-bit stereo audio ADC IP core provided by ST Microelectronics. It incurs an overall area overhead of 7.1% and the total test time is 28 ms per channel. Experimental results on fabricated chips demonstrate an excellent correlation between the BIST and the standard functional specification test.
Autors: Manuel J. Barragan;Rshdee Alhakim;Haralampos-G. Stratigopoulos;Matthieu Dubois;Salvador Mir;Hervé Le Gall;Neha Bhargava;Ankur Bal;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2016, volume: 63, issue:11, pages: 1876 - 1888
Publisher: IEEE
 
» A General Power Allocation Scheme to Guarantee Quality of Service in Downlink and Uplink NOMA Systems
Abstract:
In this paper, a novel dynamic power allocation scheme is proposed to downlink and uplink non-orthogonal multiple access (NOMA) scenarios with two users for more flexibly meeting various quality of service requirements. The exact expressions for the outage probability and the average rate achieved by the proposed scheme, as well as their high signal-to-noise ratio approximations, are established. Compared with the existing works, such as NOMA with fixed power allocation and cognitive radio inspired NOMA, the proposed scheme can: 1) strictly guarantee a performance gain over conventional orthogonal multiple access; and 2) offer more flexibility to realize different tradeoffs between the user fairness and system throughput. Monte Carlo simulation results are provided to demonstrate the accuracy of the developed analytical results and the performance gain of the proposed power allocation scheme.
Autors: Zheng Yang;Zhiguo Ding;Pingzhi Fan;Naofal Al-Dhahir;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Nov 2016, volume: 15, issue:11, pages: 7244 - 7257
Publisher: IEEE
 
» A General Simulation Framework for Modeling and Analysis of Heavy-Duty Vehicle Platooning
Abstract:
Platooning heavy-duty vehicles (HDVs) on a highway is a method for improving energy and transport efficiency. On one hand, HDV platoon driving in small intervehicle distances could increase highway capacity; on the other hand, HDVs traveling in small intervehicle distances experience significant air-drag reduction and, therefore, improve fuel efficiency. However, although the majority of research has been conducted on the development of platoon systems, very few studies have focused on quantification of the impacts of HDV platooning on traffic flow. This paper initializes a simulation framework to facilitate the study of HDV platooning and establishes the corresponding concept and operations. The longitudinal driving behaviors of HDV platoons are modeled in detail, considering the acceleration capability of an HDV. The proposed framework is applied on three experimental cases: the first case is to study the impacts of HDV platooning on traffic flow and the second and third cases are about the influence of traffic on HDV platoon formation. In the first case, simulation outcomes show that the increasing percentage of HDV platooning in traffic flow generally results in more dramatic improvements on traffic efficiency, while preserving traffic safety for passenger vehicles. In the second and third cases, for the HDV platoon formation, deceleration of the first HDV to a low speed during platoon formation will increase the formation time to a large extent in medium and heavy traffic.
Autors: Qichen Deng;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Nov 2016, volume: 17, issue:11, pages: 3252 - 3262
Publisher: IEEE
 
» A Generalized Reaction Theorem That Eliminates Internal Resonances in the Electric and Magnetic Field Integral Equations
Abstract:
This paper presents stable magnetic-field and electric-field integral equation formulations for exterior electromagnetic scattering by either penetrable or perfectly conducting closed bodies of general shape. The development relies on an extension of the conventional reciprocity theorem allowing the fields produced by some combination of sources in one environment to be connected with the fields generated by another combination of sources in a different environment. By the use of lossy metamaterials, the internal-resonance problem inherent to the original versions is eliminated, and thus the new formulations are amenable to a unique, highly accurate, and well-conditioned solution.
Autors: John L. Tsalamengas;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2016, volume: 64, issue:11, pages: 4745 - 4752
Publisher: IEEE
 
» A Generic Framework for the Development of Geospatial Processing Pipelines on Clusters
Abstract:
The amount of remote sensing (RS) data available for applications is constantly growing due to the rise of very high resolution sensors and short-repeat-cycle satellites. Consequently, tackling the computational complexity in Earth observation information extraction is rising as a major challenge. Resorting to high-performance computing (HPC) is becoming a common practice, since this provides environments and programming facilities that are able to speed up processes. In particular, clusters are flexible cost-effective systems that are able to perform data-intensive tasks ideally fulfilling any computational requirement. However, their use typically implies a significant coding effort to build proper implementations of specific processing pipelines. This letter presents a generic framework for the development of RS images processing applications targeting cluster computing. It is based on common open-source libraries and leverages the parallelization of a wide variety of image processing pipelines in a transparent way. Performances on typical RS tasks implemented using the proposed framework demonstrate a great potential for the effective and timely processing of large amount of data.
Autors: Rémi Cresson;Gabriel Hautreux;
Appeared in: IEEE Geoscience and Remote Sensing Letters
Publication date: Nov 2016, volume: 13, issue:11, pages: 1706 - 1710
Publisher: IEEE
 
» A Grouping Based on Local Girths for the Group Shuffled Belief Propagation Decoding
Abstract:
Low-density parity-check codes have been known to exhibit good error correcting performance by using with the belief propagation (BP) decoding. The group shuffled BP decoding, which is a modification of the BP decoding, can exhibit a better performance than BP decoding by suitably grouping variable nodes in a Tanner graph. In this letter, we propose a new grouping of variable nodes based on local girths and evaluate its performance.
Autors: Akiko Manada;Kyohei Yoshida;Hiroyoshi Morita;Ryuichi Tatasukawa;
Appeared in: IEEE Communications Letters
Publication date: Nov 2016, volume: 20, issue:11, pages: 2133 - 2136
Publisher: IEEE
 
» A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI
Abstract:
Pushed by the ever-increasing demand of high-speed connectivity, next generation 400 Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45 Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits feed-forward equalizer (FFE), and allows tuning the output impedance to ensure good source termination. Implemented in 28 nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, kV HBM ESD diodes, and delivers a full swing of 1.3 Vppd at 45 Gb/s, while drawing only 120 mA from 1 V supply. The power efficiency is times better than previously reported PAM-4 transmitters.
Autors: Matteo Bassi;Francesco Radice;Melchiorre Bruccoleri;Simone Erba;Andrea Mazzanti;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2016, volume: 51, issue:11, pages: 2702 - 2715
Publisher: IEEE
 
» A Highly Reliable Single-Phase High-Frequency Isolated Double Step-Down AC–AC Converter With Both Noninverting and Inverting Operations
Abstract:
In this paper, the switching cell concept is extended to isolated ac–ac converters, and a highly reliable double step-down ac–ac converter is proposed with high-frequency transformer (HFT) isolation. By using the switching cell structure and coupled inductors, the proposed converter has no commutation problem as it is immune from both short-circuit and open-circuit problems, even when all the switches are turned on or turned off, simultaneously. Therefore, it does not require pulse width modulation dead times along with bulky and lossy RC snubbers or voltage-sensing circuitry to implement soft-commutation strategies, resulting in high reliability and high quality output waveforms. The HFT in the proposed converter provides electrical isolation and safety which is required in applications such as dynamic voltage restorer (DVR), solid-state transformer (SST), etc., without the need for external bulky line frequency transformer. Moreover, all the passive components experience twice the switching frequency; therefore, their size can be reduced. The proposed converter is very suitable for application as DVR, to compensate both voltage sags and swells, owing to its ability to provide both inverting and noninverting outputs. A detailed theoretical analysis and operation of the proposed ac–ac converter are provided, and its applications as DVR and SST are also discussed. Experimental results with scaled-down prototype are also provided to verify its performance.
Autors: Hafiz Furqan Ahmed;Honnyong Cha;Ashraf Ali Khan;Heung-Geun Kim;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Nov 2016, volume: 52, issue:6, pages: 4878 - 4887
Publisher: IEEE
 
» A Homogenization Technique for Obtaining Generalized Sheet-Transition Conditions for a Metafilm Embedded in a Magnetodielectric Interface
Abstract:
Using the multiple-scale homogenization method, we derive generalized sheet-transition conditions for electromagnetic fields at the surface of a metafilm. The scatterers that compose the metafilm are of arbitrary shape and are embedded between two different magnetodielectric media. The parameters in these boundary conditions are interpreted as effective electric and magnetic surface susceptibilities, which themselves are related to the geometry of the scatterers that constitute the metafilm.
Autors: Christopher L. Holloway;Edward F. Kuester;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2016, volume: 64, issue:11, pages: 4671 - 4686
Publisher: IEEE
 
» A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence
Abstract:
Traditional cache coherence protocols manage all memory accesses equally and ensure the strongest memory model, namely, sequential consistency. Recent cache coherence protocols based on self-invalidation advocate for the model sequential consistency for data-race-free, which enables powerful optimizations for race-free code. However, for racy code these cache coherence protocols provide sub-optimal performance compared to traditional protocols. This paper proposes SPEL++, a dual-consistency cache coherence protocol that supports two execution modes: a traditional sequential-consistent protocol and a protocol that provides weak consistency (or sequential consistency for data-race-free). SPEL++ exploits a static-dynamic hybrid classification of memory accesses based on (i) a compile-time identification of extended data-race-free code regions for OpenMP applications and (ii) a runtime classification of accesses based on the operating system's memory page management. By executing racy code under the sequential-consistent protocol and race-free code under the cache coherence protocol that provides sequential consistency for data-race-free, the end result is an efficient execution of the applications while still providing sequential consistency. Compared to a traditional protocol, we show improvements in performance from 19 to 38 percent and reductions in energy consumption from 47 to 53 percent, on average for different benchmark suites, on a 64-core chip multiprocessor.
Autors: Alberto Ros;Alexandra Jimborean;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Nov 2016, volume: 27, issue:11, pages: 3101 - 3115
Publisher: IEEE
 
» A Hybrid Stochastic/Deterministic Unit Commitment Based on Projected Disjunctive MILP Reformulation
Abstract:
This letter presents a new expression of the chance constraint, representing ramping and operating reserve, in the context of the mixed integer linear programming (MILP) formulation for solving the hybrid stochastic/deterministic unit commitment (SDUC) problem. Based on projected disjunctive programming, the nonlinear chance constraint is converted into a set of linear constraints that has a more compact size. Numerical simulations highlight the primacy of the proposed MILP-SDUC reformulation as compared with other formulation approaches.
Autors: Wen-Shan Tan;Mohamed Shaaban;
Appeared in: IEEE Transactions on Power Systems
Publication date: Nov 2016, volume: 31, issue:6, pages: 5200 - 5201
Publisher: IEEE
 
» A Hybrid Transmission Grid Architecture Enabling Efficient Optimal Power Flow
Abstract:
The recent rise of electricity generation based on renewable energy sources increases the demand for transmission capacity. Capacity expansion via the upgrade of transmission line capacity, e.g., by conversion to a high-voltage direct current (HVDC) line, is an attractive option. In this paper, it is shown that if the upgrade to HVDC is applied systematically to selected transmission lines across the grid, a hybrid architecture is obtained that enables an efficient and globally optimal solution of the optimal power flow (OPF) problem. More precisely, for conventional meshed AC transmission grids the OPF problem is nonconvex and in general NP-hard, rendering it hard to solve. We prove that after the upgrade to the proposed hybrid architecture, the same mesh topology facilitates an exact convex relaxation of the OPF problem, enabling its globally optimal solution with efficient polynomial time algorithms. This OPF method is then employed in simulations, which demonstrate that the hybrid architecture can increase the effective transmission capacity and substantially reduce the generation costs, even compared to the AC grid with optimal transmission switching.
Autors: Matthias Hotz;Wolfgang Utschick;
Appeared in: IEEE Transactions on Power Systems
Publication date: Nov 2016, volume: 31, issue:6, pages: 4504 - 4516
Publisher: IEEE
 
» A K-band 24.1% PAE Wideband Unilateralized CMOS Power Amplifier Using Differential Transmission-Line Transformers in 0.18- $mu text{m}$ CMOS
Abstract:
This letter presents a K-band CMOS power amplifier that adopted a unilateralized technique to mitigate the intrinsic gate-drain feedback effect of the transistor for increasing the reverse isolation and power gain. This three-differential-stage amplifier used low-loss transmission-line transformers (TLTs) for the input/output impedance matching networks and the transformers (TFs) for the inter-stage coupling. The obtained 3-dB bandwidth is from 18.8 to 23.3 GHz with better than 58-dB reverse isolation. The amplifier achieves a power gain of 26.2 dB, a saturation output power of 20.3 dBm, an output 1-dB gain compression point of 17.2 dBm and power added efficiency (PAE) of 24.1% under a power consumption of 440 mW. The chip size is 1.12 mm2 including all pads.
Autors: Po-Hsun Chen;Hwann-Kaeo Chiou;Yuan-Chang Wang;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2016, volume: 26, issue:11, pages: 924 - 926
Publisher: IEEE
 
» A Ka-Band Single-Chip SiGe BiCMOS Phased-Array Transmit/Receive Front-End
Abstract:
This paper presents the detailed design and demonstration of a Ka-band single-chip transmit (TX)/receive (RX) front-end in 0.13- SiGe BiCMOS technology. The front-end includes single-pole double-throw (SPDT) switches, low-noise amplifier, loss compensation amplifiers (LCAs), phase shifter, and power amplifier. Distributed structures are utilized in gain amplifiers to ensure broadband performance while stacked structure is adopted in power amplifier to deliver high output power in the TX mode. A 5-b phase shifter with design strategies for low rms phase/gain errors serves as the common leg of the RX and TX paths. In the RX mode, measurements show a gain of 17 dB, an output of −1 dBm, an rms phase error less than 4°, and an rms gain error less than 0.6 dB with 0.528-W dc power from 30 to 40 GHz. In the TX mode, measurements show a gain of 14 dB, an output of 20.5 dBm, an rms phase error less than 3.7°, and an rms gain error less than 0.55 dB with 1.587-W dc power from 30 to 40 GHz. The whole front-end occupies mm2 including the testing pads. By choosing inductors and capacitors with reasonable values, designing a well-matched SPDT switch with high isolation, and optimum ordering of phase shift cells and LCAs in the phase shifter design, this TX/RX front-end achieves excellent rms phase/gain error performance without any trimming in a system-level measurement at Ka-band.
Autors: Chao Liu;Qiang Li;Yihu Li;Xiao-Dong Deng;Hailin Tang;Ruitao Wang;Haitao Liu;Yong-Zhong Xiong;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2016, volume: 64, issue:11, pages: 3667 - 3677
Publisher: IEEE
 
» A Knowledge-Based Framework of Innovation Strategy: The Differential Effect of Knowledge Sources
Abstract:
Using an exploration–exploitation framework, this study examines how firms’ innovation strategies rely on different knowledge sources (own-generated, bought-in, and codeveloped) that affect innovation performance. It utilizes data from the 2008 Community Innovation Survey covering 9054 sample firms from 14 European countries. Results derived from multiple-method empirical analysis indicate that investments into acquiring different knowledge sources will generate different values, depending on key contextual factors. In particular, we find that for firms following explorative innovation strategy (focused on developing new products, processes, and technologies), investments in own-generated and bought-in knowledge will improve innovation performance, whereas for those following exploitative innovation strategy (focused on refining existing products, processes and technologies), only investments in bought-in knowledge will create a positive impact on innovation performance. Additionally, firms that simultaneously pursue both exploration and exploitation (ambidextrous innovation strategy) will have maximal innovation performance by investing into all three types of knowledge sources. This study hence contributes new insights regarding the strategic choice of knowledge source.
Autors: Elena Revilla;Beatriz Rodriguez-Prado;Zhijian Cui;
Appeared in: IEEE Transactions on Engineering Management
Publication date: Nov 2016, volume: 63, issue:4, pages: 362 - 376
Publisher: IEEE
 

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