Electrical and Electronics Engineering publications abstract of: 11-2015 sorted by title, page: 0

» 0.34 AlGaN/GaN-on-Si Large Schottky Barrier Diode With Recessed Dual Anode Metal
Abstract:
A large GaN-Schottky barrier diode (SBD) with a recessed dual anode metal is proposed to achieve improved the forward characteristics without a degradation of the reverse performances. Using optimized dry etch condition for a large device, the electrical characteristics of the device are demonstrated when applying the recessed dual anode metal and changing the recess depths. The device size and channel width are 4 mm2 and 63 mm, respectively. The 16-nm recessed dual anode metal SBD has a turn-on voltage of 0.34 V, a breakdown voltage of 802 V, and a reverse leakage current of /mm at −15 V. The packaged SBD exhibits a forward current of 6.2 A at 2 V and a reverse recovery charge of 11.54 nC.
Autors: Lee, H.;Jung, D.Y.;Park, Y.;Na, J.;Jang, H.;Lee, H.;Jun, C.;Park, J.;Ryu, S.;Ko, S.C.;Nam, E.S.;
Appeared in: IEEE Electron Device Letters
Publication date: Nov 2015, volume: 36, issue:11, pages: 1132 - 1134
Publisher: IEEE
 
» 123 Gbit/in2 Recording Areal Density on Barium Ferrite Tape
Abstract:
The recording performance of a prototype magnetic tape based on perpendicularly oriented barium ferrite particles is investigated using an enhanced field tape write head and a 90 nm wide giant-magnetoresistive reader. A linear density of 680 kbits/in with a postdetection byte-error rate (BER) <3.2e-2 is demonstrated based on recorded data processed by a software read channel with noise-predictive maximum likelihood detection. With this detector error rate, a user BER of <1e-20 can be achieved by means of product error correction coding and iterative decoding. Several advances in the area of track-following servo control are also presented. Specifically, we describe a new timing-based servo pattern, which in combination with an optimized servo channel enables the generation of position estimates with nanoscale resolution and a high update rate. Track-following experiments are performed using an experimental low-noise tape transport, a prototype high-bandwidth actuator, and a set of speed-optimized H-infinity-based track-following controllers. Combining these technologies, we demonstrate a position-error signal (PES) with a standard deviation of 5.9 nm or less over a tape speed range of 1.23–4.08 m/s. This magnitude of PES in combination with a 90 nm wide reader allows operation with 140 nm wide tracks. Combined with a linear density of 680 kbits/in, this leads to an equivalent areal density of 123 Gbits/in2.
Autors: Lantz, M.A.;Furrer, S.;Engelen, J.B.C.;Pantazi, A.;Rothuizen, H.E.;Cideciyan, R.D.;Cherubini, G.;Haeberle, W.;Jelitto, J.;Eleftheriou, E.;Oyanagi, M.;Morooka, A.;Mori, M.;Kurihashi, Y.;Kaneko, T.;Tada, T.;Suzuki, H.;Harasawa, T.;Shimizu, O.;Ohtsu, H.
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» 140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology
Abstract:
Many design challenges exist in achieving high frequency clocking for high-speed applications. This paper describes a new clock distribution technique and clocking approach with the use of clock doublers in close proximity to sub-circuits to achieve higher data rates, and in many cases, reduce design complexity and power in serializers. A half-rate 4:1 serializer using this unique frequency doubling clock distribution technique has been implemented in a 90 nm BiCMOS process. The design includes a pattern length LFSR with phase shifting logic as the testing circuit and a high bandwidth cascoded output driver. The chip has the dimensions of 1.8 2.2 mm and consumes 5.78 W from a 3.4 V supply voltage at 140 Gb/s.
Autors: Clarke, R.;LeRoy, M.R.;Raman, S.;Neogi, T.G.;Kraft, R.P.;McDonald, J.F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2703 - 2713
Publisher: IEEE
 
» 2-D Data-Dependent Media Noise in Shingled Magnetic Recording
Abstract:
This paper investigates 2-D media noise in shingled magnetic recording (SMR) systems. The media noises caused by the overwriting of the next track and the residual information from the previous track are asymmetric in the cross-track (CT) direction and are found to vary with the linear density. The media noise after equalization is found to be 2-D data dependent, with its mean and variance affected by the nonlinear transition shift in the CT and down-track directions, respectively. Also the effect of media noise on the bit error rate (BER) is studied for increased track densities during the writing process. The effect of jitter on the BER is always significant with increased track density in SMR systems, while the effect of overwriting and inter-track interference on the BER performance are quite different for readback with rotated and normally oriented readers, even though the same writer is used during the writing process.
Autors: Wang, Y.;Victora, R.H.;Kumar, B.V.K.V.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 5
Publisher: IEEE
 
» 2-D Semianalytical Modeling of Eddy Currents in Segmented Structures
Abstract:
This paper concerns the semianalytical modeling of eddy currents in segmented structures of electromagnetic devices. A Fourier series is used to describe the spatial distribution of the conductivity and is included in the magnetic field solutions. By incorporating multiple time harmonics in the solution, the transient behavior of forces due to eddy currents can be obtained. To validate the developed method, it is applied to a coreless linear motor and compared with the finite-element results. The eddy currents in segmented conducting structures of motors, such as permanent magnet arrays, can be accurately determined with this method.
Autors: Custers, C.H.H.M.;Overboom, T.T.;Jansen, J.W.;Lomonova, E.A.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» 2015 MTT-S Graduate Student Fellowship Awards [Education News]
Abstract:
Presents the recipients of the 2015 MTT-S Graduate Student Fellowship awards.
Autors: Crupi, G.;Kaul, R.;Li, C.;Gupta, R.;
Appeared in: IEEE Microwave Magazine
Publication date: Nov 2015, volume: 16, issue:10, pages: 70 - 81
Publisher: IEEE
 
» 2D Semiconductor FETs—Projections and Design for Sub-10 nm VLSI
Abstract:
Two-dimensional (2D) crystal semiconductors, such as the well-known molybdenum disulfide (MoS2), are witnessing an explosion in research activities due to their apparent potential for various electronic and optoelectronic applications. In this paper, dissipative quantum transport simulations using nonequilibrium Green’s function formalism are performed to rigorously evaluate the scalability and performance of monolayer/multilayer 2D semiconductor-based FETs for sub-10 nm gate length very large-scale integration (VLSI) technologies. Device design considerations in terms of the choice of prospective 2D material/structure/technology to fulfill sub-10 nm International Technology Roadmap for Semiconductors (ITRS) requirements are analyzed. First, it is found that MoS2 FETs can meet high-performance (HP) requirement up to 6.6 nm gate length using bilayer MoS2 as the channel material, while low-standby-power (LSTP) requirements present significant challenges for all sub-10 nm gate lengths. Second, by studying the effects of underlap (UL) structures, scattering strength, and carrier effective mass, it is found that the high mobility and suitably low effective mass of tungsten diselenide (WSe2), aided by the UL, enable 2D FETs for both HP and LSTP applications at the smallest foreseeable (5.9 nm) gate length. Finally, possible solutions for sub-5 nm gate lengths, specifically anisotropic 2D semiconductor materials for HP and sub- switch (2D tunnel FET) for LSTP, are also proposed based on the effects of critical material parameters on the device performance.
Autors: Cao, W.;Kang, J.;Sarkar, D.;Liu, W.;Banerjee, K.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2015, volume: 62, issue:11, pages: 3459 - 3469
Publisher: IEEE
 
» 3-D Eddy Current and Fringing-Flux Distribution in an Axial-Flux Permanent-Magnet Synchronous Machine With Stator in Laminated Iron or SMC
Abstract:
This paper compares the iron losses generated by the concentrated excitation windings of an axial-flux permanent-magnet synchronous machine (AFPMSM) in the stator core elements constructed with laminated silicon steel sheets (LSSS) or with soft magnetic composite (SMC). As the flux mainly flows in one direction, we use grain-oriented LSSS. In order to provide a very accurate comparison, individual laminations are modeled in the 3-D finite-element model, including the coating layer. The model accounts for the magnetic stray field (fringing field) that causes eddy currents in the plane of the sheets, in addition to the main flux causing the classical eddy-current loss. The losses caused by the 3-D eddy-current pattern, as well as hysteresis and excess losses, are computed and measured for a test setup. A comparison of losses is made for the SMC mounted in the same setup. SMC does not suffer from eddy currents due to fringing flux. Although SMC has a 16 times higher loss than the LSSS at 1 T and 50 Hz as measured with an Epstein frame, it was shown that the iron losses in the SMC in the AFPMSM setup are only 1.5 times higher than for the LSSS.
Autors: Scheerlinck, B.;De Gersem, H.;Sergeant, P.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» 3-D Effects of Rotor Step-Skews in Permanent Magnet-Assisted Synchronous Reluctance Machines
Abstract:
This paper focuses on the 3-D effects associated with rotor step-skews performed in permanent magnet-assisted synchronous reluctance machines (PMA SynRMs). It analyzes and quantifies these effects via comparisons between 2-D and 3-D finite-element analyses (FEA) of skewed and unskewed machines. The 3-D phenomena manifested in the skewed PMA SynRM are identified into end-effects and axial interactions between skewed steps, and their influence on its electromagnetic performance is examined under load and no-load conditions. This paper exemplifies the significance of the skew-associated 3-D effects, which can result in considerable decrease of the back electromotive force and a substantially increased electromagnetic torque ripple. It, thereby, highlights the inability of the typically employed multislice 2-D FEA or other existing 2-D-based modeling techniques in taking their influence into account. The validity of the findings is experimentally verified with measurements acquired from a prototype PMA SynRM using skewed and unskewed shafts in the rotor.
Autors: Lazari, P.;Wang, J.;Sen, B.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» 3-D PIC Numerical Investigations of a Novel Concept of Multistage Axial Vircator for Enhanced Microwave Generation
Abstract:
The enhancement of power conversion efficiency of a classical axial VIRtual CAthode oscillaTOR (vircator) by introducing one or more reflectors beyond the anode in the cylindrical waveguide is numerically investigated. The targeted microwave (MW) output frequency lies in the S-band at around 3 GHz for an operation in TM01 mode. Powered by a 511-kV voltage signal for a duration of 45 ns, the design under consideration operates with an injected electron beam of mean voltage and mean current of around 508 kV and 19 kA, respectively. Full-wave 3-D modeling is performed using well-tested electromagnetic particle-in-cell codes such as Computer Simulation Technology Particle Studio and Magic. Simple rules for designing and installing the reflectors are given. The number of reflectors required to maximize the efficiency is discussed. The power conversion efficiency is shown to be improved over a classical axial vircator design by a factor of 12.8. A maximum mean output power of about 1.26 GW is delivered off-axis in the S-band at around 3 GHz, with an efficiency of nearly 13%. Besides, it is also shown that increasing the number of reflectors allows switching the operation mode from TM01 to TE11 along with a shift of MWfrequency from the S- to the L-band. A five- or six-reflector configuration is predicted to generate MW at both 2.86 and 1.4 GHz with conversion efficiencies ranging from 3.5% to 6.6%. A vircator including seven reflectors is expected to operate in TE11 mode at 1.4 GHz with an efficiency of about 8%.
Autors: Champeaux, S.;Gouard, P.;Cousin, R.;Larour, J.;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Nov 2015, volume: 43, issue:11, pages: 3841 - 3855
Publisher: IEEE
 
» 3-D Printing-Based Design of Axial Flux Magnetic Gear for High Torque Density
Abstract:
This paper investigates a novel design of the axial flux-type magnetic gears that adopts L-type ferromagnetic pole pieces and spoke-type ferrite magnet arrangement. This design not only decreases flux leakage but also improves torque density. 3-D finite element analysis is employed to compute the magnetic and torque characteristics of the 3-D design. Moreover, a newly developed 3-D printing process is introduced to overcome the fabrication difficulty and expedite the manufacturing process. A prototype of this novel magnetic gear design approach is given to verify the simulation result and the feasibility of the proposed 3-D printing approach.
Autors: Tsai, M.;Ku, L.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» 3-D Radiometric Aperture Synthesis Imaging
Abstract:
The aperture synthesis technique, historically used for imaging in radio astronomy, is generalized to three dimensions as a means to generating 3-D images in the near-field. The technique uses a multi-channel electronic cross-correlator and an array of radio receivers to generate a 3-D visibility function. This is transformed by a 3-D inverse Fourier transform into a 3-D image of space. The basic equations, experimentation, and simulation indicate the Abbe microscope half-wavelength spatial resolution is achievable in three dimensions when a subject is surrounded by receivers. At longer ranges, further from the array, the resolution perpendicular to the range is proportional to the ratio of the range to aperture size (corresponding to the Fraunhofer diffraction limit) while the resolution in range is proportional to the square of this ratio (a passive ranging capability). Experimental data from a 10-channel 94-GHz and a 32-channel 22-GHz receiver array and a digital cross-correlator demonstrate the imaging capability. The technique enables arbitrarily large volumes to be imaged using multiple inverse 3-D Fourier transforms for adjacent regions of space, when suitable phase corrections are applied to cross-correlations. The technique is mainly directed at the millimeter-wave band for the application of personnel security screening.
Autors: Salmon, N.A.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2015, volume: 63, issue:11, pages: 3579 - 3587
Publisher: IEEE
 
» 3-D Reconstruction of Flame Temperature Distribution Using Tomographic and Two-Color Pyrometric Techniques
Abstract:
Two-color pyrometric methods have been widely used in noncontact temperature measurement area. However, it is difficult to get synchronous monochromatic images for two-color pyrometric formula. Some researches use beam splitter to obtain two or more optical paths to capture the different monochromatic images, but the complex optical paths will bring spatiotemporal matching errors. Another method uses color camera to capture the Red, Green, Blue (RGB) channel images as the RGB monochromatic images, but substituting the Dirac delta function for spectral response function will result in the inaccuracy of the measurement results. In fact, the RGB monochromatic images can be obtained from the color image if the irradiance attenuations from color channel to single wavelength are calibrated. In this paper, a novel 3-D reconstruction method is proposed to measure the temperature distribution of combustion flame. First, the irradiance attenuations are calibrated to calculate the synchronous monochromatic images at R and G wavelengths. Second, the tomographic reconstruction of flame monochromatic emissive power is improved with visual hull restriction so that the energy distribution is more reasonable. Finally, the 3-D temperature distribution is calculated from the reconstructed monochromatic emissive power fields at R and G wavelengths using two-color pyrometric method. The alcohol and butane flames are tested in the laboratory-scale test rig. The experimental results indicate that our approach performs well in flame temperature field reconstruction.
Autors: Zhong Zhou;Delei Tian;Zhaohui Wu;Zhiyi Bian;Wei Wu;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Nov 2015, volume: 64, issue:11, pages: 3075 - 3084
Publisher: IEEE
 
» 3-D Scattering From a PEC Target Buried Beneath a Dielectric Rough Surface: An Efficient PILE-ACA Algorithm for Solving a Hybrid KA-EFIE Formulation
Abstract:
An efficient hybrid KA-EFIE formulation is deployed to analyze the electromagnetic (EM) scattering from a 3-D perfectly electric conducting (PEC) object buried beneath a 2-D dielectric rough surface. In this approach, the electric and magnetic current densities on the rough surface are analytically obtained through the current-based Kirchhoff approximation (KA), whereas the electric current density on the buried object is rigorously determined by solving the electric field integral equation (EFIE) using the Galerkin’s method of moments (MoM) with Rao–Wilton–Glisson (RWG) basis functions. The KA-EFIE matrix system is then efficiently solved by the iterative propagation-inside-layer-expansion (PILE) method combined with the algebraic adaptive cross approximation (ACA). The current densities on the dielectric rough surface are thereafter used to handle the bistatic normalized radar cross-section (NRCS) patterns. The proposed hybrid approach allows a significant reduction in computation time and memory requirements compared to the rigorous Poggio–Miller–Chang–Harrington–Wu (PMCHW)-EFIE formulation which requires solving a large MoM matrix equation. Moreover, the hybridization of the ACA algorithm with the PILE method improves further the computational cost thanks to the rank-deficient propriety of the coupling matrices. To validate the hybrid approach, we compare its results with those of the rigorous PMCHW-EFIE approach.
Autors: Bellez, S.;Bourlier, C.;Kubicke, G.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2015, volume: 63, issue:11, pages: 5003 - 5014
Publisher: IEEE
 
» 3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature
Abstract:
Excellent electrostatic control offered by gate-all-around (GAA) geometry makes multinanowire (multi-NW) MOSFET a promising candidate for sub-10-nm technology nodes. Unfortunately, the GAA geometry is susceptible to the increased self-heating due to poor heat dissipation from the nanowires (NWs) to the substrate. Therefore, an understanding of spatio-temporal temperature rise, , at the NW level is important for predicting activity-induced variability within an IC, as well as characterization of various reliability issues, such as, NBTI, PBTI, HCI, and TDDB that depend sensitively on self-heating. In this paper, a 3-D electrothermal simulation model is developed to explore and interpret self-heating and heat dissipation in GAA devices. Our results identify complex heat dissipation pathways characterized by multiple time constants. First, the nanowires heat up quickly ( ), then heat spreads all over the gate contact pad ( nSec), and finally, the heat exits through the heat sink at the bottom of the substrate ( ). A systematic thermoreflectance measurement of temperature helps us to identify the time constants, and validates the model. Our results have implications for the design, characterization, circuit-operation, and reliability of high-performance GAA devices.
Autors: Wahab, M.A.;Shin, S.;Alam, M.A.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2015, volume: 62, issue:11, pages: 3595 - 3604
Publisher: IEEE
 
» 3D Synthesis and Crosstalk Reduction for Lenticular Autostereoscopic Displays
Abstract:
Novel image processing methods are presented in this work for 3D synthesis of multiview images and crosstalk reduction to improve the perceived image quality of lenticular autostereoscopic displays. First, for optimizing the intensity of a screen subpixel mapped to a fraction view number, a weighting method is proposed to blend the intensities of the corresponding subpixels from the two neighboring integer view images by minimizing the mean square error. Experimental results show that, comparing with the conventional rounding method, the proposed weighting method can effectively reduce the ghosting artifacts and sharpen the object boundaries when viewing at optimal integer viewpoints. Second, the crosstalk among vertical neighboring subpixels is modeled as a shift-invariant low-pass filter, and a novel computational efficient inverse filtering method is proposed for crosstalk reduction by applying fast Fourier transform (FFT) on each column of subpixels in the multiview interlaced screen image. In addition, a novel filtering method is proposed for determining the maximum input dynamic range of screen subpixel intensities. Experimental results demonstrate that the ghost image from neighboring views can be substantially diminished by the proposed inverse filtering method.
Autors: Li, D.;Zang, D.;Qiao, X.;Wang, L.;Zhang, M.;
Appeared in: Journal of Display Technology
Publication date: Nov 2015, volume: 11, issue:11, pages: 939 - 946
Publisher: IEEE
 
» 45° Induced Magnetic Anisotropy for Isotropic High-Frequency Permeability
Abstract:
High-frequency permeability spectra and magnetic domain structures of CoZrTa films with 45° induced magnetic anisotropy were investigated in order to realize integrated flux-closed magnetic inductors. Isotropic permeability was experimentally achieved for both in-plane parallel and transversal directions. The obtained relative permeability of for both the directions of the unpatterned sample is approximately half of the conventional hard-axis permeability as expected from a magnetization rotation model. Once the films are micropatterned, permeability is typically degraded by the formation of spike domains in addition to the demagnetization effect. Through the observations of the magnetic domain structures using magneto-optical Kerr effect microscopy, we found that the formation of the spike domains is suppressed for the smaller patterned structures due to the domain walls along the 45° axis. The relative permeability of is achieved in the low-frequency range for the micropatterned structure, promising the possibility of flux-closed magnetic inductors with large inductance enhancement.
Autors: Sato, N.;El-Ghazaly, A.;White, R.M.;Wang, S.X.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» 4D Blood Flow Reconstruction Over the Entire Ventricle From Wall Motion and Blood Velocity Derived From Ultrasound Data
Abstract:
We demonstrate a new method to recover 4D blood flow over the entire ventricle from partial blood velocity measurements using multiple colour Doppler images and ventricular wall motion estimated using BMode images. We apply our approach to realistic simulated data to ascertain the ability of the method to deal with incomplete data, as typically happens in clinical practice. Experiments using synthetic data show that the use of wall motion improves velocity reconstruction, shows more accurate flow patterns and improves mean accuracy particularly when coverage of the ventricle is poor. The method was applied to patient data from 6 congenital cases, producing results consistent with the simulations. The use of wall motion produced more plausible flow patterns and reduced the reconstruction error in all patients.
Autors: Gomez, A.;de Vecchi, A.;Jantsch, M.;Shi, W.;Pushparajah, K.;Simpson, J.M.;Smith, N.P.;Rueckert, D.;Schaeffter, T.;Penney, G.P.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Nov 2015, volume: 34, issue:11, pages: 2298 - 2308
Publisher: IEEE
 
» : Channel Modeling for Metamaterial-Enhanced Magnetic Induction Communications
Abstract:
Magnetic induction (MI) communication technique has shown great potentials in complex and RF-challenging environments, such as underground and underwater, due to its advantage over EM wave-based techniques in penetrating lossy medium. However, the transmission distance of MI techniques is limited since magnetic field attenuates very fast in the near field. To this end, this paper proposes metamaterial-enhanced magnetic induction ( ) communication mechanism, where an MI coil antenna is enclosed by a metamaterial shell that can enhance the magnetic fields around the MI transceivers. As a result, the communication system can achieve tens of meters communication range by using pocket-sized antennas. In this paper, an analytical channel model is developed to explore the fundamentals of the mechanism, in the aspects of communication range and channel capacity, and the susceptibility to various hostile and complex environments. The theoretical model is validated through the finite element simulation software, Comsol Multiphysics. Proof-of-concept experiments are also conducted to validate the feasibility of .
Autors: Guo, H.;Sun, Z.;Sun, J.;Litchinitser, N.M.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2015, volume: 63, issue:11, pages: 5072 - 5087
Publisher: IEEE
 
» -Ordered MnAl Thin Films With High Perpendicular Magnetic Anisotropy Using TiN Underlayers on Si Substrates
Abstract:
Processes for the sputter deposition of -ordered -phase MnAl thin films using conductive TiN underlayers on Si substrates have been developed. Deposition parameters were systematically varied and resulting films were characterized in terms of structural and magnetic properties. Fabricated films demonstrated strong (001) texture and high perpendicular magnetic anisotropy, with an out-of-plane coercivity of up to 12 kOe, an anisotropy constant of erg/cm3, a saturation magnetization of 250 emu/cm3, and a squareness of 0.9.
Autors: Huang, E.Y.;Kryder, M.H.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» : Channel Modeling for Metamaterial-Enhanced Magnetic Induction Communications
Abstract:
Magnetic induction (MI) communication technique has shown great potentials in complex and RF-challenging environments, such as underground and underwater, due to its advantage over EM wave-based techniques in penetrating lossy medium. However, the transmission distance of MI techniques is limited since magnetic field attenuates very fast in the near field. To this end, this paper proposes metamaterial-enhanced magnetic induction ( ) communication mechanism, where an MI coil antenna is enclosed by a metamaterial shell that can enhance the magnetic fields around the MI transceivers. As a result, the communication system can achieve tens of meters communication range by using pocket-sized antennas. In this paper, an analytical channel model is developed to explore the fundamentals of the mechanism, in the aspects of communication range and channel capacity, and the susceptibility to various hostile and complex environments. The theoretical model is validated through the finite element simulation software, Comsol Multiphysics. Proof-of-concept experiments are also conducted to validate the feasibility of .
Autors: Guo, H.;Sun, Z.;Sun, J.;Litchinitser, N.M.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2015, volume: 63, issue:11, pages: 5072 - 5087
Publisher: IEEE
 
» In Situ Observation of Behavior of Magnetic Particle Clusters During Torque Transfer Between Textured Magnetic Poles
Abstract:
The viscosity of a magnetorheological fluid (MRF) changes with the magnetic field; however, the behavior of magnetic particles in an MRF under the application of a magnetic field has not been fully clarified. In our previous work, we proposed a real-time observation system in which the torque is simultaneously measured. Textured poles concentrated on a magnetic field, increasing the transfer of torque. In this paper, the behavior of magnetic particles, such as the formation, fracture, and sliding of clusters, in the presence of textured poles as well as the transfer of torque was investigated by in situ observation using our torque measurement system. With increasing depth of the pole texture, the magnetic-field gradient increased, the magnetic field at the edges of the texture increased, the clusters became concentrated in a narrower region, and the maximum torque increased. These results are expected to lead to the design of more efficient torque transfer devices using MRFs.
Autors: Nagato, K.;Oshima, T.;Kuwayama, A.;Enokizono, K.;Okada, H.;Matsushima, T.;Takag, S.;Nakao, M.;Hamaguchi, T.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» In Situ Observation of Domain Wall Pinning in Sm(Co,Fe,Cu,Zr)z Magnet by Lorentz Microscopy
Abstract:
The microstructure and magnetic domain-wall motion of a sintered Sm(Co,Fe,Cu,Zr)z permanent magnet with different Cu and Fe contents was investigated by Lorentz transmission electron microscopy. The domain-wall motion under different magnetic fields indicates that most domain walls are strongly attracted by the SmCo5 boundary phases, but some of them are repulsed to the Sm2Co17 cell phase. Differences in Cu and Fe distribution at the SmCo5 cell boundary phase and the SmCo5/Sm2Co17 interface are considered to result in domain-wall behavior, and a larger Cu and a smaller Fe content in the sample make the attractive pinning force stronger and, therefore, coercivity is higher.
Autors: Tian, Y.;Liu, Z.;Xu, H.;Du, J.;Zhang, J.;Xia, W.;Che, R.;Yan, A.;Liu, J.P.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» In-Situ Hydrothermal Synthesis of Zinc Oxide Nanostructures Using Microheaters
Abstract:
A technique for in-situ hydrothermal synthesis of transversely suspended zinc oxide nanowires (ZnO NWs) using microfabricated heaters is presented. A number of issues relating to seed layer preparation, directed alignment, local heating control, and the concentration of the synthesis solution are investigated for this method. It is shown that ZnO NWs can be synthesized and aligned from the ZnO seed surface to bridge two adjacent microheater elements. Moreover, hybrid ZnO nanotubes and nanorods are also synthesized by controlling the concentration of the synthesis solution employed. The crystalline structure of synthesized ZnO nanostructures are characterized by the transmission electron microscope and selective area electron diffraction. Finally, ZnO NW devices based on proposed microheater synthesis approach are characterised for UV photoresponsivity demonstrating the potential of this approach to address practical device applications.
Autors: Lin, W.;Lin, Y.;Esashi, M.;Seshia, A.A.;
Appeared in: IEEE Transactions on Nanotechnology
Publication date: Nov 2015, volume: 14, issue:6, pages: 1046 - 1053
Publisher: IEEE
 
» A 0.022 mm 98.5 dB SNDR Hybrid Audio Modulator With Digital ELD Compensation in 28 nm CMOS
Abstract:
This work presents a compact-area hybrid continuous-time delta-sigma modulator (CTDSM) with a shared 6 bit asynchronous successive approximation register (ASAR) quantizer for audio application. It is implemented in a 28 nm CMOS process. The modulator incorporates an analog integrator and a digital filter. Signal is digitized after the analog first stage and processed digitally thereafter. Only the first stage is left in the analog domain. Because of high integration of digital circuitry, it could benefit from process advancement such as low power consumption and small area. Moreover, the excess loop delay (ELD) is compensated in the digital domain, and the conventional analog local feedback DAC for ELD compensation is no longer needed. In addition, resistive DAC (R-DAC) is adopted for low flicker noise. The measured DR and SNDR in 24 kHz BW are 100.6 dB and 98.5 dB, respectively, while occupying 0.022 mm 2 and achieving FOMs (SNDR + 10 log(BW/Power)) of 171.8 dB.
Autors: Wang, T.-C.;Lin, Y.-H.;Liu, C.-C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2655 - 2664
Publisher: IEEE
 
» A 0.022 mm 98.5 dB SNDR Hybrid Audio Modulator With Digital ELD Compensation in 28 nm CMOS
Abstract:
This work presents a compact-area hybrid continuous-time delta-sigma modulator (CTDSM) with a shared 6 bit asynchronous successive approximation register (ASAR) quantizer for audio application. It is implemented in a 28 nm CMOS process. The modulator incorporates an analog integrator and a digital filter. Signal is digitized after the analog first stage and processed digitally thereafter. Only the first stage is left in the analog domain. Because of high integration of digital circuitry, it could benefit from process advancement such as low power consumption and small area. Moreover, the excess loop delay (ELD) is compensated in the digital domain, and the conventional analog local feedback DAC for ELD compensation is no longer needed. In addition, resistive DAC (R-DAC) is adopted for low flicker noise. The measured DR and SNDR in 24 kHz BW are 100.6 dB and 98.5 dB, respectively, while occupying 0.022 mm 2 and achieving FOMs (SNDR + 10 log(BW/Power)) of 171.8 dB.
Autors: Wang, T.-C.;Lin, Y.-H.;Liu, C.-C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2655 - 2664
Publisher: IEEE
 
» A 1 mm Pitch Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan
Abstract:
A 1 mm pitch 80 X 80 channel 322 Hz framerate capacitive multitouch distribution sensor has been developed. High-resolution multiple touch points are detected including touch-strength distribution around them. A two-step dual-mode capacitance scan scheme is proposed, where self- and mutual-capacitance measurements are hierarchically performed in two steps to increase the frame scan rate that is otherwise reduced due to high resolution. 160 row-and-column dedicated parallel ADCs further increase the scan rate. A time-domain counter-based slope ADC suppresses power and area penalty for the parallel ADC approach. A signal attenuation due to the sensor capacitance reduction in the high resolution is compensated by thorough noise-reduction techniques in the sensor analog frontend (AFE). A prototype in 0.35 μm CMOS demonstrates 41 dB signal-to-noise ratio (SNR) with >5× tighter sensor-channel pitch, >10× faster touch-point scan, >10× and >4× higher energy and area efficiency to the state-of-the-art touch distribution sensors.
Autors: Miura, N.;Dosho, S.;Tezuka, H.;Miki, T.;Fujimoto, D.;Kiriyama, T.;Nagata, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2741 - 2749
Publisher: IEEE
 
» A 1 mm Pitch Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan
Abstract:
A 1 mm pitch channel 322 Hz frame-rate capacitive multitouch distribution sensor has been developed. High-resolution multiple touch points are detected including touch-strength distribution around them. A two-step dual-mode capacitance scan scheme is proposed, where self- and mutual-capacitance measurements are hierarchically performed in two steps to increase the frame scan rate that is otherwise reduced due to high resolution. 160 row-and-column dedicated parallel ADCs further increase the scan rate. A time-domain counter-based slope ADC suppresses power and area penalty for the parallel ADC approach. A signal attenuation due to the sensor capacitance reduction in the high resolution is compensated by thorough noise-reduction techniques in the sensor analog frontend (AFE). A prototype in CMOS demonstrates 41 dB signal-to-noise ratio (SNR) with tighter sensor-channel pitch, faster touch-point scan, and higher energy and area efficiency to the state-of-the-art touch distribution sensors.
Autors: Miura, N.;Dosho, S.;Tezuka, H.;Miki, T.;Fujimoto, D.;Kiriyama, T.;Nagata, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2741 - 2749
Publisher: IEEE
 
» A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics
Abstract:
This paper presents an integrated hybrid 6-stage voltage multiplier without using high-voltage-tolerant devices. The proposed architecture obtains a good area and efficiency performance by cascading the Dickson charge pumps and the symmetrical Cockcroft-Walton charge pumps, and paralleling them with the proposed auxiliary charge pumps formed by parasitics. Implemented in a standard 0.18 µm CMOS process, the prototype provides a wide output range of 3–6 V and 30–240 µA load from a 1 V supply with an efficiency of 48–58% (52% at the 6 V output when the gain is six). By using on-chip MOS capacitors as the flying capacitors, an area reduction of 66% as compared to the Dickson charge-pump of similar performance is achieved. The area shrinks to 0.05 mm 2 per 9× interleaved cell. The entailed efficiency loss due to parasitics is compensated by the proposed auxiliary parasitic pumping paths feeding forward to redirect the parasitic charge flow. With this technique, the efficiency enhances extra 11%. The technique is applicable to other on-chip charge-pumps.
Autors: Tsai, J.-H.;Ko, S.-A.;Wang, C.-W.;Yen, Y.-C.;Wang, H.-H.;Huang, P.-C.;Lan, P.-H.;Shen, M.-H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2533 - 2548
Publisher: IEEE
 
» A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop
Abstract:
Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm , and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of 232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of 243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from 32 to 55 dBc.
Autors: Levantino, S.;Marucci, G.;Marzin, G.;Fenaroli, A.;Samori, C.;Lacaita, A.L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2678 - 2691
Publisher: IEEE
 
» A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS
Abstract:
This paper presents a low-cost successive approximation register (SAR) analog-to-digital converter (ADC) for IEEE 802.11 ac applications. In this paper, a binary-scaled recombination capacitor weighting method is disclosed. The digital sub-blocks in this ADC are composed of standard library logic cells. The prototype is fabricated in a 1P8M 20 nm CMOS technology. At 0.9 V supply and 160 MS/s, the ADC consumes 0.68 mW. It achieves an SNDR of 57.7 dB and 57.13 dB at low and Nyquist input frequency, respectively, resulting in figures of merit (FoMs) of 6.8 and 7.3 fJ/conversion-step, respectively. At 1 V supply and 320 MS/s, the ADC consumes 1.52 mW. It achieves an SNDR of 57.1 dB and 50.89 dB at low and Nyquist input frequency, respectively, resulting in FoMs of 8.1 and 16.5 fJ/conversion-step, respectively. The ADC core only occupies an active area of .
Autors: Liu, C.-C.;Kuo, C.-H.;Lin, Y.-Z.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2645 - 2654
Publisher: IEEE
 
» A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13- m CMOS Technology
Abstract:
This brief presents a zero-crossing-based pipeline analog-to-digital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13- m CMOS process and occupies a die area of 0.7 . The differential and integral nonlinearity of the ADC are less than 0.83/−0.47 and 1.05/−0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply.
Autors: Chu, M.;Kim, B.;Lee, B.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2015, volume: 23, issue:11, pages: 2671 - 2675
Publisher: IEEE
 
» A 10.4 mW Electrical Impedance Tomography SoC for Portable Real-Time Lung Ventilation Monitoring System
Abstract:
An electrical impedance tomography (EIT) SoC is proposed for the portable real-time lung ventilation monitoring system. The proposed EIT SoC is integrated into belt-typefabric system with 32 electrodes and can show the dynamic images of the lung ventilation on the mobile devices. To get high fidelity images, a T-switch is adopted for high off-isolation between electrodes more than 60 dB, and I/Q signal generation and demodulation can obtain both real and imaginary part of images. For the real-time imaging, an on-chip fast demodulation scheme is proposed, and it can also reduce speed requirements of ADC for low-power consumption. The proposed EIT SoC of 5.0 mm × 5.0 mm is fabricated in 0.18 µm CMOS technology, and consumes only 10.4 mW with 1.8 V supply. As a result, EIT images were reconstructed with 97.3% of accuracy and up to 20 frames/s real-time lung images can be displayed on the mobile devices.
Autors: Hong, S.;Lee, J.;Bae, J.;Yoo, H.-J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2501 - 2512
Publisher: IEEE
 
» A 16-Channel Patient-Specific Seizure Onset and Termination Detection SoC With Impedance-Adaptive Transcranial Electrical Stimulator
Abstract:
A 16-channel noninvasive closed-loop beginning- and end-of-seizure detection SoC is presented. The dual-channel charge recycled (DCCR) analog front end (AFE) achieves chopping and time-multiplexing an amplifier between two channels simultaneously which exploits fast-settling DC servo-loop with current consumption and NEF of /channel and 3.29/channel, respectively. The dual-detector architecture ( ) classification processor utilizes two linear support-vector machine (LSVM) classifiers based on digital hysteresis to enhance both the sensitivity and the specificity simultaneously. The pulsating voltage transcranial electrical stimulator (PVTES) automatically configures the number of pulses to control the amount of charge delivered based on skin-electrode impedance variation in efforts to suppress the seizure activity, while burning only . The SoC implemented in CMOS consumes /classification for 16 channels with an average sensitivity, specificity, and latency of 95.7%, 98%, and 1 s, respectively.
Autors: Bin Altaf, M.A.;Zhang, C.;Yoo, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2728 - 2740
Publisher: IEEE
 
» A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel
Abstract:
A 16.8 Gbps/channel single-ended transceiver for SiP-based DRAM interface on silicon carrier channel is proposed in this paper. A transmitter, receiver, and channel are all included in a single package as SiP. A current mode 4:1 MUX with 1-tap feed-forward equalizer (FFE) is used as a serializer, and this 4:1 MUX uses 25% duty clock to prevent short circuit current when consecutive 2-phase clocks overlap. Additionally, an open drain output driver with asynchronous type 1-tap FFE is used in the transmitter. Because of its small physical size, a common mode variation of Si-carrier channel from process variation is more serious than that of conventional PCB. This common mode variation degrades bit error rates (BER) at single-ended signaling. To obtain effective single-ended signaling on Si-carrier channel, a source follower-based continuous time linear equalizers and self- generator with training algorithm on the receiver are proposed. An implemented Si-carrier channel uses meshed layer as a reference to reduce insertion loss. A BER less than 1e-12 is achieved in 65 nm CMOS and the power efficiency of the transceiver is 5.9 pJ/bit with 120 terminations at each transceiver side.
Autors: Lee, H.;Song, T.;Byeon, S.;Lee, K.;Jung, I.;Kang, S.;Kwon, O.;Cheon, K.;Seol, D.;Kang, J.;Park, G.;Kim, Y.-S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2613 - 2624
Publisher: IEEE
 
» A 2.5 GHz High Efficiency High Power Low Phase Noise Monolithic Microwave Power Oscillator
Abstract:
This letter presents a 2.5 GHz high efficiency high power low phase noise monolithic microwave power oscillator using 0.5- GaAs enhancement- and depletion-mode pseudomorphic high-electron mobility transistor process. The class-E load network with finite dc-feed inductance is adopted in the power oscillators to achieve high efficiency. The shunt capacitance and load resistance of the class-E network can be larger than those of the class-E load network with the large dc-feed inductance. With a dc supply voltage of 4 V, the proposed power oscillator demonstrates a peak efficiency of 53%, a maximum output power of 24.8 dBm, and a minimum phase noise of 127 dBc/Hz at 1 MHz offset frequency.
Autors: Chang, H.-Y.;Lin, C.-H.;Liu, Y.-C.;Li, W.-P.;Wang, Y.-C.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2015, volume: 25, issue:11, pages: 730 - 732
Publisher: IEEE
 
» A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process
Abstract:
This paper presents a 22 to 26.5 Gb/s optical receiver with an all-digital clock and data recovery (AD-CDR) fabricated in a 65 nm CMOS process. The receiver consists of an optical front-end and a half-rate bang-bang clock and data recovery circuit. The optical front-end achieves low power consumption by using inverter-based amplifiers and realizes sufficient bandwidth by applying several bandwidth extension techniques. In addition, in order to minimize additional jitter at the front-end, not only magnitude and bandwidth but also group-delay responses are considered. The AD-CDR employs an LC quadrature digitally controlled oscillator (LC-QDCO) to achieve a high phase noise figure-of-merit at tens of gigahertz. The recovered clock jitter is 1.28 ps and the measured jitter tolerance exceeds the tolerance mask specified in IEEE 802.3ba. The receiver sensitivity is 106 and 184 for a bit error rate of at data rates of 25 and 26.5 Gb/s, respectively. The entire receiver chip occupies an active die area of 0.75 mm and consumes 254 mW at a data rate of 26.5 Gb/s. The energy efficiencies of the front-end and entire receiver at 26.5 Gb/s are 1.35 and 9.58 pJ/bit, respectively.
Autors: Chu, S.-H.;Bae, W.;Jeong, G.-S.;Jang, S.;Kim, S.;Joo, J.;Kim, G.;Jeong, D.-K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2603 - 2612
Publisher: IEEE
 
» A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS
Abstract:
This brief presents a 9-bit 2X time-interleaved successive approximation (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC fabricated in TSMC's 65-nm general-purpose process occupies an area of 0.0338 mm 2 and consists of two time-interleaved channels, each operating at 110 MS/s. The sampling capacitor is separated from the capacitive DAC array by performing the input and DAC reference subtraction in the current domain rather than as done traditionally in the charge domain. This allows for an extremely small input capacitance of 133 fF. The measured ADC SFDR is 57 dB and the measured ENOB is 7.55 bits at Nyquist rate while using 1.55-mW power from a 1-V supply.
Autors: Palani, R.K.;Harjani, R.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2015, volume: 62, issue:11, pages: 1053 - 1057
Publisher: IEEE
 
» A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations
Abstract:
In this paper, we present a new 9T SRAM cell that has good write ability and improves read stability at the same time. Simulation results show that the proposed design increases read static noise margin and of read path by 219% and 113%,respectively, at supply voltage of 300-mV over conventional 6T SRAM cell in a 90-nm CMOS technology. The proposed design lets us reduce the minimum operating voltage of SRAM ( ) to 350 mV, whereas conventional 6T SRAM cannot operate successfully with an acceptable failure rate at supply voltages below 725 mV. We also compared our design with three other SRAM cells from recent literature. To verify the proposed design, a 256-kb SRAM is designed using new 9T and conventional 6T SRAM cells. Operating at their minimum possible , the proposed design decreases write and read power per operation by 92% and 93%, respectively, over the conventional rival. The area of the proposed SRAM cell is increased by 83% over a conventional 6T one. However, due to large of read path for 9T cell, we are able to put 1k cells in each column of 256-kb SRAM block, resulting in the possibility for sharing write and read circuitries of each column between more cells compared with conventional 6T. Thus, the area overhead of 256-kb SRAM based on new 9T cell is reduced to 37% compared with 6T SRAM.
Autors: Pasandi, G.;Fakhraie, S.M.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2015, volume: 23, issue:11, pages: 2438 - 2446
Publisher: IEEE
 
» A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor
Abstract:
A marker-less camera pose estimation engine (CPEE) with reconfigurable logarithmic SIMD processor is proposed for the view angle estimation used in mobile augmented reality (AR) applications. Compared to previous marker-based approach, marker-less camera pose estimation can overlay virtual images directly on natural world without the help of markers. However, they require 150x larger computing costs and large power consuming floating-point operations where such requirement severely restricts real-time operations and low-power implementations in mobile platform, respectively. To overcome the gap in computational costs between marker-based and marker-less method, speculative execution (SE) and reconfigurable data-arrangement layer (RDL) are proposed to reduce computing time by 17% and 27%, respectively. For low-power implementation of floating-point units, logarithmic processing element (LPE) is designed to reduce overall power consumption by 18%. The proposed marker-less CPEE is fabricated in 65 nm Logic CMOS technology, and successfully realizes real-time marker-less camera pose estimation with only 27 mW power consumption.
Autors: Hong, I.;Kim, G.;Kim, Y.;Kim, D.;Nam, B.-G.;Yoo, H.-J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2513 - 2523
Publisher: IEEE
 
» A 3-D Analytic-Based Model of a Null-Flux Halbach Array Electrodynamic Suspension Device
Abstract:
The purpose of this paper is to present the derivation of a 3-D analytical solution of a null-flux electrodynamic suspension device for a conductive plate. The device consists of a linear Halbach magnet array placed above and below a conductive plate. The eddy current forces are derived using the second-order vector potential (SOVP). When the conductive plate is assumed to be large relative to the source field, the SOVP enables the equations to be derived in terms of reflection and transmission field components. A 3-D finite-element analysis model as well as the experimental results are used to validate the presented equations.
Autors: Chen, Y.;Zhang, W.;Bird, J.Z.;Paul, S.;Zhang, K.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 5
Publisher: IEEE
 
» A 3.12 pJ/bit, 19–27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery
Abstract:
A 19–27 Gbps receiver comprised of a continuous-time linear equalizer (CTLE) followed by a 2-tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broadband PLL to facilitate ISI and jitter suppression over wide-band operation. To accommodate different channel response, an automatic threshold tracking (ATT) circuit combining with sign-sign least mean square (LMS) adaptive engine is realized. A quadrature relaxation-type oscillator is proposed to provide the sampling phases without bulky inductors. It also provides the advantages of small form factor and wide range operation (19–27 Gbps) to compensate 20 dB channel loss at 12.5 GHz. Fabricated in a 40 nm CMOS technology, the whole receiver manifests an energy efficiency of 3.12 pJ/bit at 27 Gbps operation. The core area is 0.09 mm only.
Autors: Hong, Z.-H.;Liu, Y.-C.;Chen, W.-Z.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2625 - 2634
Publisher: IEEE
 
» A 300-nW Sensitive, 50-nA DC-DC Converter for Energy Harvesting Applications
Abstract:
A maximum-power-point-tracking DC-DC boost converter to harvest energy from sub- power sources is presented. For available input-power levels below 1 , voltage boosting is achieved by operating all circuits in the sub-threshold region, and by switching the DC-DC converter at tens of Hz, thereby reducing switching losses. The paper further explores the possibility of energizing the DC-DC inductor for an optimum duration, such that switching and resistive losses are minimized. The sub- energy harvesting circuit uses an area of 0.2 on a standard 180 nm CMOS process, and utilizes an auxiliary voltage source for start-up. The designed and fabricated system is more than 50% efficient when the available power is greater than 2 . The circuit can harvest energy whenever the available power is more than 0.3 . Efficiency at 0.3 is 25%, at 0.5 is 37% and at 1 is 48%. The complete IC consumes 50 nA for internal operations and the input voltage can be as low as 70 mV.
Autors: Chowdary, G.;Chatterjee, S.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2015, volume: 62, issue:11, pages: 2674 - 2684
Publisher: IEEE
 
» A 40 nm CMOS E-Band Transmitter With Compact and Symmetrical Layout Floor-Plans
Abstract:
This paper describes a direct-conversion E-band transmitter (TX) in 40 nm bulk CMOS. As millimeter-wave (mm-Wave) circuits are vulnerable to process variations including the mismatch between interconnects, this E-band TX design is conducted in a layout floor-plan oriented way. Compact and symmetrical floor-plans of poly-phase filter (PPF) and I/Q modulator are presented in this work to suppress the LO feed-through (LOFT) and I/Q imbalance over both 71–76 and 81–86 GHz bands. In addition, a systematic design methodology is proposed for the mm-Wave PPF to reduce required EM simulations. The calibration methods used in this design are easy to implement for further reducing LOFT and I/Q imbalance with negligible impact on other TX performance metrics. The 0.225 mm E-band TX achieves a measured output power of 12 dBm and efficiency of 15% with about 15 GHz bandwidth. It features an uncalibrated I/Q imbalance of less than 30 dB from 62.5 to 85.5 GHz. The calibration circuits further reduce the I/Q imbalance by about 4 dB and ensure the LOFT of less than 30 dBc over more than 30 dB output dynamic range. The presented TX achieves 4.5 Gb/s 64-QAM and 14 Gb/s 16-QAM.
Autors: Zhao, D.;Reynaert, P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2560 - 2571
Publisher: IEEE
 
» A 400 nW Single-Inductor Dual-Input–Tri-Output DC–DC Buck–Boost Converter With Maximum Power Point Tracking for Indoor Photovoltaic Energy Harvesting
Abstract:
This paper presents a single-inductor dual-input–tri-output buck–boost (DITOBB) converter that manages energy harvesting, energy storage, and power rail regulation of an indoor remote sensor system. The converter operates in discontinuous conduction mode (DCM) and regulates the outputs with a combination of pulse-skipping modulation (PSM) and constant-on-time pulse-frequency modulation (PFM). To reduce the quiescent power, all the circuit blocks are turned off when the outputs are within regulation, except a system clock generator. A newly designed relaxation oscillator provides the main clock of the system, which requires neither reference voltages nor comparators. The frequency of the system clock doubles or halves based on the states of the sources and outputs following a proposed algorithm. The DITOBB converter has been designed and fabricated using CMOS process. With a quiescent power of 400 nW, the designed DITOBB converter shows a measured peak efficiency of 83% at output power.
Autors: Yu, G.;Chew, K.W.R.;Sun, Z.C.;Tang, H.;Siek, L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2758 - 2772
Publisher: IEEE
 
» A 5.2 mW IEEE 802.15.6 HBC Standard Compatible Transceiver With Power Efficient Delay-Locked-Loop Based BPSK Demodulator
Abstract:
A Low-power IEEE 802.15.6 human body communication (HBC) fully compatible transceiver is implemented in 130 nm CMOS process. In this work, the proposed HBC transceiver satisfying all the standard requirements has four key features for low power consumption which includes: 1) low-power analog active filters for TX spectral mask: 30% power reduction; 2) delayed locked loop (DLL) based BPSK receiver with the S/H operation for turning off unnecessary blocks: 40% power reduction; 3) low-power mode (LP-mode) receiver with the received signal strength indicator (RSSI) output data: 50% power reduction; and 4) reconfigurable LNA with RSSI output data: 60% power reduction. As a result, the proposed transceiver can fully satisfy the HBC standard requirements while consuming 5.2 mW from the 1.2 V supply.
Autors: Cho, H.;Lee, H.;Bae, J.;Yoo, H.-J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2549 - 2559
Publisher: IEEE
 
» A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter
Abstract:
This paper presents a 6-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog converter (RASD). By applying the input folding technique in the input stage and utilizing the flash-assisted TI-SAR ADC with the proposed RASD, the static power dissipation is reduced by 69%. ON-chip and OFF-chip calibration techniques are used to compensate the interchannel error sources. The prototype was fabricated in a 65-nm CMOS process technology. The peak integral nonlinearity and differential nonlinearity are measured as 0.52 and 0.51 LSB, respectively. At 2.5 GS/s, a signal-to-noise and distortion ratio (SNDR) of 18.6/31.9 dB and a spurious-free dynamic range (SFDR) of 23.7/42.1 dBc are measured before and after the calibration at the Nyquist input frequency with 1 input signal, and the figure of merit is 0.27 pJ/conversion-step. This chip consumes 22 mW at 1.2-V supply and occupies 0.27- area.
Autors: Lee, H.;Aurangozeb,.;Park, S.;Kim, J.;Kim, C.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2015, volume: 23, issue:11, pages: 2371 - 2383
Publisher: IEEE
 
» A 77-GHz FMCW Radar System Using On-Chip Waveguide Feeders in 65-nm CMOS
Abstract:
This paper presents a 77-GHz radar system using a transmitter (Tx) and receiver (Rx) integrated with on-chip waveguide feeders in 65-nm CMOS. The newly proposed on-chip waveguide feeder shows the insertion loss of about 2 dB and more than 30% bandwidth. Additionally, both the Tx and Rx are integrated with internal 10 frequency multipliers. Therefore, a radar system can be easily implemented without sensitive millimeter-wave packaging technology by mounting the Tx and Rx chips on the waveguide aperture. The interconnections for the low-frequency reference and baseband signals can be realized on the low-cost FR-4 printed circuit board. The radar system shows 9-dBm output power and 13-dB down-conversion gain from the waveguide port.
Autors: Cui, C.;Kim, S.-K.;Song, R.;Song, J.-H.;Nam, S.;Kim, B.-S.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2015, volume: 63, issue:11, pages: 3736 - 3746
Publisher: IEEE
 
» A , Batteryless, Crystal-free, Multinode Synchronized SoC “Bionode” for Wireless Prosthesis Control
Abstract:
We present a batteryless, crystal-free, time division multiple access (TDMA) synchronized multinode wireless body sensor node (WBSN) system-on-chip (SoC), referred to as a Bionode, for continuous and real-time telemetry of electromyograms (EMGs), enabling intuitive upper limb prosthesis control by an amputee. The SoC utilizes state of the art in supercapacitive RF energy harvesting, biosensing analog-front-end, switchingoptimized SAR ADC, ultra-low-power RF transceiver, and clock circuits. The sensor node SoCs are time synchronized with a base station, mounted on the prosthetic arm, by using the ultra-lowpower TDMA controller and receiver, and the digital core circuits. A 915 MHz broadcast RF signal is utilized to synthesize the carrier frequency of the transmitter. This along with the process and voltage compensated on-chip clock obviates the need for a bulky crystal oscillator, thus providing a low-cost and highly integrated solution to the WBSNs. The SoC is verified by capturing the EMG data from a healthy human body and consumes only 24 μW, while operating exclusively from the harvested RF energy. Implemented in a 0.18 μm CMOS process, the SoC occupies 2.025 mm2 silicon area. The sensor node has an extremely low weight and physical dimensions, thanks to the flexible carbon nanotube (CNT) supercapacitor, electrically small antenna (ESA), and crystal-free operation of the SoC.
Autors: Bhamra, H.;Young-Joon Kim;Joseph, J.;Lynch, J.;Gall, O.Z.;Mei, H.;Meng, C.;Jui-Wei Tsai;Irazoqui, P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2714 - 2727
Publisher: IEEE
 
» A Hybrid OTA Driving 15 nF Capacitive Load With 1.46 MHz GBW
Abstract:
A cascade structure of six proposed signal-current enhancers is applied to a standard operational transconductance amplifier (OTA) to improve its gain-bandwidth (GBW) product, slew rate (SR), and voltage gain through significant enhancements of the small-signal and transient output currents from the proposed enhancers. The proposed hybrid OTA is implemented in a standard 0.13 μm CMOS technology, with an active chip area of 0.0027 mm2. Working under a 0.7 V supply and as proven by the measurement results, the resultant OTA when driving an output capacitor of 15 nF attained ~100 dB gain, a GBW of 1.46 MHz, and an SR of 0.47 V/μs, consuming only 24 μA of current and requiring no compensation capacitor.
Autors: Kai Ho Mak;Ming Wai Lau;Jianping Guo;Tin Wai Mui;Ho, M.;Wang Ling Goh;Ka Nang Leung;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2750 - 2757
Publisher: IEEE
 
» A Hybrid OTA Driving 15 nF Capacitive Load With 1.46 MHz GBW
Abstract:
A cascade structure of six proposed signal-current enhancers is applied to a standard operational transconductance amplifier (OTA) to improve its gain-bandwidth (GBW) product, slew rate (SR), and voltage gain through significant enhancements of the small-signal and transient output currents from the proposed enhancers. The proposed hybrid OTA is implemented in a standard CMOS technology, with an active chip area of . Working under a 0.7 V supply and as proven by the measurement results, the resultant OTA when driving an output capacitor of 15 nF attained gain, a GBW of 1.46 MHz, and an SR of , consuming only of current and requiring no compensation capacitor.
Autors: Mak, K.H.;Lau, M.W.;Guo, J.;Mui, T.W.;Ho, M.;Goh, W.L.;Leung, K.N.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2750 - 2757
Publisher: IEEE
 
» A , Batteryless, Crystal-free, Multinode Synchronized SoC “Bionode” for Wireless Prosthesis Control
Abstract:
We present a batteryless, crystal-free, time division multiple access (TDMA) synchronized multinode wireless body sensor node (WBSN) system-on-chip (SoC), referred to as a Bionode, for continuous and real-time telemetry of electromyograms (EMGs), enabling intuitive upper limb prosthesis control by an amputee. The SoC utilizes state of the art in supercapacitive RF energy harvesting, biosensing analog-front-end, switching-optimized SAR ADC, ultra-low-power RF transceiver, and clock circuits. The sensor node SoCs are time synchronized with a base station, mounted on the prosthetic arm, by using the ultra-low-power TDMA controller and receiver, and the digital core circuits. A 915 MHz broadcast RF signal is utilized to synthesize the carrier frequency of the transmitter. This along with the process and voltage compensated on-chip clock obviates the need for a bulky crystal oscillator, thus providing a low-cost and highly integrated solution to the WBSNs. The SoC is verified by capturing the EMG data from a healthy human body and consumes only , while operating exclusively from the harvested RF energy. Implemented in a CMOS process, the SoC occupies silicon area. The sensor node has an extremely low weight and physical dimensions, thanks to the flexible carbon nanotube (CNT) supercapacitor, electrically small antenna (ESA), and crystal-free operation of the SoC.
Autors: Bhamra, H.;Kim, Y.;Joseph, J.;Lynch, J.;Gall, O.Z.;Mei, H.;Meng, C.;Tsai, J.;Irazoqui, P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2714 - 2727
Publisher: IEEE
 
» A Basic Study of a Novel Homopolar-Type Magnetic Bearing Unifying Four C-Shaped Cores for High Output and Low Loss
Abstract:
A magnetic bearing (MB) can suspend a rotor shaft with noncontact, so the MB has been used for high-output and high-speed machines. In general, heteropolar-type MB structure is used, because of its simple structure and low cost. However, the heteropolartype MB structure has a problem in terms of rotor iron loss caused by an alternating magnetic field on a rotor core. On the other hand, general homopolar-type MB structure has a low rotor iron loss caused by a dc magnetic field on a rotor core. However, as the general homopolar-type MB has a complicated structure and needs a large magnet for generating the bias flux, it becomes costly. Therefore, this paper discusses a novel homopolar-type MB structure unifying four C-shaped cores for high output and low iron loss. It is shown with three-dimensional finite element analysis that the novel homopolar-type MB has lower iron loss and lower cost than the general homopolar-type MB, which is known for its low iron loss.
Autors: Matsuzaki, T.;Takemoto, M.;Ogasawara, S.;Nishihama, K.;Kori, D.;Nagata, K.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» A Bi-Level Branch and Bound Method for Economic Dispatch With Disjoint Prohibited Zones Considering Network Losses
Abstract:
This paper proposes a bi-level branch-and-bound ((B&B) method to solve the economic dispatch problem with prohibited zones and network losses. The approach employs binary variables for each prohibited zone and utilizes the B-coefficient for network losses, which can be transformed into a mixed-integer quadratically constrained quadratic programming (MIQCQP), where linear relaxation technique is applied on each bilinear term. Due to the complexity in solving the MIQCQP problem, this paper proposes a bi-level B&B method to achieve global optimum. A spatial B&B method is utilized in the higher level to solve the quadratically constrained quadratic programming (QCQP) problem, whereas a simple B&B method is employed in the lower level to solve a mixed-integer quadratic programming (MIQP) problem. The bi-level B&B algorithm that combines spatial and simple B&B methods is actually a deterministic optimization method and can produce global optimal solutions. Numerical results on 6-unit, 15-unit, and 40-unit test systems show that the bi-level B&B method can solve the MIQCQP problem with superior solution quality and convergence characteristics.
Autors: Tao Ding;Rui Bo;Fangxing Li;Hongbin Sun;
Appeared in: IEEE Transactions on Power Systems
Publication date: Nov 2015, volume: 30, issue:6, pages: 2841 - 2855
Publisher: IEEE
 
» A Boundary Assembling Method for Chinese Entity-Mention Recognition
Abstract:
A boundary assembling (BA) method is presented for Chinese entity-mention recognition. Given a sentence, instead of recognizing entity mentions in a unitary style, the authors' BA method first detects boundaries of entity mentions and then assembles detected boundaries into entity-mention candidates. Each candidate is further assessed by a classifier trained on nonlocal features. This method can make better use of nonlocal features and effectively recognize nested entity mentions. Using the ACE 2005 Chinese corpus, the authors' experimental results show an improvement over state-of-the-art techniques, outperforming existing methods in F-score by 5 percent for entity-mention detection and 4.23 percent for entity-mention recognition.
Autors: Chen, Yanping;Zheng, Qinghua;Chen, Ping;
Appeared in: IEEE Intelligent Systems
Publication date: Nov 2015, volume: 30, issue:6, pages: 50 - 58
Publisher: IEEE
 
» A Brief History of Experiments in Art and Technology
Abstract:
In the 1960s, there was a growing interest among visual artists, dancers, and composers in using new technology and new technical materials generated by rapid technological developments. The magazine Scientific American was some artists? favorite read.
Autors: Martin, J.;
Appeared in: IEEE Potentials
Publication date: Nov 2015, volume: 34, issue:6, pages: 13 - 19
Publisher: IEEE
 
» A Broadband Highly Efficient Harmonic-Tuned Power Amplifier Exploiting Compact Matching Network
Abstract:
In this letter, a systematic method to design compact output matching network of power amplifier (PA) is proposed, which is based on the simplified real frequency technique. The produced network is mainly constructed with commensurate transmission lines, containing cascaded unit elements and open-shunt stubs, as well as a shorted-series stub for dc bias. A GaN PA is designed to verify the method. The measured results show that the PA achieves 68.07%–79.49% drain efficiency and 40.93 to 42.4 dBm output power from 1.7 to 3.1 GHz. Moreover, the fabricated PA has a small size of only 2015 mm , due to the compact matching networks.
Autors: Ma, L.;Zhou, J.;Huang, W.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2015, volume: 25, issue:11, pages: 718 - 720
Publisher: IEEE
 
» A Brushless Double Mechanical Port Permanent Magnet Motor for Plug-In HEVs
Abstract:
This paper proposes a new brushless double mechanical port flux-switching permanent magnet (BDMP-FSPM) motor for plug-in hybrid electric vehicles applications. The key is to highly integrate two rotors and single stator into one motor frame, which is based on the concept of incorporating the double-rotor motor into a stator-permanent-magnet motor. In addition, by combining the non-contact magnetic planetary gear with the proposed motor, the new resulting electric continuous variable transmission system can not only realize the required speed and torque transmission, but also manage the power split and combination in various driving cycles. The electromagnetic performances of the proposed motor are analyzed by using the finite-element method, such as magnetic field distribution, coupled back-EMF, torque performances, torque-speed curves, and power-speed curves. Experimental results of the BDMP-FSPM prototype are also given to verify the validity.
Autors: Xiang, Z.;Quan, L.;Zhu, X.;Wang, L.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» A Circuit Model of Transverse Electric Eddy-Current Problems in Magnetic Rings
Abstract:
A circuit model consisting of inductance–resistance ladder network to solve the transverse electric eddy-current problems was proposed. The general idea is to divide the region to be solved into a number of eddy shells, which are modeled by a series of coils magnetically coupled with each other. Detailed discussions of the model were made under two special cases where analytical solutions are available. First, it was proved in theory that the limit form of the recursive formula of the circuit model is identical with the Maxwell equations. Next, numerical accuracy of the model was evaluated by making comparison between the circuit solutions and the analytical solutions. It turns out that when the width of each shell is less than the skin depth, the results match the analytical solutions quite well. The proposed circuit model could find its application in the simulation of very fast transient overvoltage mitigation by magnetic rings, where analytical solutions do not exist and other commonly used numerical methods cost too much calculation amount.
Autors: He, J.;Guan, Y.;Liu, W.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» A Class of Two-Weight and Three-Weight Codes and Their Applications in Secret Sharing
Abstract:
In this paper, a class of two-weight and three-weight linear codes over is constructed, and their application in secret sharing is investigated. Some of the linear codes obtained are optimal in the sense that they meet certain bounds on linear codes. These codes have applications also in authentication codes, association schemes, and strongly regular graphs, in addition to their applications in consumer electronics, communication and data storage systems.
Autors: Ding, K.;Ding, C.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Nov 2015, volume: 61, issue:11, pages: 5835 - 5842
Publisher: IEEE
 
» A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning
Abstract:
Nanoscale resistive memory devices are expected to fuel dense integration of electronic synapses for large-scale neuromorphic systems. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in situ learning and computing while driving a large number of resistive synapses is desired. This brief presents a novel leaky integrate-and-fire neuron design that implements the dual-mode operation of current integration and synaptic drive, with a single operational amplifier (opamp) and enables in situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18- CMOS technology. Measurements show neuron's ability to drive a thousand resistive synapses and demonstrate in situ associative learning. The neuron circuit occupies a small area of 0.01 mm 2 and has an energy efficiency value of 9.3 pJ/spike/synapse.
Autors: Wu, X.;Saxena, V.;Zhu, K.;Balagopal, S.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2015, volume: 62, issue:11, pages: 1088 - 1092
Publisher: IEEE
 
» A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor With a Resolution FoM of 0.65 pJ C
Abstract:
In a smart temperature sensor system, two individual building blocks, a sensing front-end and an analog-to-digital converter, are cascaded to implement the temperature-to-digital conversion. In this work, a thermistor-embedded continuous-time delta-sigma modulator (CTDSM), which merges these two building blocks into one, is proposed for a hardware- and energy-efficient temperature acquisition. The thermistor-based sensing front-end is reused in a 2nd-order 1 bit CTDSM to attain a high-resolution, low hardware complexity, and energy-efficient temperature sensing. Furthermore, a resistor-ladder with a switch on-resistance compensation scheme is proposed to implement the trimming circuit. Over a range of -45°C ~ 125°C, the proposed smart temperature sensor consumes 64.5 μW from 1.5 V supply voltage and achieves a resolution around 0.01°C rms (1 σ) temperature resolution with a single conversion time of 100 μs. The corresponding resolution FoM is 0.65 pJ°C2. With 1-point trimming, this design achieves ±1°C temperature inaccuracy; this inaccuracy can be further improved to ±0.4°C with additional batch calibration.
Autors: Chan-Hsiang Weng;Chun-Kuan Wu;Tsung-Hsien Lin;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2491 - 2500
Publisher: IEEE
 
» A coarse-graining approach to rate equations of the composite AC-NBTI model
Abstract:
For ac negative bias temperature instability (NBTI), the composite model that combines the reaction–diffusion (R–D) model for permanent component and the trap–detrap (T–D) model for recoverable component has almost been accepted. However, simple analytical formulas, which are useful for product qualification, have not yet been established. In this paper, we present a coarse-graining approach to analyze the rate equations in the T–D and R–D schemes. Here, the time-averaged rate equations are derived from the equations for stress and recovery phases. The analytical solutions obtained by solving this set of equations can explain the essential features of ac-NBTI, such as the duty-cycle dependence and the memory effect of hole-trapping determined by the standby condition. For the T–D scheme, the exact analytical solutions of the original equations verify this approach, whereas for the R–D scheme, the double-interface R–D model rather than the conventional R–D model captures the duty-cycle dependence observed in the experimental universal curve. Our experimental data on the ac-NBTI are also consistent with the developed analytical model providing a general validity of the approach presented here.
Autors: Murakami, E.;Aono, H.;Ogasawara, M.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2015, volume: 62, issue:11, pages: 3581 - 3587
Publisher: IEEE
 
» A coherent fiber link for very long baseline interferometry
Abstract:
We realize a coherent fiber link for application in very long baseline interferometry (VLBI) for radio astronomy and geodesy. A 550-km optical fiber connects the Italian National Metrological Institute (INRIM) to a radio telescope in Italy and is used for the primary Cs fountain clock stability and accuracy dissemination. We use an ultrastable laser frequency- referenced to the primary standard as a transfer oscillator; at the radio telescope, an RF signal is generated from the laser by using an optical frequency comb. This scheme now provides the traceability of the local maser to the SI second, realized by the Cs fountain at the 1.7 ?? 10???16 accuracy. The fiber link never limits the experiment and is robust enough to sustain radio astronomical campaigns. This experiment opens the possibility of replacing the local hydrogen masers at the VLBI sites with optically-synthesized RF signals. This could improve VLBI resolution by providing more accurate and stable frequency references and, in perspective, by enabling common- clock VLBI based on a network of telescopes connected by fiber links.
Autors: Clivati, C.;Costanzo, G.A.;Frittelli, M.;Levi, F.;Mura, A.;Zucco, M.;Ambrosini, R.;Bortolotti, C.;Perini, F.;Roma, M.;Calonico, D.;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Nov 2015, volume: 62, issue:11, pages: 1907 - 1912
Publisher: IEEE
 
» A Communication Theoretic Analysis of Synaptic Channels Under Axonal Noise
Abstract:
Molecular communication is an emerging communication technology for applications requiring nanoscale networks. Transferring vital information about external and internal conditions of the body through the nervous system is an important type of intra-body molecular nanonetworks. Thus, investigating the performance of such systems from the communication theoretic perspective gives us insight on the limitation of neuro-spike communication and ways to design artificial neural systems. In this letter, we study the performance of the neuro-spike communication under different stochastic impairments such as axonal shot noise, synaptic noise, and random vesicle release. The objective is to optimally detect the spikes at the receiving neuron. Since several uncertainties occur under each hypothesis, composite hypothesis is employed to find the optimum detection policy. Furthermore, we obtain closed-form solutions for the optimal detector and derive the binary decision error at the postsynaptic terminal.
Autors: Maham, B.;
Appeared in: IEEE Communications Letters
Publication date: Nov 2015, volume: 19, issue:11, pages: 1901 - 1904
Publisher: IEEE
 
» A Compact Wide Stopband HTS Filter With Ground Surrounded Quasi-Interdigital Structures
Abstract:
A ground surrounded quasi-interdigital structure (GSQIS) is proposed in this letter. The GSQIS, consisted of several fingers stretching from one end of the microstrip line and the ground, can be conveniently loaded on a quarter-wavelength microstrip resonator. The resonator loaded with the GSQIS can obtain a large ratio of the first spurious frequency to the fundamental resonant frequency , which is suitable for the design of filters with wide stopbands and high out-of-band rejections. Moreover, because the GSQISs are buried inside the ground, couplings between resonators with or without GSQISs are similar. A compact four-pole high temperature superconducting (HTS) filter at 143 MHz is designed and fabricated using the proposed resonators. The measured 80 dB rejection stop-band of the filter is up to 1040 MHz, which is 7.27 times of the fundamental frequency. The size of the filter layout is 27 mm 14 mm or , where is the guided wavelength at 143 MHz.
Autors: Wang, D.;Wei, B.;Cao, B.;Chen, J.;Zhen, T.;Gao, T.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2015, volume: 25, issue:11, pages: 703 - 705
Publisher: IEEE
 
» A Comparative Study of Predicting DBH and Stem Volume of Individual Trees in a Temperate Forest Using Airborne Waveform LiDAR
Abstract:
Using airborne full-waveform LiDAR metrics derived by 3-D tree segmentation, this study estimated single tree's diameter at breast height (DBH) and stem volume (STV). Four regression models were used, including multilinear regression and three up-to-date regression models (i.e., least square boosting trees regression, random forest, and -support vector regression) from the machine learning field. This study aimed to comparatively evaluate these regression models in predicting DBH and STV at single-tree level and find some clues to regression model's selection. The study sites were located in the Bavarian Forest National Park, Germany, a mixed temperate mountain forest. Our comparisons were performed across different tree species types (coniferous and deciduous) and foliage conditions (leaf-on/leaf-off seasons). The importance of predictor variables was also examined. Experimental results revealed that the best accuracy from machine learning methods outperformed the multilinear model by 1.5 cm for DBH and 0.18 m 3 for STV in terms of rmse. Through comparative analysis, our work provided some clues to the performance variation of regression models for extracting 3-D tree parameters.
Autors: Wu, J.;Yao, W.;Choi, S.;Park, T.;Myneni, R.B.;
Appeared in: IEEE Geoscience and Remote Sensing Letters
Publication date: Nov 2015, volume: 12, issue:11, pages: 2267 - 2271
Publisher: IEEE
 
» A Complex-Envelope FDTD Formulation Using Alternating In-Phase and Quadrature Field Variables
Abstract:
Real-valued partial differential equations (PDEs) are obtained by substituting the rectangular form of the complex envelope (CE) field and source quantities into the CE versions of Faraday’s and Ampere’s laws, and then separating each resulting complex PDE into real and imaginary parts. These real-valued PDEs result in a CE FDTD scheme that uses only real numbers and operations. As presented here, this CE FDTD scheme alternates at intervals of half a time step between solving for the real and imaginary portions of the CE fields, exactly as the Yee grid alternates spatial components of the fields at half spatial steps. The scheme is demonstrated here for the two-dimensional (2-D) transverse-magnetic case. A split-step method is used in the implicit formation such that only tridiagonal matrices have to be solved. FDTD results are presented for a 2-D cavity with an electric current source.
Autors: Goggans, P.M.;Liu, Q.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2015, volume: 63, issue:11, pages: 5169 - 5175
Publisher: IEEE
 
» A Construction of New MDS Symbol-Pair Codes
Abstract:
Recently, symbol-pair codes are proposed to protect against pair errors in symbol-pair read channels. One main task in symbol-pair coding theory is to design codes with large minimum pair distance. Maximum distance separable (MDS) symbol-pair codes are optimal in the sense they attain maximal minimum pair distance. In this paper, based on constacyclic codes, we construct some new MDS symbol-pair codes with minimum pair-distance five and six. Compared with classical -ary MDS codes, the constructed MDS symbol-pair codes have length up to .
Autors: Kai, X.;Zhu, S.;Li, P.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Nov 2015, volume: 61, issue:11, pages: 5828 - 5834
Publisher: IEEE
 
» A Continuous Learning Framework for Activity Recognition Using Deep Hybrid Feature Models
Abstract:
Most of the research on human activity recognition has focused on learning a static model, considering that all the training instances are labeled and present in advance, while in streaming videos new instances continuously arrive and are not labeled. Moreover, these methods generally use application- specific hand-engineered and static feature models, which are not suitable for continuous learning. Some recent approaches on activity recognition use deep-learning-based hierarchical feature models, but the large size of these networks constrain them from being used in continuous learning scenarios. In this work, we propose a continuous activity learning framework for streaming videos by intricately tying together deep hybrid feature models and active learning. This allows us to automatically select the most suitable features and take the advantage of incoming unlabeled instances to improve the existing model incrementally. Given the segmented activities from streaming videos, we learn features in an unsupervised manner using deep hybrid networks, which have the ability to take the advantage of both the local hand-engineered features and the deep model in an efficient way. Additionally, we use active learning to train the activity classifier using a reduced amount of manually labeled instances. Retraining the models with a huge amount of accumulated examples is computationally expensive and not suitable for continuous learning. Hence, we propose a method to select the best subset of these examples to update the models incrementally. We conduct rigorous experiments on four challenging human activity datasets to demonstrate the effectiveness of our framework.
Autors: Hasan, M.;Roy-Chowdhury, A.K.;
Appeared in: IEEE Transactions on Multimedia
Publication date: Nov 2015, volume: 17, issue:11, pages: 1909 - 1922
Publisher: IEEE
 
» A Continuous-Time ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation
Abstract:
This brief presents a 120-MS/s continuous-time delta-sigma analog-to-digital conversion with a dual-slope-based time-interleaved quantizer in a 0.18- complementary metal–oxide–semiconductor process. Excess loop delay of two sample clocks is compensated using the time information made available through interleaved channel coupling. As a result, one full clock cycle is afforded to digital-to-analog conversion dynamic element matching (DEM) operation, allowing for a digitally synthesized DEM block.
Autors: Hu, Y.;Venkatram, H.;Maghari, N.;Moon, U.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2015, volume: 62, issue:11, pages: 1063 - 1067
Publisher: IEEE
 
» A Continuous-Time ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation
Abstract:
This brief presents a 120-MS/s continuous-time delta-sigma analog-to-digital conversion with a dual-slope-based time-interleaved quantizer in a 0.18- complementary metal–oxide–semiconductor process. Excess loop delay of two sample clocks is compensated using the time information made available through interleaved channel coupling. As a result, one full clock cycle is afforded to digital-to-analog conversion dynamic element matching (DEM) operation, allowing for a digitally synthesized DEM block.
Autors: Hu, Y.;Venkatram, H.;Maghari, N.;Moon, U.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2015, volume: 62, issue:11, pages: 1063 - 1067
Publisher: IEEE
 
» A Data-Centric Framework for Cyber-Physical-Social Systems
Abstract:
Cyber-physical-social systems (CPSS) that integrate and derive information from cyberspace, physical space, and social space are data-driven, but have yet to be fully investigated. In this article, the authors study CPSS from a data-centric perspective, characterize its core features, and present a layered framework (architecture), focusing on multispace collaborative sensing and cross-space data fusion.
Autors: Guo, Bin;Yu, Zhiwen;Zhou, Xingshe;
Appeared in: IT Professional
Publication date: Nov 2015, volume: 17, issue:6, pages: 4 - 7
Publisher: IEEE
 
» A Diffraction Measurement Model and Particle Filter Tracking Method for RSS-Based DFL
Abstract:
Device-free localization (DFL) based on received signal strength (RSS) measurements functions by measuring RSS variation due to the presence of the target. The accuracy of a certain localization method closely depends on the accuracy of the measurement model itself. Existing models have been found not accurate enough under certain circumstances as they cannot explain some phenomena observed in DFL practices. In light of this, we propose a new model to characterize the RSS variation, which invokes diffraction theory and regards the target as a cylinder instead of a point mass. It is observed that the proposed model agrees well with experimental measurements, particularly when the target crosses the link or is in the vicinity of the link. Since the proposed measurement model is highly nonlinear, a particle filter-based tracking method is used to generate the approximate Bayesian estimate of the target position. As a performance benchmark, we have also derived the posterior Cramér–Rao lower bound of DFL for a diffraction model. A field test has shown that the proposed diffraction model may improve the tracking accuracy at least by 45% in a single-target case and by 27% in a double-target case.
Autors: Wang, Z.;Liu, H.;Xu, S.;Bu, X.;An, J.;
Appeared in: IEEE Journal on Selected Areas in Communications
Publication date: Nov 2015, volume: 33, issue:11, pages: 2391 - 2403
Publisher: IEEE
 
» A Digital Preclinical PET/MRI Insert and Initial Results
Abstract:
Combining Positron Emission Tomography (PET) with Magnetic Resonance Imaging (MRI) results in a promising hybrid molecular imaging modality as it unifies the high sensitivity of PET for molecular and cellular processes with the functional and anatomical information from MRI. Digital Silicon Photomultipliers (dSiPMs) are the digital evolution in scintillation light detector technology and promise high PET SNR. DSiPMs from Philips Digital Photon Counting (PDPC) were used to develop a preclinical PET/RF gantry with 1-mm scintillation crystal pitch as an insert for clinical MRI scanners. With three exchangeable RF coils, the hybrid field of view has a maximum size of 160 mm 96.6 mm (transaxial axial). 0.1 ppm volume-root-mean-square B -homogeneity is kept within a spherical diameter of 96 mm (automatic volume shimming). Depending on the coil, MRI SNR is decreased by 13% or 5% by the PET system. PET count rates, energy resolution of 12.6% FWHM, and spatial resolution of 0.73 mm (isometric volume resolution at isocenter) are not affected by applied MRI sequences. PET time resolution of 565 ps (FWHM) degraded by 6 ps during an EPI sequence. Timing-optimized settings yielded 260 ps time resolution. PET and MR images of a hot-rod phantom show no visible differences when the other modality was in operation and both resolve 0.8-mm rods. Versatility of the insert is shown by successfully combining multi-nuclei MRI ( F) with simultaneously measured PET ( F-FDG). A longitudinal study of a tumor-bearing mouse verifies the operabilit- , stability, and in vivo capabilities of the system. Cardiac- and respiratory-gated PET/MRI motion-capturing (CINE) images of the mouse heart demonstrate the advantage of simultaneous acquisition for temporal and spatial image registration.
Autors: Weissler, B.;Gebhardt, P.;Dueppenbecker, P.M.;Wehner, J.;Schug, D.;Lerche, C.W.;Goldschmidt, B.;Salomon, A.;Verel, I.;Heijman, E.;Perkuhn, M.;Heberling, D.;Botnar, R.M.;Kiessling, F.;Schulz, V.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Nov 2015, volume: 34, issue:11, pages: 2258 - 2270
Publisher: IEEE
 
» A Direct-Sampling Pulsed Time-of-Flight Radar With Frequency-Defined Vernier Digital-to-Time Converter in 65 nm CMOS
Abstract:
This paper presents a direct-sampling pulsed radar with a high-resolution digital-to-time converter (DTC) for estimating the time of flight (TOF), which is to identify the distance between a target and radar. The implemented direct-sampling radar can reconstruct the scanning waveforms in digital domain. The link budget of the radar transceivers is analyzed for the overall scanning range. The scanning range of the radar is dependent on the TOF between radar transmitter and receiver. The range resolution of the pulsed TOF radar is determined by DTC. With the help of exquisite DTC, a high resolution radar can be achieved. The vernier concept has been adopted to achieve an accurate timing resolution design in the DTC. The vernier time steps are defined by the oscillating frequency of the phase-locked loops (PLL), and therefore the DTC with a high resolution in the order of picosecond and with high immunity to PVT variation was developed and demonstrated. The proposed radar was fabricated using 65 nm CMOS technology and occupies a chip area of 2 mm , consumes 88.4 mW of DC power. The receiver has a 10 GHz instantaneous front-end bandwidth for capturing all scattering reflected waveforms and a 666 GS/s equivalent sampling rate for recording all received signals for subsequent digital signal processing (DSP) analysis.
Autors: Kao, Y.-H.;Chu, T.-S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2015, volume: 50, issue:11, pages: 2665 - 2677
Publisher: IEEE
 
» A Distributed Algorithm for Solving a Linear Algebraic Equation
Abstract:
A distributed algorithm is described for solving a linear algebraic equation of the form assuming the equation has at least one solution. The equation is simultaneously solved by agents assuming each agent knows only a subset of the rows of the partitioned matrix , the current estimates of the equation's solution generated by its neighbors, and nothing more. Each agent recursively updates its estimate by utilizing the current estimates generated by each of its neighbors. Neighbor relations are characterized by a time-dependent directed graph whose vertices correspond to agents and whose arcs depict neighbor relations. It is shown that for any matrix for which the equation has a solution and any sequence of “repeatedly jointly strongly connected graphs” , , the algorithm causes all agents' estimates to converge exponentially fast to the same solution to . It is also shown that, under mild assumptions, the neighbor graph sequence must actually be repeatedly jointly strongly connected if exponential convergence is to be assured. A worst case convergence rate bound is derived for the case when has a unique solution. It is demonstrated that with minor modification, the algorithm can track the solution to $Ax = b$, even if and are changing with time, provided the rates of change of and are sufficiently small. It is also shown that in the absence of communication delays, exponential convergence to a solution occurs even if the times at which each agent updates its estimates are not synchronized with the update times of its neighbors. A modification of the algorithm is outlined which enables it to obtain a least squares solution to in a distributed manner, even if does not have a solution.
Autors: Mou, S.;Liu, J.;Morse, A.S.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Nov 2015, volume: 60, issue:11, pages: 2863 - 2878
Publisher: IEEE
 
» A Dynamic Mode Decomposition Framework for Global Power System Oscillation Analysis
Abstract:
A global multiscale method based on a dynamic mode decomposition (DMD) algorithm to characterize the global behavior of transient processes recorded using wide-area sensors is proposed. The method interprets global dynamic behavior in terms of both, spatial patterns or shapes and temporal patterns associated with dynamic modes containing essentially single-frequency components, from which the mode shapes, frequencies and growth and decay rates of the modes can be extracted simultaneously. These modes are then used to detect the coherent and dominant structures within the data. The technique is well suited for fast wide-area monitoring and assessment of global instability in the context of modern data fusion-based estimation techniques. Results of the application of the proposed method to large, high-dimensional data sets are encouraging.
Autors: Barocio, E.;Pal, B.C.;Thornhill, N.F.;Messina, A.R.;
Appeared in: IEEE Transactions on Power Systems
Publication date: Nov 2015, volume: 30, issue:6, pages: 2902 - 2912
Publisher: IEEE
 
» A Family of -Ary Signature Codes for Noisy Multiple-Access Adder Channel
Abstract:
A coding scheme of -ary error-correcting signature codes for a noisy multiple-access adder channel is proposed. Given a signature matrix and a difference matrix a priori, a larger signature matrix is obtained by replacing each element in the Hadamard matrix with , or , or depending on the values of the elements and their locations in the Hadamard matrix. The set of rows in the proposed matrix gives an error-correcting signature code. Introducing a difference matrix makes it possible to construct an error-correcting signature code whose sum rate is increased with an increase in the order of the Hadamard matrix. Either binary or non-binary signature codes are constructed when the pairs of matrices and are given.
Autors: Lu, S.;Hou, W.;Cheng, J.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Nov 2015, volume: 61, issue:11, pages: 5848 - 5853
Publisher: IEEE
 
» A Family of -Ary Signature Codes for Noisy Multiple-Access Adder Channel
Abstract:
A coding scheme of (k+1) -ary error-correcting signature codes for a noisy multiple-access adder channel is proposed. Given a signature matrix A and a difference matrix D=D+ - D- a priori, a larger signature matrix is obtained by replacing each element in the Hadamard matrix with A , or D+ , or D- depending on the values of the elements and their locations in the Hadamard matrix. The set of rows in the proposed matrix gives an error-correcting signature code. Introducing a difference matrix makes it possible to construct an error-correcting signature code whose sum rate is increased with an increase in the order of the Hadamard matrix. Either binary or non-binary signature codes are constructed when the pairs of matrices A and D are given.
Autors: Shan Lu;Wei Hou;Jun Cheng;
Appeared in: IEEE Transactions on Information Theory
Publication date: Nov 2015, volume: 61, issue:11, pages: 5848 - 5853
Publisher: IEEE
 
» A Family of Rank Similarity Measures Based on Maximized Effectiveness Difference
Abstract:
Rank similarity measures provide a method for quantifying differences between search engine results without the need for relevance judgments. For example, the providers of a search service might use such measures to estimate the impact of a proposed algorithmic change across a large number of queries—perhaps millions—identifying those queries where the impact is greatest. In this paper, we propose and validate a family of rank similarity measures, each derived from an associated effectiveness measure. Each member of the family is based on the maximization of effectiveness difference under this associated measure. Computing this maximized effectiveness difference (MED) requires the solution of an optimization problem that varies in difficulty, depending on the associated measure. We present solutions for several standard effectiveness measures, including nDCG, AP, and ERR. Through an experimental validation, we show that MED reveals meaningful differences between retrieval runs. Mathematically, MED is a metric, regardless of the associated measure. Prior work has established a number of other desiderata for rank similarity in the context of search, and we demonstrate that MED satisfies these requirements. Unlike previous proposals, MED allows us to directly translate assumptions about user behavior from any established effectiveness measure to create a corresponding rank similarity measure. In addition, MED cleanly accommodates partial relevance judgments, and if complete relevance information is available, it reduces to a simple difference between effectiveness values.
Autors: Tan, L.;Clarke, C.L.;
Appeared in: IEEE Transactions on Knowledge and Data Engineering
Publication date: Nov 2015, volume: 27, issue:11, pages: 2865 - 2877
Publisher: IEEE
 
» A Fast Cloud-Based Network Selection Scheme Using Coalition Formation Games in Vehicular Networks
Abstract:
Leveraging multiple wireless technologies and radio access networks (RANs), vehicles on the move have the potential to get robust connectivity and continuous service. To support the demands of as many vehicles as possible, an efficient and fast network selection scheme is critically important to achieve high performance and efficiency. So far, prior works have primarily focused on design of optimization algorithms and utility functions for either user or network performance. Most such studies do not address the complexities involved in the acquisition of needed information and the execution of algorithms, making them unsuitable for practical implementations in vehicles. This paper proposes a fast cloud-based network selection scheme for vehicular networks. By leveraging a compute cloud's abundant computing and data storage resources, vehicles can leverage wider scope network information for decision-making. Vehicles select best access networks through a coalition formation game approach. A one-iteration fast convergence algorithm is proposed to achieve the final state of coalition structure in the game. Through extensive simulation, the proposed network selection scheme was shown to balance system throughput and fairness with a built-in utility division rule of the framework. The algorithm efficiency showed eightfold enhancement over a conventional coalition formation algorithm. Such features validate the potential of implementation in practice.
Autors: Xu, K.;Wang, K.;Amin, R.;Martin, J.;Izard, R.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Nov 2015, volume: 64, issue:11, pages: 5327 - 5339
Publisher: IEEE
 
» A Fast Method for Calculating Magnetic Hysteresis Loops
Abstract:
Calculating magnetic hysteresis loops by means of classical spin dynamic methods is a computationally challenging task. To reduce the computing time, we have developed a method that divides the complete hysteresis cycle into intervals. These intervals can be calculated in parallel leading to a significant speedup. We have applied our method to two different examples: first, the switchable exchange bias system Co/ -Cr2O3 with perpendicular magnetization and second, a single layer CoFe(B) as part of a magnetic spin valve system. However, our approach can be applied to other spin systems, even with finite temperatures.
Autors: Stockem, I.;Schroder, C.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures
Abstract:
This paper proposes a flexible energy- and reliability-aware application mapping approach for network-on-chip (NoC)-based reconfigurable architecture. A parameterized cost model is first developed by combining energy and reliability with a weight parameter that defines the optimization priority. Using this model, the overall mapping cost could be evaluated. Subsequently, a mapping method using branch and bound with a partial cost ratio is employed to find the best mapping by enumerating all the possible patterns organized in a search tree. To improve the search efficiency, nonoptimal mappings are discarded at early stages using the partial cost ratio. Using the proposed approach, applications can be mapped onto most NoC topologies and running with various routing algorithms when considering both energy and reliability. Other state-of-the-art works have also done substantial research for the same topic but only limited to a specific topology or routing algorithm. Even for the same topology and routing algorithm, the proposed approach still shows considerable advantages in many aspects. Experiments show that this approach gains not only significant reduction in energy but also improvement in reliability. It also outperforms other approaches in throughput and latency with competitive run time.
Autors: Liu, L.;Wu, C.;Deng, C.;Yin, S.;Wu, Q.;Han, J.;Wei, S.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2015, volume: 23, issue:11, pages: 2566 - 2580
Publisher: IEEE
 
» A Flux-Focusing Cycloidal Magnetic Gearbox
Abstract:
This paper investigates the performance of a −25:1 gear ratio cycloidal magnetic gearbox (CMG) with a flux-focusing rotor topology. The performance of the CMG is investigated by conducting an iterative parameter sweep analysis. An active region torque density of 291 Nm/L is calculated to be achievable with a 0.46% torque ripple. The cycloidal gearbox operates utilizing a nonuniform rotor air gap and this has the adverse effect of creating large nonsymmetric radial forces.
Autors: Li, K.;Bird, J.;Kadel, J.;Williams, W.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» A Fluxgate Current Sensor With a U-Shaped Magnetic Gathering Shell
Abstract:
This paper presents a new current sensor based on fluxgate principle. The sensor consists of a U-shaped magnetic gathering shell. In the designed sensor, the exciting winding and the secondary winding are arranged orthogonally, so that the magnetic fields produced by the two windings are mutually orthogonal and decoupled. Introducing a magnetic gathering shell into the sensor is to concentrate the detected magnetic field and to reduce the interference of an external stray field. Based on the theoretical analysis and the simulation results, a prototype was designed. Test results show that the proposed sensor can measure currents up to 25 A, and has an accuracy of 0.6% and a remarkable resolution.
Autors: Yang, X.;Guo, W.;Li, C.;Zhu, B.;Pang, L.;Wang, Y.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2015, volume: 51, issue:11, pages: 1 - 4
Publisher: IEEE
 
» A Fortescue Approach for Real-Time Short Circuit Computation in Multiphase Distribution Networks
Abstract:
This paper discusses the need for short circuit analysis in real-time applications of modern distribution networks and presents a short circuit tool that builds on recent advances in Fortescue-based current injection power flow. The proposed short circuit computation (SCC) method is fundamentally based on the symmetrical components transformation of three-phase, two-phase, and one-phase systems. Unlike the classical symmetrical components SCC method that postulates a structurally symmetrical three-phase pre-fault network with balanced loading, the proposed method accounts for multiphase networks that are comprised of three-phase, two-phase, and one-phase network parts; given a pre-fault power flow solution, it requires a maximum of three current injection iterations to compute the short circuit current flow in the entire network. Numerical results show that the Fortescue SCC approach with multiphase lines exhibits significant computational performance improvement on large-scale networks as compared to classical SCC in phase coordinates.
Autors: Jabr, R.A.;Dzafic, I.;
Appeared in: IEEE Transactions on Power Systems
Publication date: Nov 2015, volume: 30, issue:6, pages: 3276 - 3285
Publisher: IEEE
 

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