Log in
Register
Pages: 0123456789101112


Electrical and Electronics Engineering publications abstract of: 11-2014 sorted by title, page: 0
» "Just Good Enough" Can Be Great [Editorial]
Abstract:
Autors: Martin, L.;
Appeared in: IEEE Potentials
Publication date: Nov 2014, volume: 33, issue:6, pages: 3 - 3
Publisher: IEEE
 
» 0.7–1.0-GHz Reconfigurable Bandpass-to-Bandstop Filter With Selectable 2- and 4-Pole Responses
Abstract:
A 0.7–1.0-GHz reconfigurable bandpass-to-bandstop filter with selectable 2- and 4-pole responses is presented. The proposed filter can act as a 2- or 4-pole bandpass or bandstop filter by changing the coupling paths using zero-value coupling coefficients. The 4-pole bandpass filter mode also includes bandwidth control. The filter is built on a Duroid substrate with and mil. The center frequency tuning, as well as the bandpass-to-bandstop transformation and the selection of the number of poles are achieved using silicon varactor diodes and RF microelectromechanical systems switches. In the 2- and 4-pole bandpass modes, an insertion loss of 4.9–2.9 and 6.1–4.8 dB is measured at 0.71–0.99 and 0.72–1.01 GHz, respectively. The 4-pole bandpass mode also shows a bandwidth tuning of 28–85 MHz at 0.9 GHz. In the 2- and 4-pole bandstop modes, rejection levels of 24–28 and 32–41 dB are measured at 0.64–0.96 and 0.71–0.96 GHz, respectively. The application areas are in reconfigurable filters for wideband radios under high interference environments.
Autors: Cho, Y.-H.;Rebeiz, G.M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2014, volume: 62, issue:11, pages: 2626 - 2632
Publisher: IEEE
 
» 1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis
Abstract:
We present a 64-channel cross-correlator system for space-borne synthetic aperture imaging. Two different types of ASICs were developed to fit into this system: An 8-channel comparator ASIC implemented in a 130 nm SiGe BiCMOS process technology performs A/D conversion, while a single 64-channel digital cross-correlator ASIC implemented in a 65 nm CMOS process performs the signal processing. The digital ASIC handles 2016 cross-correlations at up to 3.6 GS/s and has a power dissipation of only 0.13 mW/correlation/GHz at a supply voltage of 1 V. The comparator ASIC can handle sample rates of at least 4.5 GS/s with a power dissipation of 47 mW/channel or 1 GS/s with a power dissipation of 17 mW/channel. The assembled system consists of a single board measuring a mere 136 136 mm and weighing only 135 g. The assembled system demonstrates crosstalk of 0.04% between neighboring channels and stability of 800 s. We provide ASIC and system-board measurement results that demonstrate that aperture synthesis can be a viable approach for Earth observation from a geostationary Earth orbit.
Autors: Ryman, E.;Emrich, A.;Andersson, S.B.;Svensson, L.;Larsson-Edefors, P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2720 - 2729
Publisher: IEEE
 
» 250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit
Abstract:
This brief proposes a subthreshold CMOS voltage reference circuit, which reduces the minimum supply voltage by replacing the analog amplifier in the conventional CMOS voltage reference circuit with a low-voltage comparator, a charge-pump circuit, and a digital control circuit. The subthreshold CMOS voltage reference circuit was fabricated using a 0.11- CMOS process. Its core area was 0.013 and it consumed 5.35 at and . Its minimum supply voltage was 242 mV. Ten sample chips generated 193–207-mV reference voltage with 0.4–3.2-mV/100-mV line sensitivity at – and – temperature coefficient at – .
Autors: Yang, B.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2014, volume: 61, issue:11, pages: 850 - 854
Publisher: IEEE
 
» 3-D Interfaces to Improve the Performance of Visual Known-Item Search
Abstract:
Most interfaces in the field of image and video search use a two-dimensional grid interface, which presents image thumbnails in a left-to-right arrangement that can be browsed from top to bottom. This grid interface, however, has several drawbacks that become particularly apparent when performing interactive search tasks for target items in large collections of images or videos. Therefore, we propose to use 3-D interfaces as an alternative to the grid interface for interactive known-item search in visual data as they can partially overcome these drawbacks. In this paper, we first summarize our ideas and discuss design aspects of a 3-D ring and a 3-D globe interface. Next, we present results from four different user studies, where we evaluated the performance of these interfaces for known-item search tasks in image collections. Our results from these studies show that the proposed 3-D interfaces allow for significantly faster visual target search on desktop computers with mouse interaction as well as on tablet devices. The interfaces also achieve better subjective ratings. However, our evaluation also shows that on smartphones with 3.5-in screens an improvement over the grid interface in terms of visual search time is only possible in collections with more than 200 images.
Autors: Schoeffmann, K.;Ahlstrom, D.;Hudelist, M.A.;
Appeared in: IEEE Transactions on Multimedia
Publication date: Nov 2014, volume: 16, issue:7, pages: 1942 - 1951
Publisher: IEEE
 
» 3-D reconstruction of sub-wavelength scatterers from the measurement of scattered fields in elastic waveguides
Abstract:
In nondestructive testing, being able to remotely locate and size defects with good accuracy is an important requirement in many industrial sectors, such as the petrochemical, nuclear, and aerospace industries. The potential of ultrasonic guided waves is well known for this type of problem, but interpreting the measured data and extracting useful information about the defects remains challenging. This paper introduces a Bayesian approach to measuring the geometry of a defect while providing at the same time an estimate of the uncertainty in the solution. To this end, a Markov-chain Monte Carlo algorithm is used to fit simulated scattered fields to the measured ones. Simulations are made with efficient models where the geometries of the defects are provided as input parameters, so that statistical information on the defect properties such as depth, shape, and dimensions can be obtained. The method is first investigated on simulations to evaluate its sensitivity to noise and to the amount of measured data, and it is then demonstrated on experimental data. The defect geometries vary from simple elliptical flat-bottomed holes to complex corrosion profiles.
Autors: Moreau, L.;Hunter, A.J.;Velichko, A.;Wilcox, P.D.;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Nov 2014, volume: 61, issue:11, pages: 1864 - 1879
Publisher: IEEE
 
» 3-MV compact very fast transient overvoltage generator for testing ultra-high-voltage gas-insulated switchgear
Abstract:
Gas-insulated switchgear (GIS) is widely used today in electrical power systems because of its reliability, compaction, long maintenance cycle, and small impact on the environment [1]. In its use the normal operation of the disconnector generates very fast transient overvoltages (VFTO) with frequencies ranging from 1 to 100 MHz [2] and amplitudes up to 2.5 p.u. [3]. For systems above 330 kV, the insulation strength of the GIS under VFTO is of concern as insulation failures caused by VFTO have exceeded those caused by lightning impulse (LI) [4]. This characteristic has attracted the attention of researchers worldwide and currently is a hot topic in the field of ultra-high-voltage (UHV) GIS insulation.
Autors: Wen, T.;Zhang, Q.;Guo, C.;Liu, X.;Pang, L.;Zhao, J.;Yin, Y.;Shi, W.;Chen, W.;Tan, X.;
Appeared in: IEEE Electrical Insulation Magazine
Publication date: Nov 2014, volume: 30, issue:6, pages: 26 - 33
Publisher: IEEE
 
» 30 Gbps High-Speed Characterization and Channel Performance of Coaxial Through Silicon Via
Abstract:
Coaxial through silicon via (TSV) technique allows reduction of high frequency loss due to conductivity in silicon substrate and flexibility in impedance by controlling the ratio of shield to center radii. For the first time, we measured and analyzed the high-speed channel performance of coaxial TSV. This letter presents the measurement results of the fabricated test vehicle in S-parameter and eye-diagram. The eye-diagram measurement results prove that coaxial TSV is capable of supporting signal transmission up to bit rate of 30 Gbps. The equivalent circuit model is suggested and experimentally verified by S-parameter comparison. Furthermore, the superiority of coaxial TSV over conventional TSV is confirmed by comparison of S-parameter results from equivalent circuit model simulation.
Autors: Jung, D.H.;Kim, H.;Kim, S.;Kim, J.J.;Bae, B.;Kim, J.;Yook, J.-M.;Kim, J.-C.;Kim, J.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2014, volume: 24, issue:11, pages: 814 - 816
Publisher: IEEE
 
» 300-GHz Step-Profiled Corrugated Horn Antennas Integrated in LTCC
Abstract:
This paper presents 300-GHz step-profiled corrugated horn antennas, aiming at their integration in low-temperature co-fired ceramic (LTCC) packages. Using substrate integrated waveguide technology, the cavity inside the multi-layer LTCC substrate and a surrounding via fence are used to form a feeding hollow waveguide and horn structure. Owing to the vertical configuration, we were able to design the corrugations and stepped profile of horn antennas to approximate smooth metallic surface. To verify the design experimentally, the LTCC waveguides and horn antennas were fabricated with an LTCC multi-layer process. The LTCC waveguide exhibits insertion loss of 0.6 dB/mm, and the LTCC horn antenna exhibits 18-dBi peak gain and 100-GHz bandwidth with more than 10-dB return loss. The size of the horn antenna is only , which makes it easy to integrate it in LTCC transceiver modules.
Autors: Tajima, T.;Song, H.-J.;Ajito, K.;Yaita, M.;Kukutsu, N.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2014, volume: 62, issue:11, pages: 5437 - 5444
Publisher: IEEE
 
» Pinning Synchronization of Directed Networks With Aperiodic Sampled-Data Communications
Abstract:
This paper addresses the global pinning synchronization problem for a class of directed networks with aperiodic sampled-data communications. Important yet challenging issues of how many and which nodes should be pinned for realizing global synchronization in a fixed directed network without external disturbances are first discussed. By using a combined tool from the input-delay approach and free-weighting matrices technique, some sufficient synchronizability conditions are then derived for such networks. Furthermore, a multi-step algorithm is designed to estimate the upper bound of the maximum allowable sampling intervals for achieving synchronization. Theoretical results are then extended to global pinning synchronization in fixed and switched directed networks with external disturbances, showing that a finite performance index can be guaranteed under some suitable conditions. Finally, numerical simulations are performed to demonstrate the effectiveness of the analytical results.
Autors: Wen, G.;Yu, W.;Chen, M.Z.Q.;Yu, X.;Chen, G.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2014, volume: 61, issue:11, pages: 3245 - 3255
Publisher: IEEE
 
» Consensus Achievement of Multi-Agent Systems With Directed and Switching Topology Networks
Abstract:
The consensus problems with and weighted bounds for a homogeneous team of linear time-invariant (LTI) multi-agent systems with a switching topology and directed communication network graph are studied in this technical note. Sufficient conditions to design distributed controllers are proposed based on state feedback corresponding to bounded gain and rms bounded disturbances. Based on the solution of an algebraic Riccati equation that circumvents the need to solve linear matrix inequalities (LMIs), a design methodology is proposed to properly select the controller gains. The stability properties of the proposed controllers are then investigated based on Lyapunov analysis. The effectiveness of our proposed consensus algorithms are then illustrated by performing simulations for diving consensus of a team of unmanned underwater vehicles (UUVs).
Autors: Saboori, I.;Khorasani, K.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Nov 2014, volume: 59, issue:11, pages: 3104 - 3109
Publisher: IEEE
 
» -Adaptive Control: Stability, Robustness, and Interpretations
Abstract:
An adaptive control design approach that involves the insertion of a strictly proper stable filter at the input of standard Model Reference Adaptive Control (MRAC) schemes has been proposed in the recent years. This approach was given the name -Adaptive Control ( -AC) due to the bounds obtained for various signals. As part of the approach it is recommended to use very high adaptive gains for fast and robust adaptation. The purpose of this note is to analyze whether -AC provides any improvements to existing MRAC schemes by focusing on a simple plant whose states are available for measurement presented in [1]. Our analysis shows that the insertion of the proposed filter deteriorates the performance and robust stability margin bounds compared to standard MRAC, i.e., when the filter is removed. The use of high adaptive gains recommended in the -AC approach may cause two major problems. First, it makes the differential equation of the adaptive law very stiff leading to possible numerical instabilities. Second, it makes the adaptive scheme less robust with respect to unmodeled dynamics.
Autors: Ioannou, P.A.;Annaswamy, A.M.;Narendra, K.S.;Jafari, S.;Rudd, L.;Ortega, R.;Boskovic, J.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Nov 2014, volume: 59, issue:11, pages: 3075 - 3080
Publisher: IEEE
 
» -norms in One-Class Classification for Intrusion Detection in SCADA Systems
Abstract:
The massive use of information and communication technologies in supervisory control and data acquisition (SCADA) systems opens new ways for carrying out cyberattacks against critical infrastructures relying on SCADA networks. The various vulnerabilities in these systems and the heterogeneity of cyberattacks make the task extremely difficult for traditional intrusion detection systems (IDS). Modeling cyberattacks has become nearly impossible and their potential consequences may be very severe. The primary objective of this work is to detect malicious intrusions once they have already bypassed traditional IDS and firewalls. This paper investigates the use of machine learning for intrusion detection in SCADA systems using one-class classification algorithms. Two approaches of one-class classification are investigated: 1) the support vector data description (SVDD); and 2) the kernel principle component analysis. The impact of the considered metric is examined in detail with the study of -norms in radial basis function (RBF) kernels. A heuristic is proposed to find an optimal choice of the bandwidth parameter in these kernels. Tests are conducted on real data with several types of cyberattacks.
Autors: Nader, P.;Honeine, P.;Beauseroy, P.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Nov 2014, volume: 10, issue:4, pages: 2308 - 2317
Publisher: IEEE
 
» LCL-Filter Design for Robust Active Damping in Grid-Connected Converters
Abstract:
Grid-connected converters employ LCL-filters, instead of simple inductors, because they allow lower inductances while reducing cost and size. Active damping, without dissipative elements, is preferred to passive damping for solving the associated stability problems. However, large variations in the grid inductance may compromise system stability, and this problem is more severe for parallel converters. This situation, typical of rural areas with solar and wind resources, calls for robust LCL-filter design. This paper proposes a design procedure with remarkable results under severe grid inductance variation. The procedure considers active damping using lead-lag network and capacitor current feedback. Passive damping is also discussed. The design flow, with little iteration and no complex algorithms, selects the proper ratios between the switching and resonance frequency, the grid and converter inductance, and the filter capacitance and total inductance. An estimation for the grid current total harmonic distortion (THD) is also proposed. Simulation and experiments validate the proposals.
Autors: Pena-Alzola, R.;Liserre, M.;Blaabjerg, F.;Ordonez, M.;Yang, Y.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Nov 2014, volume: 10, issue:4, pages: 2192 - 2203
Publisher: IEEE
 
» A 0.1–5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications
Abstract:
A 0.1–5.0 GHz 65 nm CMOS reconfigurable transmitter for private network wireless communications is presented. The transmitter integrates a 0.1–1.5 GHz high-efficiency dual-mode power amplifier to support low-cost narrowband applications and a 0.45–5.0 GHz efficiency-optimized pre-power amplifier to support high-performance wideband applications. A wideband PLL frequency synthesizer, DACs with reconfigurable sampling rate and the reconfigurable digital baseband processing with standard JESD207 interface are all included to implement the highly-integrated transmitter. Specifically, with the proposed digitally-assisted self-calibration technique for LO leakage and image rejection, the transmitter achieves 52 dBc LO leakage and 53 dBc image rejection ratio (IRR), showing 20 dB and 30 dB improvement compared with the un-calibrated cases, respectively. The system verifications have demonstrated an EVM of 1.7% for 905 MHz EDGE with 19.5 dBm output power, and an EVM of 3.2% for LTE Band42 with 5.5 dBm output power. This proposed transmitter has achieved the comparable or even better performance in linearity, noise floor and power consumption compared with the state-of-the-art reconfigurable transmitters.
Autors: Yin, Y.;Chi, B.;Gao, Y.;Liu, X.;Wang, Z.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2014, volume: 61, issue:11, pages: 3266 - 3277
Publisher: IEEE
 
» A 0.13- CMOS Low-Power Capacitor-Less LDO Regulator Using Bulk-Modulation Technique
Abstract:
In this paper, a bulk-modulation technique is introduced for improving the performance of low-drop-out (LDO) voltage regulators. Compared to conventional LDO voltage regulators, the proposed circuit achieves improved accuracy, stability, and output load current capability. The technique is particularly suited for low-power applications such as biomedical implants and portable devices. A proof-of-concept prototype is designed and fabricated in 0.13- CMOS, to illustrate the enhancement that can be achieved by applying this technique. The proposed enhanced LDO regulator which is based on conventional LDO regulators is able to delivers up to 5 mA of load current while providing a 1 V ( 1.5% load regulation) drawing 99.0 from a 1.2 V supply. Measurement results confirm that as compared to conventional LDOs, the proposed circuit offers better stability as well as %75 improvement in the load current delivery and faster recovery time for no-load to and from full-load transitions.
Autors: Keikhosravy, K.;Mirabbasi, S.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2014, volume: 61, issue:11, pages: 3105 - 3114
Publisher: IEEE
 
» A 0.5-V, 1.47- 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation
Abstract:
A 13-bit successive approximation analog-to-digital converter (ADC) is presented for an ultralow-power sensor interface. Capacitor error compensation is achieved by swapping the roles of two identical capacitor banks in a digital-to-analog converter. The ADC is implemented in a standard 0.13- CMOS. With a single supply voltage of 0.5 V and a rail-to-rail conversion range, the ADC dissipates 1.47 at a sampling rate of 40 kS/s. It shows a figure of merit of 17.9 fJ/conversion-step with an effective number of 11.0 bits.
Autors: Ha, H.;Lee, S.;Kim, B.;Park, H.;Sim, J.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2014, volume: 61, issue:11, pages: 840 - 844
Publisher: IEEE
 
» A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS
Abstract:
This paper presents a 0.6 V input, 0.3–0.55 V output buck converter in 40 nm CMOS, for low-voltage low-power wireless sensor network systems. A low power CCM/DCM controller of the buck converter enables automatic selection of DCM or CCM operation depending on load situation, therefore improving the power efficiency. A dual-mode-body-biased (DMBB) zero-crossing detector with both forward body bias mode and zero body bias mode is designed to enable DCM operation with both low supply voltage and normal supply voltage. An ultra-low-power hysteresis voltage detector is proposed for body bias modes selection. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50 µA to 10 mA. Thanks to the DCM operation, the efficiency at an output current of 10 µA is improved by 20% and 9%, with an output voltage of 0.35 V and 0.5 V, respectively .
Autors: Zhang, X.;Chen, P.-H.;Okuma, Y.;Ishida, K.;Ryu, Y.;Watanabe, K.;Sakurai, T.;Takamiya, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2377 - 2386
Publisher: IEEE
 
» A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS
Abstract:
This paper presents the compute voltage regulator module (C-VRM), an architecture that embeds the information processing subsystem into the energy delivery subsystem for ultra-low power (ULP) platforms. The C-VRM employs multiple voltage domain stacking and core swapping to achieve high total system energy efficiency in near/sub-threshold region. Energy models for the C-VRM are derived, and employed in system simulations to compare the energy efficiency benefits of the C-VRM over a switched capacitor VRM (SC-VRM). A prototype IC incorporating a C-VRM and a SC-VRM supplying energy to an 8-tap fully folded FIR filter core is implemented in a 1.2 V, 130 nm CMOS process. Measured results indicate that the C-VRM has up to 44.8% savings in system-level energy per operation compared to the SC-VRM system, and an efficiency ranging from 79% to 83% over an output voltage range of 0.52 V to 0.6 V. Measured values of the and match those predicted by system simulations thereby validating the energy models.
Autors: Zhang, S.;Tu, J.S.;Shanbhag, N.R.;Krein, P.T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2644 - 2657
Publisher: IEEE
 
» A 1-V–0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry
Abstract:
This brief presents a successive approximation register (SAR) analog-to-digital converter (ADC) that literally obviates the need for a reference supply. The reference (charge) of the digital-to-analog converter (DAC) is instead passively recovered from the residual input common-mode signal after each conversion. Such a fully passive DAC is proved to consume no switching energy in silicon, and the ADC is able to sustain a signal-to-noise-and-distortion ratio (SNDR) of 47 dB with only one supply even if the supply voltage varies from 1 to 0.6 V. Implemented in the 0.18- CMOS process, the ADC dissipates a linearly scalable dynamic power of 20.5–0.77 at a speed from 1.5 to 0.13 MS/s. As no power rail is connected to the DAC, the power supply modulation ratio is improved by 59 dB as compared to conventional designs. Without the need for a reference supply or a supply regulator, the ADC is able to share the same supply with digital systems while achieving energy-efficient data conversion regardless of the supply noise.
Autors: Tsai, J.;Wang, H.;Chen, Y.;Wei, Y.;Kao, Y.;Yen, Y.;Huang, P.;Shen, M.;Chen, H.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2014, volume: 61, issue:11, pages: 825 - 829
Publisher: IEEE
 
» A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers
Abstract:
We present the design of an integrated multiplexer and a dc clamp for the input analog interface of a high-speed video digitizer in the 1.1-V 65-nm complementary metal–oxide–semiconductor process. The ac-coupled video signal is dc restored using a novel all-digital current-mode charge pump. An eight-input multiplexer is realized with T-switches, each containing two series-connected bootstrapped switches. A T-switch's grounding branch is merged with the pull-down end of the clamping charge pump. An adaptive digital feedback loop encompassing a video analog-to-digital converter (ADC) controls the clamp charge pump. The bootstrapped switches have been adapted to suit the video environment, allowing on-the-fly recharging. The varying on-resistance of the conventional bootstrapped switch is utilized to linearize the multiplexer response by canceling the effect of the nonlinear load capacitance contributed by the clamp transistors. Under worst case conditions, the multiplexer maintains a 62–85-dB spurious-free dynamic range over a range of known input video frequencies, and it reduces the second-order harmonic component upon optimization. The dc clamp provides 12-bit precision over the full range of the video ADC and can set the dc at the target level for at most 194 video lines.
Autors: Angelov, P.;Aamir, S.A.;Wikner, J.J.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2014, volume: 61, issue:11, pages: 860 - 864
Publisher: IEEE
 
» A 1.2-V 90-nm Fully Integrated Compact CMOS Linear Power Amplifier Using the Coupled L-Shape Concentric Vortical Transformer
Abstract:
This paper presents a 90-nm fully integrated CMOS linear power amplifier (PA) using a coupled L-shape concentric vortical transformer (CL-CVT) for the fourth-generation long-term evolution (LTE) communication standard. Using the proposed output combining CL-CVT architecture, the outer diameter required by the power combiner is reduced by 66% compared to the distributed active transformer with similar performance. Moreover, the PA is able to efficiently combine four push–pull output stages and achieve nearly constant power over several LTE bands with a total chip area less than 1 . With a 1.2-V supply voltage, the PA delivers 27.3-dBm maximum output power with a peak drain efficiency of 47% at 2.4 GHz. Using a 20-MHz LTE 16-QAM test signal, the PA achieves 24.6% power-added efficiency at an output power level of 22 dBm and passes the spectral requirements defined by the LTE standard without using any pre-distortion or calibration techniques.
Autors: Yang, H.-S.;Chen, J.-H.;Chen, Y.-J.E.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2014, volume: 62, issue:11, pages: 2689 - 2699
Publisher: IEEE
 
» A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector
Abstract:
This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71- . With input 10-Gb/s data of a PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 . At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage.
Autors: Chen, F.-T.;Kao, M.-S.;Hsu, Y.-H.;Wu, J.-M.;Chiu, C.-T.;Hsu, S.S.H.;Chang, M.-C.F.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2014, volume: 61, issue:11, pages: 3278 - 3287
Publisher: IEEE
 
» A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Amplifier
Abstract:
Present-day smartphones and tablets demand high audio fidelity (e.g., total harmonic distortion + noise, THD + N 0.01%), and high noise immunity (e.g., power supply rejection ratio, PSRR 80 dB) to allow high integration in an SoC. The design of conventional closed-loop pulse width modulation (PWM) Class-D amplifiers (CDAs) typically involves undesirable trade-offs between fidelity (qualified by THD + N), PSRR and switching frequency. In this paper, we propose a fully integrated CMOS CDA that embodies a novel input-modulated carrier generator and a novel phase-error-free PWM modulator, collectively allowing the employment of high loop-gain to achieve high PSRR, yet without compromising linearity/dynamic-range or resorting to high switching frequency. The prototype CDA, realized in 65 nm CMOS, achieves a THD + N of 0.0027% and a power efficiency of 94% when delivering 500 mW to an 8 Ω load from V = 3.6 V. The PSRR of the prototype CDA is very high, –101 dB @217 Hz and 90 dB @1 kHz, arguably the highest to-date. Furthermore, the switching frequency of the prototype CDA varies from 320 to 420 kHz, potentially reducing the EMI due to spread-spectrum. In addition, the prototype CDA is versatile with a large operating-voltage range, with V ranging from rechargeable 1.2 V single battery to standard 3.6 V smart-device supply voltages.
Autors: Guo, L.;Ge, T.;Chang, J.S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2608 - 2617
Publisher: IEEE
 
» A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro
Abstract:
To advance our understanding of the functioning of neuronal ensembles, systems are needed to enable simultaneous recording from a large number of individual neurons at high spatiotemporal resolution and good signal-to-noise ratio. Moreover, stimulation capability is highly desirable for investigating, for example, plasticity and learning processes. Here, we present a microelectrode array (MEA) system on a single CMOS die for in vitro recording and stimulation. The system incorporates 26,400 platinum electrodes, fabricated by in-house post-processing, over a large sensing area (3.85 2.10 mm ) with sub-cellular spatial resolution (pitch of 17.5 µm). Owing to an area and power efficient implementation, we were able to integrate 1024 readout channels on chip to record extracellular signals from a user-specified selection of electrodes. These channels feature noise values of 2.4 µV in the action-potential band (300 Hz–10 kHz) and 5.4 µV in the local-field-potential band (1 Hz–300 Hz), and provide programmable gain (up to 78 dB) to accommodate various biological preparations. Amplified and filtered signals are digitized by 10 bit parallel single-slope ADCs at 20 kSamples/s. The system also includes 32 stimulation units, which can elicit neural spikes through either current or voltage pulses. The chip consumes only 75 mW in total, which obviates the need of active cooling even for sensitive cell cultures.
Autors: Ballini, M.;Muller, J.;Livi, P.;Chen, Y.;Frey, U.;Stettler, A.;Shadmani, A.;Viswam, V.;Jones, I.L.;Jackel, D.;Radivojevic, M.;Lewandowska, M.K.;Gong, W.;Fiscella, M.;Bakkum, D.J.;Heer, F.;Hierlemann, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2705 - 2719
Publisher: IEEE
 
» A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology
Abstract:
A charge redistribution successive-approximation-register analog-to-digital converter (ADC) with nonbinary redundant search tree is presented. The combination of thermometer-coded and series-split binary-weighted capacitive digital to analog converters is area efficient and enables high resolution in a standard digital process without high matching requirements. A power and timing-effective latch-based implementation of the digital conversion control is introduced. Fabricated in 28-nm CMOS, the ADC achieves an effective number of bits of 10.1 b and consumes at a conversion rate of 4-MS/s. Measurement results offer a direct comparison of attainable speed at different redundancy settings.
Autors: Haenzsche, S.;Hoppner, S.;Ellguth, G.;Schuffny, R.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2014, volume: 61, issue:11, pages: 835 - 839
Publisher: IEEE
 
» A 128 Kbit SRAM With an Embedded Energy Monitoring Circuit and Sense-Amplifier Offset Compensation Using Body Biasing
Abstract:
Embedded SRAMs are continuing to be one of the most critical components that limit the performance and energy budget of today's systems. To enable better system level optimization, this paper introduces an embedded energy monitoring circuit that measures the absolute energy consumption of a 128 kbit SRAM circuit that is fabricated using a 65 nm low-power CMOS process. Monitoring circuit results are measured to be accurate within 10% of the actual energy consumption and it works with minimal overhead (below 1% active power). Secondly, to achieve energy-efficient and high-performance SRAM operation, various circuit techniques are employed. 8T bit-cells with word-line voltage boosting is used to enable operation for a wide supply range from 370 mV to 1.2 V. Since variation effects are more prominent at low-voltages, SRAM performance is improved by using a two stage sensing scheme. Global sensing is performed by offset compensated sense amplifiers that leverage body biasing to achieve up to 2× offset reduction for only 3.5% area overhead compared to SRAM area.
Autors: Sinangil, Y.;Chandrakasan, A.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2730 - 2739
Publisher: IEEE
 
» A 13 pJ/bit 900 MHz QPSK/16-QAM Band Shaped Transmitter Based on Injection Locking and Digital PA for Biomedical Applications
Abstract:
This paper presents a 900 MHz highly digital transmitter capable of providing band shaped QPSK/16-QAM modulation for high data-rate applications with high energy efficiency. Injection-locked ring oscillator is used for multi-phase carrier generation which eliminates the use of power-hungry phase-locked loop. It also provides fast settling time that enables heavy duty cycling to maximize energy conservation. Direct modulation at power amplifier is adopted to simplify the transmitter architecture. Fabricated in 65 nm CMOS, the transmitter achieves maximum data rate of 50 Mbps/100 Mbps for QPSK/16-QAM with effective sideband suppression more than 38 dB. The chip occupies an active area of 0.08 mm and achieves a settling time of less than 88 ns. Under 0.77 V supply, it achieves an energy efficiency of 26 pJ/bit and 13 pJ/bit with and without band shaping respectively. The measured EVM is better than 6% for QPSK (at 50 Mbps) and 16-QAM (at 100 Mbps) while delivering 15 dBm of output power.
Autors: Liu, X.;Izad, M.M.;Yao, L.;Heng, C.-H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2408 - 2421
Publisher: IEEE
 
» A 13.56 MHz 40 mW CMOS High-Efficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices
Abstract:
In this paper, a 13.56 MHz CMOS near-field inductive link power supply (ILPS) that can deliver 20 mA output current for implantable medical devices (IMDs) is proposed and fabricated. In the proposed ILPS, the pair of inductive link coils is constructed in the spiral shape with a ferrite core to save space and increase efficiency. Experimental results have shown that the near-field coils can transmit power at the resonant frequency of 13.56 MHz with the transmission efficiency up to 76.3%. The CMOS power regulator is composed of active voltage doubler rectifier (VD) and low-dropout regulators (LDOs). In the active VD with the comparator, the input offset voltage is adjustable for delay compensation and a start-up control circuit is added to achieve robust start-up mechanism. On-chip delay compensation control with SR-latches is proposed to prevent from error glitch switching on offset voltage control and achieve accurate delay compensation so that the reverse current conduction can be avoided and the efficiency can be increased. Three fully-integrated LDOs with rectifier output voltage of 2 V to 1.8 V are realized for analog (ALDO), digital (DLDO), and reference-voltage (RLDO) circuits. Thus the performance of individual LDO can be optimized. The measured output ripple voltage of the active VD is 10.4 mV. The power conversion efficiency (PCE) is 85% under 20 mA output current. The measured dropout voltage is 384 mV. As compared with other designs, the proposed ILPS has lower ripple voltages, lower dropout voltage, and higher PCE.
Autors: Wu, C.-Y.;Qian, X.-H.;Cheng, M.-S.;Liang, Y.-A.;Chen, W.-M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2397 - 2407
Publisher: IEEE
 
» A 134 GHz dBm Frequency Doubler at in 130 nm CMOS
Abstract:
A dBm 134 GHz frequency doubler operating at the maximum oscillation frequency of the technology is shown in an IBM 130 nm CMOS process. The doubler is implemented in a balanced topology, driven by a chain of stacked Class-AB amplifiers, and generates the highest reported power in 130 nm CMOS beyond 100 GHz. A theoretical study of frequency doublers is presented including scaling trends across frequency and CMOS technology nodes.
Autors: Sharma, J.;Dinc, T.;Krishnaswamy, H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2014, volume: 24, issue:11, pages: 784 - 786
Publisher: IEEE
 
» A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth
Abstract:
A 16 Gb/s I/O link receiver fabricated in 22 nm CMOS SOI technology is presented. Attenuation and ISI of transmitted NRZ data across PCB channels are equalized with a CTLE feeding an 8-tap DFE. The first tap uses digital speculation and the following seven taps are realized by means of the switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud-rate CDR. The architecture is half-rate and requires one phase rotator. In total, each slice has six comparators to recover data and timing information. The second-order digital CDR operates at quarter-rate and features a low-latency implementation of the proportional path. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization is recovered across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 31 kppm (16 GHz ± 496 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered (BER < 10 ) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver.
Autors: Francese, P.A.;Toifl, T.;Buchmann, P.;Brandli, M.;Menolfi, C.;Kossel, M.;Morf, T.;Kull, L.;Andersen, T.M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2490 - 2502
Publisher: IEEE
 
» A 19-nW 0.7-V CMOS Voltage Reference With No Amplifiers and No Clock Circuits
Abstract:
This brief provides a novel voltage reference circuit that uses four optimization techniques to effectively save power dissipation: 1) All the amplifiers have been eliminated, but two important voltages are still successfully equalized without using any amplifier; 2) the clock circuits are not required in the proposed design; 3) there is no need for extra biasing circuit; and 4) all the MOS transistors are in the subthreshold region to make the power supply voltage low. Moreover, a trimming circuit has been adopted to ensure the accuracy of the reference voltage. This novel voltage reference circuit has been fabricated with the Semiconductor Manufacturing International Corporation 0.18- 1.8-V CMOS process. The measurement results show that the power consumption is only 19 nW, the power supply voltage is only 700 mV, the temperature coefficient is 22.11 under a temperature of – , and the line sensitivity is as good as 571 .
Autors: Zhuang, H.;Zhu, Z.;Yang, Y.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2014, volume: 61, issue:11, pages: 830 - 834
Publisher: IEEE
 
» A 200 GHz Medium Power Amplifier MMIC in Cascode Metamorphic HEMT Technology
Abstract:
A 200 GHz power amplifier is presented. The millimeter-wave monolithic integrated circuit (MMIC) has been realized in a 35 nm InAlAs/InGaAs cascode metamorphic high electron mobility transistor (MHEMT) process in grounded coplanar waveguide technology (GCPW). The amplifier demonstrates an output power of 14 mW with 11.4 dB compressed power gain at 200 GHz. This represents an increase in output power in comparison to previous reported MHEMT-based MMIC amplifiers. The small-signal gain demonstrates a peak value of 20 dB and is above 15.9 dB from 185 to 215 GHz.
Autors: Campos-Roca, Y.;Tessmann, A.;Amado-Rey, B.;Wagner, S.;Massler, H.;Hurm, V.;Leuther, A.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2014, volume: 24, issue:11, pages: 787 - 789
Publisher: IEEE
 
» A 3–25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA
Abstract:
A 3–25 Gb/s four-channel receiver with noise-canceling transimpedance amplifiers and power-scalable limiting amplifiers is presented. It is fabricated in a 40-nm CMOS process. Each channel provides an overall gain of 64 . The measured input integrated noise is 2.7 , and the measured bit error rate is for a 25-Gb/s pseudorandom bit sequence of . The power consumption is 103 mW per channel from a 1.3-V supply. The total area is 1.16 .
Autors: Chien, Y.;Fu, K.;Liu, S.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2014, volume: 61, issue:11, pages: 845 - 849
Publisher: IEEE
 
» A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology
Abstract:
This paper describes key design features of a 32 Gb/s 4-tap FFE/15-tap DFE transceiver in 32 nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver employs a passive feed-forward restore (FFR) scheme in an on-chip AC-coupling network to prevent pattern-dependent baseline wander, a low-latency clock and data recovery (CDR) to improve high-frequency jitter tolerance, and a token-based power management scheme to reduce supply ripple. At 32 Gb/s, the transceiver can equalize a channel with 30 dB of loss at a bit-error rate below 10 while consuming 21 mW/Gbps at 1 V supply and an area of 0.7 mm .
Autors: Gangasani, G.R.;Hsu, C.-M.;Bulzacchelli, J.F.;Beukema, T.;Kelly, W.;Xu, H.H.;Freitas, D.;Prati, A.;Gardellini, D.;Reutemann, R.;Cervelli, G.;Hertle, J.;Baecher, M.;Garlett, J.;Francese, P.-A.;Ewen, J.F.;Hanson, D.;Storaska, D.W.;Meghelli, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2474 - 2489
Publisher: IEEE
 
» A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits
Abstract:
The need for fine-grained power management in digital ICs has led to the design and implementation of compact, scalable low-drop out regulators (LDOs) embedded deep within logic blocks. While analog LDOs have traditionally been used in digital ICs, the need for digitally implementable LDOs embedded in digital functional units for ultrafine grained power management is paramount. This paper presents a fully-digital, phase locked LDO implemented in 32 nm CMOS. The control model of the proposed design has been provided and limits of stability have been shown. Measurement results with a resistive load as well as a digital load exhibit peak current efficiency of 98%.
Autors: Gangopadhyay, S.;Somasekhar, D.;Tschanz, J.W.;Raychowdhury, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2684 - 2693
Publisher: IEEE
 
» A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS
Abstract:
We present a 346 µm 2 reference-free, asynchronous VCO-based sensor interface circuit demonstrated in 28 nm LP bulk CMOS. This design is specifically for sensor node interfaces which do not have the power or volume available for the high accuracy current sources, voltage sources, or low jitter timing references needed for traditional ADCs. By using a straightforward VCO design, it achieves wide resolution, voltage scalability, and process portability while consuming only 1/100th the area of prior approaches and avoiding costly reference circuitry. In the design measured for this paper, resolution can be scaled from 2.8 to 11.7 bits and V DD from 500 mV to 1.0 V. The design contains a single-point calibration scheme that works across temperature, voltage, and resolution settings. Minimum power consumption is 11.7 µW at 0.6 V V DD and minimum energy per conversion step is 41.2 fJ/b at 0.6 V V DD and 9.42 bits of effective resolution.
Autors: Fick, L.;Fick, D.;Alioto, M.;Blaauw, D.;Sylvester, D.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2462 - 2473
Publisher: IEEE
 
» A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring
Abstract:
A low-power multi-functional electrocardiogram (ECG) signal processor is presented in this paper. To enable long-term monitoring, several architecture-level power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An ultra-low-voltage ADC is designed for low-power signal digitization with adaptive clocking. Through these architecture-level techniques, the total power consumption can be significantly reduced by 63% as compared to the conventional design. Several circuit-level design techniques are also developed, including ultra-low-voltage operation and near-threshold level shifting, to further reduce the power consumption by 33%. In addition, a low-complexity cardiac analysis scheme is proposed to realize comprehensive on-chip cardiac analysis. Implemented in 0.18 µm CMOS process, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V for real-time ECG recording and diagnosis.
Autors: Liu, X.;Zhou, J.;Yang, Y.;Wang, B.;Lan, J.;Wang, C.;Luo, J.;Goh, W.L.;Kim, T.T.-H.;Je, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2422 - 2434
Publisher: IEEE
 
» A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications
Abstract:
High-speed ADC front-ends in wireline receivers allow for implementing flexible, complex, and robust equalization in the digital domain, as well as easily supporting bandwidth-efficient modulation schemes, such as PAM4 and duobinary. However, the power consumption of these ADC front-ends and subsequent digital signal processing is a major issue. This paper presents a 64-way 6 bit 10 GS/s time-interleaved successive-approximation-based ADC front-end that efficiently incorporates a two-tap embedded FFE and a one-tap embedded DFE, providing the potential for a lower complexity back-end DSP and/or decreased ADC resolution. Fabricated in a 1.1V GP 65nm CMOS process, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33 mm 2 core ADC area. The effectiveness of the embedded FFE and DFE is demonstrated with significant timing margin improvement observed for 10 Gb/s operation over several FR4 channels.
Autors: Tabasy, E.Z.;Shafik, A.;Lee, K.;Hoyos, S.;Palermo, S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2560 - 2574
Publisher: IEEE
 
» A 6.13 and 96 dB CMOS Exponential Generator
Abstract:
In this brief, a new low-voltage CMOS circuit to produce current-mode exponential characteristics is proposed. MOSFET transistors in weak-inversion region and translinear principle for the temperature cancellation were used. The functionality of the proposed design confirmed with 0.35 CMOS process technology using supply voltage. Results demonstrate the theoretical analysis and verify the efficiency of the proposed structure compared with previously reported designs. Around 96 linear-in-dB output current range is achieved with linearity error over normalized input range from to 5.75. The maximum deviation in the output current is and due to 100 temperature variations and supply voltage fluctuation, respectively.
Autors: Al-Tamimi, K.M.;Al-Absi, M.A.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2014, volume: 22, issue:11, pages: 2440 - 2445
Publisher: IEEE
 
» A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors
Abstract:
A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper}. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18 technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit.
Autors: Chen, D.G.;Tang, F.;Law, M.-K.;Zhong, X.;Bermak, A.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2014, volume: 61, issue:11, pages: 3085 - 3093
Publisher: IEEE
 
» A 65-nm CMOS 10-GS/s 4-bit Background-Calibrated Noninterleaved Flash ADC for Radio Astronomy
Abstract:
This paper presents a 4-bit noninterleaved single-clock-phase 10-GS/s analog-to-digital converter (ADC) fabricated in TSMC 65-nm CMOS technology. The ADC is realized using novel switched dynamic comparators (SDCs), which alleviate the clock-frequency-limiting long regeneration time in prior-art dynamic comparators, and avoid the phase-skew issue associated with time-interleaved ADCs that limits their signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range. The SDC employs a reference-free topology and has no static power consumption. The trip voltage errors of the SDCs are corrected by an efficient on-chip digital background calibration technique. The noninterleaved ADC presents an estimated 100 fF of capacitance at its input, excluding bondpad capacitance, with most of it contributed by the traces leading to the ADC and the shielding structures associated with the input traces. At 10-GS/s sampling rate, the prototype ADC achieves an SNDR of 24.9 dB [3.84 effective number of bit (ENOB)], and 23.4 dB (3.59 ENOB) at low input signal frequencies and Nyquist, respectively. The chip consumes 104 mW from a 1.3 V supply. The ADC has an active area of 0.1 .
Autors: Xu, Y.;Belostotski, L.;Haslett, J.W.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2014, volume: 22, issue:11, pages: 2316 - 2325
Publisher: IEEE
 
» A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- CMOS Process
Abstract:
This brief proposes a 7.5-Gb/s transceiver with adaptive equalization and a bandwidth (BW)-shifting technique for ultrahigh-definition television. By applying dynamic preemphasis calibration and a BW-shifting phase-locked loop/clock and data recovery, the measured jitter of the output data with a 16.88-dB loss cable and clock are enhanced by 49.9% and 40%, respectively. In addition, a data-width-comparison-based adaptive equalizer with a self-adjusting reference voltage is proposed. With a 3.37-MHz sinusoidal jitter, the measured jitter tolerance of the proposed receiver is improved from 1.07UI to 2.97UI. The transmitter and the receiver consume 10.08 and 9.28 mW/Gb/s at 7.5 Gb/s, respectively, and occupy 0.14 and 0.15 , respectively, using a 0.13- complementary metal–oxide–semiconductor process.
Autors: Song, J.;Hwang, S.;Lee, H.;Kim, C.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2014, volume: 61, issue:11, pages: 865 - 869
Publisher: IEEE
 
» A 77–81-GHz 16-Element Phased-Array Receiver With Beam Scanning for Advanced Automotive Radars
Abstract:
A 16-element phased-array receiver has been developed for advanced W-band automotive radars. The phased-array receiver is based on a single SiGe chip with RF beamforming capabilities, which is packaged using low-cost bond-wire techniques and attached to a 16-element linear microstrip array. The antenna results in a directivity of 29.3 dB and a gain of 28.0 dB at 77–81 GHz, and can be scanned to in the azimuth plane in steps. The packaging details are presented together with the steps taken to ensure a wideband impedance match and low coupling between the phased-array channels. Gain measurements done at 79 GHz agree well with simulations. The 16-element phased array receiver was used with a 2-element frequency-modulated continuous-wave transmitter at 76.5–77 GHz and high-resolution millimeter-wave images were obtained. The work shows that complex millimeter-wave phased arrays can be packaged using traditional bond-wire techniques, and can be a powerful solution for advanced automotive radars.
Autors: Ku, B.-H.;Schmalenberg, P.;Inac, O.;Gurbuz, O.D.;Lee, J.S.;Shiozaki, K.;Rebeiz, G.M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2014, volume: 62, issue:11, pages: 2823 - 2832
Publisher: IEEE
 
» A -Band -Plane Waveguide Magic-T With Coplanar Arms
Abstract:
In this paper, an -plane waveguide power divider and a waveguide-to-microstrip transition are used to form a waveguide magic-T with four arms in the same -plane. The input port of the original -plane waveguide power divider acts as the difference port of the magic-T, and a waveguide-to-microstrip transition is utilized to realize the sum port. The four arms are in the same plane, and traditional matching elements, such as cones, wedges, pins, and irises are not needed. The proposed magic-T features easy connection, fabrication, and assembly. The principle and design procedure are described in detail. A -band -plane waveguide magic-T is designed, fabricated, and measured. A fractional bandwidth of 21% is achieved. The measured and simulated results show good amplitude, phase, and isolation characteristics validating the proposed magic-T.
Autors: Chu, Q.-X.;Wu, Q.-S.;Mo, D.-Y.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2014, volume: 62, issue:11, pages: 2673 - 2679
Publisher: IEEE
 
» A Beam Scanning Leaky-Wave Slot Antenna With Enhanced Scanning Angle Range and Flat Gain Characteristic Using Composite Phase-Shifting Transmission Line
Abstract:
In this communication, a planar beam scanning substrate integrated waveguide (SIW) slot leaky-wave antenna (LWA) is proposed for enhancing scanning range and gain flatness using a modified composite right/left-handed transmission line (CRLH TL) structure. The curved phase-shifting characteristics of the modified CRLH TLs positioned between the radiation slots are adopted to increase the scanning range of the proposed antenna. Compared with conventional SIW CRLH LWAs, this antenna offers less gain variation due to its better balance between left-handed and right-handed bands and less sensitivity to its geometrical dimensions. The proposed antenna operating at the center frequency of 25.45 GHz is designed and experimentally verified for an automotive collision avoidance radar. The results show that the antenna achieves a twofold improvement in beam scanning ability with identical overall size.
Autors: Cao, W.;Chen, Z.N.;Hong, W.;Zhang, B.;Liu, A.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2014, volume: 62, issue:11, pages: 5871 - 5875
Publisher: IEEE
 
» A Bio-Inspired Algorithm for Route Selection in Wireless Sensor Networks
Abstract:
How to determine the optimal communication path in wireless sensor networks (WSNs) is a fundamental problem. In this letter, we formulate the optimal communication path problem and convert it into the shortest path tree (SPT) problem by considering an external base station and sensors as the root node and leaf nodes, respectively. Inspired by a path-finding mathematical model Physarum solver, a novel bio-inspired algorithm is proposed to solve the SPT problem in WSNs. Experimental results demonstrate that the proposed algorithm also has an advantage of adaptivity and performs better than Physarum solver in dynamic small WSNs.
Autors: Gao, C.;Yan, C.;Adamatzky, A.;Deng, Y.;
Appeared in: IEEE Communications Letters
Publication date: Nov 2014, volume: 18, issue:11, pages: 2019 - 2022
Publisher: IEEE
 
» A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction
Abstract:
The test cost and yield improvement of embedded memories have become very important as memory capacity and density have grown. For embedded memories, built-in redundancy analysis (BIRA) is widely used to improve yield by replacing faulty cells with a 2-D redundancy architecture. However, the most important factor in BIRA is the reduction of hardware overhead while keeping optimal repair rate. Most BIRA approaches require extra hardware overhead in order to store and analyze faults in the memory. These approaches do not utilize spare memories during the redundancy analysis (RA) procedure. However, the proposed BIRA minimizes area overhead by utilizing a part of the spare memory as an address mapping table (AMT). Since storing the faulty memory addresses take most of the extra hardware overhead, the reduced logical addresses produced by the AMT are used to reduce the extra hardware overhead. In addition, the reduced addresses are stored in content-addressable memories (CAMs) and used in the RA procedure. The proposed BIRA can achieve an optimal repair rate by using an exhaustive search RA algorithm. The proposed RA algorithm compares the repair solution candidates with all the fault addresses stored in the proposed CAMs to guarantee an exhaustive search. The experimental results show that the proposed BIRA requires a smaller area overhead than that of the previous state-of-the-art BIRA with an optimal repair rate.
Autors: Kang, W.;Cho, H.;Lee, J.;Kang, S.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2014, volume: 22, issue:11, pages: 2336 - 2349
Publisher: IEEE
 
» A Broadband 200 GHz Amplifier with 17 dB Gain and 18 mW DC-Power Consumption in 0.13 m SiGe BiCMOS
Abstract:
This letter presents a 200 GHz amplifier for low-power high data-rate wireless communications. With large bandwidth and energy efficiency as concurrent goals, cascode stages for high power gain and dual-band matching networks to maximize the bandwidth have been employed. The resulting amplifier has been implemented in a 450 GHz SiGe BiCMOS technology, requiring a circuit area of only 800 m 300 m. The characterized circuit exhibits 16.9 dB of maximum power gain, 44 GHz of bandwidth and 3.5 dBm of output power at 1 dB compression, while requiring only 18 mW of DC-power.
Autors: Fritsche, D.;Carta, C.;Ellinger, F.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2014, volume: 24, issue:11, pages: 790 - 792
Publisher: IEEE
 
» A Brushless DC Motor Drive With Power Factor Correction Using Isolated Zeta Converter
Abstract:
This paper presents a brushless dc (BLDC) motor drive with power factor correction (PFC) for low-power applications. In this work, the speed of the BLDC motor is controlled by adjusting the dc link voltage of the voltage source inverter (VSI) feeding a BLDC motor. Therefore, VSI is used for achieving only an electronic commutation of the BLDC motor and operates in a low frequency switching for reduced switching losses. A PFC-based isolated zeta converter operating in discontinuous conduction mode (DCM) is used for controlling the dc link voltage of the VSI with inherent PFC at ac mains using single voltage sensor. The proposed drive is implemented to achieve a unity power factor at ac mains for a wide range of speed control and supply voltage fluctuations. An improved power quality is achieved with power quality indices within limits of IEC 61000-3-2 standard.
Autors: Bist, V.;Singh, B.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Nov 2014, volume: 10, issue:4, pages: 2064 - 2072
Publisher: IEEE
 
» A Cascaded Coupled Resonator Decoupling Network for Mitigating Interference Between Two Radios in Adjacent Frequency Bands
Abstract:
A new microwave device called the cascaded type of coupled resonator decoupling network (C-CRDN) is proposed in this paper. The four-port device can be used to reduce the interference between two radio systems that work in adjacent or even contiguous frequency bands. A C-CRDN is cascaded between the two antennas to be decoupled and the I/O ports of their radio systems, respectively. The coupling matrix of a C-CRDN can be designed to meet the required isolation and return-loss specifications. To prove the concept, a fourth- and sixth-order C-CRDN using coaxial combline cavities are designed, fabricated, and measured according to the characteristics of a testing array that consists of two high-gain sleeve dipoles working in the adjacent time-division long-term evolution and wireless fidelity bands. The measured results have demonstrated that the proposed C-CRDN can effectively mitigate the coexistence interference between the two collocated systems by providing at least 20-dB isolation improvement and enhanced matching performance. The proposed technique is general and can find many applications in heterogeneous wireless systems.
Autors: Zhao, L.;Qian, K.-W.;Wu, K.-L.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2014, volume: 62, issue:11, pages: 2680 - 2688
Publisher: IEEE
 
» A Channel-Hopping Multichannel MAC Protocol for Mobile Ad Hoc Networks
Abstract:
Although multiple channels are supported in the physical layer, the IEEE 802.11 MAC-layer mechanism is designed for a single channel. Exploiting multiple channels enhances spatial reuse and reduces transmission collisions and, thus, improves network throughput. Designing a multichannel MAC protocol is much more difficult than designing a single-channel MAC protocol. New challenges, such as the channel allocation problem and the missing receiver problem, must be overcome. Existing multichannel MAC protocols suffer from either higher hardware cost (because of applying multiple transceivers) or lower channel utilization (due to limited transmission opportunity). In this paper, a fully distributed channel-hopping solution, i.e., the cyclic-quorum-based multichannel MAC protocol, is proposed. We use the cyclic quorum in a novel way and the proposed protocol has several attractive features. First, only a single transceiver is needed for each node. Second, any sender is guaranteed to meet its receiver in a short time. Third, each node's channel-hopping sequence is derived from its node ID. This avoids exchanging control messages, such as each node's hopping sequence or available channel list. Fourth, multiple transmission pairs can accomplish handshaking simultaneously. The proposed protocol is simple and efficient. Simulation and real system implementation results verify that our mechanism is a promising multichannel MAC protocol for mobile ad hoc networks.
Autors: Chao, C.;Tsai, H.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Nov 2014, volume: 63, issue:9, pages: 4464 - 4475
Publisher: IEEE
 
» A chapter??s role in networking and continuing education [President's Message]
Abstract:
The IEEE is a nonprofit organization whose goal is to serve its Members. The IEEE Signal Processing Society (SPS) is one of the IEEE's 38 technical Societies. We are a membership organization, and our primary goal is to serve you, so it is very important for us to understand our members and what they expect from us. We cannot use a one-sizefits- all approach as our membership is very diverse, both in terms on the job function (academia, graduate students, undergraduate students, industry, government) and geography. The Society's Membership Board understands how important Chapters are in serving many of our members and how they help create a sense of community and pride in our profession. We have started to recognize Chapters that have done a great job through the Chapter of the Year Award: the Malaysia Chapter won the first award in 2011, the Tainan Chapter in 2012, and the Italy Chapter in 2013. We have also started a Chapter certification process to help all our Chapters leverage best practices. Chapters can also request funding from the SPS Membership Board (sp. bd.membership@ieee.org) for activities such as SPS seasonal schools, meetings featuring industry executives, outreach programs to get students in primary schools interested in signal processing, and more. Please help us increase the vitality of our Chapters by volunteering to serve on the board of your Chapter.
Autors: Acero, A.;
Appeared in: IEEE Signal Processing Magazine
Publication date: Nov 2014, volume: 31, issue:6, pages: 8 - 8
Publisher: IEEE
 
» A Circuit Synthesis Flow for Controllable-Polarity Transistors
Abstract:
Double-gate (DG) controllable-polarity field-effect transistors (FETs) are devices whose n- or p- polarity is online configurable by adjusting the second gate voltage. Such emerging transistors have been fabricated in silicon nanowires, carbon nanotubes, and graphene technologies. Thanks to their enhanced functionality, DG controllable-polarity FETs implement arithmetic functions, such as XOR and MAJ, with limited physical resources enabling compact and high-performance datapaths. In order to design digital circuits with this technology, automated design techniques are of paramount importance. In this paper, we describe a design automation framework for DG controllable-polarity transistors. First, we present a novel dedicated logic representation form capable to exploit the polarity control during logic synthesis. Then, we tackle challenges at the physical level, presenting a regular layout technique that alleviates the interconnection issue deriving from the second gate routing. We use logic and physical synthesis tools to form a complete design automation flow. Experimental results show that the proposed flow is able to reduce the area and delay of digital circuits, based on 22-nm DG controllable-polarity Silicon nanowire (SiNW) FETs, by 22% and 42%, respectively, as compared to a commercial synthesis tool. With respect to a 22-nm FinFET technology, the proposed flow produces circuits, based on 22-nm DG controllable-polarity SiNWFETs, with 2.9 smaller area-delay product.
Autors: Amaru, L.;Gaillardon, P.;De Micheli, G.;
Appeared in: IEEE Transactions on Nanotechnology
Publication date: Nov 2014, volume: 13, issue:6, pages: 1074 - 1083
Publisher: IEEE
 
» A Coding-Theoretic Application of Baranyai’s Theorem
Abstract:
Baranyai’s theorem is well known in the theory of hypergraphs. A corollary of this theorem says that one can partition the family of all -subsets of an -element set into subfamilies such that each subfamily forms a partition of the -element set, where is divisible by . In this paper, we present a coding-theoretic application of Baranyai’s theorem. More precisely, we propose a combinatorial construction of locally decodable codes. Locally decodable codes are error-correcting codes that allow the recovery of any message symbol by looking at only a few symbols of the codeword. The number of looked codeword symbols is called query complexity. Such codes have attracted a lot of attention in recent years. The Walsh–Hadamard code is a well-known binary two-query locally decodable code of exponential length that can recover any message bit using 2 bits of the codeword. Our construction can give locally decodable codes over small finite fields for any constant query complexities. In particular, it gives a ternary two-query locally decodable code of length asymptotically shorter than the Walsh–Hadamard code.
Autors: Zhang, L.F.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Nov 2014, volume: 60, issue:11, pages: 6988 - 6992
Publisher: IEEE
 
» A Compact Model for Erratic Event Simulation in Flash Memory Arrays
Abstract:
The simulation of the erratic bits phenomenon in Flash memory arrays for reliability projections has been a matter of study in the last decade from many standpoints. However, the majority of the developed simulation framework lacked both a direct link with the physics underlying the phenomenon and an easy integration with circuit simulators for fast analysis. In this paper, we have developed a compact model for erratic events starting from the PSP-model description of a Flash cell using Verilog-A. The model has been focused on the reproduction of the overerase phenomenon in a 90-nm NOR Flash array. Its accurate and fast simulation capabilities allowed the evaluation of the array reliability against the erratic erase operation.
Autors: Zambelli, C.;Vincenzi, T.;Olivo, P.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2014, volume: 61, issue:11, pages: 3716 - 3722
Publisher: IEEE
 
» A Comparative Study of Downlink MIMO Cellular Networks With Co-Located and Distributed Base-Station Antennas
Abstract:
Despite the common belief that substantial capacity gains can be achieved by using more antennas at the base-station (BS) side in cellular networks, the effect of BS antenna topology on the capacity scaling behavior is little understood. In this paper, we present a comparative study on the ergodic capacity of a downlink single-user multiple-input-multiple-output (MIMO) system where BS antennas are either co-located at the center or grouped into uniformly distributed antenna clusters in a circular cell. By assuming that the number of BS antennas and the number of user antennas go to infinity with a fixed ratio , the asymptotic analysis reveals that the average per-antenna capacities in both cases logarithmically increase with , but in the orders of and , for the co-located and distributed BS antenna layouts, respectively, where denotes the path-loss factor. The analysis is further extended to the multi-user case where a 1-tier (7-cell) MIMO cellular network with uniformly distributed users in each cell is considered. By assuming that the number of BS antennas and the number of user antennas go to infinity with a fixed ratio , an asymptotic analysis is presented on the downlink rate performance with block diagonalization (BD) adopted at each BS. It is shown that the average per-antenna rates with the co-located and distributed BS antenna layouts scale in the orders of $log_{2}{L over K}$ and , respectively. The rate performance of MIMO cellular networks with small cells is also discussed, which highlights the importance of employing a large number of distributed BS antennas for the next-generation cellular networks.
Autors: Liu, Z.;Dai, L.;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Nov 2014, volume: 13, issue:11, pages: 6259 - 6274
Publisher: IEEE
 
» A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic
Abstract:
Single-poly embedded flash (eFlash) memory is a unique category of embedded nonvolatile memory (eNVM) that can be built in a generic logic technology. Several single-poly eFlash cells have been proposed for cost-effective moderate density eNVM applications. However, the optimal cell configuration of single-poly eFlash is still under debate. In this paper, we compared various single-poly eFlash memory structures in terms of disturbance, program/erase speed, endurance, and retention characteristic based on simulated and experimental data from two eFlash test chips fabricated in a generic 65-nm logic process using standard 2.5 V I/O transistors with 5-nm tunnel oxide. We conclude that a 5T eFlash cell structure combining a pMOS coupling device, an NCAP tunneling device, and an nMOS read/program device with two additional pass transistors to support self-boosting is the most attractive option for logic-compatible eNVMs.
Autors: Song, S.;Kim, J.;Kim, C.H.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2014, volume: 61, issue:11, pages: 3737 - 3743
Publisher: IEEE
 
» A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs
Abstract:
Magnetic random access memory (MRAM) is an emerging technology with potential to become the universal on-chip memory. Among existing MRAM technologies, thermally assisted switching (TAS)-MRAM technology offers several advantages compared with other technologies: selectivity, single magnetic field, and high-integration density. In this paper, we analyze the impact of resistive-open defects on TAS-MRAM behavior. Electrical simulations were performed on a hypothetical 16 word TAS-MRAM architecture enabling any combination of read and write operations. Results show that read and write sequences may be affected by resistive-open defects that may induce single and double-cell faulty behaviors. As a next step, we will exploit the analyses results to guide the test phase by providing effective test algorithms targeting faults related to actual defects affecting TAS-MRAM architectures.
Autors: Azevedo, J.;Virazel, A.;Bosio, A.;Dilillo, L.;Girard, P.;Todri-Sanial, A.;Alvarez-Herault, J.;Mackay, K.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2014, volume: 22, issue:11, pages: 2326 - 2335
Publisher: IEEE
 
» A Component Model for Model Transformations
Abstract:
Model-driven engineering promotes an active use of models to conduct the software development process. In this way, models are used to specify, simulate, verify, test and generate code for the final systems. Model transformations are key enablers for this approach, being used to manipulate instance models of a certain modelling language. However, while other development paradigms make available techniques to increase productivity through reutilization, there are few proposals for the reuse of model transformations across different modelling languages. As a result, transformations have to be developed from scratch even if other similar ones exist. In this paper, we propose a technique for the flexible reutilization of model transformations. Our proposal is based on generic programming for the definition and instantiation of transformation templates, and on component-based development for the encapsulation and composition of transformations. We have designed a component model for model transformations, supported by an implementation currently targeting the Atlas Transformation Language (ATL). To evaluate its reusability potential, we report on a generic transformation component to analyse workflow models through their transformation into Petri nets, which we have reused for eight workflow languages, including UML Activity Diagrams, YAWL and two versions of BPMN.
Autors: Cuadrado, J.S.;Guerra, E.;de Lara, J.;
Appeared in: IEEE Transactions on Software Engineering
Publication date: Nov 2014, volume: 40, issue:11, pages: 1042 - 1060
Publisher: IEEE
 
» A Computerized Recognition System for the Home-Based Physiotherapy Exercises Using an RGBD Camera
Abstract:
Computerized recognition of the home based physiotherapy exercises has many benefits and it has attracted considerable interest among the computer vision community. However, most methods in the literature view this task as a special case of motion recognition. In contrast, we propose to employ the three main components of a physiotherapy exercise (the motion patterns, the stance knowledge, and the exercise object) as different recognition tasks and embed them separately into the recognition system. The low level information about each component is gathered using machine learning methods. Then, we use a generative Bayesian network to recognize the exercise types by combining the information from these sources at an abstract level, which takes the advantage of domain knowledge for a more robust system. Finally, a novel postprocessing step is employed to estimate the exercise repetitions counts. The performance evaluation of the system is conducted with a new dataset which contains RGB (red, green, and blue) and depth videos of home-based exercise sessions for commonly applied shoulder and knee exercises. The proposed system works without any body-part segmentation, bodypart tracking, joint detection, and temporal segmentation methods. In the end, favorable exercise recognition rates and encouraging results on the estimation of repetition counts are obtained.
Autors: Ar, I.;Akgul, Y.S.;
Appeared in: IEEE Transactions on Neural Systems and Rehabilitation Engineering
Publication date: Nov 2014, volume: 22, issue:6, pages: 1160 - 1171
Publisher: IEEE
 
» A Configurable Monitoring Infrastructure for NoC-Based Architectures
Abstract:
In this brief, we propose a monitoring architecture for networks-on-chip that provides system information useful for designers to efficiently exploit, at design time and run-time, the system resources available in multiprocessor system-on-chip platforms. We focus on the analysis of the architectural details and design challenges of such a system, by describing powerful tools for monitoring information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. This brief describes the design of the monitoring probes, together with the events detectable by them, and discusses an architecture for collecting, storing, and analyzing the information gathered during an application execution.
Autors: Fiorin, L.;Palermo, G.;Silvano, C.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2014, volume: 22, issue:11, pages: 2436 - 2440
Publisher: IEEE
 
» A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems
Abstract:
We propose in this paper a novel configurable multi-power-rail pad that combines power supply support circuits and a digital input/output (I/O) buffers designed for a wafer-scale system. This wafer-scale platform includes a reconfigurable wafer-scale circuit, the WaferIC, comprising an alignment-insensitive surface that can be configured to interconnect any digital components manually deposited on its surface. The proposed multi-power-rail pad minimizes power losses and heat dissipation within the circuit. The pad that is fed from two distinct voltage sources providing power at 1.8 and 3.3 V has been implemented and tested. This pad has two merged configurable control loops that can select the power source. Merging takes place through shared transistors. This dual supply pad embeds a voltage regulator that achieves a fast response time of 21.1 ns and that can operate over a wide range of configurable regulated output voltage, from 500 mV up to 2.955 V. This regulator is capable of providing a maximum output current of 40 mA while needing only a very small quiescent current of 126 A. The regulator's power supply noise rejection ranges from 25 down to 40 dB for frequencies ranging from 1 kHz up to 1 MHz. The embedded digital I/O pad shares a common output with the power distribution and can be configured from 0.5 up to 3.3 V for a maximum speed of 250 MHz.
Autors: Laflamme-Mayer, N.;Blaquiere, Y.;Savaria, Y.;Sawan, M.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2014, volume: 61, issue:11, pages: 3135 - 3144
Publisher: IEEE
 
» A Continuous Electrical Conductivity Model for Monolayer Graphene From Near Intrinsic to Far Extrinsic Region
Abstract:
We present a closed-form continuous model for the electrical conductivity of a single layer graphene (SLG) sheet in the presence of short-range impurities, long-range screened impurities, and acoustic phonons. The validity of the model extends from very low doping levels (chemical potential close to the Dirac cone vertex) to very high doping levels. We demonstrate complete functional relations of the chemical potential, polarization function, and conductivity with respect to both doping level and temperature ( ), which were otherwise developed for SLG sheet only in the very low and very high doping levels. The advantage of the continuous conductivity model reported in this paper lies in its simple form which depends only on three adjustable parameters: the short-range impurity density, the long-range screened impurity density, and temperature . The proposed theoretical model was successfully used to correlate various experiments in the midtemperature and moderate density regimes.
Autors: Bhattacharya, S.;Saha, D.;Bid, A.;Mahapatra, S.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2014, volume: 61, issue:11, pages: 3646 - 3653
Publisher: IEEE
 
» A Control Strategy for Electric Traction Systems Using a PM-Motor Fed by a Bidirectional -Source Inverter
Abstract:
This paper deals with a control method that adapts the dc bus voltage of electric traction systems using permanent-magnet synchronous machine (PMSM) fed by bidirectional -source inverter (ZSI) or other improved topologies. This control allows reducing both the overestimation of the dc bus voltage and losses in the inverter. The sliding-mode control (SMC) method is used to control the -source converter, whereas flatness-based control is proposed to drive the actuator and generate the peak dc bus voltage reference. Flatness-based control is chosen because the actuator transients are well mastered. Extra shoot-through zero inverter states are inserted by means of implemented algorithm on a space-vector-modulation (SVM) scheme. Different short-circuit strategies are studied and compared according to constraint criteria. Both simulation and experimental results are presented and discussed to validate the proposed voltage adaptation strategy and the improvement on global efficiency.
Autors: Battiston, A.;Miliani, E.;Martin, J.;Nahid-Mobarakeh, B.;Pierfederici, S.;Meibody-Tabar, F.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Nov 2014, volume: 63, issue:9, pages: 4178 - 4191
Publisher: IEEE
 
» A Cooperative Transmission Scheme for Improving the Secondary Access in Cognitive Radio Networks
Abstract:
In this paper, we examine the problem of secondary access blocking in cognitive radio networks when secondary transmissions cause unacceptably high interference to primary transmissions. In general, the access of secondary users (SUs) to a licensed spectrum band is only allowed when this access does not alter the performance of primary users that can be defined by the primary QoS requirement. In this paper, we propose a cooperative scheme that allows SUs to increase their access to the spectrum band and access the spectrum even when the primary QoS is not satisfied. Using relay selection and a proper power allocation method, we show that the secondary outage performance can be significantly improved, whereas the primary outage performance is either not altered or slightly improved. Moreover, closed-form expressions of the primary and secondary outage probabilities are derived, and the achieved diversity order is calculated. Finally, analytical and simulation results illustrate the primary outage performance and secondary outage performance of the proposed scheme and show its advantages compared with conventional schemes.
Autors: Jaafar, W.;Ajib, W.;Haccoun, D.;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Nov 2014, volume: 13, issue:11, pages: 6219 - 6231
Publisher: IEEE
 
» A Current-Shared Cascade Structure With an Auxiliary Power Regulator for Switching Mode RF Power Amplifiers
Abstract:
In this study, we propose an auxiliary power regulator (APR) for the current-shared cascade (CSC) structure of the driver stages of RF CMOS power. Although the CSC structure provides a method to reduce the power consumption at the driver stages of a differential power amplifier (PA), it is difficult to obtain optimum levels of effective supply voltage for the first and second driver stages. Additionally, the transistor sizes of the first and second driver stages of the CSC structure must be identical to ensure the proper operation of the PA. Thus, in this work, we propose an APR structure that ensures the proper operation of a PA with different transistor sizes in its first and second driver stages. To prove the feasibility of the proposed technique, we designed the PA with a CSC structure using an APR. From the measured results, we successfully verify the feasibility of the proposed structure. Additionally, we provide experimental results for a typical CMOS PA to determine the optimum supply voltage for the second driver stage.
Autors: Hwang, H.;Lee, C.;Park, J.;Park, C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2014, volume: 62, issue:11, pages: 2711 - 2722
Publisher: IEEE
 
» A D-Band Keyable High Efficiency Frequency Quadrupler
Abstract:
A D-band frequency quadrupler consisting of two cascaded push-push doublers is designed and manufactured in a 0.25 InP DHBT technology. Each doubler has a Marchand balun implemented by broadside-coupled transmission lines, folded in a rectangular shape. The second balun, operating at a half of output frequency, is located inside of the first one for minimizing the chip size. The frequency quadrupler with a dc power consumption of 47 mW has a maximum conversion gain of 2 dB, and exhibits 12 to 25 dBc rejection ratio of the undesired first to fifth harmonics in the frequency range from 110 to 130 GHz. The quadrupler demonstrates a power efficiency of 10%, which is the highest among published quadruplers, as well as the highest conversion gain and an output power of 5 7 dBm without using power amplifiers. The chip size is 0.77 . By switching a cascode transistor, the quadrupler can also be used as an on-off keying modulator.
Autors: Bao, M.;Kozhuharov, R.;Chen, J.;Zirath, H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2014, volume: 24, issue:11, pages: 793 - 795
Publisher: IEEE
 
» A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories
Abstract:
The limits of technology scaling for smaller chip size, higher performance, and lower power consumption are being reached. For this reason, the memory semiconductor industry is searching for new technology. 3-D stacked memory using through-silicon via (TSV) has been considered as a promising solution for overcoming this challenge. However, to guarantee quality and yield for mass production of 3-D stacked memories, effective test techniques for TSV are required. In this paper, a new test architecture for testing TSVs in 3-D stacked memories is proposed. By comparing voltage changes generated due to resistive open defects with a reference voltage applied externally, the test circuit estimates delay across the TSV. This allows the possibility of a delay test with low-frequency test equipment. Experimental results demonstrate that the proposed test architecture can be effective in the testing of TSV with resistive open defects, and have lower area overhead and lower peak current consumption.
Autors: Sung, H.;Cho, K.;Yoon, K.;Kang, S.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2014, volume: 22, issue:11, pages: 2380 - 2387
Publisher: IEEE
 
» A Demand Response Energy Management Scheme for Industrial Facilities in Smart Grid
Abstract:
Demand response (DR) smart grid technology provides an opportunity for electricity consumers to actively participate in the management of power systems. Industry is one of the major consumers of electric power. In this study, we propose a DR energy management scheme for industrial facilities based on the state task network (STN) and mixed integer linear programming (MILP). The scheme divides the processing tasks in industrial facilities into nonschedulable tasks (NSTs) and schedulable tasks (STs), and takes advantage of distributed energy resources (DERs) to implement DR. Based on day-ahead hourly electricity prices, the scheme determines the scheduling of STs and DERs in order to shift the demand from peak periods (with high electricity prices) to off-peak periods (with low electricity prices), which not only improves the reliability of the electric power system, but also reduces energy costs for industrial facilities.
Autors: Ding, Y.M.;Hong, S.H.;Li, X.H.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Nov 2014, volume: 10, issue:4, pages: 2257 - 2269
Publisher: IEEE
 
» A Digital Interpretation of Frequency-Periodic Signal-Interference Microwave Passive Filters
Abstract:
This paper addresses, for the first time, the digital representation of spectrally periodic signal-interference microwave passive filters. Starting from the theoretical rational transfer function of a synthesized transmission-line signal-interference analog filter, the real-valued coefficients of its digital-domain filter counterpart are derived. This discrete-time formulation for this type of microwave filters allows to clarify some confusing concepts into them, such as filter order. Moreover, some particular phenomena observed in associated experimental proof-of-concept planar prototypes, such as the appearance of out-of-band/spurious resonance peaks, are also explained by this study as zero-pole quasi-cancellations. In addition, it is demonstrated here that the use of the adjective “transversal” for this class of microwave passive filters could be no rigorous as it is understood in a digital sense since its discrete-time modeling commonly obeys an infinite-impulse-response structure. For validation, the expounded theoretical framework is applied to three examples of signal-interference passive filters exhibiting quasi-elliptic-type single-passband, six-passband, and low-pass responses.
Autors: Munoz-Ferreras, J.-M.;Gomez-Garcia, R.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2014, volume: 62, issue:11, pages: 2633 - 2640
Publisher: IEEE
 
» A Digital Parallel Current-Mode Control Algorithm for DC–DC Converters
Abstract:
This paper presents a novel digital current-mode control strategy for dc–dc converters. In the proposed algorithm, the required duty cycle is calculated directly by two parallel terms. With some simple operations in digital implementation, the resultant control system achieves rapid and precise output voltage regulation under the input voltage and output load change. Moreover, the implementation of the proposed algorithm with a digital controller is discussed in detail. Analysis shows that the parallel current-mode control does not exhibit subharmonic oscillation. A 400-kHz switching frequency buck converter based on field-programmable gate array implementation is built to verify the feasibility and advantages of the parallel current-mode control.
Autors: Fang, W.;Liu, X.;Liu, S.;Liu, Y.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Nov 2014, volume: 10, issue:4, pages: 2146 - 2153
Publisher: IEEE
 
» A Distributed Algorithm for Managing Residential Demand Response in Smart Grids
Abstract:
Demand response enabled by time-varying prices can propel the power industry toward a greater efficiency. However, a noncoordinated response of customers may lead to severe peak rebounds at periods with lower prices. In this regard, a coordinated demand response scheme can mitigate concerns about the peak rebounds. This paper presents a system-wide demand response management model to coordinate demand response provided by residential customers. The objective of the model is to flatten the total load profile that is subject to minimum individual cost of customers. The model is first formulated as a bi-level optimization problem. It is then casted into equivalent single-level problems, which are solved via an iterative distributed algorithm. Home load management (HLM) modules embedded in customers’ smart meters are autonomous agents associated with the algorithm. In the algorithm, at first, HLM modules, in response to prices announced by the utility, optimize the daily operation of household appliances and send back the scheduled load profiles. Then, the total load profile is calculated and released by the utility. Thereafter, the HLM modules asynchronously update their schedule such that, given their least energy expenses, the most evenly distributed total load profile is achieved. The mutual interaction between the utility and HLM modules is continued to the point in which no further improvement is obtained. Convergence and optimality of the algorithm are proved.
Autors: Safdarian, A.;Fotuhi-Firuzabad, M.;Lehtonen, M.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Nov 2014, volume: 10, issue:4, pages: 2385 - 2393
Publisher: IEEE
 
» A Dual-Operation-Mode Bio-Inspired Pixel
Abstract:
A new bio-inspired pixel concept is proposed. It can compute the spatial contrast and provide intensity images. The pixel sends spikes to communicate with its neighbors, computing the spatial contrast. Its expected fixed-pattern noise within neuromorphic arrays is 1% without using calibration. Its fill factor is 8.5%. Furthermore, the pixel has two different readout modes: pulse density modulation and time to first spike. The user can toggle any time between operation and readout modes, depending on the desired image quality and the bandwidth and power consumption requirements. The pixel has been implemented in AMS4M2P 0.35- CMOS technology. Experimental results are provided.
Autors: Lenero-Bardallo, J.A.;Hafliger, P.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2014, volume: 61, issue:11, pages: 855 - 859
Publisher: IEEE
 
» A Formal Proof of the Optimal Frame Setting for Dynamic-Frame Aloha With Known Population Size
Abstract:
In dynamic-frame Aloha, subsequent frame lengths must be optimally chosen to maximize throughput. When the initial population size is known, numerical evaluations show that the maximum efficiency is achieved by setting the frame length equal to the backlog size at each subsequent frame; however, to the best of our knowledge, a formal proof of this result is still missing, and is provided here. As byproduct, we also prove that the asymptotic efficiency in the optimal case is , provide tight upper and lower bounds for the length of the entire transmission period, and show that its asymptotic behavior is with .
Autors: Barletta, L.;Borgonovo, F.;Cesana, M.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Nov 2014, volume: 60, issue:11, pages: 7221 - 7230
Publisher: IEEE
 
» A Four-FET Method for Extracting Mobility in FETs Without Field Oxide
Abstract:
Many fabricated III–V MOSFETs have electrically thin field oxide (FOX) that leads to parasitic currents and parasitic capacitances. When extracting long-channel mobility of such devices using the conventional two-FET method, some of these parasitic components are not subtracted out. In this paper, we present a simple four-FET method for extracting long-channel mobility that works well even when the equivalent oxide thickness (EOT) of the FOX is equal to the EOT of the FET gate oxide.
Autors: Majumdar, A.;Lee, K.;Cheng, C.;Shiu, K.;Sadana, D.K.;Leobandung, E.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2014, volume: 61, issue:11, pages: 3833 - 3837
Publisher: IEEE
 
» A Fourth-Order Lumped-Element Bandpass Filter Constructed on Multilayer Substrates
Abstract:
A fourth-order bandpass filter scheme and its implementation with multilayer substrates are proposed in this letter. The filter is composed of two second-order filters and an impedance matching network between them, which provides one additional controllable transmission zero. By using two different feedback capacitors, two additional transmission zeros are introduced. The physical layout is fully interpreted and an experimental prototype is fabricated and measured. Good agreement between measured results and simulated results is observed. The results show the high out-of-band suppression.
Autors: Cao, K.;Li, Q.-W.;Cheng, C.-H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2014, volume: 24, issue:11, pages: 745 - 747
Publisher: IEEE
 
» A Framework for Root Cause Detection of Sub-Batch Processing System for Semiconductor Manufacturing Big Data Analytics
Abstract:
Root cause detecting and rapid yield ramping for advanced technology nodes are crucial to maintain competitive advantages for semiconductor manufacturing. Since the data structure is increasingly complicated in a fully automated wafer fabrication facility, it is difficult to diagnose the whole production system for fault detection. A number of approaches have been proposed for fault diagnosis and root cause detection. However, many constraints in real settings restrict the usage of conventional approaches, due to the big data with complicated data structure. In particular, a batch may not be considered as a run in the present sub-batch processing system for wafer fabrication, in which the processing paths of the wafers in a batch could be different. Motivated by realistic needs, this paper aims to develop a root cause detection framework for the sub-batch processing system. Briefly, the proposed framework consists of three phases: data preparation, data dimension reduction, and the sub-batch processing model construction and evaluation. The proposed approach has been validated by a sequence of simulations and an empirical study conducted in a leading semiconductor manufacturing company in Taiwan. The results have shown practical viability of the proposed approach. Indeed, the developed approach is incorporated in the engineering data analysis system in this case company.
Autors: Chien, C.;Chuang, S.;
Appeared in: IEEE Transactions on Semiconductor Manufacturing
Publication date: Nov 2014, volume: 27, issue:4, pages: 475 - 488
Publisher: IEEE
 
» A Fully Integrated Multilayer Power Distribution Network for SAR Dual-Polarized Linear Arrays
Abstract:
The design, manufacturing and testing of a planar technology, fully integrated, multilayer, dual-polarized power distribution network, feeding a six element X-band linear array is presented. The selected technology, not used yet for space applications, is particularly suitable for large scale, low cost manufacturing. The proposed architecture provides an isolation between the two polarizations better than 40 dB, an input ports return loss better than 25 dB, and a 0.6 dB worst case amplitude unbalancing with a maximum phase shift of about 9 degrees between output ports, within a 16.7% bandwidth.
Autors: Capece, P.;Lucci, L.;Pelosi, G.;Porfilio, M.;Righini, M.;Steffe, W.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2014, volume: 24, issue:11, pages: 760 - 762
Publisher: IEEE
 
» A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver
Abstract:
This paper presents a fully integrated SAR ADC for GSM/WCDMA/LTE triple-mode transceiver (RFIC) with non-binary DAC structure and digital correction techniques. All blocks including input buffer, ADC core, bias, references and ADC logics are implemented in a single chip with a small die area of 0.044 mm /0.066 mm for ADC core and ADC logic. The proposed ADC does not require off-chip decoupling capacitor for reference voltage by employing charge-sharing topology. Reconfigurable structure is used for multi-mode operation by adjusting ADC speed and noise, where SNDR of 67.0 dB in GSM and 58.2 dB in WCDMA/LTE are achieved at the sampling frequencies of 52 MS/s and 80 MS/s, respectively.
Autors: Nakane, H.;Ujiie, R.;Oshima, T.;Yamamoto, T.;Kimura, K.;Okuda, Y.;Tsuiji, K.;Matsuura, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2503 - 2514
Publisher: IEEE
 
» A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving
Abstract:
An extremely low-power flip-flop (FF) named topologically-compressed flip-flop (TCFF) is proposed. As compared with conventional FFs, the FF reduces power dissipation by 75% at 0% data activity. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression method, merger of logically equivalent transistors to an unconventional latch structure. The very small number of transistors, only three, connected to clock signal reduces the power drastically, and the smaller total transistor count assures the same cell area as conventional FFs. In addition, fully static full-swing operation makes the cell tolerant of supply voltage and input slew variation. An experimental chip design with 40 nm CMOS technology shows that almost all conventional FFs are replaceable with proposed FF while preserving the same system performance and layout area.
Autors: Kawai, N.;Takayama, S.;Masumi, J.;Kikuchi, N.;Itoh, Y.;Ogawa, K.;Ugawa, A.;Suzuki, H.;Tanaka, Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2526 - 2533
Publisher: IEEE
 
» A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot Detection
Abstract:
In advanced IC manufacturing, as the gap increases between lithography optical wavelength and feature size, it becomes challenging to detect problematic layout patterns called lithography hotspot. In this paper, we propose a novel fuzzy matching model which extracts appropriate feature vectors of hotspot and nonhotspot patterns. Our model can dynamically tune appropriate fuzzy regions around known hotspots. Based on this paper, we develop a fast algorithm for lithography hotspot detection with high accuracy of detection and low probability of false-alarm counts. In addition, since higher dimensional size of feature vectors can produce better accuracy but requires longer run time, this paper proposes a grid reduction technique to significantly reduce the CPU run time with very minor impact on the advantages of higher dimensional space. Our results are very encouraging, with average 94.5% accuracy and low false-alarm counts on a set of test benchmarks.
Autors: Wen, W.;Li, J.;Lin, S.;Chen, J.;Chang, S.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Nov 2014, volume: 33, issue:11, pages: 1671 - 1680
Publisher: IEEE
 
» A Ge Ultrathin-Body n-Channel Tunnel FET: Effects of Surface Orientation
Abstract:
We theoretically investigated the surface orientation effects on the complex band structures and performance of a 5-nm ultrathin-body Ge n-channel double gate tunnel field-effect transistor. The Ge is an indirect bandgap material, and the direct band-to-band (BTB) tunneling rate in Ge is not appreciated. We use (001) and (011) Ge thin-body to project the X[001] and X[100] valley to the 2-D Brillouin zone center, and (111) Ge thin-body to project the L[111] valley pair to the zone center. The trajectory of imaginary is the key factor for direct BTB tunneling, and we find that the imaginary -axis of the projected L[111] valley of (111) Ge thin-body provides the best BTB tunneling rate among the three orientations. The direct bandgap of (111) orientation is lowest among the three orientations, which results in the thinnest tunnel barrier in (111) device. The drive current of (111) device is higher than (011) device and higher than (001) device. The (001), (011), and (111) devices have subthreshold slope substantially lower than thermal limit, however, only (111) device has an (current at 60 mV/decade slope) value close to the desired limit. We use lower Gaussian doping in drain region to suppress ambipolar current. A lower doping results in a longer tunnel barrier at the drain-channel interface and more than two orders of magnitude suppression of ambipolar current.
Autors: Alam, K.;Takagi, S.;Takenaka, M.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2014, volume: 61, issue:11, pages: 3594 - 3600
Publisher: IEEE
 
» A Generalized Convergence Criterion to Achieve Maximum Fairness Among Users in Downlink Asynchronous Networks Using OFDM/FBMC
Abstract:
In this letter, we address the problem of maximizing the minimum user rates known as rate adaptive (RA) for asynchronous cellular networks with multicarrier modulation such as filter-bank-based multicarrier and orthogonal frequency-division multiplexing. By exploiting the relationship between margin adaptive (MA) and RA, we propose a general convergence criterion to solve the MA power control problem permitting to achieve maximum fairness among all users for the RA problem. Simulation results demonstrate a remarkable improvement in terms of higher minimum user data rates for the RA when the proposed convergence criterion is utilized over the traditional iterative waterfilling for the power control scheme of the MA problem.
Autors: Denis, J.;Pischella, M.;Le Ruyet, D.;
Appeared in: IEEE Communications Letters
Publication date: Nov 2014, volume: 18, issue:11, pages: 2003 - 2006
Publisher: IEEE
 
» A Generalized Decentralized Robust Control of Islanded Microgrids
Abstract:
This paper presents the fundamental concepts of a generalized central power management system and a decentralized, robust control strategy for autonomous mode of operation of a microgrid that includes multiple distributed energy resource (DER) units. DER units are divided into voltage-controlled and power-controlled DER units. The frequency of each DER unit is determined by its independent internal oscillator and all oscillators are synchronized by a common time-reference signal based on a global positioning system (GPS). The power management system (PMS) specifies the power and voltage set points for the local controllers of each DER unit. A linear, time-invariant, multivariable, robust, decentralized control system is designed to track the setpoints. Each control agent guarantees fast tracking, zero steady state error, and robust performance despite uncertainties of the microgrid parameters, topology, and the operating point. Existence conditions, control design procedures, eigenanalysis and robust stability analysis of the closed-loop system, and performance of the control strategy based on digital time-domain simulation studies in PSCAD/EMTDC platform, are reported. Performance of the control system is also verified based on hardware-in-the-loop (HIL) studies in the RTDS environment.
Autors: Etemadi, A.H.;Davison, E.J.;Iravani, R.;
Appeared in: IEEE Transactions on Power Systems
Publication date: Nov 2014, volume: 29, issue:6, pages: 3102 - 3113
Publisher: IEEE
 
» A Generalized Rectangular Cavity Approach for Determination of Complex Permittivity of Materials
Abstract:
A novel cavity-based unified approach to measure the complex permittivity of dielectric samples placed in the E-plane of a rectangular cavity is presented. The proposed generalized cavity method is not limited to test specimens of smaller electrical dimensions, and requires two basic steps. The first step modifies the conventional cavity perturbation technique, where the effects of possible air gap between the cavity slot and the test specimen are also considered. The second step of the proposed approach employs a numerical optimization scheme, where the actual 3-D geometry of the fabricated cavity is simulated using the numerical field simulator, the Computer Simulation Technology (CST) Microwave Studio. The dielectric properties of the test specimen in this case are determined with the help of a MATLAB-based optimization routine, which calls the CST modules over the component object model interface and minimizes the error between the measured and the simulated scattering coefficients. The permittivity of the test specimen determined using the first step is provided as the initial guess to improve the convergence of the numerical optimization scheme. The proposed unified approach is validated by designing two rectangular cavities having different slot sizes operating in the mode. A number of standard dielectric samples are measured with the help of a vector network analyzer, and a very good agreement is observed between the measured permittivity values and the published data available in the literature having a typical error of less than 2% for samples of even larger dimensions.
Autors: Jha, A.K.;Akhtar, M.J.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Nov 2014, volume: 63, issue:11, pages: 2632 - 2641
Publisher: IEEE
 
» A Head Impact Detection System Using SVM Classification and Proximity Sensing in an Instrumented Mouthguard
Abstract:
Injury from blunt head impacts causes acute neurological deficits and may lead to chronic neurodegeneration. A head impact detection device can serve both as a research tool for studying head injury mechanisms and a clinical tool for real-time trauma screening. The simplest approach is an acceleration thresholding algorithm, which may falsely detect high-acceleration spurious events such as manual manipulation of the device. We designed a head impact detection system that distinguishes head impacts from nonimpacts through two subsystems. First, we use infrared proximity sensing to determine if the mouthguard is worn on the teeth to filter out all off-teeth events. Second, on-teeth, nonimpact events are rejected using a support vector machine classifier trained on frequency domain features of linear acceleration and rotational velocity. The remaining events are classified as head impacts. In a controlled laboratory evaluation, the present system performed substantially better than a 10-g acceleration threshold in head impact detection (98% sensitivity, 99.99% specificity, 99% accuracy, and 99.98% precision, compared to 92% sensitivity, 58% specificity, 65% accuracy, and 37% precision). Once adapted for field deployment by training and validation with field data, this system has the potential to effectively detect head trauma in sports, military service, and other high-risk activities.
Autors: Wu, L.C.;Zarnescu, L.;Nangia, V.;Cam, B.;Camarillo, D.B.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Nov 2014, volume: 61, issue:11, pages: 2659 - 2668
Publisher: IEEE
 
» A Health-IoT Platform Based on the Integration of Intelligent Packaging, Unobtrusive Bio-Sensor, and Intelligent Medicine Box
Abstract:
In-home healthcare services based on the Internet-of-Things (IoT) have great business potential; however, a comprehensive platform is still missing. In this paper, an intelligent home-based platform, the iHome Health-IoT, is proposed and implemented. In particular, the platform involves an open-platform-based intelligent medicine box (iMedBox) with enhanced connectivity and interchangeability for the integration of devices and services; intelligent pharmaceutical packaging (iMedPack) with communication capability enabled by passive radio-frequency identification (RFID) and actuation capability enabled by functional materials; and a flexible and wearable bio-medical sensor device (Bio-Patch) enabled by the state-of-the-art inkjet printing technology and system-on-chip. The proposed platform seamlessly fuses IoT devices (e.g., wearable sensors and intelligent medicine packages) with in-home healthcare services (e.g., telemedicine) for an improved user experience and service efficiency. The feasibility of the implemented iHome Health-IoT platform has been proven in field trials.
Autors: Yang, G.;Xie, L.;Mantysalo, M.;Zhou, X.;Pang, Z.;Xu, L.D.;Kao-Walter, S.;Chen, Q.;Zheng, L.-R.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Nov 2014, volume: 10, issue:4, pages: 2180 - 2191
Publisher: IEEE
 
» A High-Selectivity Tunable Dual-Band Bandpass Filter Using Stub-Loaded Stepped-Impedance Resonators
Abstract:
A novel varactor tunable dual-band bandpass filter (BPF) using stub-loaded stepped-impedance resonators is proposed in this letter. Compared with the traditional tunable filters, the source-load coupling and T-shape stub-loaded lines are employed in this design. The proposed BPF architecture has the advantages of high selectivity and less control voltages. In the overall tuning range, the proposed filter is designed with 5–6 transmission zeros and more than 30 dB rejection between the two passbands. Meanwhile, only one control voltage is needed for each passband. A prototype of this filter is fabricated and measured. The measurement results show great agreement with simulated results, which show that the first passband can be tuned in a frequency range from 0.8 to 1.02 GHz, and the second passband varies from 2.02 to 2.48 GHz.
Autors: You, B.;Chen, L.;Liang, Y.;Wen, X.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2014, volume: 24, issue:11, pages: 736 - 738
Publisher: IEEE
 
» A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy
Abstract:
In this paper, a 2-D forward discrete cosine transform (FDCT) and inverse DCT (IDCT) core are presented. The proposed DCT core uses a single 1-D transform core and a transpose memory in order to achieve an area-efficient design. By exploiting the even and odd symmetrical properties of the FDCT and IDCT computations, the DCT core can share hardware resources. Furthermore, first-dimensional (1st-D) and second-dimensional (2nd-D) operations can be run simultaneously (1st-D FDCT, 2nd-D FDCT, 1st-D IDCT, 2nd-D IDCT) in the proposed 1-D core by using the proposed time division strategy, which shares hardware resources achieving a high-throughput design. Measurement results show that the DCT core achieves a throughput of 250 MP/s when simultaneously operating FDCT and IDCT, consuming only 19650 logic gates when fabricated using the TSMC 0.18- CMOS process. The DCT core achieves superior hardware efficiency compared to the existing cores.
Autors: Chen, Y.;Jou, R.;Chang, T.;Lu, C.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Nov 2014, volume: 22, issue:11, pages: 2268 - 2277
Publisher: IEEE
 
» A Hybrid Approach for Receiving Antennas: Concepts and Applications
Abstract:
The long-standing problem of constructing an accurate equivalent circuit for receiving antennas by handling both the absorbed and scattered powers for all kinds of antennas, is addressed. By combining the electrical properties of the antenna with its radiating and scattering characteristics, it is shown that the input impedance, radiation pattern and vectorial effective height are three essential parameters to which the open-circuit scattering parameter (new) should be added. The antenna's power budget is then established and applied to various kinds of antennas. Theoretical results showed a perfect agreement with the method of moment (MoM) and the finite integration technique (FIT) over a large frequency-range under various conjugate-matched loads. It comes out that good radiating antennas are good scatterers as well but, without a precise power budget calculation, it is not evident to predict whether an antenna would absorb more or less than it scatters. Thin-metallic structure directive antennas (TMSDA) appear to be the best candidates to absorb more than they scatter under matching conditions. The two-element Yagi antenna can reach an absorption efficiency of 65%, while the pyramidal horn achieves only 12% maximum. The dipole is confirmed at 50%-absorption efficiency.
Autors: Niamien, M.A.C.;Collardey, S.;Mahdjoubi, K.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2014, volume: 62, issue:11, pages: 5462 - 5473
Publisher: IEEE
 
» A Hybrid FMCW-Interferometry Radar for Indoor Precise Positioning and Versatile Life Activity Monitoring
Abstract:
This paper presents a hybrid radar system that incorporates a linear frequency-modulated continuous-wave (FMCW) mode and an interferometry mode for indoor human localization and life activity monitoring applications. The unique operating principle and signal processing method allow the radar to work at two different modes for different purposes. The FMCW mode is responsible for range detection while the interferometry mode is responsible for life activities (respiration, heart beat, body motion, and gesture) monitoring. Such cooperation is built on each mode's own strength. Beam scanning is employed to determine azimuth information, which enables the system to plot 360 2-D maps on which the room layout and objects' location can be clearly identified. Additionally, the transmitted chirp signal is coherent in phase, which is very sensitive to physiological motion and allows the proposed technique to distinguish human from nearby stationary clutters even when the human subjects are sitting still. Hence, the proposed radar is able to continuously track the location of individuals and monitor their life activities regardless of the complex indoor environment. A series of experiments have been carried out to demonstrate the proposed versatile life activity monitoring system.
Autors: Wang, G.;Gu, C.;Inoue, T.;Li, C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2014, volume: 62, issue:11, pages: 2812 - 2822
Publisher: IEEE
 
» A Hybrid Metaheuristic Optimization Algorithm for Strategic Planning of 4D Aircraft Trajectories at the Continental Scale
Abstract:
Global air-traffic demand is continuously increasing. To handle such a tremendous traffic volume while maintaining at least the same level of safety, a more efficient strategic trajectory planning is necessary. In this work, we present a strategic trajectory planning methodology which aims to minimize interaction between aircraft at the European-continent scale. In addition, we propose a preliminary study that takes into account uncertainties of aircraft positions in the horizontal plane. The proposed methodology separates aircraft by modifying their trajectories and departure times. This route/departure-time assignment problem is modeled as a mixed-integer optimization problem. Due to the very high combinatorics involved in the continent-scale context (involving more than 30,000 flights), we develop and implement a hybrid-metaheuristic optimization algorithm. In addition, we present a computationally-efficient interaction detection method for large trajectory sets. The proposed methodology is successfully implemented and tested on a full-day simulated air traffic over the European airspace, yielding to an interaction-free trajectory plan.
Autors: Chaimatanan, S.;Delahaye, D.;Mongeau, M.;
Appeared in: IEEE Computational Intelligence Magazine
Publication date: Nov 2014, volume: 9, issue:4, pages: 46 - 61
Publisher: IEEE
 
» A Hybrid Particle-Swarm Tabu Search Algorithm for Solving Job Shop Scheduling Problems
Abstract:
This paper proposes a method for the job shop scheduling problem (JSSP) based on the hybrid metaheuristic method. This method makes use of the merits of an improved particle swarm optimization (PSO) and a tabu search (TS) algorithm. In this work, based on scanning a valuable region thoroughly, a balance strategy is introduced into the PSO for enhancing its exploration ability. Then, the improved PSO could provide diverse and elite initial solutions to the TS for making a better search in the global space. We also present a new local search strategy for obtaining better results in JSSP. A real-integer encode and decode scheme for associating a solution in continuous space to a discrete schedule solution is designed for the improved PSO and the tabu algorithm to directly apply their solutions for intensifying the search of better solutions. Experimental comparisons with several traditional metaheuristic methods demonstrate the effectiveness of the proposed PSO–TS algorithm.
Autors: Gao, H.;Kwong, S.;Fan, B.;Wang, R.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Nov 2014, volume: 10, issue:4, pages: 2044 - 2054
Publisher: IEEE
 
» A Ka-Band Reflectarray Antenna Integrated With Solar Cells
Abstract:
A Ka-band reflectarray antenna integrated with solar cells has been designed, manufactured and tested. The electromagnetic characteristics of solar cells as antenna substrates have been studied and measured. The simulation and measurement results of a reflectarray antenna prototype show good radiation characteristics with measured gain of 26.3 dBi and 1-dB gain bandwidth of 8.75%, while having an optical blockage of 17.6% on solar energy. The proposed technique integrates the two largest components on a satellite platform – solar cells and high gain antennas into one, significantly reducing the volume, mass and cost of satellites.
Autors: An, W.;Xu, S.;Yang, F.;Gao, J.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Nov 2014, volume: 62, issue:11, pages: 5539 - 5546
Publisher: IEEE
 
» A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF–10 nF Capacitive Load
Abstract:
A Weighted Current Feedback (WCF) technique for output capacitorless low-dropout (OCL-LDO) regulator is presented in this paper. Through feedback of a weighted current, the WCF permits smart management of the output impedance as well as the gain from the inter-gain stage. Based on the Routh–Hurwitz stability criterion, the WCF can avoid the right-half plane (RHP) pole and push the left-half plane (LHP) non-dominant complex pole pair to a higher frequency. Besides, it provides good regulator loop gain and fast transient response. Validated by UMC 65 nm CMOS process, the simulation and measurement results have shown that the WCF LDO regulator can operate at a load capacitance ( ) range from 470 pF to 10 nF with only 3.8 pF compensation capacitor. At a supply of 0.75 V and a quiescent current of 15.9 µA, the proposed circuit can support a maximum load current of 50 mA. When switches from 0 to 50 mA in 100 ns, the output can settle within 400 ns for the whole range. For a case of single capacitor ( 470 pF), the settling time is only 250 ns. The comparison results have shown that the WCF LDO regulator offers a comparable or better transient figure-of-merit (FOM) and additional merit to drive wide load capacitance range.
Autors: Tan, X.L.;Chong, S.S.;Chan, P.K.;Dasgupta, U.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2014, volume: 49, issue:11, pages: 2658 - 2672
Publisher: IEEE
 
» A Low Energy and High Performance Adder
Abstract:
A novel Dual Mode Square adder is proposed. The adder achieves low energy, high performance and small area by combining two independent techniques recently proposed by the authors: dual-mode logic (DML) and dual-mode addition (DMADD). DML is a special gate topology that allows on-the-fly adaptation of the gates to real time system requirements, and also shows a wide energy-performance tradeoff. DMADD is probability based circuit architecture with a wide energy-performance tradeoff; however its utilization in a pipelined processor requires multi-cycle operation in some cases. We show how DML circuits avoid this requirement, and thus make it possible to transparently plug-in the adder and derive full benefits from the DMADD. Previous work showed that the DMADD can lead to energy savings of up to 50% at the same clock cycle, compared to conventional CMOS solutions. Simulation results in a 40 nm standard process shows that the proposed approach achieves additional energy savings of 27% to 36% for 64-bit and 32-bit adders, respectively, compared to DMADD.
Autors: Levi, I.;Albeck, A.;Fish, A.;Wimer, S.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2014, volume: 61, issue:11, pages: 3175 - 3183
Publisher: IEEE
 
» A Low Transmission Overhead Framework of Mobile Visual Search Based on Vocabulary Decomposition
Abstract:
Due to the bandwidth limitation in wireless networks, transmission overhead is a big problem in Mobile Visual Search (MVS). Existing work proposes transmitting the compressed local feature descriptors instead of the query image to reduce the transmission overhead. Although many kinds of compressed descriptors are proposed, designing a suitable lossless compressed descriptor has proven elusive. In this paper, we propose a novel framework for MVS with low transmission overhead rather than focusing on compressed descriptors. The key point of the proposed framework is to migrate the vector quantization in the bag of visual words model from the server to the client. In this framework, no matter what descriptors are used, the client only transmits the ID numbers of the visual words to the server, thereby reaching the minimal possible transmission overhead. To achieve this goal, we present vocabulary decomposition by which we can decompose the large vocabulary into several small ones satisfying storage constraints on mobile devices. In this paper, we first formulate vocabulary decomposition as an optimization problem. We then present Joint Product Quantization (JPQ) and Joint Optimized Product Quantization (JOPQ) to address the proposed optimization problem. Finally , we conduct a large number of simulation experiments and real experiments. The experimental results show that the proposed framework outperforms the existing framework by reducing more than 95% of the transmission overhead.
Autors: Qi, H.;Stojmenovic, M.;Li, K.;Li, Z.;Qu, W.;
Appeared in: IEEE Transactions on Multimedia
Publication date: Nov 2014, volume: 16, issue:7, pages: 1963 - 1972
Publisher: IEEE
 
» A Low-Cost Field-Programmable Pin-Constrained Digital Microfluidic Biochip
Abstract:
This paper introduces a field-programmable pin-constrained digital microfluidic biochip (FPPC-DMFB), which offers general-purpose assay execution at a lower cost than general-purpose direct addressing DMFBs and highly optimized application-specific pin-constrained DMFBs. One of the key cost drivers for DMFBs is the number of printed circuit board (PCB) layers, onto which the device is mounted. We demonstrate a scalable single-layer PCB wiring scheme for several FPPC-DMFB variations, for PCB technology with orthogonal routing capacity of at least three; for PCB technology with orthogonal capacity of two, more PCB layers are required, but the FPPC-DMFB retains its cost advantage. These results offer new insights on the relationship between PCB layer count, pin count, and cost. Additionally, to reduce the execution time of assays on the FPPC-DMFB, we present efficient algorithms for droplet routing, with and without contamination removal via wash droplets.
Autors: Grissom, D.T.;McDaniel, J.;Brisk, P.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Nov 2014, volume: 33, issue:11, pages: 1657 - 1670
Publisher: IEEE
 
» A Low-Power Wearable Dual-Band Wireless Body Area Network System: Development and Experimental Evaluation
Abstract:
Wireless body area network (WBAN) applications benefit extensively from the advantages offered by unique features of ultra-wideband (UWB) wireless communication, such as high data rate, low power consumption, and simple transmitter design. A major disadvantage in using UWB for WBAN applications is the complexities introduced by UWB receivers, such as high power consumption, poor receiver performance due to low sensitivity, and complex hardware implementation. This paper presents hardware implementation of a new communication system, where UWB is used for high data-rate transmission from sensor nodes and a 433-MHz industrial, scientific, and medical (ISM) band receiver is used for receiving low data-rate control messages at the sensor nodes. A full network system for WBAN applications has been implemented including a unique medium access control protocol. The proposed WBAN system is designed to dynamically control the pulses per bit value used for the UWB data communication using control messages received via the narrowband feedback link (i.e., the 433-MHz ISM link). This leads to dynamic bit error rate (BER) and power control at the sensor nodes, which improves the reliability of communication and power efficiency of sensor nodes under dynamic channel conditions. The performance of the system is evaluated in terms of BER, sensor initialization delay, and power consumption. This novel dual-band architecture utilizes the unique advantages offered by UWB communication and narrowband technology to enable high data rate, low-complexity hardware design, low power consumption, and small form factor for WBAN sensor systems.
Autors: Thotahewa, K.M.S.;Redoute, J.-M.;Yuce, M.R.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2014, volume: 62, issue:11, pages: 2802 - 2811
Publisher: IEEE
 

Publication archives by date

  2017:   January     February     March     April     May     June     July     August     September     October     November     December    

  2016:   January     February     March     April     May     June     July     August     September     October     November     December    

  2015:   January     February     March     April     May     June     July     August     September     October     November     December    

  2014:   January     February     March     April     May     June     July     August     September     October     November     December    

  2013:   January     February     March     April     May     June     July     August     September     October     November     December    

  2012:   January     February     March     April     May     June     July     August     September     October     November     December    

  2011:   January     February     March     April     May     June     July     August     September     October     November     December    

  2010:   January     February     March     April     May     June     July     August     September     October     November     December    

  2009:   January     February     March     April     May     June     July     August     September     October     November     December    

 
0-C     D-L     M-R     S-Z