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Electrical and Electronics Engineering publications abstract of: 11-2012 sorted by title, page: 0
» (110) and (100) Sidewall-oriented FinFETs: A performance and reliability investigation
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Highlights

Appeared in: Solid-State Electronics
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 0.5V bulk-driven analog building blocks
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Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 0.8V PLL-based automatic frequency tuning system for current-mode filters
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Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 1-D electro-optic beam steering device
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Appeared in: Sensors and Actuators A: Physical
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 1-W 3.3–16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller
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This paper presents SD-card-size wireless power transfer system for large-volume contactless memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the dc–dc converter or charge-pump circuit for data write operation into the flash memory chip. The proposed approach reduces the number of components and BOM cost and improves the total power efficiency. A vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18- m-CMOS with high voltage option. Voltage boost from 3.3 to 16.3 V and 1-W power transfer with 50% total efficiency have been successfully demonstrated, and the response time for the power control loop is shorter than 35 .
Autors: Tomita, K.;Shinoda, R.;Kuroda, T.;Ishikuro, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2576 - 2585
Publisher: IEEE
 
» 100 dB A-Weighted SNR Microphone Preamplifier With On-Chip Decoupling Capacitors
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This paper presents the design and realization of a gain-programmable microphone audio preamplifier that does not need external input-decoupling capacitors. Three possible preamplifier implementations with on-chip decoupling capacitors have been presented and compared in terms of audio quality performance, power consumption, and silicon area occupation. The chosen solution has been integrated in a 40-nm digital CMOS process with seven metal layers and a double gate-oxide option. Process fringe capacitors have been used to implement the internal decoupling, amplifying, and dc biasing functions. The active area is 0.19 mm , whereas the power consumption is 330 W at a 1.5-V power supply. Measured dynamic range (DR) and maximum signal-to-noise-and-distortion ratio (SNDR) of approximately 105 dB A-weighted and 101 dB A-weighted, respectively, have been achieved for 0-dB gain and balanced inputs. The preamplifier can process both balanced and single-ended inputs, and its gain can be programmed from 0 to 19.5 dB in 1.5-dB/steps with acceptable performance losses.
Autors: Barbieri, A.;Nicollini, G.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2737 - 2750
Publisher: IEEE
 
» 100 dB A-Weighted SNR Microphone Preamplifier With On-Chip Decoupling Capacitors
Abstract:
This paper presents the design and realization of a gain-programmable microphone audio preamplifier that does not need external input-decoupling capacitors. Three possible preamplifier implementations with on-chip decoupling capacitors have been presented and compared in terms of audio quality performance, power consumption, and silicon area occupation. The chosen solution has been integrated in a 40-nm digital CMOS process with seven metal layers and a double gate-oxide option. Process fringe capacitors have been used to implement the internal decoupling, amplifying, and dc biasing functions. The active area is 0.19 mm , whereas the power consumption is 330 W at a 1.5-V power supply. Measured dynamic range (DR) and maximum signal-to-noise-and-distortion ratio (SNDR) of approximately 105 dB A-weighted and 101 dB A-weighted, respectively, have been achieved for 0-dB gain and balanced inputs. The preamplifier can process both balanced and single-ended inputs, and its gain can be programmed from 0 to 19.5 dB in 1.5-dB/steps with acceptable performance losses.
Autors: Barbieri, A.;Nicollini, G.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2737 - 2750
Publisher: IEEE
 
» 16-Term Error Model in Reciprocal Systems
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By taking reciprocity of the error network into account, full and accurate calibration of a 16-term error model can be performed using only four two-port calibration standards or termination pairs. Moreover, there is no need for a nonsymmetrical calibration standard that is strictly required in a more conventional five-standard calibration. Commercially available standard substrates can thus be used. Detailed theory of the reciprocal 16-term error model and a new calibration method are presented. Reciprocity assumption is valid in on-wafer and other measurements when two-tier calibration is applied. However, the calibration scheme allows measurement of nonreciprocal devices too. The usefulness of the new method is confirmed by practical wideband on-wafer measurements.
Autors: Silvonen, K.;Dahlberg, K.;Kiuru, T.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2012, volume: 60, issue:11, pages: 3551 - 3558
Publisher: IEEE
 
» 180 and 90 Reflection-Type Phase Shifters Using Over-Coupled Lange Couplers
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Reflection-type phase shifters (RTPSs) of 180 and 90 using over-coupled Lange couplers to obtain multioctave bandwidth are presented. A thorough theoretical analysis of the effect of coupler parameters on the RTPS performance is provided. The impact of coupler parameters on the RTPS performance is further illustrated with vector plots. Each measured phase shifter is comprised of an over-coupled Lange coupler, two low-loss single-pole double-throw switches, and two pairs of LC reflection loads on a Rogers RO4003C substrate with a thickness of 0.8 mm (32 mil) and 1.5 mm (60 mil). By using the 1.5-mm substrate, the coupling can be increased. Phase shifts of 90 and 180 using Lange couplers with 2–3-dB coupling in steps of 0.2 dB are designed, fabricated, and measured. The experimental results show that an over-coupling of 2.2 dB is able to obtain a return loss larger than 10 dB over a 127% bandwidth from 550 to 2450 MHz for all states. Worst case measured insertion loss and phase error on the 0.8-mm substrate with an over-coupling of 2.8 dB is dB and , respectively, for both 180 and 90 phase states. On the 1.5-mm substrate with an over-coupling of 2.4 dB, they are dB and ${pm}{- box{16}}^{circ}$, respectively, for both phase states.
Autors: Fang, H. R.;Tang, X.;Mouthaan, K.;Guinvarc'h, R.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2012, volume: 60, issue:11, pages: 3440 - 3448
Publisher: IEEE
 
» 2 MeV electron irradiation effects on the electrical characteristics of metal-oxide-silicon capacitors with atomic layer deposited Al2O3, HfO2 and nanolaminated dielectrics
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Appeared in: Solid-State Electronics
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 2-Axis Magnetometers Based on Full Wheatstone Bridges Incorporating Magnetic Tunnel Junctions Connected in Series
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Full Wheatstone Bridge incorporating a serially connected ensemble of Magnetic tunnel junctions was produced, targeting an application as a magnetic field compass. To that end, MTJs with , –200%, and were produced. In order to achieve a full bridge signal, two stacks with an asymmetric SAF reference structure where used to produce MTJs with opposite dR/dH upon annealing in the same substrate. The resulting Bridges exhibit sensitivities between 13.5–32 mV/V/Oe depending on the field range and provide a significantly advantageous alternative to AMR and GMR based bridges.
Autors: Ferreira, R.;Paz, E.;Freitas, P. P.;Ribeiro, J.;Germano, J.;Sousa, L.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2012, volume: 48, issue:11, pages: 4107 - 4110
Publisher: IEEE
 
» 2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors
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This paper describes an all-digital PVT-variation tolerant true-random number generator (TRNG), fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die entropy generation in high-performance microprocessors. The TRNG harvests differential thermal-noise at the diffusion nodes of a pre-charged cross-coupled inverter pair to resolve out of metastability, generating one random bit/cycle. A self-calibrating 2-step tuning mechanism using coarse-grained configurable inverters and fine-grained programmable clock delay generators, along with an entropy-tracking feedback loop provide tolerance to 20% PVT variation-induced device mismatches, enabling lowest-reported energy-consumption of 2.9 pJ/bit with a dense layout occupying 4004 µm , while achieving: (i) 2.4 Gbps random bit throughput, 7 mW total power consumption with 0.7 mW leakage power component, measured at 1.1 V, 50 C, (ii) random bitstreams that passes all NIST RNG tests with raw entropy/bit measured up to 0.9999999993, (iii) good distribution of 1's with 4-bit entropy of 3.97996 and high-entropy pattern probability of 0.066 (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 14 Mbps, 5.6 µW, measured at 280 mV, 50 C, (v) 12 fine-grained high-entropy settings for the TRNG to dither in during steady-state operation, (vi) 3% error while using an analytical ergodic Markov chain model for predicting pattern probabilities and (vii) 200x higher throughput and 9x higher energy-efficiency than previously reported implementations. Design modifications for robust operation in 22 nm high-volume manufacturing in the presence of 3$sigma$ process variations demonstrate scalability of the all-digital design to future technologies.
Autors: Mathew, S. K.;Srinivasan, S.;Anders, M. A.;Kaul, H.;Hsu, S. K.;Sheikh, F.;Agarwal, A.;Satpathy, S.;Krishnamurthy, R. K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2807 - 2821
Publisher: IEEE
 
» 2012 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology (IEEE CIBCB 2012) [Conference Reports]
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Autors: Jin, Y.;
Appeared in: IEEE Computational Intelligence Magazine
Publication date: Nov 2012, volume: 7, issue:4, pages: 17 - 17
Publisher: IEEE
 
» 2012 list of reviewers for Automatica
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Appeared in: Automatica
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 2012 Zucker Design Contest Winners [Education Department News]
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Autors: Sottile, J.;
Appeared in: IEEE Industry Applications Magazine
Publication date: Nov 2012, volume: 18, issue:6, pages: 85 - 86
Publisher: IEEE
 
» 2013 IEEE CIS Awards [Society Briefs]
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Autors: Alippi, C.;
Appeared in: IEEE Computational Intelligence Magazine
Publication date: Nov 2012, volume: 7, issue:4, pages: 4 - 9
Publisher: IEEE
 
» 21-kV SiC BJTs With Space-Modulated Junction Termination Extension
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We report here 20-kV-class small-area (0.035 ) 4H-SiC bipolar junction transistors. We implemented edge termination techniques featuring two-zone junction termination extension and space-modulated rings. on-state characteristics showed a current gain of 63 and a specific on-resistance of 321 , which is slightly below the SiC unipolar limit. We achieved the open-base blocking voltage of 21 kV at a leakage current of 0.1 , which is the highest blocking voltage among any semiconductor switching devices.
Autors: Miyake, H.;Okuda, T.;Niwa, H.;Kimoto, T.;Suda, J.;
Appeared in: IEEE Electron Device Letters
Publication date: Nov 2012, volume: 33, issue:11, pages: 1598 - 1600
Publisher: IEEE
 
» 3-D Analytical Modeling of No-Load Magnetic Field of Ironless Axial Flux Permanent Magnet Machine
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A three-dimensional analytical modeling of the magnetic field of the stator-ironless axial flux permanent magnet (AFPM) machine under open-circuit condition is presented in this paper. It involves the analytical solution of the governing field equations in the region between back-irons in the cylindrical coordinate, in which the magnets are assumed to be axially magnetized and have constant relative recoil permeability. The proposed modeling method is applied to a specific AFPM machine, and the analytical results are in good agreement with those of three-dimensional finite element analysis (FEA).
Autors: Huang, Y.;Ge, B.;Dong, J.;Lin, H.;Zhu, J.;Guo, Y.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2012, volume: 48, issue:11, pages: 2929 - 2932
Publisher: IEEE
 
» 3-D Architectural Approach for Manipulation of the Micromagnetic Configuration in Nanodisks
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We report on novel method of manipulation of the micromagnetic configuration realized in 3-D nanostructures “small disk on the big disk”. Our method allows to control vortex chirality in a submicrometer magnetic disk without use of its deformation or defects of shape. Manipulation is performed by means of the fabrication on the top of disk a smaller disk with a diameter 200 nm. This paper shows that it is possible to explicitly set the magnetization direction of the small disk. Thus, the proposed system has four stable magnetic configurations that are uniquely specified by the direction of an external magnetic field.
Autors: Stebliy, M. E.;Ognev, A. V.;Samardak, A. S.;Diga, K. S.;Chebotkevich, L. A.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2012, volume: 48, issue:11, pages: 4406 - 4408
Publisher: IEEE
 
» 3-D modeling and analysis of meander-line-coil surface wave EMATs
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Appeared in: Mechatronics
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 3-D Simulator of Laser Crystallization for Polycrystalline-Silicon Thin-Film Transistors
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A 3-D simulator of laser crystallization for polycrystalline-silicon thin-film transistors has been developed. Random nucleation, crystal growth velocity, latent heat emission, and partial crystallization are modeled, and a 2-D algorithm is extended to a 3-D algorithm. The -Czochralski technique is analyzed using the 3-D simulator, and it is found that the grain size becomes large when the initial temperature is high after the laser irradiation.
Autors: Matsuki, K.;Kimura, M.;Ishihara, R.;
Appeared in: IEEE Transactions on Semiconductor Manufacturing
Publication date: Nov 2012, volume: 25, issue:4, pages: 650 - 656
Publisher: IEEE
 
» 3-D Volume Reconstruction of Skin Lesions for Melanin and Blood Volume Estimation and Lesion Severity Analysis
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Subsurface information about skin lesions, such as the blood volume beneath the lesion, is important for the analysis of lesion severity towards early detection of skin cancer such as malignant melanoma. Depth information can be obtained from diffuse reflectance based multispectral transillumination images of the skin. An inverse volume reconstruction method is presented which uses a genetic algorithm optimization procedure with a novel population initialization routine and nudge operator based on the multispectral images to reconstruct the melanin and blood layer volume components. Forward model evaluation for fitness calculation is performed using a parallel processing voxel-based Monte Carlo simulation of light in skin. Reconstruction results for simulated lesions show excellent volume accuracy. Preliminary validation is also done using a set of 14 clinical lesions, categorized into lesion severity by an expert dermatologist. Using two features, the average blood layer thickness and the ratio of blood volume to total lesion volume, the lesions can be classified into mild and moderate/severe classes with 100% accuracy. The method therefore has excellent potential for detection and analysis of pre- malignant lesions.Pub /_nolinebreak
Autors: D'Alessandro, B.;Dhawan, A. P.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Nov 2012, volume: 31, issue:11, pages: 2083 - 2092
Publisher: IEEE
 
» 35th ERF: Progress in Rotorcraft Research
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Appeared in: Aerospace Science and Technology
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 3D modified unitary matrix pencil method with automatic grouping of unknown parameters of far field signals
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Appeared in: Digital Signal Processing
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 3D numerical model of the electrostatic coating process with moving objects using a moving mesh
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Appeared in: Journal of Electrostatics
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 3D Steerable Wavelets in Practice
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We introduce a systematic and practical design for steerable wavelet frames in 3D. Our steerable wavelets are obtained by applying a 3D version of the generalized Riesz transform to a primary isotropic wavelet frame. The novel transform is self-reversible (tight frame) and its elementary constituents (Riesz wavelets) can be efficiently rotated in any 3D direction by forming appropriate linear combinations. Moreover, the basis functions at a given location can be linearly combined to design custom (and adaptive) steerable wavelets. The features of the proposed method are illustrated with the processing and analysis of 3D biomedical data. In particular, we show how those wavelets can be used to characterize directional patterns and to detect edges by means of a 3D monogenic analysis. We also propose a new inverse-problem formalism along with an optimization algorithm for reconstructing 3D images from a sparse set of wavelet-domain edges. The scheme results in high-quality image reconstructions which demonstrate the feature-reduction ability of the steerable wavelets as well as their potential for solving inverse problems.
Autors: Chenouard, N.;Unser, M.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Nov 2012, volume: 21, issue:11, pages: 4522 - 4533
Publisher: IEEE
 
» 3D thermal-aware floorplanner using a MILP approximation
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Appeared in: Microprocessors and Microsystems
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 4-D Reconstruction for Dynamic Fluorescence Diffuse Optical Tomography
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Dynamic fluorescence diffuse optical tomography (FDOT) is important for the research of drug delivery, medical diagnosis, and treatment. Conventionally, dynamic tomographic images are reconstructed frame-by-frame, independently. This approach fails to account for the temporal correlations in measurement data. Ideally, the entire image sequence should be considered as a whole and a 4-D reconstruction should be performed. However, the fully 4-D reconstruction is computationally intensive. In this paper, we propose a new 4-D reconstruction approach for dynamic FDOT, which is achieved by applying a temporal Karhunen–Loève (KL) transformation to the imaging equation. By taking advantage of the decorrelation and compression properties of the KL transformation, the complex 4-D optical reconstruction problem is greatly simplified. To evaluate the performance of the method, simulation, phantom, and in vivo experiments are performed on a hybrid FDOT/X-ray computed tomography imaging system. The experimental results indicate that the reconstruction images obtained by the KL method provide good reconstruction quality. Additionally, by discarding high-order KL components, the computation time involved with fully 4-D reconstruction can be greatly reduced in contrast to the conventional frame-by-frame reconstruction.
Autors: Liu, X.;Zhang, B.;Luo, J.;Bai, J.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Nov 2012, volume: 31, issue:11, pages: 2120 - 2132
Publisher: IEEE
 
» 4H–SiC Metal–Semiconductor–Metal Ultraviolet Photodetectors in Operation of 450
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This work demonstrates the high-temperature operation of metal–semiconductor–metal (MSM) photodetectors (PDs) up to 450 using lightly Al-doped epitaxial 4H–SiC thin films. The responsivity of the PDs under 325-nm illumination is 0.0305 A/W at 20-V bias at room temperature. The photocurrent-to-dark-current ratio of the SiC MSM PDs is as high as at 25 and is 0.62 at 450 . The rise/fall time of the PDs is increased slightly from to as the temperature increases from room temperature to 400 . These results support the use of 4H–SiC PDs in extremely high temperature applications.
Autors: Lien, W.-C.;Tsai, D.-S.;Lien, D.-H.;Senesky, D. G.;He, J.-H.;Pisano, A. P.;
Appeared in: IEEE Electron Device Letters
Publication date: Nov 2012, volume: 33, issue:11, pages: 1586 - 1588
Publisher: IEEE
 
» 5-11GHz CMOS PA with 158.941ps group delay and low power using current-reused technique
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Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 56nm pitch Cu Dual-Damascene Interconnects with Self-Aligned Via using Negative-Tone Development lithography-etch-lithography-etch Patterning Scheme
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Appeared in: Microelectronic Engineering
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 5R 2dof parallel kinematic manipulator - A multidisciplinary test case in mechatronics
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Appeared in: Mechatronics
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 6-DoF miniature maglev positioning stage for application in haptic micro-manipulation
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Appeared in: Mechatronics
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» 60-GHz transmit/receive switch using a p-n diode and MOS transistors in 130-nm CMOS
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Appeared in: Solid-State Electronics
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» Noise in 45-nm RESET-State Phase-Change Memory Devices: Characterization, Impact on Memory Readout Operation, and Scaling Perspectives
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In this letter, we study the low-frequency noise behavior of RESET-state Phase-Change Memory (PCM) devices belonging to a 45-nm technology node. Furthermore, by dealing with a typical case study, we calculate the fluctuation of the cell readout current induced by noise and provide predictions for estimating its effect in RESET-state PCM of future technology nodes.
Autors: Betti Beneventi, G.;Ferro, M.;Fantini, P.;
Appeared in: IEEE Electron Device Letters
Publication date: Nov 2012, volume: 33, issue:11, pages: 1559 - 1561
Publisher: IEEE
 
» -Gated Silicon and Strained Silicon Nanowire Array Tunneling FETs
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This letter presents experimental results on tunneling field-effect transistors featuring arrays of -gated uniaxially strained and unstrained silicon nanowires. The gate control of a gate stack is compared with a high- /metal gate stack. Steep inverse subthreshold slopes down to 76 mV/dec and relatively high on -currents were achieved with the combination of high- /metal gate and strained silicon nanowires. We observed negative differential conductance in the output characteristics, which we attribute to hot-carrier effects in the strong electric fields at the reverse-biased tunnel junction.
Autors: Richter, S.;Sandow, C.;Nichau, A.;Trellenkamp, S.;Schmidt, M.;Luptak, R.;Bourdelle, K. K.;Zhao, Q. T.;Mantl, S.;
Appeared in: IEEE Electron Device Letters
Publication date: Nov 2012, volume: 33, issue:11, pages: 1535 - 1537
Publisher: IEEE
 
» ????Enhanced Encoding with Improved Fuzzy Decision Tree Testing Using CASP Templates
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A novel protein model assessment technique using an improved fuzzy decision tree was tested using CASP8 and CASP9 templates. The testing was conducted in three phases. In the first two phases, templates were classified without explicit scoring. In phase three, a new scoring method was created for performance evaluation. The new protein model assessment technique was compared with several common prominent model assessment techniques for CASP competitions. The performance was analyzed based on correlation between our scores and GDT_TS scores of the templates. Finally, it is concluded that although the novel protein model assessment technique resulted in reduced correlation when compared to best competitors in CASP, its uniqueness in using the improved fuzzy decision tree and a single model stands as a new paradigm in the protein model assessment field.
Autors: Chida, A.;Zhang, Y.-Q.;Harrison, R.;
Appeared in: IEEE Computational Intelligence Magazine
Publication date: Nov 2012, volume: 7, issue:4, pages: 55 - 60
Publisher: IEEE
 
» A 0.5-V R-MOSFET-C Filter Design Using Subthreshold R-MOSFET Resistors and OTAs With Cross-Forward Common-Mode Cancellation Technique
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A 0.5-V fully integrated R-MOSFET-C filter with low power, good linearity, and wide frequency tunability is demonstrated. It relies upon the operational transconductance amplifier using the cross-forward common-mode cancellation and the linear sub-threshold R-MOSFET resistor—both employ subthreshold operation of the transistors. A fifth-order Chebyshev low-pass filter using regular transistors with a 0.5-V threshold voltage in a 0.18- triple-well CMOS process is implemented for a 0.5-V supply. The filter's bandwidth can be tuned from 91 to 268 kHz, which is almost a 3-to-1 tuning ratio. At a nominal bandwidth of 135 kHz automatically set by the on-chip PLL circuit, the dynamic range is at 61.0 dB for 1% total harmonic distortion, while the spurious-free dynamic range under two-tone signals is at 53.7 dB. The total current and power consumptions including bias circuits are 1.2 mA and 0.6 mW, respectively.
Autors: Khumsat, P.;Worapishet, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2751 - 2762
Publisher: IEEE
 
» A 0.7V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35?m CMOS technology
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Appeared in: Microelectronics Journal
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications
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This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-µm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 µW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm .
Autors: Huang, G.-Y.;Chang, S.-J.;Liu, C.-C.;Lin, Y.-Z.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2783 - 2795
Publisher: IEEE
 
» A 1.2-V 5.2-mW 20–30-GHz Wideband Receiver Front-End in 0.18- CMOS
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This paper presents a low-power wideband receiver front-end design using a resonator coupling technique. Inductively coupled resonators, composed of an on-chip transformer and parasitic capacitances from a low-noise amplifier, a mixer, and the transformer itself, not only provide wideband signal transfer, but also realize wideband high-to-low impedance transformation. The coupled resonators also function as a wideband balun to give single-to-differential conversion. Analytic expressions for the coupled resonators with asymmetric loads are presented for design guidelines. The proposed receiver front-end only needs a few passive components so that gain degradation caused by the passive loss is minimized. Hence, power consumption and chip area can be greatly reduced. The chip is implemented in 0.18- CMOS technology. The experimental result shows that the bandwidth can span from 20 to 30 GHz with a peak conversion gain of 18.7 dB. The measured input return loss and third-order intercept point are better than 16.7 dB and , respectively, over the bandwidth. The minimum noise figure is 7.1 dB. The power consumption is only 5.2 mW from a 1.2-V supply. The chip area is only 0.18 .
Autors: Li, C.-H.;Kuo, C.-N.;Kuo, M.-C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2012, volume: 60, issue:11, pages: 3502 - 3512
Publisher: IEEE
 
» A 10-b Ternary SAR ADC With Quantization Time Information Utilization
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The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC) with quantization time information utilization is proposed. The TSAR examines the transient information of a typical dynamic SAR voltage comparator to provide accuracy, speed, and power benefits. Full half-bit redundancy is shown, allowing for residue shaping which provides an additional 6 dB of signal-to-quantization-noise ratio (SQNR). Synchronous quantizer speed enhancements allow for a shorter worst case conversion time. An increased monotonicity switching algorithm, stage skipping due to reference grouping, and SAR logic modifications minimize overall dynamic energy. The architecture has been shown to reduce capacitor array switching power consumption and digital-to-analog converter (DAC) driver power by about 60% in a mismatch limited SAR, reduce comparator activity by about 20%, and require only 8.03 average comparisons and 6.53 average DAC movements for a 10-b ADC output word. A prototype is fabricated in 0.13- m CMOS employing on-chip statistical time reference calibration, supply variability from 0.8 to 1.2 V, and small input signal power scaling. The chip consumes 84 W at 8 MHz with an effective number of bits of 9.3 for a figure of merit of 16.9 fJ/C-S for the 10-b prototype and 10.0 fJ/C-S for a 12-b enhanced prototype chip.
Autors: Guerber, J.;Venkatram, H.;Gande, M.;Waters, A.;Moon, U.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2604 - 2613
Publisher: IEEE
 
» A 10GHz wideband VCO with low KVCO variation
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Appeared in: Microelectronics Journal
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A 12.5Gb/s 6.6mW receiver with analog equalizer and 1-tap DFE
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Appeared in: Microelectronics Journal
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A 15fJ/conversion-step 8-bit 50MS/s asynchronous SAR ADC with efficient charge recycling technique
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Appeared in: Microelectronics Journal
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A 190- zero-IF GFSK Demodulator With a 4-b Phase-Domain ADC
Abstract:
This paper presents a zero-IF Gaussian frequency-shift keying (GFSK) demodulator based on a phase-domain analog-to-digital converter (Ph-ADC) which directly quantizes the phase information of the received complex baseband signal. The Ph-ADC linearly combines the in-phase and quadrature parts of the incoming signal, and the generated phase-shifted versions are fed to comparators to detect the zero-crossings and build a 4-b digital representation of the signal phase. Seeking for a low-area and low-power consumption realization, our proposal employs a resistor-less scheme which performs phase rotations in current domain. Together with the Ph-ADC, the fully integrated GFSK demodulator also includes a channel-filtering programmable gain amplifier and a symbol decision block. Altogether, the demodulator occupies 0.14 in a 0.13- CMOS technology with a total power consumption of 190 from a 1-V supply. For a data rate of 1 Mbps and 0.5 modulation depth, the GFSK demodulator requires an of 14.8 dB for a bit error rate of 0.1% considering a flicker noise corner of 150 kHz, obtains a dynamic range of 74 dB, and is able to tolerate carrier frequency offsets of 170 kHz. This performance safely complies with the requirements of the Bluetooth Low Energy (BLE) standard.
Autors: Masuch, J.;Delgado-Restituto, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2796 - 2806
Publisher: IEEE
 
» A 190- zero-IF GFSK Demodulator With a 4-b Phase-Domain ADC
Abstract:
This paper presents a zero-IF Gaussian frequency-shift keying (GFSK) demodulator based on a phase-domain analog-to-digital converter (Ph-ADC) which directly quantizes the phase information of the received complex baseband signal. The Ph-ADC linearly combines the in-phase and quadrature parts of the incoming signal, and the generated phase-shifted versions are fed to comparators to detect the zero-crossings and build a 4-b digital representation of the signal phase. Seeking for a low-area and low-power consumption realization, our proposal employs a resistor-less scheme which performs phase rotations in current domain. Together with the Ph-ADC, the fully integrated GFSK demodulator also includes a channel-filtering programmable gain amplifier and a symbol decision block. Altogether, the demodulator occupies 0.14 in a 0.13- CMOS technology with a total power consumption of 190 from a 1-V supply. For a data rate of 1 Mbps and 0.5 modulation depth, the GFSK demodulator requires an of 14.8 dB for a bit error rate of 0.1% considering a flicker noise corner of 150 kHz, obtains a dynamic range of 74 dB, and is able to tolerate carrier frequency offsets of 170 kHz. This performance safely complies with the requirements of the Bluetooth Low Energy (BLE) standard.
Autors: Masuch, J.;Delgado-Restituto, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2796 - 2806
Publisher: IEEE
 
» A 20Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A 3-axis accelerometer and strain sensor system for building integrity monitoring
Abstract:


Autors:
Appeared in: Sensors and Actuators A: Physical
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A 3.2ppm/C curvature-compensated bandgap reference with wide supply voltage range
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video
Abstract:
To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54 k gate counts under 90-nm CMOS technology.
Autors: Liao, Y.-H.;Li, G.-L.;Chang, T.-S.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Nov 2012, volume: 22, issue:11, pages: 1604 - 1610
Publisher: IEEE
 
» A 40 nm Dual-Width Standard Cell Library for Near/Sub-Threshold Operation
Abstract:
Near/sub-threshold operation is promising to achieve energy minimization when high performance is not required. The device sizing in sub-threshold region is different from super-threshold region due to significantly different IV characteristics and impact of parasitic effects in these two regions. We have investigated the impact of the inverse narrow width effect (INWE) on transistor drain current in the near/sub-threshold region at three different technology nodes (90 nm, 65 nm, and 40 nm) and proposed an INWE-aware sub-threshold device sizing method to mitigate the impact of INWE to reduce delay, power consumption and area. We applied the proposed device sizing method to designing an INWE-aware standard cell library and achieved up to 20% less delay, 34% less power consumption and 47% less area, compared with the sub-threshold library designed using conventional sizing method. For further optimization, we proposed a dual-width library by combining the INWE-aware library and the minimum sized library. A near-threshold baseband processor designed with the dual width library achieved a total power consumption of 4 µW with 6 MHz at 0.5 V, which is 30% better than the counterpart design.
Autors: Zhou, J.;Jayapal, S.;Busze, B.;Huang, L.;Stuyt, J.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2012, volume: 59, issue:11, pages: 2569 - 2577
Publisher: IEEE
 
» A 490 GHz planar circuit balanced Nb-Al2O3-Nb quasiparticle mixer for radio astronomy: Application to quantitative local oscillator noise determination
Abstract:
This article presents a heterodyne experiment which uses a 380–520 GHz planar circuit balanced Nb-Al2O3-Nb superconductor-insulator-superconductor (SIS) quasiparticle mixer with 4–8 GHz instantaneous intermediate frequency (IF) bandwidth to quantitatively determine local oscillator (LO) noise. A balanced mixer is a unique tool to separate noise at the mixer's LO port from other noise sources. This is not possible in single-ended mixers. The antisymmetric IV characteristic of a SIS mixer further helps to simplify the measurements. The double-sideband receiver sensitivity of the balanced mixer is 2–4 times the quantum noise limit hν/kB over the measured frequencies with a maximum LO noise rejection of 15 dB. This work presents independent measurements with three different LO sources that produce the reference frequency but also an amount of near-carrier noise power which is quantified in the experiment as a function of the LO and IF frequency in terms of an equivalent noise temperature TLO. Two types of LO sources are used: a synthesizer driven amplifier/multiplier chain and a Gunn oscillator driven multiplier chain. With the first type of LO we find different near-carrier noise contributions using two different power pre-amplifiers of the LO system. For one of the two power pre-amplifiers we measure TLO=30±4 K at the LO frequency 380 GHz and TLO=38±10 K at 420 GHz. At the frequency band center 465 GHz of the Gunn driven LO we measure- a comparable value of TLO=32±6 K. For the second power pre-amplifier, a significant higher TLO value of the synthesizer driven LO is found which is up to six times larger compared with the best values found for the Gunn driven LO. In a second experiment, we use only one of two SIS mixers of the balanced mixer chip in order to verify the influence of near-carrier LO noise power on a single-ended heterodyne mixer measurement. We find an IF frequency dependence of near-carrier LO noise power. The frequency-resolved IF noise temperature slope is flat or slightly negative for the single-ended mixer. This is in contrast to the IF slope of the balanced mixer itself which is positive due to the expected IF roll-off of the mixer. This indicates a higher noise level closer to the LO's carrier frequency. Our findings imply that near-carrier LO noise has the largest impact on the sensitivity of a receiver system which uses mixers with a low IF band, for example, superconducting hot-electron bolometer HEB mixers.
Autors: Peter Westig, Marc;Justen, Matthias;Jacobs, Karl;Stutzki, Jurgen;Schultz, Michael;Schomacker, Florian;Honingh, Netty;
Appeared in: Journal of Applied Physics
Publication date: Nov 2012, volume: 112, issue:9, pages: 093919 - 093919-12
Publisher: IEEE
 
» A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation
Abstract:
This paper presents a 5.4-Gb/s clock and data recovery circuit using a seamless loop transition scheme which has minimal phase noise degradation. The proposed scheme enables the CDR circuit to change the operation mode without output phase noise degradation or stability problems. A modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufactured using 0.13-µm CMOS technology. The rms jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps lower than the CDR circuit with the conventional scheme. The measured power dissipation is 138 mW with output drivers and an embedded 2:1 MUX at 5.4-Gb/s data rate.
Autors: Lee, W.-Y.;Kim, L.-S.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2012, volume: 59, issue:11, pages: 2518 - 2528
Publisher: IEEE
 
» A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation
Abstract:
This paper presents a time-interleaved pipelined-SAR ADC with on-chip offset cancellation technique. The design reuses the SAR ADC to perform offset cancellation, thus saving calibration costs. The inter-stage gain of 8 is implemented in a 6-bit capacitive DAC with a flip-around operation. A capacitive attenuation used in both the first and second DACs significantly reduces the power dissipation and optimizes conversion speed. The detailed circuit implementation of the subthreshold op-amp is discussed, and the possible limits caused by nonidealities are analyzed for a proper correction in the design. These include the inter-stage-gain error and various channel mismatches of offset, gain, and timing. Measurements of a 65-nm CMOS prototype operating at 160 MS/s and 1.1-V supply show an SNDR of 55.4 dB and 2.72 mW total power consumption.
Autors: Zhu, Y.;Chan, C.-H.;Sin, S.-W.;U, S.-P.;Martins, R. P.;Maloberti, F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2614 - 2626
Publisher: IEEE
 
» A 5MSps 13.25?W 8-bit SAR ADC with single-ended or differential input
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A 60-GHz Active Receiving Switched-Beam Antenna Array With Integrated Butler Matrix and GaAs Amplifiers
Abstract:
This paper presents for the first time a 60-GHz receiving switched-beam antenna on organic liquid crystal polymer (LCP) platform. A 4 1 quasi-Yagi array is incorporated with a 4 4 Butler matrix beamforming network and GaAs low-noise amplifiers on an LCP substrate. The active beam is controlled by GaAs single-pole-double-throw switches to access the four output states of the Butler matrix. The entire 4 1 active array is 1.4 cm 1.75 cm and consumes 1.1 W of dc power. Successful comparisons of the measured and simulated results verify a working phased array with a return loss better than 10 dB across the frequency band of 56.7–63.7 GHz. A comparison of radiation patterns demonstrate beam steering of with a peak active gain of 27.5 dB. The combined antenna and receiver noise performance at 60 GHz exhibits an estimated merit of 18.6 dB/K and noise figure of 5.4 dB.
Autors: Patterson, C. E.;Khan, W. T.;Ponchak, G. E.;May, G. S.;Papapolymerou, J.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2012, volume: 60, issue:11, pages: 3599 - 3607
Publisher: IEEE
 
» A 7.9-mW 5.6-GHz Digitally Controlled Variable Gain Amplifier With Linearization
Abstract:
This paper presents the design and validation of a compact high-performance digitally controlled variable-gain amplifier (DVGA). By using MOS switches and a linearizer, the designed DVGA demonstrates high linearity and gain flatness over a wide gain control range. The 6-bit DVGA is designed in a commercial 0.18- SiGe BiCMOS technology achieving a variable gain range from 16.5 to 6.5 dB, a 3-dB bandwidth from dc to 5.6 GHz, a 0.75-dB gain flatness from dc to 4 GHz, both input and output return loss greater than 15 dB, consuming 7.9 mW over the entire gain control range, and has a core circuit area of .
Autors: Kumar, T. B.;Ma, K.;Yeo, K. S.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2012, volume: 60, issue:11, pages: 3482 - 3490
Publisher: IEEE
 
» A 92-mW Real-Time Traffic Sign Recognition System With Robust Illumination Adaptation and Support Vector Machine
Abstract:
A low-power real-time traffic sign recognition system that is robust under various illumination conditions is proposed. It is composed of a Retinex preprocessor and an SVM processor. The Retinex preprocessor performs the Multi-Scale Retinex (MSR) algorithm for robust light and dark adaptation under harsh illumination environments. In the Retinex preprocessor, the recursive Gaussian engine (RGE) and reflectance engine (RE) exploit parallelism of the MSR tasks with a two-stage pipeline, and a mixed-mode scale generator (SG) with adaptive neuro-fuzzy inference system (ANFIS) performs parameter optimizations for various scene conditions. The SVM processor performs the SVM algorithm for robust traffic sign classification. The proposed algorithm-optimized small-sized kernel cache and memory controller reduce power consumption and memory redundancy by 78% and 35%, respectively. The proposed system is implemented as two separated ICs in a 0.13- CMOS process, and the two chips are connected using network-on-chip off-chip gateway. The system achieves robust sign recognition operation with 90% sign recognition accuracy under harsh illumination conditions while consuming just 92 mW at 1.2 V.
Autors: Park, J.;Kwon, J.;Oh, J.;Lee, S.;Kim, J.-Y.;Yoo, H.-J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2012, volume: 47, issue:11, pages: 2711 - 2723
Publisher: IEEE
 
» A Nanowire MIS Photodetector With Polymer Insulator
Abstract:
The authors report the growth of nanowires by heating the Ti/glass template and the fabrication of a nanowire metal–insulator–semiconductor (MIS) photodetector (PD). Compared with a nanowire metal–semiconductor–metal PD, it was found that we could achieve a photocurrent 29 times larger. It was also found that the dynamic response of the nanowire MIS PD was stable and reproducible with an on/off current contrast ratio of around 180. With an incident light wavelength of 390 nm and an applied bias of 5 V, it was found that the measured responsivity of the PD was . Furthermore, the noise equivalent power and the detectivity of the fabricated nanowire MIS PD were and , respectively.
Autors: Chang, S.-J.;Tsai, T.-Y.;Jiao, Z.-Y.;Chiu, C.-J.;Weng, W.-Y.;Wang, S.-H.;Hsu, C.-L.;Hsueh, T.-J.;Wu, S.-L.;
Appeared in: IEEE Electron Device Letters
Publication date: Nov 2012, volume: 33, issue:11, pages: 1577 - 1579
Publisher: IEEE
 
» A Balancing Act: What Software Practitioners Have to Say about Technical Debt
Abstract:
An interview study involving 35 practitioners from a variety of domains aimed to characterize technical debt at the ground level to find out how software practitioners perceive it. The study also aimed to understand the context in which technical debt occurs, including its causes, symptoms, and effects. In addition, the study focused on how practitioners currently deal with technical debt. This analysis paints a picture of a large, complex balancing act of various short- and long-term concerns. The Web Extra gives the interview questions used by Erin Lim, Nitin Taksande, and Carolyn Seaman.
Autors: Lim, Erin;Taksande, Nitin;Seaman, Carolyn;
Appeared in: IEEE Software
Publication date: Nov 2012, volume: 29, issue:6, pages: 22 - 27
Publisher: IEEE
 
» A base-sequence-modulated golay code improves the excitation and measurement of ultrasonic guided waves in long bones
Abstract:
Researchers are interested in using ultrasonic guided waves (GWs) to assess long bones. However, GWs suffer high attenuation when they propagate in long bones, resulting in a low SNR. To overcome this limitation, this paper introduces a base-sequence-modulated Golay code (BSGC) to produce larger amplitude and improve the SNR in the ultrasound evaluation of long bones. A 16-bit Golay code was used for excitation in computer simulation. The decoded GWs and the traditional GWs, which were generated by a single pulse, agreed well after decoding the received signals, and the SNR was improved by 26.12 dB. In the experiments using bovine bones, the BSGC excitation produced the amplitudes which were at least 237 times greater than those produced by a single pulse excitation. The BSGC excitation also allowed the GWs to be received over a longer distance between two transducers. The results suggest the BSGC excitation has the potential to measure GWs and assess long bones.
Autors: Song, X.;Ta, D.;Wang, W.;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Nov 2012, volume: 59, issue:11, pages: 2580 - 2583
Publisher: IEEE
 
» A Beam Phase and Energy Measurement Instrument Based on Direct RF Signal IQ Undersampling Technique
Abstract:
A diagnostic instrument being designed to measure the beam phase and energy of the drift tube linac in the proton accelerator of the China Spallation Neutron Source is described, and the characterization of the system is presented. The signals received from fast current transformers are radio-frequency (RF) signals with a frequency of 352.2 MHz and a dynamic range from 30 to 3.5 dBm. The RF signals are converted to orthogonal streams directly with the in- and quadrature-phase undersampling technique based on high-speed high-resolution analog-to-digital (A/D) conversion. To guarantee a high-quality A/D conversion, two different sampling clock circuits are designed with corresponding simulations and tests conducted for comparison. To build a stand-alone instrument with compact architecture, all digital signal processing algorithms are implemented within one single field-programmable gate array; meanwhile, a Nios II embedded system is also integrated in it for data transfer through the Ethernet. This system achieves a phase resolution better than 0.09 over the input signal amplitude range from 41 to 7 dBm, well beyond the 0.5 required.
Autors: Tang, S.;Zhao, L.;Liu, S.;Hao, X.;Wu, W.;An, Q.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Nov 2012, volume: 61, issue:11, pages: 2870 - 2878
Publisher: IEEE
 
» A behaviour sequencing and composition architecture based on ontologies for entertainment humanoid robots
Abstract:


Autors:

Highlights

Appeared in: Robotics and Autonomous Systems
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A behaviour-based control architecture for heterogeneous modular, multi-configurable, chained micro-robots
Abstract:


Autors:

Highlights

Appeared in: Robotics and Autonomous Systems
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A Bidirectional 60-GHz Wireless-Over-Fiber Transport System With Centralized Local Oscillator Service Delivered to Mobile Terminals and Base Stations
Abstract:
We propose a novel 60-GHz wireless-over-fiber (WoF) access system for multigigabit bidirectional data transmission. In conventional microwave wireless system designs, electrical local oscillator (LO) sources are required for frequency conversions in both base station (BS) and mobile terminal (MT), incurring considerable cost for system integration and maintenance at millimeter-wave frequencies. We design a WoF transport system, aiming to centralize system functions in the central office (CO), without requiring electrical LO devices in both BS and MT. In our proposed scheme, LO has been centralized in CO, the LO signal is distributed as a service to carry out frequency up-/down-conversion functions required in BS and MT. Thus, in this simplified system architecture, the overall cost can be reduced and the operation quality of centralized LO service enhanced. The operation principle and feasibility of error-free transmission of multigigabit, bidirectional data streams over both fiber and free space has been demonstrated experimentally.
Autors: Ye, C.;Zhang, L.;Zhu, M.;Yu, J.;He, S.;Chang, G.-K.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Nov 2012, volume: 24, issue:22, pages: 1984 - 1987
Publisher: IEEE
 
» A Bilevel Approach to Operational Decision Making of a Distribution Company in Competitive Environments
Abstract:
This paper presents a model for operational decision making of a distribution company (disco) with distributed generation (DG) and interruptible loads (IL) in a competitive market. The disco objective, modeled through the upper-level problem, is to minimize the cost of market purchases and DG unit dispatch while taking into account the responses of the other discos. This upper-level problem is constrained by a lower-level market clearing problem whose objective corresponds to maximization of social welfare. Such a setting results in a multi-disco equilibrium problem formulated as an equilibrium problem with equilibrium constraints (EPEC) by combining the optimality conditions of all upper-level problems. Using a nonlinear approach, the EPEC problem is reformulated as a single nonlinear optimization model which is simultaneously solved for all discos. The proposed approach is applied to an ac model of a power system to account for voltage and reactive power constraints of the transmission and distribution networks. Numerical examples based on two test systems are presented to illustrate the application of the proposed method.
Autors: Haghighat, H.;Kennedy, S. W.;
Appeared in: IEEE Transactions on Power Systems
Publication date: Nov 2012, volume: 27, issue:4, pages: 1797 - 1807
Publisher: IEEE
 
» A biologically motivated approach towards modular and robust low-level sensor fusion for application in agricultural machinery design
Abstract:


Autors:

Highlights

Appeared in: Computers and Electronics in Agriculture
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A biomimetic underwater microrobot with multifunctional locomotion
Abstract:


Autors:
Appeared in: Robotics and Autonomous Systems
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A bistable SMA microvalve for 3/2-way control
Abstract:


Autors:
Appeared in: Sensors and Actuators A: Physical
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A black box method for solving the complex exponentials approximation problem
Abstract:


Autors:
Appeared in: Digital Signal Processing
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A boolean algebraic-based solution for multiple fault diagnosis: Application to a spatial mission
Abstract:


Autors:
Appeared in: Aerospace Science and Technology
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A Boundary Condition-Based Approach to the Modeling of Memristor Nanostructures
Abstract:
A deep theoretical discussion proves that in Joglekar's and Biolek's models the memductance-flux relation of a memristor driven by a sign-varying voltage source may only exhibit single-valuedness and multi-valuedness respectively. This manuscript derives a novel boundary condition-based Model for memristor nanostructures. Unlike previous models, the proposed one allows for closed-form solutions. More importantly, subject to the nonlinear behavior under exam, this model enables a suitable tuning of boundary conditions, which may result in the detection of both single-valued and multi-valued memductance-flux relations under certain sign-varying inputs of interest. The large class of modeled dynamics include all behaviors reported in the legendary paper revealing the existence of memory-resistance at the nano scale.
Autors: Corinto, F.;Ascoli, A.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2012, volume: 59, issue:11, pages: 2713 - 2726
Publisher: IEEE
 
» A bounded controller for multirobot navigation while maintaining network connectivity in the presence of obstacles
Abstract:


Autors:
Appeared in: Automatica
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A Brief Overview of the America Invents Act
Abstract:
The eleventh in a series of articles providing basic information on legal issues facing people and businesses that operate in computing-related markets discusses the America Invents Act. The Web extra at http://youtu.be/WUjsIQOabxs is an audio recording of authors Brian M. Gaff, Ralph A. Loren, and Amy M. DeCloux discussing the America Invents Act.
Autors: Gaff, Brian M.;Loren, Ralph A.;DeCloux, Amy M.;
Appeared in: Computer
Publication date: Nov 2012, volume: 45, issue:11, pages: 8 - 10
Publisher: IEEE
 
» A Camera-Driven Power Management of Computer Display
Abstract:
Effective display power management is essential to reduce the cost of operating desktop computers as well as prolonging the lifetime of battery-operated notebooks and laptops between consecutive battery recharges. Although displays are dedicated for our eyes, existing display power management technologies “sense” only our fingers or temperature or motion through keyboard, mouse, or special sensors. Therefore, display may either switch off when its user looks at the screen or loose energy by keeping the screen on when nobody looks at it. This paper discusses a new display power management technology and outlines its implementation in personal computer systems. Unlike presently used power management, our technology “watches” the user through a single video camera. The technology tracks the user's eyes, keeping the display active only if the user looks at the screen. Otherwise, it dims the display down or even switches it off to save energy. We implemented the technology in field-programmable gate array-based hardware and present results of its experimental evaluation.
Autors: Moshnyaga, V. G.;Hashimoto, K.;Suetsugu, T.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Nov 2012, volume: 22, issue:11, pages: 1542 - 1553
Publisher: IEEE
 
» A cascade face recognition system using hybrid feature extraction
Abstract:


Autors:

Highlights

Appeared in: Digital Signal Processing
Publication date: Nov 2012
Publisher: Elsevier B.V.
 
» A Catheterization-Training Simulator Based on a Fast Multigrid Solver
Abstract:
A VR-based simulator helps trainees develop skills for catheterization, a fundamental but difficult procedure in vascular interventional radiology. A deformable model simulates the complicated behavior of guide wires and catheters, using the principle of minimum total potential energy. A fast, stable multigrid solver ensures realistic simulation and real-time interaction. In addition, the system employs geometrically and topologically accurate vascular models based on improved parallel-transport frames, and it implements efficient collision detection. Experiments evaluated the method's stability, the solver's execution time, how well the simulation preserved the catheter's curved tip, and the catheter deformation's realism. An empirical study based on a typical selective-catheterization procedure assessed the system's feasibility and effectiveness.
Autors: Li, Shun;Guo, Jixiang;Wang, Qiong;Meng, Qiang;Chui, Yim-Pan;Qin, Jing;Heng, Pheng-Ann;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Nov 2012, volume: 32, issue:6, pages: 56 - 70
Publisher: IEEE
 
» A Characteristic Galerkin Method for Eddy-Current Field Analysis in High-Speed Rotating Solid Conductors
Abstract:
Standard Galerkin finite element method (FEM) performs poorly when simulating convection dominated problems using the Eulerian formulation. A numerical method for analyzing transient eddy-current magnetic field in high-speed rotating solid conductors using characteristic Galerkin finite element method (CGFEM) is presented. The convection-diffusion equation is discretized implicitly in time domain via the method of characteristics and in space via piecewise quadratic finite elements. An example with extremely large Peclet number is solved by using the CGFEM to validate its effectiveness. TEAM workshop problem 30 A which is a practical case with high-speed rotating conductors is studied to showcase the efficiency and accuracy of the proposed method.
Autors: Ho, S. L.;Zhao, Y.;Fu, W. N.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Nov 2012, volume: 48, issue:11, pages: 4634 - 4637
Publisher: IEEE
 
» A Closed-Form Power Allocation and Signal Alignment for a Diagonalized MIMO Two-Way Relay Channel With Linear Receivers
Abstract:
A novel channel diagonalization scheme for an amplify-and-forward, multiple-input multiple-output (MIMO), two-way relay channel (TWRC) is proposed using generalized singular value decomposition (GSVD). Diagonalization of the MIMO TWRC is a sub-optimal approach that achieves two main purposes: reducing the computational complexity for optimizing the linear precoders at each node; and reducing the detection complexity at the source nodes by separating the multiple data streams. For the given diagonalized structure, we first align the entries of the diagonalized channels using a permutation to maximize a lower bound of average achievable sum rate (ASR), and a joint source-relay power allocation is then performed to maximize the ASR of the aligned TWRC; the overall problem is divided into two convex subproblems, the solutions to which are provided in closed-form. Our analysis for the proposed scheme underlines the benefits of acquiring channel state information. Simulation results demonstrate that the proposed GSVD-based relaying scheme, with the signal alignment and closed-form power allocation, significantly improves the ASR while retaining the diagonalized channel structure. In addition, the proposed scheme achieves the same level of ASR with much less computational complexity as compared to the iterative schemes.
Autors: Park, H.;Yang, H. J.;Chun, J.;Adve, R.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Nov 2012, volume: 60, issue:11, pages: 5948 - 5962
Publisher: IEEE
 

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