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Electrical and Electronics Engineering publications abstract of: 11-2011 sorted by title, page: 0
» 'Tis the Season to be Healthy! [Editor's Remarks]
Abstract:
The mimicking of human intelligence towards the betterment of the society has always been a part of my dream since young. Till this day, on every visit to the hospital, I would often imagine the possibilities of applying my knowledge in Computational Intelligence (CI) to replace the doctor on non-critical medical prognosis and diagnosis such as the flu and cough, so as to relieve the stress on our healthcare system and reduce the waiting time. Such an intelligent device will be equipped with a comprehensive set of basic symptoms a patient may relate and the knowledge database consisting of rules in the form of “IF input X THEN diagnosis Y ELSE…” will then offer medical diagnosis to illness based on a combination of these human interpretable rules.
Autors: Tan, K.C.;
Appeared in: IEEE Computational Intelligence Magazine
Publication date: Nov 2011, volume: 6, issue:4, pages: 2 - 10
Publisher: IEEE
 
» “Trends” Expert Overview Sessions Revived at ICASSP 2011: Part 2
Abstract:
This is the second in a series of three columns summarizing the “Trends” expert sessions organized by the Signal Processing Society Technical Committees during ICASSP 2011 in Prague, Czech Republic. Readers have an opportunity to access these Trends session summaries authored by the Technical Committees.
Autors: van der Veen, A.-J.;Principe, J.C.;
Appeared in: IEEE Signal Processing Magazine
Publication date: Nov 2011, volume: 28, issue:6, pages: 200 - 200
Publisher: IEEE
 
» 1-D Electro-Optic Beam Steering Device
Abstract:
In this paper, we present the design and fabrication of a 1D beam steering device based on planar electro-optic thermal-plastic prisms and a collimator lens array. With the elimination of moving parts, the proposed device is able to overcome the mechanical limitations of present scanning devices, such as fatigue and low operating frequency, while maintaining a small system footprint (~0.5mm × 0.5 mm). From experimental data, our prototype device is able to achieve a maximum deflection angle of 5.6° for a single stage prism design and 29.2for a cascaded three prisms stage design. The lens array shows a 4 ?m collimated beam diameter.
Autors: Wei-Chih Wang, Chi Leung Tsui
Appeared in: Sensors and Actuators A: Physical
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» 10 MLOC in Your Office Copier
Abstract:
Amid the obvious volume of digital copiers and multifunction printers, the system size is in the millions of lines of code with functionality creep into several overlapping areas—a theme of many modern systems.
Autors: Tsuchitoi, Yuki;Sugiura, Hideki;
Appeared in: IEEE Software
Publication date: Nov 2011, volume: 28, issue:6, pages: 93 - 95
Publisher: IEEE
 
» 150-GHz RF SOI-CMOS Technology in Ultrathin Regime on Organic Substrate
Abstract:
This letter provides an experimental demonstration of high-performance industrial MOSFETs thinned down to 5.7 and transferred onto a 125- -thick polyethylene naphthalate foil. The die stack transferred onto the organic substrate comprises the 200-nm-thick active layer and the 5.5- -thick interconnection multilayer stack resulting in a light, compact, and bendable thin film. We unveil that dc and RF performances are invariant even for ultimate thinning down to the buried oxide layer. Furthermore, n-MOSFET performance is improved by compared with previous work, and the first demonstration of 100-GHz p-MOSFETs on an organic substrate is presented. Unity-current-gain cutoff and maximum oscillation frequencies as high as 150/160 GHz for n-MOSFETs and 100/130 GHz for p-MOSFETs on a plastic substrate have been measured, respectively.
Autors: Lecavelier des Etangs-Levallois, A.;Dubois, E.;Lesecq, M. r.;Danneville, F.;Poulain, L.;Tagro, Y.;Lepilliet, S.;Gloria, D.;Raynaud, C.;Troadec, D.;
Appeared in: IEEE Electron Device Letters
Publication date: Nov 2011, volume: 32, issue:11, pages: 1510 - 1512
Publisher: IEEE
 
» 1945–2010: 65 Years of Satellite History From Early Visions to Latest Missions
Abstract:
This paper takes a broad view on the history and the present status of satellite communications and broadcasting. The necessary starting point of this overview is the visionary papers produced by Sir Arthur C. Clarke and John Pierce. This was the real dawn of the satellite communication era. This paper attempts to explain the “fil rouge” of the evolution of satellite technologies across six decades, analyzing successes and failures of past satellite missions, and concluding with a picture of future satellite communications.
Autors: Evans, B. G.;Thompson, P. T.;Corazza, G. E.;Vanelli-Coralli, A.;Candreva, E. A.;
Appeared in: Proceedings of the IEEE
Publication date: Nov 2011, volume: 99, issue:11, pages: 1840 - 1857
Publisher: IEEE
 
» 1D analog behavioral SPICE model for hot wire sensors in the continuum regime
Abstract:
We have developed an efficient 1D electrothermal SPICE model for hot-wire sensors simulation which takes into account self-heating and temperature gradients generated by the electrical contacts, regardless of the operating regime of the hot-wire. Our approach, based on the ability of SPICE to calculate the inverse Laplace transform by convolution, leads to a very fast, accurate and compact model where both time and space could be considered as continuous variables. A test of our model is by simulating the operation of a hot-wire anemometer in the constant temperature mode and in the 3?mode. Our simulated results reproduce very closely the experiments and confirm the relevance of such an approach.
Autors: R. Heyd, A. Hadaoui, M.L. Saboungi
Appeared in: Sensors and Actuators A: Physical
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» 2011 IEEE Symposium Series on Computational Intelligence [Conference Reports]
Abstract:
Autors: Bouchon-Meunier, B.;
Appeared in: IEEE Computational Intelligence Magazine
Publication date: Nov 2011, volume: 6, issue:4, pages: 19 - 22
Publisher: IEEE
 
» 2011 list of reviewers forAutomatica
Abstract:
[No author name available]
Autors: Source: Automatica, Volume 47, Issue 12, December 2011, Pages 2811-2821
Appeared in: Automatica
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» 2012 IEEE CIS Awards [Society Briefs]
Abstract:
Autors: Keller, J.M.;
Appeared in: IEEE Computational Intelligence Magazine
Publication date: Nov 2011, volume: 6, issue:4, pages: 4 - 10
Publisher: IEEE
 
» 24 hours at Fukushima
Abstract:
Sometimes it takes a disaster before we humans really figure out how to design something. In fact, sometimes it takes more than one. Millions of people had to die on highways, for example, before governments forced auto companies to get serious about safety in the 1980s. But with nuclear power, learning by disaster has never really been an option. Or so it seemed, until officials found themselves grappling with the world??s third major accident at a nuclear plant. On 11 March, a tidal wave set in motion a sequence of events that led to meltdowns in three reactors at the Fukushima Dai-ichi power station, 250 kilometers northeast of Tokyo. After
Autors: Strickland, E.;
Appeared in: IEEE Spectrum
Publication date: Nov 2011, volume: 48, issue:11, pages: 35 - 42
Publisher: IEEE
 
» 250 Mbps–5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 m CMOS
Abstract:
A multi-port serial link with wide-range CDR using digital vernier phase shifting and dual-mode control is presented. The proposed vernier phase shifter generates finely-spaced phase steps and provides unlimited phase rotating with a 13.34-ps phase step at 5 Gbps. By inherently digital nature, the vernier phase shifter enables semi-digital dual-loop CDR with precise tracking performance, and with the dual-mode control, the proposed CDR extends the operating range from 250 Mbps to 5 Gbps and achieves a BER of less than 10 at 5 Gbps with 2 1 PRBS. Fabricated in a 0.13- m CMOS process, the main PLL and the single receiver dissipate 9.0 mW and 19.2 mW respectively at 5 Gbps from a 1.2 V supply.
Autors: Lee, S.-Y.;Lee, H.-R.;Kwak, Y.-H.;Choi, W.-S.;Yoo, B.-J.;Shim, D.;Kim, C.;Jeong, D.-K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2560 - 2570
Publisher: IEEE
 
» 3-D Thin-Wire FDTD Analysis of Coaxial Probe Fed in Asymmetric Microwave Components
Abstract:
For the coaxial probe fed in asymmetric microwave components, an improved scheme on the 3-D thin-wire (TW) finite-difference time-domain (FDTD) is implemented without additional grid refinements and/or auxiliary update terms. The fine geometrical discontinuity such as the conductive arm, feed aperture, and finite end of the coaxial probe is approximated to the quasi-static models. The near fields in the vicinity of the probe end are also theoretically calculated from the uniformly charged disk model. It is shown that the spatial dependency of the near fields around the finite end of its probe agrees well with the direct solutions of the fine-grid (FG) FDTD simulation. The dominant functions of the near-field behaviors in the vicinity of the probe are easily incorporated into the correction factors of the coefficients for the 3-D Cartesian FDTD update equations. For the choice of the cell size in the proposed TW FDTD, the input admittances of a coaxial monopole probe in air are calculated and compared with the FG FDTD and the measured data. To evaluate the effects of the asymmetric geometry in the vicinity of the coaxial probe, coaxial-probe fed waveguide launchers are numerically analyzed as a function of the excitation frequency, the eccentric position, and the axial height of the coaxial probe. In comparison with the standard TW FDTD, the proposed TW FDTD provides a very close agreement with the reference data.
Autors: Hyun, S.-Y.;Kim, S.-Y.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2011, volume: 59, issue:11, pages: 2808 - 2815
Publisher: IEEE
 
» 300-GHz InAlN/GaN HEMTs With InGaN Back Barrier
Abstract:
This letter reports lattice-matched high-electron-mobility transistors on a SiC substrate with a record current gain cutoff frequency of 300 GHz. To suppress the short-channel effects (SCEs), an back barrier is applied in an InAlN/GaN heterostructure for the first time. The GaN channel thickness is also scaled to 26 nm, which allows a good immunity to SCEs for gate lengths down to 70 nm even with a relatively thick top barrier (9.4–10.4 nm). In a 30-nm-gate-length device with an on-resistance of 1.2 and an extrinsic transconductance of 530 mS/mm, a peak of 300 GHz is achieved. An electron velocity of 1.37– is extracted by two different delay analysis methods.
Autors: Lee, D. S.;Gao, X.;Guo, S.;Kopp, D.;Fay, P.;Palacios, T.;
Appeared in: IEEE Electron Device Letters
Publication date: Nov 2011, volume: 32, issue:11, pages: 1525 - 1527
Publisher: IEEE
 
» 3D fabrication by stacking prepatterned, rigidly held membranes
Abstract:
The authors describe an approach to fabricating high resolution, complex 3D structures based on the stacking of thin membranes that have been patterned in advance. The membranes are attached to a rigid frame by means of tethers that are strong enough to permit normal handling but can be cleaved after bonding. The tether shape was designed using finite-element analysis to enable clean cleavage at a specific location so that fragments are avoided that would interfere with the bonding of subsequent layers. The authors used 12 × 12 mm SiNx membranes, 350 nm thick, patterned with a square array of holes at 600 nm pitch and demonstrate the stacking of three layers.
Autors: Patel, Amil A.;Fucetola, Corey P.;Moon, Euclid E.;Smith, Henry I.;
Appeared in: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures
Publication date: Nov 2011, volume: 29, issue:6, pages: 06F402 - 06F402-3
Publisher: IEEE
 
» 3D nanostructures by stacking pre-patterned fluid-supported single-crystal Si membranes
Abstract:
The fabrication of complex three-dimensional (3D) structures at sub-100 nm resolution presents a difficult challenge. 3D photonic crystals that contain waveguides, resonant cavities, filters or other devices, and require deep-sub-100 nm dimensional control, are a particular example of this challenge. Multilayer 3D structures can be formed by stacking and bonding thin membranes that have been patterned in advance. This approach enables the full panoply of 2D planar-fabrication techniques to be employed. Membranes containing patterns that are not perfectly regular will exhibit in-plane distortion unless their intrinsic stress is zero. To minimize the effects of intrinsic stress we float individual membranes on the surface of a liquid. Thin single-crystal Si membranes on an oxide substrate are first patterned and then removed by etching the oxide in hydrofluoric acid. The freed Si membranes readily float on the liquid surface, aided by the hydrophobic nature of H-terminated Si. The authors describe methods for cleaning, patterning, manipulating, bonding and stacking such freely floating membranes.
Autors: Ghadarghadr, Shabnam;Fucetola, Corey P.;Lee Cheong, Lin;E. Moon, Euclid;I. Smith, Henry;
Appeared in: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures
Publication date: Nov 2011, volume: 29, issue:6, pages: 06F401 - 06F401-3
Publisher: IEEE
 
» 3D Nanostructuring of hydrogen silsesquioxane resist by 100 keV electron beam lithography
Abstract:
The authors investigated the three-dimensional nanostructuring of hydrogen silsesquioxane (HSQ) resist by multiple-step 100 keV electron beam lithography. Consecutive overlay exposures were used to create two- and three-levels in high aspect ratio HSQ structures with lateral dimensions down to 30 nm and resist thicknesses of about 1 μm. The HSQ resist was developed by a high contrast solution and supercritically dried in a carbon dioxide environment after each exposure step. The three-dimensional HSQ patterning has potential applications in the fabrication of performance enhanced devices such as photonic crystals, nanoelectromechanical systems, and diffractive X-ray lenses.
Autors: Vila-Comamala, Joan;Gorelick, Sergey;Guzenko, Vitaliy A.;David, Christian;
Appeared in: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures
Publication date: Nov 2011, volume: 29, issue:6, pages: 06F301 - 06F301-5
Publisher: IEEE
 
» 3D Rotations
Abstract:
The author describes four methods to achieve rotations using elementary concepts from algebra, analytic geometry, and calculus.
Autors: Taubin, Gabriel;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Nov 2011, volume: 31, issue:6, pages: 84 - 89
Publisher: IEEE
 
» 4096-Ary OCDM/OCDMA System Using Multidimensional PSK Codes Generated by a Single Multiport En/Decoder
Abstract:
We experimentally demonstrate a record -ary optical code division multiplexing (OCDM) system at 2.5 Gbps using multidimensional phase shift keying (PSK) codes generated/processed by a single multiport optical encoder/decoder (E/D). To analyze the system performance, we evaluate the power margin and the data confidentiality. For application to access networks, we propose and numerically evaluate the performance of 10 Gbps, 4096-ary optical code division multiple access (OCDMA)-based passive optical network (PON).
Autors: Kodama, T.;Kataoka, N.;Wada, N.;Cincotti, G.;Wang, X.;Kitayama, K.;
Appeared in: Journal of Lightwave Technology
Publication date: Nov 2011, volume: 29, issue:22, pages: 3372 - 3380
Publisher: IEEE
 
» 6-GHz Radio-Over-Fiber Upstream Transmission Using a Directly Modulated RSOA
Abstract:
We propose and demonstrate 40-km upstream transmission of a 2-Gb/s 6-GHz binary phase-shift keyed radio signal using a directly modulated reflective semiconductor optical amplifier (RSOA). A delay interferometer, acting as an optical equalizer, compensates for limited RSOA modulation bandwidth and simultaneously performs single sideband filtering to relieve dispersion-induced radio-frequency (RF) fading effect. Furthermore, extended transmission distance of up to 40 km is shown to be made possible by reduced Rayleigh backscattering-induced crosstalk.Pub _bookmark Command="[Quick Mark]"
Autors: Meiyappan, A.;Kam, P. Y.;Kim, H.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Nov 2011, volume: 23, issue:22, pages: 1730 - 1732
Publisher: IEEE
 
» 60-nm-Wide Tunable Single-Longitudinal-Mode Ytterbium Fiber Laser With Passive Multiple-Ring Cavity
Abstract:
A broadband tunable, single-longitudinal-mode (SLM) ytterbium fiber laser based on a passive multiple-ring cavity (MRC) technique is proposed and demonstrated experimentally for the first time to our knowledge. Two different short ring cavities are inserted into the main ring cavity and serve as wideband mode filters to ensure SLM oscillation. With 1-m ytterbium-doped fiber as the gain medium, the SLM operation is achieved with over 60-nm wavelength tuning range at 100-mW pump power. The laser is very stable with output power of 6 dBm and an optical signal-to-noise ratio of higher than 53 dB in all the 60-nm tuning range.Pub _bookmark Command="[Quick Mark]"
Autors: Yin, F.;Yang, S.;Chen, H.;Chen, M.;Xie, S.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Nov 2011, volume: 23, issue:22, pages: 1658 - 1660
Publisher: IEEE
 
» 80-MHz intravascular ultrasound transducer using PMN-PT free-standing film
Abstract:
[Pb(Mg1/3Nb2/3)O3]0.63[PbTiO3]0.37 (PMN-PT) free-standing film of comparable piezoelectric properties to bulk material with thickness of 30 μm has been fabricated using a modified precursor coating approach. At 1 kHz, the dielectric permittivity and loss were 4364 and 0.033, respectively. The remnant polarization and coercive field were 28 μC/ cm2 and 18.43 kV/cm. The electromechanical coupling coefficient kt was measured to be 0.55, which was close to that of bulk PMN-PT single-crystal material. Based on this film, high-frequency (82 MHz) miniature ultrasonic transducers were fabricated with 65% bandwidth and 23 dB insertion loss. Axial and lateral resolutions were determined to be as high as 35 and 176 μ m. In vitro intravascular imaging on healthy rabbit aorta was performed using the thin film transducers. In comparison with a 35-MHz IVUS transducer, the 80-MHz transducer showed superior resolution and contrast with satisfactory penetration depth. The imaging results suggest that PMN-PT free-standing thin film technology is a feasible and efficient way to fabricate very-high-frequency ultrasonic transducers.
Autors: Xiang Li;Wei Wu;Youngsoo Chung;Shih, W.Y.;Wei-Heng Shih;Qifa Zhou;Shung, K.K.;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Nov 2011, volume: 58, issue:11, pages: 2281 - 2288
Publisher: IEEE
 
» A 0.24-nJ/bit Super-Regenerative Pulsed UWB Receiver in 0.18- m CMOS
Abstract:
This paper describes a receiver system design for impulse-radio ultra-wideband (IR-UWB) that operates at two carrier frequencies—3.494 and 3.993 GHz—with a 10-Mbps data rate. To reduce the power consumption of the front-end amplifiers, a super-regenerative architecture is used. An integrated circuit, implemented in a CMOS 0.18- technology and operating with a 1.5-V power supply, exhibits energy consumption of 0.24 nJ/bit with a measured sensitivity of and at 3.494 and 3.993 GHz, respectively, with a BER of . Also included on the integrated circuit is an automatic tuning circuit based on a digital phase-locked loop that is used to set the resonant frequency of the super-regenerative block.
Autors: Thoppay, P. E.;Dehollain, C.;Green, M. M.;Declercq, M. J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2623 - 2634
Publisher: IEEE
 
» A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC
Abstract:
Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a nonoversampled clock, thus enabling a much higher speed of operation. At the same time, the low complexity and the inherent accuracy of the slope-architecture enable very good power-efficiency without using complex calibration techniques. A two-channel time-interleaved 5-bit asynchronous digital slope ADC was implemented in a 90-nm CMOS technology and occupies 160 m 300 m. The measured prototype achieves an ENOB of 4.6 bit, while operating at 250 MS/s and consuming 0.8 mW from a 1-V supply.
Autors: Harpe, P. J. A.;Zhou, C.;Philips, K.;de Groot, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2450 - 2457
Publisher: IEEE
 
» A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration
Abstract:
This paper presents a sub-radix-2 redundant architecture to improve the performance of switched-capacitor successive-approximation-register (SAR) analog-to-digital converters (ADCs). The redundancy not only guarantees digitally correctable static nonlinearities of the converter, it also offers means to combat dynamic errors in the conversion process, and thus, accelerating the speed of the SAR architecture. A perturbation-based digital calibration technique is also described that closely couples with the architecture choice to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area. A 12-bit prototype measured a Nyquist 70.1-dB signal-to-noise-plus-distortion ratio (SNDR) and a Nyquist 90.3-dB spurious free dynamic range (SFDR) at 22.5 MS/s, while dissipating 3.0-mW power from a 1.2-V supply and occupying 0.06- silicon area in a 0.13- CMOS process. The figure of merit (FoM) of this ADC is 51.3 fJ/step measured at 22.5 MS/s and 36.7 fJ/step at 45 MS/s.
Autors: Liu, W.;Huang, P.;Chiu, Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2661 - 2672
Publisher: IEEE
 
» A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering
Abstract:
This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%–0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal–oxide–semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory.
Autors: Tseng, Y.-C.;Hsu, P.-H.;Chang, T.-S.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Nov 2011, volume: 20, issue:11, pages: 3231 - 3241
Publisher: IEEE
 
» A 15-dBm SiGe BiCMOS PA for 77-GHz Automotive Radar
Abstract:
This paper presents a 15-dBm power amplifier for 77-GHz automotive radar applications, which is fabricated in a 0.13- SiGe:C BiCMOS process featuring bipolar transistors with of 230/280 GHz. The circuit consists of a two-stage pseudodifferential cascode with fully integrated input/output matching networks. State-of-art performance is achieved with the proposed design algorithm and layout optimization. The amplifier demonstrates a figure-of-merit of 2500 achieving a 22.5-dB power gain and a power-added efficiency of 7.5% at 77 GHz, while drawing 130 mA from a 2.5-V voltage supply.
Autors: Giammello, V.;Ragonese, E.;Palmisano, G.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2011, volume: 59, issue:11, pages: 2910 - 2918
Publisher: IEEE
 
» A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band
Abstract:
The wide unlicensed bandwidth of a 60 GHz channel presents an attractive opportunity for high data rate and low power personal area networks (PANs). The use of single-carrier modulation can yield energy-efficient transmitter and receiver implementation, but equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a significant challenge. A digital equalizer for 60 GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions to meet the IEEE WPAN standard. Power consumption is minimized by using a parallelized distributed arithmetic (DA) architecture. A 2 mm 2 mm test chip in 65nm CMOS implements a 6 tap feedforward and 32 tap feedback equalizer that can be configured to cancel the response of up to 72 symbols, and consumes 5.6 mW at 2 Gb/s throughput. The chip also includes a channel estimator based on a Golay correlator for setting the equalizer coefficients and estimating frequency and timing error.
Autors: Park, J.-H.;Richards, B.;Nikolic, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2524 - 2534
Publisher: IEEE
 
» A 2.3 W Wireless Intraocular Pressure/Temperature Monitor
Abstract:
We present the design of an ultra-low power, wireless pressure/temperature sensing device for continuous intraocular pressure monitoring. The device is wirelessly powered and demonstrates a power consumption of 2.3 at 1.5 V during continuous monitoring. The chip converts both capacitance and temperature to frequency using a time-interleaved relaxation oscillator, which modulates RF backscatter to a reader for computation of measured samples. A significant reduction in power consumption results from the elimination of the digitization circuitry, time-multiplexed operation, and moving the signal processing burden to the external reader using analog IF-modulated backscatter. The chip exhibits measured capacitance and temperature standard deviations of 1.4 fF and 0.4 , respectively.
Autors: Shih, Y.-C.;Shen, T.;Otis, B. P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2592 - 2601
Publisher: IEEE
 
» A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA
Abstract:
A 20-MHz bandwidth continuous-time (CT) sigma-delta modulator (SDM) with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13- CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resistor (FSCR) digital-to-analog converter (DAC) for feedback. A new data weighted averaging (DWA) technique is developed to remove the timing bottleneck at 640 MHz clock frequency. The CT SDM achieves 63.9 dB peak signal-to-noise-and-distortion ratio (SNDR) and 68 dB dynamic range (DR) which decreases by only 2.3 dB when the RMS jitter of the 640 MHz clock is 15.6 ps. The power consumption is 58 mW from a 1.2-V supply.
Autors: Jo, J.-G.;Noh, J.;Yoo, C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2469 - 2477
Publisher: IEEE
 
» A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)
Abstract:
Low voltage operation of digital circuits continues to be an attractive option for aggressive power reduction. As standard SRAM bitcells are limited to operation in the strong-inversion regimes due to process variations and local mismatch, the development of specially designed SRAMs for low voltage operation has become popular in recent years. In this paper, we present a novel 9T bitcell, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations. As opposed to the majority of existing solutions, this is achieved without the need for additional peripheral circuits and techniques. The proposed bitcell is fully functional under global and local variations at voltages from 250 mV to 1.1 V. In addition, the proposed cell presents a low-leakage state reducing power up to 60%, as compared to an identically supplied 8T bitcell. An 8 kbit SF-SRAM array was implemented and fabricated in a low-power 40 nm process, showing full functionality and ultra-low power.
Autors: Teman, A.;Pergament, L.;Cohen, O.;Fish, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2713 - 2726
Publisher: IEEE
 
» A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues
Abstract:
Showing that the worst minimum operating voltage (Vmin) of an 8T dual-port (DP) SRAM is determined by the write/read-disturbing condition with a finite clock skew, we propose a circuit technique to detect the worst Vmin in asynchronous clock operation. This circuitry allows us to screen the worst bit in an array that is conventionally obtained by a costly and time-consuming test procedure. For instance, we can at least realize 400x speed-up for the test time compared to the conventional method. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed experimentally that the worst Vmin can be successfully reproduced within 6% discrepancy by our proposed circuit.
Autors: Ishii, Y.;Fujiwara, H.;Tanaka, S.;Tsukamoto, Y.;Nii, K.;Kihara, Y.;Yanagisawa, K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2535 - 2544
Publisher: IEEE
 
» A 280-GHz Schottky Diode Detector in 130-nm Digital CMOS
Abstract:
A 2 2 array of 280-GHz Schottky-barrier diode detectors with an on-chip patch antenna (255 250 m ) is fabricated in a 130-nm logic CMOS process. The series resistance of diode is minimized using poly-gate separation (PGS), and exhibits a cut-off frequency of 2 THz. Each detector unit can detect an incident carrier with 100-Hz 2-MHz amplitude modulation. At 1-MHz modulation frequency, the estimated voltage responsivity and noise equivalent power (NEP) of the detector unit are 250 V/W and 33 , respectively. An integrated low-noise amplifier further boosts the responsivity to 80 kV/W. At supply voltage of 1.2 V, the entire chip consumes 1.6 mW. The array occupies 1.5 0.8 mm . A set of millimeter-wave images with a signal-noise ratio of 48 dB is formed using the detector. These suggest potential utility of Schottky diode detectors fabricated in CMOS for millimeter wave and sub-millimeter wave imaging.
Autors: Han, R.;Zhang, Y.;Coquillat, D.;Videlier, H.;Knap, W.;Brown, E.;O, K. K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2602 - 2612
Publisher: IEEE
 
» A 3-AXIS ACCELEROMETER AND STRAIN SENSOR SYSTEM FOR BUILDING INTEGRITY MONITORING
Abstract:
An Ultra-Low-Power readout architecture for capacitive MEMS-based accelerometers and strain sensors is presented. The system can read both accelerometers and strain sensors in a half-bridge configuration. An accurate VerilogA model of the sensor was made to improve simulations. The gain of the system is controlled by integrating pulses from the excitation circuit allowing accurate control of the Signal-to-Noise ratio. A Figure-of-Merit of 4.41 × 10F?(W/Hz) was achieved for a sensor range of ±2.0 g and ±20,000 ?? over a 100 Hz bandwidth. A minimum of 440nW power consumption was recorded. Residual motion artifacts are also cancelled by the system.
Autors: J. Santana, R. van den Hoven, C. van Liempd, M. Colin, N. Saillen, ...
Appeared in: Sensors and Actuators A: Physical
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» A 3-DOF parallel manufacturing module and its kinematic optimization
Abstract:

Highlights

? A decoupled 3-DOF parallel tool head without parasitic motion is proposed. ? Investigation of the inverse kinematics and orientational capability of the tool head is carried out. ? Performance indices taking into account the motion/force transmissibility are defined and corresponding atlases are presented. ? Using atlases as bases, optimal kinematic design of tool head is carried out, a preferable set of optimized parameters is gain.


Autors: Parallel tool heads with three degrees of freedom (DOFs), namely, two orientational DOFs and one translational DOF, have become important manufacturing module in the field of machine tools so that these have drawn extensive attention from academia an
Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» A 30 Gb/s/Link 2.2 Tb/s/mm Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface
Abstract:
This paper presents a 30 Gb/s/link 2.2 Tb/s/mm inductive-coupling link for a high-speed DRAM interface. The data rate per layout area is the highest among DRAM interfaces reported up to now. The proposed interface employs a high-speed injection-locking CDR technique that utilizes the derivative property of inductive coupling. Compared to conventional injection-locking CDR based on an XOR edge detector, the proposed technique doubles the operation speed and increases the data rate to 30 Gb/s/link. As a result, the data rate per layout area is increased to 2.2 Tb/s/mm , which is 2X that of the state-of-the-art inductive-coupling link, and 22X that of the state-of-the-art wired link.
Autors: Take, Y.;Miura, N.;Kuroda, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2552 - 2559
Publisher: IEEE
 
» A 40-Gb/s Full-Rate 2:1 MUX in 0.18- CMOS
Abstract:
This paper demonstrates high-speed design techniques that enable realization of a full-rate broadband serializer operating at 40 Gb/s using a 0.18- CMOS process. Bandwidth enhancement techniques, including shunt-peaking and multipole bandwidth enhancement, have been incorporated in the different high-speed blocks in the serializer. A dynamic retiming circuit capable of clocked 40-GHz operation is presented, which reduces the periodic jitter at the serial output. A low-power distributed buffer with unequal characteristic impedances in the gate line and drain line is designed as a 40-Gb/s output buffer. A method for generating a differential 40-GHz clock using two coupled 20-GHz oscillators with a “push–push” topology is also presented. An injection-locked divider based on a four-stage ring oscillator with four injection points has been designed for generating a 10-GHz clock signal.
Autors: Yazdi, A.;Green, M. M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2011, volume: 59, issue:11, pages: 2879 - 2887
Publisher: IEEE
 
» A 6.75 mW 12.45 dBm IIP3 1.76 dB NF 0.9 GHz CMOS LNA Employing Multiple Gated Transistors With Bulk-Bias Control
Abstract:
This letter presents a gm''-cancellation range extension method with bulk-bias control that was applied to a Multiple Gated Transistors (MGTR) technique, which is a linearity enhancement technique for RF amplifiers. Instead of adjusting the gate-biasing voltage of the auxiliary transistor (AT) (Vshift) in conventional gm'' -cancellation, we propose to use the bulk-biasing voltage, VBS, which allows for range extension of the gm''-cancellation of AT. The proposed technique does not require any other additional biasing circuits and has the benefit of consuming less power. The proposed low noise amplifier (LNA) is implemented in 0.18 μm 1-poly-6-metal CMOS technology. Our results show that the LNA achieves a noise figure of 1.76 dB, a +12.45 dBm input third order intercept point (IIP3), and a 15 dB power gain at 0.9 GHz, with the core LNA consuming 4.5 mA from a 1.5 V power supply.
Autors: Tae Hwan Jin;Tae Wook Kim;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2011, volume: 21, issue:11, pages: 616 - 618
Publisher: IEEE
 
» A 6.75 mW 12.45 dBm IIP3 1.76 dB NF 0.9 GHz CMOS LNA Employing Multiple Gated Transistors With Bulk-Bias Control
Abstract:
This letter presents a -cancellation range extension method with bulk-bias control that was applied to a Multiple Gated Transistors (MGTR) technique, which is a linearity enhancement technique for RF amplifiers. Instead of adjusting the gate-biasing voltage of the auxiliary transistor (AT) in conventional -cancellation, we propose to use the bulk-biasing voltage, , which allows for range extension of the -cancellation of AT. The proposed technique does not require any other additional biasing circuits and has the benefit of consuming less power. The proposed low noise amplifier (LNA) is implemented in 0.18 1-poly-6-metal CMOS technology. Our results show that the LNA achieves a noise figure of 1.76 dB, a 12.45 dBm input third order intercept point (IIP3), and a 15 dB power gain at 0.9 GHz, with the core LNA consuming 4.5 mA from a 1.5 V power supply.
Autors: Jin, T. H.;Kim, T. W.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2011, volume: 21, issue:11, pages: 616 - 618
Publisher: IEEE
 
» A 60 GHz Broadband Low-Noise Amplifier With Variable-Gain Control in 65 nm CMOS
Abstract:
A 60 GHz low-noise amplifier (LNA) implemented in a 65 nm CMOS process is presented. Due to the use of a gain-boosted input stage and binary controlled attenuators, the LNA exhibits a broadband response and four programmable gain levels from 18.9 to 7.9 dB while maintaining impedance matching at the 60 GHz frequency band. The fabricated circuit consumes a dc current of 25 mA from a 1.8 V supply.
Autors: Hsieh, Y.-K.;Kuo, J.-L.;Wang, H.;Lu, L.-H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2011, volume: 21, issue:11, pages: 610 - 612
Publisher: IEEE
 
» A 60 Ghz Scanning Near-Field Microscope With High Spatial Resolution Sub-Surface Imaging
Abstract:
We report a 60 GHz near-field scanning microscope for surface and sub-surface imaging. The sensing evanescent millimeter-wave probe is made of an alumina microstrip line tapered to 7 to achieve high spatial resolution. The scanning probe microscopy platform provides amplitude and phase-shift mappings of the reflection coefficient. Our microscope demonstrates the ability to achieve subsurface microscale-resolution images of buried structures.
Autors: Haddadi, K.;Glay, D.;Lasri, T.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2011, volume: 21, issue:11, pages: 625 - 627
Publisher: IEEE
 
» A 60-GHz 1-V Supply Band-Tunable Power Amplifier in 65-nm CMOS
Abstract:
This brief presents the design of a band-tunable 60-GHz CMOS power amplifier using 65-nm standard CMOS technology. To achieve high gain and PAE over the whole 7-GHz frequency band, this amplifier utilizes a differential band-switching circuit to tune the center frequency to the channel in use, whereas high- transformer matching and deep-neutralized differential pairs are employed to achieve high gain and PAE in a narrow bandwidth. The amplifier achieves saturated output power of 12.3 dBm and peak PAE of 20.4% with a 1-V supply and a 63-mA current. The peak gain is 17.1 dB at 59 GHz and 16.2 dB at 53.5 GHz for the two different frequency bands, respectively.
Autors: Bi, X.;Guo, Y.;Brinkhoff, J.;Jia, L.;Wang, L.;Xiong, Y. Z.;Leong, M. S.;Lin, F.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2011, volume: 58, issue:11, pages: 719 - 723
Publisher: IEEE
 
» A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation
Abstract:
A 65 nm self-synchronous field programmable gate array (SSFPGA) with delay insensitive operation and pipeline granularity at the gate level, is shown to be robust to process voltage and temperature (PVT) variations. The proposed SSFPGA employs a 38 38 array of four-input, three-stage self-synchronous configurable logic blocks, with the introduction of a new dual tree-divider four-input, three-pipeline stage LUT to achieve a 2.97 GHz throughput at 1.2 V. Correct operation is measured with 500 mVp-p, 1.12 GHz externally introduced power supply noise at 1.2 V power supply, equivalent to 42% power supply bounce. Sensitivity against power supply noise frequency has been measured, and confirmed with simulation results to show a strong correlation with the average operating frequency. Correct operation was shown over 10 chips with 16% performance variation, with VDD change from 728 mV to 2 V, and temperature change from 0 C to 120 C, without tuning any input parameters such as clock frequency, supply voltages and biases. Results show the SSFPGA can adapt and is inherently robust to these variations with internal throughput measured from 300 MHz to 4.07 GHz, while maintaining correct operation. The operation under noisey power supply conditions is compared to a conventional synchronous FPGA, which show the SSFPGA has 4.2 times error free operation. The failure mode is also measured on the SSFPGA using an accelerated stress cycle between 0 C and 120 C at 2 V, showing the SSFPGA has 8% longer correct operation before chip malfunction past a 10% delay margin commonly used in synchronous systems.
Autors: Devlin, B.;Ikeda, M.;Asada, K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2500 - 2513
Publisher: IEEE
 
» A 90 nm CMOS V-Band Low-Noise Active Balun With Broadband Phase-Correction Technique
Abstract:
This paper presents a V-band low-noise active balun with broadband phase-correction technique (PCT). The proposed technique effectively mitigates the phase deviation of active balun caused by parasitic imbalance and circuit mismatch. This technique is insensitive to frequency, which makes the operation frequency of active balun with the PCT can be extended to millimeter-wave (MMW) band. Within the low noise current-reuse pre-amplifier, this active balun circuit can be employed as low-noise amplifier as well. The measured phase error keeps less than 10 degrees from 50 GHz to 67 GHz, which demonstrates the robust calibration of phase error at MMW frequency. The measured voltage gain and noise figure at 63 GHz are 17.6 dB and 8.6 dB, respectively. The core power consumption is 19 mW from 1.4 V supply voltage with a core area of 0.275 mm .
Autors: Chiang, H.-H.;Huang, F.-C.;Wang, C.-S.;Wang, C.-K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2583 - 2591
Publisher: IEEE
 
» A Bayesian approach for place recognition
Abstract:
This paper presents a robust place recognition algorithm for mobile robots that can be used for planning and navigation tasks. The proposed framework combines nonlinear dimensionality reduction, nonlinear regression under noise, and Bayesian learning to create consistent probabilistic representations of places from images. These generative models are incrementally learnt from very small training sets and used for multi-class place recognition. Recognition can be performed in near real-time and accounts for complexity such as changes in illumination, occlusions, blurring and moving objects. The algorithm was tested with a mobile robot in indoor and outdoor environments with sequences of 1579 and 3820 images respectively. This framework has several potential applications such as map building, autonomous navigation, search-rescue tasks and context recognition.
Autors: Fabio Ramos, Ben Upcroft, Suresh Kumar, Hugh Durrant-Whyte
Appeared in: Robotics and Autonomous Systems
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» A Behavior-Authoring Framework for Multiactor Simulations
Abstract:
Interest has been growing in the behavioral animation of autonomous actors in virtual worlds. However, authoring complicated interactions between multiple actors in a way that balances control flexibility and automation remains a considerable challenge. A proposed behavior-authoring framework gives users complete control over the domain of the system: the state space, action space, and cost of executing actions. To specialize actors, the framework uses effect and cost modifiers, which modify existing action definitions, and constraints, which prune action choices in a state-dependent manner. The framework groups actors with common or conflicting goals to form a composite domain, and a multiagent planner generates complicated interactions between multiple actors. The Web extra is a video that shows how multiactor simulations should aim to strike a happy medium between the automation of generation and the flexibility of specification.
Autors: Kapadia, Mubbasir;Singh, Shawn;Reinman, Glenn;Faloutsos, Petros;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Nov 2011, volume: 31, issue:6, pages: 45 - 55
Publisher: IEEE
 
» A bistable SMA microvalve for 3/2-way control
Abstract:
In this paper the layout, fabrication, and characterization of a first-of-its-kind bistable 3/2-way shape memory microvalve are presented. A symmetric arrangement of two counteracting shape memory alloy (SMA) microbridges is used for switching. The stable states in power-off condition are realized by magnetostatic contact forces between a movable hard-magnetic cylinder and two soft-magnetic layers. A detailed design study of the magnetic retaining system is performed to meet the requirements of a large pressure range and identical flow rates in the open valve state and a low leakage in the closed valve state in both outlet ports. The overall dimensions of first demonstrators are 11 × 6x4 mm. The 3/2-way bistable microvalve performance is demonstrated, showing identical flow rates in both outlet ports for a pressure difference up to 200 kPa for gas (N2) and up to 100 kPa for liquid (water) with flow rates of 1250sccm and 11 ml/min, respectively.
Autors: C. Megnin, J. Barth, M. Kohl
Appeared in: Sensors and Actuators A: Physical
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» A Blast of Activity
Abstract:
The growth of wind power activities within the IEEE power & energy Society (PES) has been nothing short of phenomenal. Those who thought electric power was a mature industry have learned that it is far from that. Wind power has changed the face of the industry and has instigated fundamental changes in the ways power systems are designed and operated. Wind power blurs the traditional distinction between generating resources, which produce power according to dispatch commands from operators, and system load, which is variable and uncertain but predictable by means of forecasts. A lot has been learned, but as wind power penetration continues to increase, the challenges do too. PES has responded with a greatly increased level of wind-related activities.
Autors: Piwko, R.;Bradt, M.;Camm, E.;Ellis, A.;Walling, R.;O'Malley, M.;
Appeared in: IEEE Power and Energy Magazine
Publication date: Nov 2011, volume: 9, issue:6, pages: 26 - 35
Publisher: IEEE
 
» A Broadband Double-Balanced Phase-Coherent Degenerate Parametric Amplifier
Abstract:
A broadband double-balanced phase-coherent degenerate parametric amplifier is presented that provides an average gain of 26 dB over 1 GHz of usable bandwidth centered at 650 MHz. A prototype board was constructed, and its measured and simulated data match well with one another. Using a harmonic-balance simulator, the stability of the amplifier was analyzed by observing the evolution of the system poles as both the pump power level and the temperature of operation varied.
Autors: Gray, B.;Ramirez, F.;Melville, B.;Suarez, A.;Kenney, J. S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Nov 2011, volume: 21, issue:11, pages: 607 - 609
Publisher: IEEE
 
» A Buck Converter With Reduced Output Spurs Using Asynchronous Frequency Hopping
Abstract:
A frequency-hopped buck converter with reduced output spurs in 0.35- CMOS is presented. The converter uses pulsewidth-modulation control with eight switching frequencies to achieve 13.2-dB reduction in output spurs from the traditional single-frequency case. The proposed implementation maintains the continuity of the ramp signal, regardless of the frequency selected or when it is selected. Therefore, the hopping rate can be set independently using a clock that is asynchronous to the internal switching frequencies of the converter, and no synchronization between the switching frequencies themselves or between them and the hopping clock is necessary. Moreover, the proposed continuous ramp signal minimizes transients associated with hopping, hence maximizing the hopping rate and spur reduction.
Autors: Tao, C.;Fayed, A. A.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2011, volume: 58, issue:11, pages: 709 - 713
Publisher: IEEE
 
» A CFAR Adaptive Subspace Detector for First-Order or Second-Order Gaussian Signals Based on a Single Observation
Abstract:
In this paper, we consider the problem of detecting a signal in Gaussian noise with unknown covariance matrix, in partially homogeneous environments where the test and training data samples share the same noise covariance matrix up to an unknown scaling factor. One solution to this problem is the adaptive subspace detector (ASD) with a single or multiple observations. However, the probabilities of false alarm and detection of this ASD have not been obtained yet. In this paper, these expressions are derived on the basis of a single observation, which are confirmed with Monte Carlo simulations. It is shown that the ASD has a constant false alarm rate property with respect to both the shared noise covariance matrix structure and the independent scaling of the noise in the test data. In addition, we prove that for the First-Order model where the signal of interest is assumed to be a deterministic but unknown vector, the ASD derived with the generalized likelihood ratio test is consistent with that derived with an ad hoc two-step design procedure.
Autors: Liu, J.;Zhang, Z.-J.;Yang, Y.;Liu, H.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Nov 2011, volume: 59, issue:11, pages: 5126 - 5140
Publisher: IEEE
 
» A Channel Differential EZW Coding Scheme for EEG Data Compression
Abstract:
In this paper, a method is proposed to compress multichannel electroencephalographic (EEG) signals in a scalable fashion. Correlation between EEG channels is exploited through clustering using a k-means method. Representative channels for each of the clusters are encoded individually while other channels are encoded differentially, i.e., with respect to their respective cluster representatives. The compression is performed using the embedded zero-tree wavelet encoding adapted to 1-D signals. Simulations show that the scalable features of the scheme lead to a flexible quality/rate tradeoff, without requiring detailed EEG signal modeling.
Autors: Dehkordi, V. R.;Daou, H.;Labeau, F.;
Appeared in: IEEE Transactions on Information Technology in Biomedicine
Publication date: Nov 2011, volume: 15, issue:6, pages: 831 - 838
Publisher: IEEE
 
» A Chirp-z-Transform-Based Software Synchronization Method for Optical Performance Monitoring
Abstract:
A software synchronization method based on chirp-z transform is proposed for optical performance monitoring in this letter. In comparison with the previously reported software synchronization methods, the proposed method is shown to have higher spectral resolution and shorter calculation time. The accuracy of the sampling step size for eye diagram recovery is efficiently improved. The experimental results of the eye-diagram and factor demonstrate the validity of the newly developed method.Pub _bookmark Command="[Quick Mark]"
Autors: Yang, A.;Lai, J.;Sun, Y.-N.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Nov 2011, volume: 23, issue:22, pages: 1739 - 1741
Publisher: IEEE
 
» A classic collaboration: Michael Davies on Plaque Vulnerability
Abstract:
The British Heart Foundation sponsors the Michael Davies Young Investigator Award, and at its presentation in the Spring of 2009 two collaborators of Michael Davies spoke regarding their experiences on the Plaque Vulnerability project with him. This was to provide the winner and other nominees for the award, and colleagues at the meeting, descriptions of collaborating with Michael to sustain more than his name in association with the award. This article is an expansion of the personal reminiscences given at the time as a tribute to him, and to provide an inside story of how collaboration with such a prominent cardiac pathologist worked.
Autors: G.V.R. Born, P.D. Richardson
Appeared in: Sensors and Actuators A: Physical
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» A CMOS Colpitts VCO Using Negative-Conductance Boosted Technology
Abstract:
A circuit topology suitable for a low-voltage low-power Colpitts voltage-controlled oscillator (VCO) is presented in this paper. By employing inductors for a negative-conductance boosted structure, the dc power consumption of the Colpitts VCO can be effectively reduced. Based on the proposed architecture, the VCO fabricated in 0.18- CMOS exhibits a measured 1.3% tuning range around 30 GHz. Operating at a supply voltage of 1.0 V, the VCO core consumes 2.3-mW dc power, and the measured phase noise is at 1-MHz offset. Compared to the recently published 20- to 30-GHz 0.18- CMOS VCOs, this work achieves a reduced supply voltage, minimized dc power consumption, small chip size, superior figure-of-merit (FOM), and better figure-of-merit including the tuning range . Formulas for considering the nonlinear characteristics of varactors and active devices are also presented, and the accuracy of predicting the VCO tuning curve is validated by measurement.
Autors: Wang, T.-P.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2011, volume: 58, issue:11, pages: 2623 - 2635
Publisher: IEEE
 
» A CMOS Highly Linear Digitally Programmable Active-RC Design Approach
Abstract:
A new approach providing the active-RC integrator with programmable time constant is proposed. An inherently linear current division network (CDN) preserving the high linearity property of the active RC technique while providing wide tuning characteristics is adopted. The proposed integrator provides wider tuning range, and higher tuning resolution accompanied with better linearity and/or reduced area than what could be obtained from capacitor and resistor banks. The proposed integrator uses two opamps per integrator just like its MOSFET-C counterpart but it inherently exhibits better linearity and wider tuning range particularly for low voltage supply. A reconfigurable filter exhibiting complex bandpass and normal lowpass responses is realized. Experimental results obtained from a 4th-order filter fabricated in a standard 0.18 CMOS process are given. The complex and lowpass filters achieve in-band spurious-free dynamic ranges (SFDRs) of about 70 dB and 71 dB for bandwidths of 1 MHz and 5.5 MHz, respectively.
Autors: Alzaher, H. A.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2011, volume: 58, issue:11, pages: 2636 - 2646
Publisher: IEEE
 
» A CMOS Power Amplifier With Integrated-Passive-Device Spiral-Shaped Directional Coupler for Mobile UHF RFID Reader
Abstract:
A CMOS power amplifier (PA) with a compact spiral-shaped directional coupler for a mobile UHF RF identification (RFID) reader is proposed here, and its output power combiner and the directional coupler are implemented using an integrated passive device process. The two-chip solution not only enables a CMOS PA to be highly efficient, but also allows the directional coupler and the power combiner to be mounted in a compact standard package. A polar transmitter is implemented using the CMOS PA with the directional coupler to verify the operation of the proposed configuration for a UHF RFID reader. Measurements indicate that the CMOS PA with the directional coupler transmits 27.3 dBm of output with 44.6% of power-added efficiency and that the implemented polar transmitter satisfies the required UHF RFID reader specifications.
Autors: Shim, S.;Hong, S.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Nov 2011, volume: 59, issue:11, pages: 2888 - 2897
Publisher: IEEE
 
» A CMOS-MEMS Gyroscope Interface Circuit Design With High Gain and Low Temperature Dependence
Abstract:
This paper describes an interface circuit design for monolithic CMOS-MEMS gyroscopes, based on a novel differential difference amplifier (DDA) with high gain, low temperature and process dependence, low noise, and low power consumption. The DDA achieves a 4 fF equivalent transcapacitance with a 0.01 temperature variation. The DDA-based interface circuit has been integrated with a -axis gyroscope on a foundry CMOS chip. A 4.5 input-referred noise is achieved at 2 kHz, with a total power consumption of 4.25 mW. The gyroscope is fabricated with a post-CMOS bulk micromachining process and the device achieves a sensitivity of 1.2 and a noise floor 0.05 .
Autors: Sun, H.;Jia, K.;Liu, X.;Yan, G.;Hsu, Y.-W.;Fox, R. M.;Xie, H.;
Appeared in: IEEE Sensors Journal
Publication date: Nov 2011, volume: 11, issue:11, pages: 2740 - 2748
Publisher: IEEE
 
» A Cochlear Implant Signal Processing Lab: Exploration of a Problem-Based Learning Exercise
Abstract:
This paper presents an introductory signal processing laboratory and examines this laboratory exercise in the context of problem-based learning (PBL). Centered in a real-world application, a cochlear implant, the exercise challenged students to demonstrate a working software-based signal processor. Partnering in groups of two or three, second-year electrical and computer engineering and biomedical engineering students used MATLAB graphical user interface programs, complemented with their own original MATLAB code, to design filters suitable for achieving a filter bank decomposition of an audio signal. Rather than using the envelope-detected output for direct electrical stimulation of auditory nerve fibers as in an implant, the students reconstructed the signal by modulating sinusoids to yield an acoustic simulation. To appreciate the impact of filter order on sound intelligibility, students were asked to reconstruct signals using 4-16 filter channels for both speech and music and to examine the results critically. The lab served as a substrate upon which to solidify fundamental signal processing concepts such as the distinction between time and frequency domains, constructing and interpreting spectrograms, sampling, spectral decomposition, filtering, and reconstruction. In the spirit of PBL, the students examined engineering tradeoffs and discussed implementations when they were asked to consider realizing a significantly higher channel count (128-channel) device. To determine how the laboratory exercise impacted student learning and comprehension, as well as the level of student engagement achieved with this compelling application, an anonymous online survey was administered at the end of the course. The survey outcomes, as well as the components of the lab, are discussed in the context of PBL pedagogy.
Autors: Bhatti, P.T.;McClellan, J.H.;
Appeared in: IEEE Transactions on Education
Publication date: Nov 2011, volume: 54, issue:4, pages: 628 - 636
Publisher: IEEE
 
» A Coding Theory Approach to Noisy Compressive Sensing Using Low Density Frames
Abstract:
We consider the compressive sensing of a sparse or compressible signal . We explicitly construct a class of measurement matrices inspired by coding theory, referred to as low density frames, and develop decoding algorithms that produce an accurate estimate even in the presence of additive noise. Low density frames are sparse matrices and have small storage requirements. Our decoding algorithms can be implemented in complexity, where is the left degree of the underlying bipartite graph. Simulation results are provided, demonstrating that our approach outperforms state-of-the-art recovery algorithms for numerous cases of interest. In particular, for Gaussian sparse signals and Gaussian noise, we are within 2-dB range of the theoretical lower bound in most cases.
Autors: Akcakaya, M.;Park, J.;Tarokh, V.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Nov 2011, volume: 59, issue:11, pages: 5369 - 5379
Publisher: IEEE
 
» A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to and InP Capacitors
Abstract:
By taking into account simultaneously the effects of border traps and interface states, the authors model the alternating current capacitance–voltage ( ) behavior of high-mobility substrate metal–oxide–semiconductor (MOS) capacitors. The results are validated with the experimental and InP/high- ( ) curves. The simulated and conductance–voltage ( ) curves reproduce comprehensively the experimentally measured capacitance and conductance data as a function of bias voltage and measurement frequency, over the full bias range going from accumulation to inversion and full frequency spectra from 100 Hz to 1 MHz. The interface state densities of and InP MOS devices with various high- dielectrics, together with the corresponding border trap density inside the high- oxide, were derived accordingly. The derived interface state densities are consistent to those previously obtained with other measurement methods- - . The border traps, distributed over the thickness of the high- oxide, show a large peak density above the two semiconductor conduction band minima. The total density of border traps extracted is on the order of . Interface and border trap distributions for InP and interfaces with high- oxides show remarkable similarities on an energy scale relative to the vacuum reference.
Autors: Brammertz, G.;Alian, A.;Lin, D. H.-C.;Meuris, M.;Caymax, M.;Wang, W.-E.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2011, volume: 58, issue:11, pages: 3890 - 3897
Publisher: IEEE
 
» A compact low-profile dual-band antenna for WLAN and WAVE applications
Abstract:
A compact and low-profile patch antenna with a simple structure is presented for the wireless local-area network (WLAN) and the wireless access in the vehicular environment (WAVE) applications. The proposed antenna with an overall size of only 23 mm × 25 mm is fed by a coplanar waveguide (CPW), and yields 10-dB impedance bandwidths of about 250 MHz centered at 2.44 GHz and of about 22% ranging from 5.13 to 6.38 GHz suitable for the WLAN 2.4/5.2/5.8 GHz and the WAVE 5.9 GHz (IEEE 802.11p) applications. Also, good dipole-like patterns and high average antenna gain of >=2.3 dBi over the operating bands have been obtained. In this design, resonance can be effectively controlled by simply tuning the shaped slots on the patch. Mechanism of mode excitations and effect of the added slot's length on resonance for the proposed antenna are examined and discussed in detail. The experimental results have validated the proposed design as useful for modern mobile communication.
Autors: Wen-Chung Liu, Chao-Ming Wu, Nien-Chang Chu
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» A Comparative Analysis of Peaking Methods for Output Stages of Broadband Amplifiers
Abstract:
This paper presents a general analysis of peaking methods in output stages of amplifiers for broadband communication systems. It is shown that common peaking methods, although providing significant signal bandwidth enhancement ratios (BWER), are limited to 30%–50% of their speed potential by output matching requirements. A modified T-coil peaking is analyzed which enhances both signal bandwidth and output matching frequency range by up to 200% compared to common peaking methods. A broadband amplifier using this inductive output matching with 69-GHz bandwidth implemented in a SiGe BiCMOS technology is presented to prove the validity of the analysis.
Autors: Knochenhauer, C.;Sedighi, B.;Ellinger, F.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2011, volume: 58, issue:11, pages: 2581 - 2589
Publisher: IEEE
 
» A comparative study for quantum transport calculations of nanosized field-effect transistors
Abstract:

Highlights

? We examine the validity of two quantum simulation methods named QFL and TBS. ? QFL overestimates subthreshold charge density and current at large drain bias. ? QFL works fine for ON states even under high drain bias. ? Results from TBS and QFL tend to coincide at small drain bias. ? Strict transport should be studied by scattering calculation or TBS approximation.


Autors: This article presents a comparative study on quantum mechanical frameworks between the widely used local Quasi-Fermi Level (QFL) model and a recently developed top of the barrier splitting (TBS) model. Both models are based on an atomistic quantum me
Appeared in: Solid-State Electronics
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» A comparative study of charge pumping circuits for flash memory applications
Abstract:
Flash memories are now widely used in many portable electronic devices, in embedded systems and are even as replacement for computer hard disks. In flash memory systems, high-voltages (up to about 10 V) are indispensable for programming operations. In many cases, however, such programming voltages are not directly available from the supply, and are usually generated by embedded voltage converting or charge pumping circuits. These circuits produce the required programming voltage from available external supplies with voltages in the approximate range of 1-5 V. The power conversion efficiency, the chip size, the voltage regulation, as well as the loading characteristics have been the major concerns for such circuits. The present paper discusses some recently proposed charge pumping circuits for flash memory applications. We focus on the effects of the dynamic gate control, the 4-phase gate-boosting and cross-coupled configuration for enhancing the performance of the charge pump circuits. Several different charge pumps operated under different working conditions are then investigated in detail.
Autors: O.Y. Wong, H. Wong, W.S. Tam, C.W. Kok
Appeared in: Microelectronics Reliability
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» A Comparative Study of Loop Filter Alternatives in Second-Order High-Pass Modulators
Abstract:
High-pass (HP) delta-sigma modulators possess the qualities of high immunity to low-frequency noise and direct digitisation at intermediate frequency (IF) stage , . This paper presents three loop-filter alternatives for second-order HP modulator and performs a comparative analysis. The two of the three architectures have already been utilized for low-pass (LP) modulators while the third one has not been explored before. This particular topology mitigates the shortcomings of the other two modulator architectures. It is a mixture of feedforward and feedback structures and hence takes advantages of both of them. The topology is less sensitive to the nonlinearities of the operational transconductance amplifiers (OTAs) and hence has low distortion. The output swing requirements of the OTA are minimized as they just process the quantization noise. This way the design of the OTA is fairly relaxed with reduced power consumption. The analog adder before the quantizer is also simplified as there are just two branches to add in contrast to three branches for pure feedforward topologies. This makes the modulator more robust against comparator offset, hysteresis and metastability. Hence this adder can be implemented passively without increasing the design requirements on comparator enormously.
Autors: Khushk, H. A.;Loumeau, P.;Nguyen, V. T.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Nov 2011, volume: 58, issue:11, pages: 2604 - 2613
Publisher: IEEE
 
» A Competition for Innovation [Education Department News]
Abstract:
Autors: Sottile, J.;
Appeared in: IEEE Industry Applications Magazine
Publication date: Nov 2011, volume: 17, issue:6, pages: 70 - 70
Publisher: IEEE
 
» A Comprehensive Solution for Deterministic Replay Debugging of SoftPLC Applications
Abstract:
Deterministic replay debugging is an approach to finding bugs in deployed software. It records an application run in the field so that it can deterministically be replayed offline in a development system for debugging purposes. To enable deterministic replay debugging, it is necessary to record all external influences and sources of nondeterminism in the original program run. From that trace log and from a known initial state, the program can be replayed deterministically without requiring any connection to the original environment. In this paper, we present a solution for deterministic replay debugging of hard real-time multitasking SoftPLC applications written in the IEC 61131-3 languages. By taking advantage of the special properties of these programs and by careful engineering, our technique allows recording a SoftPLC application run in the field with minimal overhead and obeying real-time constraints. In later phases, which are offline, the original program run is reconstructed from the minimal information recorded so it can be replayed for debugging. In comparison to previous work, our solution has several advantages: Instead of recording task scheduling information, it reconstructs the task interleaving based on data dependencies, thereby significantly simplifying the recording phase. Additionally, it incorporates a technique for periodically capturing the complete internal state of the system, which can later be used as a starting point for replay. We present the conceptual basis of our approach, a tool chain which provides deterministic replay debugging to the user as a set of fully automated tools, and an evaluation as well as an industrial case study for validating the approach.
Autors: Prahofer, H.;Schatz, R.;Wirth, C.;Mossenbock, H.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Nov 2011, volume: 7, issue:4, pages: 641 - 651
Publisher: IEEE
 
» A Comprehensive Study of Neutral-Point Self-Balancing Effect in Neutral-Point-Clamped Three-Level Inverters
Abstract:
Neutral point (NP) balancing problems in neutral-point-clamped (NPC) three-level inverters have been widely discussed in the past. Most of the previous researches have focused on the active NP control algorithms based on the common-mode duty cycle injection or the differential-mode harmonic current injection. Various active control methods have been proven to work well in real applications. On the other hand, it is well known that sometimes the NP is self-balanced, even without any active NP control. However, due to the uncertainty and lack of the theoretical explanations, active NP controllers are typically preferred for real applications, and the self-balancing characteristic of the NPC topology did not draw much attention in the past. Our paper covers this gap: the mechanisms of self-balancing characteristic are explored systematically. With the help of a precise mathematical model, readers can easily evaluate the self-balancing capability of their own design. In addition, this paper discusses some methods to enhance the self-balancing capability of an existing system. It is shown here that the self-balancing effect depends strongly on the switching frequency. Especially, for high-power insulated gate bipolar transistor/integrated gate-commutated thyristor/gate turn-OFF thyristors (IGBT/IGCT/GTO) applications, the effect is so strong at all power factors that this “do-nothing” control is sufficient and no other active NP controls are needed.
Autors: Shen, J.;Schröder, S.;Rösner, R.;El-Barbari, S.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Nov 2011, volume: 26, issue:11, pages: 3084 - 3095
Publisher: IEEE
 
» A Computational Intelligibility Model for Assessment and Compression of American Sign Language Video
Abstract:
Real-time, two-way transmission of American Sign Language (ASL) video over cellular networks provides natural communication among members of the Deaf community. As a communication tool, compressed ASL video must be evaluated according to the intelligibility of the conversation, not according to conventional definitions of video quality. Guided by linguistic principles and human perception of ASL, this paper proposes a full-reference computational model of intelligibility for ASL (CIM-ASL) that is suitable for evaluating compressed ASL video. The CIM-ASL measures distortions only in regions relevant for ASL communication, using spatial and temporal pooling mechanisms that vary the contribution of distortions according to their relative impact on the intelligibility of the compressed video. The model is trained and evaluating using ground truth experimental data collected in three separate studies. The CIM-ASL provides accurate estimates of subjective intelligibility and demonstrates statistically significant improvements over computational models traditionally used to estimate video quality. The CIM-ASL is incorporated into an H.264 compliant video coding framework, creating a closed-loop encoding system optimized explicitly for ASL intelligibility. The ASL-optimized encoder achieves bitrate reductions between 10% and 42%, without reducing intelligibility, when compared to a general purpose H.264 encoder.
Autors: Ciaramello, F. M.;Hemami, S. S.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Nov 2011, volume: 20, issue:11, pages: 3014 - 3027
Publisher: IEEE
 
» A Conditional Random Field Framework for Robust and Scalable Audio-to-Score Matching
Abstract:
In this paper, we introduce the use of conditional random fields (CRFs) for the audio-to-score alignment task. This framework encompasses the statistical models which are used in the literature and allows for more flexible dependency structures. In particular, it allows observation functions to be computed from several analysis frames. Three different CRF models are proposed for our task, for different choices of tradeoff between accuracy and complexity. Three types of features are used, characterizing the local harmony, note attacks and tempo. We also propose a novel hierarchical approach, which takes advantage of the score structure for an approximate decoding of the statistical model. This strategy reduces the complexity, yielding a better overall efficiency than the classic beam search method used in HMM-based models. Experiments run on a large database of classical piano and popular music exhibit very accurate alignments. Indeed, with the best performing system, more than 95% of the note onsets are detected with a precision finer than 100 ms. We additionally show how the proposed framework can be modified in order to be robust to possible structural differences between the score and the musical performance.
Autors: Joder, C.;Essid, S.;Richard, G.;
Appeared in: IEEE Transactions on Audio, Speech, and Language Processing
Publication date: Nov 2011, volume: 19, issue:8, pages: 2385 - 2397
Publisher: IEEE
 
» A Continuously Tunable Microwave Fractional Hilbert Transformer Based on a Photonic Microwave Delay-Line Filter Using a Polarization Modulator
Abstract:
A continuously tunable microwave fractional Hilbert transformer (FHT) implemented based on a photonic microwave delay-line filter is proposed and demonstrated. The photonic microwave delay-line filter with negative coefficients is realized based on polarization-modulation using a polarization modulator (PolM) and polarization-modulation to intensity-modulation conversion in an optical polarizer. The tunability of the fractional order is achieved by tuning the coefficient of the zeroth tap. An FHT with a tunable order from 0.3 to 1 is demonstrated. The accuracy of the FHT is evaluated; a phase deviation less than 5 within the passband is achieved.Pub _bookmark Command="[Quick Mark]"
Autors: Li, Z.;Chi, H.;Zhang, X.;Yao, J.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Nov 2011, volume: 23, issue:22, pages: 1694 - 1696
Publisher: IEEE
 
» A Correlation-Based Background Error Estimation Technique for Bandpass Delta–Sigma ADC DACs
Abstract:
This brief presents a background digital-to-analog converter (DAC) error estimation technique for multibit bandpass Delta–Sigma analog-to-digital converters ( ADCs). The technique is used to estimate and linearize the intrinsic mismatches of feedback DAC unit elements of ADCs. It consists of three building blocks, namely, a correlation-based error estimation, which utilizes a test signal to estimate DAC unit element gain mismatches; a digital error correction, which corrects the estimated DAC nonlinearities; and a unit establishing background operation. The method has been successfully utilized for lowpass ADCs and is extended here by using an additional bandpass filter to create a modified test signal, which meets the requirements of bandpass modulators. The method restores highly nonlinear systems back to their ideal linearity while requiring only little additional hardware effort and enables the design of linear multibit bandpass modulators.
Autors: Witte, P.;Kauffman, J. G.;Becker, J.;Ortmanns, M.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Nov 2011, volume: 58, issue:11, pages: 748 - 752
Publisher: IEEE
 
» A Cost-Effective Metal–Insulator–Metal Capacitor Processed at 300 Using Laser Annealing and a Fully Silicided Amorphous Silicon Bottom Electrode
Abstract:
Without requiring noble metal electrodes and expensive dielectric materials, a low-cost metal–insulator–metal (MIM) capacitor processed at 300 has been developed using laser annealing and a nickel fully silicided (Ni-FUSI) amorphous silicon bottom electrode. A high capacitance density of 31 , along with low electrode resistivities, was achieved. At 25 , this MIM capacitor also displays a good leakage current density of at 1 V. From X-ray diffraction measurement results, the dielectric constants of have been enhanced by KrF excimer laser annealing with different energy values due to hexagonal or orthorhombic phase formations that increase capacitance densities. Predicted 10-year of 0.8% is achieved at 1-V operation. The time-dependent dielectric breakdown (TDDB) characteristics also meet the 10-year lifetime criteria within the operation voltage range. Both the and TDDB characteristics have tradeoff relationships with the capacitance value. The combination of the improved dielectric by laser annealing, an inserted $hbox{Al}_{2}- - hbox{O}_{3}$ layer, a high-work-function Ni top electrode, and the low-resistivity -FUSI bottom electrode leads to excellent device integrity.
Autors: Lee, J.-H.;Lin, Y.-C.;Chen, M.-Y.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Nov 2011, volume: 58, issue:11, pages: 3920 - 3924
Publisher: IEEE
 
» A cylindrical traveling wave ultrasonic motor using a circumferential composite transducer
Abstract:
This paper intends to present and verify a new idea for constructing traveling wave ultrasonic motors that may effectively avoid the drawbacks of conventional traveling wave motors using bonded PZT plates as the exciting elements. In the configuration of the motor's stator, a composite sandwich type transducer is used to excite a traveling wave in a cylinder with two cantilevers as the coupling bridges between the transducer and the cylinder. The design process of the stator is described using the FEM modal analysis method, and the establishment of traveling wave on the cylindrical stator was simulated by FEM transient analysis. To verify the theoretical analysis results, a laser Doppler scanner was employed to test the mode shapes of a prototype stator excited by the longitudinal and bending vibrations respectively. Finally, to validate the design idea, a prototype motor was fabricated and tested; the typical output features are no-load speed of 156 rpm and maximum torque of 0.75 N·m under exciting voltages of 70 Vrms applied to excite the longitudinal vibration of the transducer and 200 Vrms applied to excite the bending vibration.
Autors: Liu, Y.;Liu, J.;Chen, W.;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Nov 2011, volume: 58, issue:11, pages: 2397 - 2404
Publisher: IEEE
 
» A Data-Driven Approach to Interactive Visualization of Power Systems
Abstract:
Information visualization appears to be a promising technique for improving the business practices in today's electric power industry. The legacy power system visualization tools, however, restrict the visualization process to follow a limited number of pre-defined patterns created by human designers, thus hindering users' ability to discover. This paper proposes a data-driven approach to interactive visualization of power systems. The proposed approach relies on developing powerful data manipulation algorithms to create visualizations based on the characteristics of empirically or mathematically derived data. Based on this approach, a data-driven model exploratory tool has been developed to enable users to visualize the power system's physical/electrical configurations at various levels and from different perspectives. The conducted case studies have demonstrated that the data-driven approach could result in an interactive and user-driven power system visualization tool that fosters scientific understanding and insight, therefore unleashing the power of visualization.
Autors: Zhu, J.;Zhuang, E.;Ivanov, C.;Yao, Z.;
Appeared in: IEEE Transactions on Power Systems
Publication date: Nov 2011, volume: 26, issue:4, pages: 2539 - 2546
Publisher: IEEE
 
» A day-ahead energy market simulation framework for assessing the impact of decentralized generators on step-down transformer power flows
Abstract:

Highlights

? Day ahead simulation framework to predict step down transformer power flows. ? Capability of integrating in a single platform different types of loads, DG technologies and grid. ? Different models have been integrated to represent the behavior of the DG. ? Load modeling with clustering techniques. ? Validation and practical application is presented with realistic data.


Autors: The world wide expected high penetration levels of distributed generation technologies (DG) will modify the operation paradigm of power systems. In this context, this work presents a day-ahead simulation framework to predict, in quarter hour periods,
Appeared in: International Journal of Electrical Power & Energy Systems
Publication date: Nov 2011
Publisher: Elsevier B.V.
 
» A DCT-Based Speech Enhancement System With Pitch Synchronous Analysis
Abstract:
Discrete cosine transform (DCT) has been proven to be a good approximation to the Karhunen-Loeve Transform (KLT) and has similar properties to the discrete Fourier transform (DFT). It also possesses a better energy compaction capability which is advantageous for speech enhancement. However, frame to frame variations of DCT coefficients even for a perfectly stationary signal can be observed. Therefore a DCT-based speech enhancement system with pitch synchronous analysis is proposed to overcome this problem. It reduces the drawbacks of fixed window shift and the amount of shift in the analysis window is now based on the pitch period, thus increasing the inter-frame similarities. Furthermore, a Wiener filter using the a priori signal-to-noise ratio (SNR) with an adaptive parameter is also derived and implemented as an advanced noise reduction filter. This proposed speech enhancement system is evaluated in terms of several objective measures and the experimental results demonstrate the good performance of the proposed system.
Autors: Huijun Ding;Ing Yann Soon;Chai Kiat Yeo;
Appeared in: IEEE Transactions on Audio, Speech, and Language Processing
Publication date: Nov 2011, volume: 19, issue:8, pages: 2614 - 2623
Publisher: IEEE
 
» A Deep UV Sensitive TFT
Abstract:
The authors report the fabrication of a deep-ultraviolet (deep-UV) sensitive a-IGZO thin-film-transistor (TFT) with a Ta2O5 gate dielectric. It was found that carrier mobility, threshold voltage and subthreshold swing were 48.5 cm2/Vs, 1.25 V and 0.49 V/decade, respectively, when measured in dark. It was also found that measured current increased from 1.5×10-9 A to 5.56×10-5 A , as we illuminated the sample with λ = 250 nm UV light when VG was biased at 0 V. Furthermore, it was found that deep-UV-to-visible rejection ratio could reach 1.0×106 for the fabricated Ta2O5/a-IGZO TFT.
Autors: Chiu, C.J.;Weng, W.Y.;Chang, S.J.;Chang, S.-P.;Chang, T.H.;
Appeared in: IEEE Sensors Journal
Publication date: Nov 2011, volume: 11, issue:11, pages: 2902 - 2905
Publisher: IEEE
 
» A Digitally Corrected 5-mW 2-MS/s SC ADC in 0.25- m CMOS With 94-dB SFDR
Abstract:
A digital correction scheme that allows a switched-capacitor (SC) ADC to operate with significantly reduced power consumption is proposed. As power dissipation is reduced in the integrators, nonlinear settling errors cause increasing harmonic distortion. The correction technique uses a polynomial approximation to correct the nonlinearity and reduce distortion in the post-filtered digital output. With correction, experimental results yield a peak SNDR of 75 dB, a THD of dB and a SFDR of 94 dB. The total analog power dissipation of the corrected modulator is 5 mW at 2.4 V, saving 38% over a similarly performing uncorrected modulator output. The active area is 0.39 mm in 0.25- m CMOS.
Autors: O'Donoghue, K. A.;Hurst, P. J.;Lewis, S. H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2673 - 2684
Publisher: IEEE
 
» A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers
Abstract:
A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static random access memory (SRAM) sense amplifiers (SA). The timing variation of SA attributable to the random variation of transistor threshold voltage is reduced by a sufficient count of replica cells, and replica bitline delay is digitized and multiplied to adjust it to the target timing for SA. The variation of the generated timing was 41% smaller than that with a conventional technique and cycle time was reduced 20% at the supply voltage of 0.6 V in 40 nm CMOS technology with this scheme.
Autors: Niki, Y.;Kawasumi, A.;Suzuki, A.;Takeyama, Y.;Hirabayashi, O.;Kushida, K.;Tachibana, F.;Fujimura, Y.;Yabe, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2545 - 2551
Publisher: IEEE
 
» A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter
Abstract:
This paper presents a wide-bandwidth, low-noise 4 GHz All-Digital PLL. It uses a rotary traveling wave oscillator (RTWO) as the oscillator core. By using multiphase signals available from the RTWO, the analog phase information is directly converted into the digital domain. Unlike the conventional time-to-digital converter (TDC) approach, it eliminates power hungry inverter delay chains as well as real time period normalization. The proposed approach significantly simplifies the ADPLL architecture while maintaining excellent phase noise. The PLL is implemented in a 65 nm CMOS process. The 32-phase embedded phase-to-digital converter (PDC) achieves 2 /64 phase resolution. The measured in-band phase noise is 108 dBc/Hz at 4 GHz with a 78 MHz reference and a 1 MHz loop bandwidth.
Autors: Takinami, K.;Strandberg, R.;Liang, P. C. P.;Le Grand de Mercey, G.;Wong, T.;Hassibi, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Nov 2011, volume: 46, issue:11, pages: 2650 - 2660
Publisher: IEEE
 
» A DTN-Based Sensor Data Gathering for Agricultural Applications
Abstract:
This paper presents our field experience in data collection from remote sensors. By letting tractors, farmers, and sensors have short-range radio communication devices with delay-disruption tolerant networking (DTN), we can collect data from those sensors to our central database. Although, several implementations have been made with cellular phones or mesh networks in the past, DTN-based systems for such applications are still under explored. The main objective of this paper is to present our practical implementation and experiences in DTN-based data collection from remote sensors. The software, which we have developed for this research, has about 50 kbyte footprint, which is much smaller than any other DTN implementation. We carried out an experiment with 39 DTN nodes at the University of Tokyo assuming an agricultural scenario. They achieved 99.8% success rate for data gathering with moderate latency, showing sufficient usefulness in data granularity.
Autors: Ochiai, H.;Ishizuka, H.;Kawakami, Y.;Esaki, H.;
Appeared in: IEEE Sensors Journal
Publication date: Nov 2011, volume: 11, issue:11, pages: 2861 - 2868
Publisher: IEEE
 

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