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Electrical and Electronics Engineering publications abstract of: 10-2013 sorted by title, page: 0
» "I Love Deadlines ..." [From the Editor's Desk]
Abstract:
Autors: Wood, J.;
Appeared in: IEEE Microwave Magazine
Publication date: Oct 2013, volume: 14, issue:6, pages: 6 - 8
Publisher: IEEE
 
» "What did you mean when you said...?"
Abstract:
There are many occasions when the word used is not important, and the meaning intended can indeed be left to the listener. In technical communications, specifications, requirements, and presentations, it is important that what is being said truly reflects the meaning intended by the speaker in certain terms. The author urgers readers "when it's your turn, leave no doubt about what you intended to say - use the appropriate words and descriptions."
Autors: Floyd, R.;Spencer, R.;
Appeared in: IEEE Potentials
Publication date: Oct 2013, volume: 32, issue:5, pages: 13 - 14
Publisher: IEEE
 
» “SRF Theory Revisited” to Control Self-Supported Dynamic Voltage Restorer (DVR) for Unbalanced and Nonlinear Loads
Abstract:
The protection of the sensitive unbalanced nonlinear loads from sag/swell, distortion, and unbalance in supply voltage is achieved economically using the dynamic voltage restorer (DVR). A simple generalized algorithm based on basic synchronous-reference-frame theory has been developed for the generation of instantaneous reference compensating voltages for controlling a DVR. This novel algorithm makes use of the fundamental positive-sequence phase voltages extracted by sensing only two unbalanced and/or distorted line voltages. The algorithm is general enough to handle linear as well as nonlinear loads. The compensating voltages when injected in series with a distribution feeder by three single-phase H-bridge voltage-source converters with a constant switching frequency hysteresis band voltage controller tightly regulate the voltage at the load terminals against any power quality problems on the source side. A capacitor-supported DVR does not need any active power during steady-state operation because the injected voltage is in quadrature with the feeder current. The proposed control strategy is validated through extensive simulation and real-time experimental studies.
Autors: Kanjiya, P.;Singh, B.;Chandra, A.;Al-Haddad, K.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Oct 2013, volume: 49, issue:5, pages: 2330 - 2340
Publisher: IEEE
 
» 100 kHz MEMS Vibratory Gyroscope
Abstract:
The behavior of MEMS rate gyroscopes depends on the sensor's resonance frequency . Key features like robustness against external vibrations and ease of integration can be optimized by increasing . We designed and fabricated a device with for experimental and theoretical investigation of MEMS vibratory gyroscopes with increased . The frequency of 100 kHz is significantly above the typical of current gyroscopes which is in the range of 10 kHz to 30 kHz. Measurements prove that key parameters that are theoretically derived from a 15 kHz reference model can be scaled to 100 kHz with good accuracy. It is shown that the increase of to 100 kHz has—on the one hand—design trade offs like a much lower sensitivity and higher quadrature and—on the other hand—major advantages like the significantly improved vibration robustness.
Autors: Liewald, J.-T.;Kuhlmann, B.;Balslink, T.;Trachtler, M.;Dienger, M.;Manoli, Y.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Oct 2013, volume: 22, issue:5, pages: 1115 - 1125
Publisher: IEEE
 
» 119-W Monolithic Single-Mode 1173-nm Raman Fiber Laser
Abstract:
We report a high-power high-efficiency single-mode all-fiber Raman fiber laser (RFL) operating at 1173 nm. With the core pumped by a 144-W 1120-nm Yb-doped fiber laser, an output power of 119 W at a wavelength of 1173 nm was obtained, corresponding to an optical efficiency of 82%. To the best of our knowledge, it is the highest power at the 1150–1200-nm laser band by using common silica fiber. The optical efficiency of the RFL with high output coupler (OC) reflectivity and short fiber length is discussed. We also carefully measured the output Raman spectrums under different cavity parameters and presented primary analysis. The results show that the bandwidth increases near linearly with laser output power, rather than a square-root law concluded for high -value and long-cavity RFLs in previous published literatures. Increasing the length of the gain fiber and the reflectivity of the OC would also broaden the output spectral bandwidth.
Autors: Zhang, H.;Xiao, H.;Zhou, P.;Wang, X.;Xu, X.;
Appeared in: IEEE Photonics Journal
Publication date: Oct 2013, volume: 5, issue:5, pages: 1501706 - 1501706
Publisher: IEEE
 
» 15-nW Biopotential LPFs in 0.35- CMOS Using Subthreshold-Source-Follower Biquads With and Without Gain Compensation
Abstract:
Most biopotential readout front-ends rely on the - lowpass filter (LPF) for forefront signal conditioning. A small realizes a large time constant ( ) suitable for ultra-low-cutoff filtering, saving both power and area. Yet, the noise and linearity can be compromised, given that each cell can involve one or several noisy and nonlinear - conversions originated from the active devices. This paper proposes the subthreshold-source-follower (SSF) Biquad as a prospective alternative. It features: 1) a very small number of active devices reducing the noise and nonlinearity footsteps; 2) No explicit feedback in differential implementation, and 3) extension of filter order by cascading. This paper presents an in-depth treatment of SSF Biquad in the nW-power regime, analyzing its power and area tradeoffs with gain, linearity and noise. A gain-compensation (GC) scheme addressing the gain-loss problem of NMOS-based SSF Biquad due to the body effect is also proposed. Two 100-Hz 4th-order Butterworth LPFs using the SSF Biquads with and without GC were fabricated in 0.35- CMOS. Measurement results show that the non-GC (GC) LPF can achieve a DC gain of (0 dB), an input-referred noise of 36 (29 $,mu{rm V} _{rm rms}$ ), a HD3@60 Hz of ( ) and a die size of 0.11 (0.08 ). Both LPFs draw 15 nW at 3 V. The achieved figure-of-merits (FoMs) are favorably comparable with the state-of-the-art.
Autors: Zhang, T.-T.;Mak, P.-I.;Vai, M.-I.;Mak, P.-U.;Law, M.-K.;Pun, S.-H.;Wan, F.;Martins, R;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Oct 2013, volume: 7, issue:5, pages: 690 - 702
Publisher: IEEE
 
» 2-D Simulation and Experimental Investigation of an Axial Vircator
Abstract:
A method for 2-D simulation of an axial vircator with a resonance cavity is described. It uses a self-consistent solution of relativistic motion equations and Maxwell equations for scalar and vector potentials in the Coulomb gauge. The vector potential is represented as a superposition of resonator eigenmodes, where each eigenmode corresponds to a damping oscillator. Damping enables considering radiative energy losses from the open end of the resonator. Compliance of the simulation results with both published experimental studies and those performed by our team is demonstrated.
Autors: Baryshevsky, V.;Gurinovich, A.;Molchanov, P.;Anishchenko, S.;Gurnevich, E.;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Oct 2013, volume: 41, issue:10, pages: 2712 - 2716
Publisher: IEEE
 
» 2-D simulation of dual frequency capacitively coupled helium plasma, using COMSOL multiphysics
Abstract:
A two-dimensional (2D) self-consistent fluid simulation of dual frequency capacitively coupled radio discharges of helium plasma is presented. The model solves the continuity equations for charged species and the electron energy balance equation, coupled with Poisson's equation by finite element method, using COMSOL Multiphysics software. In this study, the low frequency (LF) is set to 13.56 MHz with low frequency voltage of 250 V and the high frequency (HF) is set to 54.24 MHz with high frequency voltage of 100 V. The simulations yield the two-dimensional profiles of plasma components as well as the charge densities, electric field, electron temperature and ionization rate between symmetric parallel plate electrodes. The effects of low and high frequency sources parameters such as frequency values and applied voltage amplitude on the discharge characteristics are investigated. It is shown that the increase of the HF frequency causes a moderate increase of electron temperature and plasma density, whereas, the increase of the LF potential produced an increase in the plasma potential, the voltage of the sheath and the ion energy.
Autors: Rebiai, S.;Bahouh, H.;Sahli, S.;
Appeared in: IEEE Transactions on Dielectrics and Electrical Insulation
Publication date: Oct 2013, volume: 20, issue:5, pages: 1616 - 1624
Publisher: IEEE
 
» 2012 IEEE Visualization Contest Winner: Visualizing Polarization Domains in Barium Titanate
Abstract:
The winners of the 2012 IEEE Visualization Contest combined methods from molecular, flow, and scalar data visualization to reveal the characteristics and processes in the contest data. Because the simulated material didn't behave according to theory from textbooks, one challenge was to find meaningful visualizations to facilitate exploratory analysis. The contest winners created an interactive visual-analysis application based on MegaMol, their visualization framework. The tailored visualizations revealed data characteristics such as thermal vibrations and the spatial distribution of polarization domains. Domain expert knowledge verified the results. This video at http://youtu.be/RXnNKekY7VE shows the dataset used and the development of vector clusters over time.
Autors: Scharnowski, Katrin;Krone, Michael;Sadlo, Filip;Beck, Philipp;Roth, Johannes;Trebin, Hans-Rainer;Ertl, Thomas;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Oct 2013, volume: 33, issue:5, pages: 9 - 17
Publisher: IEEE
 
» 2013 distinguished lecturers & tutorials
Abstract:
Lists AESS lecturers and tutorials presented in 2013.
Autors: Fabrizio, Joe;
Appeared in: IEEE Aerospace and Electronic Systems Magazine
Publication date: Oct 2013, volume: 28, issue:10, pages: 47 - 47
Publisher: IEEE
 
» 250-GHz Passive Harmonic Mode-Locked Er-Doped Fiber Laser by Dissipative Four-Wave Mixing With Silicon-Based Micro-Ring
Abstract:
We propose and demonstrate a 250-GHz high-repetition-rate mode-locked Er-doped fiber laser, which utilizes a silicon micro-ring resonator (SMRR). The SMRR acts as an optical comb filter to help achieve passive mode-locking through the dissipative four-wave-mixing effect induced by a piece of high nonlinear fiber. A short section of polarization-maintaining fiber is inserted in the cavity to induce birefringence filtering to significantly enhance the stability of the proposed laser through the combined effects of optical filtering and nonlinear spectral broadening. The laser can operate about 2 and 6 nm in the case of 1.48-ps and 875-fs output pulsewidth, with 3-dB bandwidth, respectively. The laser can remain mode locked, during our measurement time, without any cavity length or temperature feedback control.
Autors: Jyu, S.-S.;Yang, L.-G.;Wong, C.-Y.;Yeh, C.-H.;Chow, C.-W.;Tsang, H.-K.;Lai, Y.;
Appeared in: IEEE Photonics Journal
Publication date: Oct 2013, volume: 5, issue:5, pages: 1 - 7
Publisher: IEEE
 
» 28-nm 2T High- Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes
Abstract:
A new two-transistor embedded resistive RAM (RRAM) cell with fully Taiwan Semiconductor Manufacturing Company 28-nm CMOS logic compatible process is reported. The new 28-nm logic compatible RRAM cell consists of two logic standard high- metal gate (HKMG) CMOS transistors with a composite resistive gate dielectric of TiN/ /Si as a resistive memory storage node. Using one of the transistor gates as a source line in RRAM SET/RESET operation, the resistive memory states can be efficiently read and sensed by selecting the other transistor gate and its corresponding bitline. Therefore, the new 2T embedded RRAM cell has realized a logic nonvolatile memory (NVM) solution with cost effective, and fully compatible with 28-nm HKMG CMOS logic platforms. Besides, through adapting the existing high- gate dielectric in the RRAM cell, the embedded memory cell does not need any additional deposition of resistive film or extra process steps and it will be very scalable and compatible with the fast progress of CMOS technologies in embedded NVM applications. Furthermore, its low voltage requirement makes this cell conveniently fit in logic intellectual properties and circuits for local data storages or level trimming devices on system-on-chip logic NVM products.
Autors: Mei, C.Y.;Shen, W.C.;Wu, C.H.;Chih, Y.-D.;King, Y.-C.;Lin, C.J.;Tsai, M.-J.;Tsai, K.-H.;Chen, F.T.;
Appeared in: IEEE Electron Device Letters
Publication date: Oct 2013, volume: 34, issue:10, pages: 1253 - 1255
Publisher: IEEE
 
» 28-nm 2T High- Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes
Abstract:
A new two-transistor embedded resistive RAM (RRAM) cell with fully Taiwan Semiconductor Manufacturing Company 28-nm CMOS logic compatible process is reported. The new 28-nm logic compatible RRAM cell consists of two logic standard high- metal gate (HKMG) CMOS transistors with a composite resistive gate dielectric of TiN/ /Si as a resistive memory storage node. Using one of the transistor gates as a source line in RRAM SET/RESET operation, the resistive memory states can be efficiently read and sensed by selecting the other transistor gate and its corresponding bitline. Therefore, the new 2T embedded RRAM cell has realized a logic nonvolatile memory (NVM) solution with cost effective, and fully compatible with 28-nm HKMG CMOS logic platforms. Besides, through adapting the existing high- gate dielectric in the RRAM cell, the embedded memory cell does not need any additional deposition of resistive film or extra process steps and it will be very scalable and compatible with the fast progress of CMOS technologies in embedded NVM applications. Furthermore, its low voltage requirement makes this cell conveniently fit in logic intellectual properties and circuits for local data storages or level trimming devices on system-on-chip logic NVM products.
Autors: Mei, C.Y.;Shen, W.C.;Wu, C.H.;Chih, Y.-D.;King, Y.-C.;Lin, C.J.;Tsai, M.-J.;Tsai, K.-H.;Chen, F.T.;
Appeared in: IEEE Electron Device Letters
Publication date: Oct 2013, volume: 34, issue:10, pages: 1253 - 1255
Publisher: IEEE
 
» 3-D Localization Method for a Magnetically Actuated Soft Capsule Endoscope and Its Applications
Abstract:
In this paper, we present a 3-D localization method for a magnetically actuated soft capsule endoscope (MASCE). The proposed localization scheme consists of three steps. First, MASCE is oriented to be coaxially aligned with an external permanent magnet (EPM). Second, MASCE is axially contracted by the enhanced magnetic attraction of the approaching EPM. Third, MASCE recovers its initial shape by the retracting EPM as the magnetic attraction weakens. The combination of the estimated direction in the coaxial alignment step and the estimated distance in the shape deformation (recovery) step provides the position of MASCE in 3-D. It is experimentally shown that the proposed localization method could provide 2.0–3.7 mm of distance error in 3-D. This study also introduces two new applications of the proposed localization method. First, based on the trace of contact points between the MASCE and the surface of the stomach, the 3-D geometrical model of a synthetic stomach was reconstructed. Next, the relative tissue compliance at each local contact point in the stomach was characterized by measuring the local tissue deformation at each point due to the preloading force. Finally, the characterized relative tissue compliance parameter was mapped onto the geometrical model of the stomach toward future use in disease diagnosis.
Autors: Yim, S.;Sitti, M.;
Appeared in: IEEE Transactions on Robotics
Publication date: Oct 2013, volume: 29, issue:5, pages: 1139 - 1151
Publisher: IEEE
 
» 3D for the Web
Abstract:
This special issue features three articles on interactive 3D developments for the Web. Two articles discuss exploiting GPU ubiquity and performance; the other applies current Web3D languages to a real-world education challenge.
Autors: Macedonia, Michael;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Oct 2013, volume: 33, issue:5, pages: 24 - 25
Publisher: IEEE
 
» 4-Gb/s Parallel Receivers With Adaptive FEXT Cancellation by Pulse Width and Amplitude Calibrations
Abstract:
Two 4-Gb/s parallel receivers with adaptive far-end crosstalk (FEXT) cancellation are presented, which requires a calibration mode. A digitally controlled high-pass filter and a variable-gain amplifier are used to generate the crosstalk cancellation (XTC) signal. The pulse width and amplitude of the XTC signal are automatically calibrated to match the FEXT signal for different channel spacing. It is expected to minimize the residual FEXT signal. Two receivers using the proposed adaptive XTC are fabricated in 40-nm CMOS technology and the core area occupies 0.045 . The power consumption from a 0.9-V supply is 19.8 mW. For two 4-Gb/s PRBS of passing through FR4 PCB traces with 5-in long and 8-mil spacing, the measured peak-to-peak jitter of data is reduced by 27.78 ps by using the proposed adaptive XTC.
Autors: Lin, Y.-Y.;Liu, S.-I.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Oct 2013, volume: 60, issue:10, pages: 622 - 626
Publisher: IEEE
 
» 50 years in the development of insulating liquids
Abstract:
The role of electrical insulation is critical for the proper operation of electrical equipment. Power equipment cannot operate without energy losses, which lead to rises in temperature. It is therefore essential to dissipate the heat generated by the energy losses, especially under high load conditions. Failing to do so results in premature aging, and ultimately to failure of the equipment. Heat dissipation can be achieved by circulating certain liquids, which also ensure electrical insulation of energized conductors. The insulating-fluids market is therefore likely to be dominated by liquids, leaving to gases (such as compressed air and SF6) limited applications in power equipment such as circuit breakers and switchgear [1]-[3]. Several billion liters of insulating liquids are used worldwide in power equipment such as transformers (power, rectifier, distribution, traction, furnace, potential, current) [4], resistors [5], reactors [6], capacitors [7], cables [8], bushings [9], circuit breakers [10], tap changers [11], thyristor cooling in power electronics, etc. [12]. In addition to their main functions of protecting solid insulation, quenching arc discharges, and dissipating heat, insulating liquids can also act as acoustic dampening media in power equipment such as transformers. More importantly, they provide a convenient means of routine evaluation of the condition of electrical equipment over its service life. Indeed, liquids play a vital role in maintaining the equipment in good condition (like blood in the human body). In particular they are responsible for the functional serviceability of the dielectric (insulation) system, the condition of which can be a decisive factor in determining the life span of the equipment [13]. Testing the physicochemical and electrical properties of the liquids can provide information on incipient electrical and mechanical failures. In some equipment, liquid samples can be obtained without service interruption.
Autors: Fofana, I.;
Appeared in: IEEE Electrical Insulation Magazine
Publication date: Oct 2013, volume: 29, issue:5, pages: 13 - 25
Publisher: IEEE
 
» 50 years of electrical-stress control in cable accessories
Abstract:
Maxwell and Felici developed the theoretical basis of geometrical stress control during the period 1846 to 1862. The first practical implementation, however, was that of Nagel in Germany in 1906 (Figure 1). He developed the socalled Nagel-bushing on the basis of conductive layers [1]. Around the same time, the Swiss professor Kuhlmann invented the refractive method [2]. His aim was to decrease the electrical stress at the points where it was highest, rather than distributing it to other areas. The famous Rogowski profile was introduced in 1923. The basic principles are the same today, although the applications have become more complex, and stress control is still an important research area in HV engineering. Developments in stress control during the last 50 years (Figure 1) have been due mainly to new materials and production processes, and modern technologies, which have made possible to create cable accessories of more compact design and to improve their reliability. These developments have included impedance stress control based on heat-shrinkable tubing, and nonlinear stress control. In both cases the driving force was the need to improve the stress-control system of cable accessories.
Autors: Eigner, A.;Semino, S.;
Appeared in: IEEE Electrical Insulation Magazine
Publication date: Oct 2013, volume: 29, issue:5, pages: 47 - 55
Publisher: IEEE
 
» 50th Anniversary of the Light-Emitting Diode (LED): An Ultimate Lamp [Scanning the Issue]
Abstract:
The articles in this special issue focus on the history and development of light emitting diode (LED) technology and industry applications over the last fifty years.
Autors: Craford, M.G.;Dupuis, R.D.;Feng, M.;Kish, F.A.;Laskar, J.;
Appeared in: Proceedings of the IEEE
Publication date: Oct 2013, volume: 101, issue:10, pages: 2154 - 2157
Publisher: IEEE
 
» 6 Degree-of-Freedom Motion Estimation of a Moving Target using Monocular Image Sequences
Abstract:
A novel estimation method for the 6 degree-of-freedom (6-DOF) motion of a target moving with slowly varying velocity is proposed, which is based on the monocular image sequences from a moving camera. The homography matrix for moving targets is derived. It is shown that the dynamic model of the target in 6-DOF motion can be described as a linear time-varying system. Consequently, the Kalman filter can be directly applied. Our estimation method does not need a priori information of target depth or size. The observability condition of our estimator is much milder than that of the previously known bearings-only tracking methods.
Autors: Kwon, Jeong-Hoon;Song, Eun-Han;Ha, In-Joong;
Appeared in: IEEE Transactions on Aerospace and Electronic Systems
Publication date: Oct 2013, volume: 49, issue:4, pages: 2818 - 2827
Publisher: IEEE
 
» 60th Anniversary of the IEEE IAS PCIC [History]
Abstract:
For the first time since 1981, the IEEE Industry Applications Society (IAS) Petroleum and Chemical Industry Committee (PCIC) annual conference will be held in Chicago. Scheduled for 23 September, this will be the 60th PCIC annual conference. In view of these noteworthy aspects, it seems appropriate to review the history of the PCIC.
Autors: Bried, R.;
Appeared in: IEEE Industry Applications Magazine
Publication date: Oct 2013, volume: 19, issue:5, pages: 8 - 13
Publisher: IEEE
 
» 64-Channel UWB Wireless Neural Vector Analyzer SOC With a Closed-Loop Phase Synchrony-Triggered Neurostimulator
Abstract:
An ultra wideband (UWB) 64-channel responsive neural stimulator system-on-chip (SoC) is presented. It demonstrates the first on-chip neural vector analyzer capable of wirelessly monitoring magnitude, phase and phase synchronization of neural signals. In a closed-loop, abnormal phase synchrony triggers the programmable-waveform biphasic current-mode neural stimulator. To implement these functionalities, the SoC integrates 64 neural recording amplifiers with tunable switched-capacitor (SC) bandpass filters, 64 multiplying 8-bit SAR ADCs, 64 programmable 16-tap FIR filters, a tri-core CORDIC processor, 64 biphasic current stimulation channels, and a 3.1–10.6 GHz UWB wireless transmitter onto a 4 mm × 3 mm 0.13 µm CMOS die. To minimize both the area and power dissipation of the SoC, the SAR ADC is re-used as a multiplier for FIR filtering and as a DAC and duty cycle controller for the biphasic neural stimulator. The SoC has been validated in the early detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line.
Autors: Abdelhalim, K.;Jafari, H.M.;Kokarovtseva, L.;Velazquez, J.L.P.;Genov, R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2013, volume: 48, issue:10, pages: 2494 - 2510
Publisher: IEEE
 
» 8-bit 5-MS/s Analog-to-Digital Converter for Pixel-Level Integration
Abstract:
A pixel-level 8-bit 5-MS/s Wilkinson-type analog-to-digital converter was designed and fabricated in the IBM 8M1P 130-nm CMOS technology. The pixel blocks are implemented with a core area of 130 by 140 , consuming about 560 at 1.2 V. Taking the measured dynamic range of 0.86 V into account, a signal-to-noise ratio above 65 dB was achieved for small signal amplitudes. The maximum differential and integral nonlinearity remains well below 0.4 LSB and 0.5 LSB, respectively. The conversion time is 160 ns, and the energy per conversion step 470 fJ. The digitizer permits the trimming of gain and offset.
Autors: Hansen, K.;Reckleben, C.;Kalavakuru, P.;Szymanski, J.;Diehl, I.;
Appeared in: IEEE Transactions on Nuclear Science
Publication date: Oct 2013, volume: 60, issue:5, pages: 3843 - 3851
Publisher: IEEE
 
» 850-nm Edge-Illuminated Si Photodiodes Fabricated With CMOS-MEMS Technology
Abstract:
This letter examines edge-illuminated silicon photodiodes (PDs) fabricated using standard CMOS technology operated at 850-nm wavelength. A micro-electro-mechanical systems (MEMS) process was employed to expose the illuminated surface and achieve edge illumination. A single-mode lensed fiber is employed to inject light into the depletion region of the PD directly, limiting and reducing the diffusive carriers within the bulk Si substrate. Through employing this procedure, this letter achieved a superior performance in the 3-dB bandwidth compared with that yielded by vertically illuminated PDs. The 5.4 GHz high bandwidth was obtained using an edge-illuminated PD with a 20 15.6 active region.
Autors: Hsieh, Y.-C.;Chou, F.-P.;Wang, C.-W.;Huang, C.-A.;Hsin, Y.-M.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Oct 2013, volume: 25, issue:20, pages: 2018 - 2021
Publisher: IEEE
 
» 915-MHz FSK/OOK Wireless Neural Recording SoC With 64 Mixed-Signal FIR Filters
Abstract:
A system-on-chip (SoC) neural recording interface with 64 channels, 64 16-tap programmable mixed-signal FIR filters and a fully integrated 915 MHz OOK/FSK PLL-based wireless transmitter is presented. Each recording channel has a fully differential amplifier with 54 dB gain and utilizes a tunable low-distortion subthreshold MOS-resistor to reject DC offsets with an input-referred noise of 6.5 µV and a CMRR of 75 dB. Each channel contains a modified 8-bit SAR ADC with an ENOB of 7.8-bits and can provide analog-digital multiplication by modifying the the sampling phase of the ADC. It is used in conjunction with 12-bit digital adders and registers to implement 64 programmable transposed FIR filters. The 915 MHz FSK/OOK transmitter offers data rates up to 1.5 Mbps and a maximum output power of 0 dBm. The 4×3 mm² chip fabricated in a 0.13 µm CMOS process dissipates 5.03 mW from a 1.2 V supply. Experimental measurements characterize the electrical performance of the wireless SoC. In vivo measurement results from freely moving rats are also presented.
Autors: Abdelhalim, K.;Kokarovtseva, L.;Perez Velazquez, J.L.P.;Genov, R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2013, volume: 48, issue:10, pages: 2478 - 2493
Publisher: IEEE
 
» 98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits
Abstract:
Recently, short-distance high-speed wireless communication using a 60 GHz band has been studied for mobile application. To realize higher-speed wireless communication while maintaining low power consumption for mobile application D band (110–170 GHz) is promising since it can potentially provide a wider frequency band. Thus, we have studied D-band CMOS circuits to realize low-power ultrahigh-speed wireless communication. In the D band, however, since no sufficient device model is provided, research generally has to start from device modeling. In this paper, a design procedure for D-band CMOS circuits is overviewed from the device layer to the system layer, where the architecture is optimized to realize both low power and high data transfer rate. Finally, a 10 Gbps wireless transceiver with a power consumption of 98 mW is demonstrated using the 135 GHz band.
Autors: Fujishima, M.;Motoyoshi, M.;Katayama, K.;Takano, K.;Ono, N.;Fujimoto, R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2013, volume: 48, issue:10, pages: 2273 - 2284
Publisher: IEEE
 
» -Optimal Actuator Location
Abstract:
Pub DtlIn many control applications, there is freedom to place the actuators. The actuator location should be chosen to optimize certain performance objectives. In this paper, -performance with state-feedback is considered. That is, both the controller and the actuator locations are chosen to minimize the effect of disturbances on the output. A framework for calculating -optimal actuator locations is developed. Conditions for well-posedness of the -optimal actuator location problem are presented. Many optimal actuator problems involve systems modelled by partial differential equations and conditions under which approximations yield reliable results are given. A derivative-free optimization algorithm to calculate -optimal actuator locations is described. The results are illustrated using several examples.
Autors: Kasinathan, D.;Morris, K.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Oct 2013, volume: 58, issue:10, pages: 2522 - 2535
Publisher: IEEE
 
» A 0.18 Biosensor Front-End Based on Noise, Distortion Cancelation and Chopper Stabilization Techniques
Abstract:
This paper presents a novel sensor front-end circuit that addresses the issues of noise and distortion in a unique way by using canceling techniques. The proposed front-end is a fully differential transimpedance amplifier (TIA) targeted for current mode electrochemical biosensing applications. In this paper, we discuss the architecture of this canceling based front-end and the optimization methods followed for achieving low noise, low distortion performance at minimum current consumption are presented. To validate the employed canceling based front-end, it has been realized in a 0.18 CMOS process and the characterization results are presented. The front-end has also been tested as part of a complete wireless sensing system and the cyclic voltammetry (CV) test results from electrochemical sensors are provided. Overall current consumption in the front-end is 50 while operating on a 1.8 V supply.
Autors: Balasubramanian, V.;Ruedi, P.-F.;Temiz, Y.;Ferretti, A.;Guiducci, C.;Enz, C.C.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Oct 2013, volume: 7, issue:5, pages: 660 - 673
Publisher: IEEE
 
» A 0.18- m CMOS Dual-Band Frequency Synthesizer With Spur Reduction Calibration
Abstract:
This letter presents a 0.18 m CMOS dual-band frequency synthesizer with charge-pump current mismatch calibration to reduce reference spurs. To enhance calibration accuracy the high-resolution phase detector (HRPD) is incorporated in this work. The measured output spur level is less than dBc after the calibration circuits are activated and the reference spur reduction is more than 5.6 dB throughout the whole frequency range. The frequency synthesizer draws 16 mA from a 1.8 V power supply, and the covered frequency bands are 5.18–5.32 GHz and 5.74–5.82 GHz.
Autors: Chen, Y.-W.;Yu, Y.-H.;Chen, Y.-J.E.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Oct 2013, volume: 23, issue:10, pages: 551 - 553
Publisher: IEEE
 
» A 0.18- m CMOS Dual-Band Frequency Synthesizer With Spur Reduction Calibration
Abstract:
This letter presents a 0.18 m CMOS dual-band frequency synthesizer with charge-pump current mismatch calibration to reduce reference spurs. To enhance calibration accuracy the high-resolution phase detector (HRPD) is incorporated in this work. The measured output spur level is less than dBc after the calibration circuits are activated and the reference spur reduction is more than 5.6 dB throughout the whole frequency range. The frequency synthesizer draws 16 mA from a 1.8 V power supply, and the covered frequency bands are 5.18–5.32 GHz and 5.74–5.82 GHz.
Autors: Chen, Y.-W.;Yu, Y.-H.;Chen, Y.-J.E.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Oct 2013, volume: 23, issue:10, pages: 551 - 553
Publisher: IEEE
 
» A 0.5 V PWM CMOS Imager With 82 dB Dynamic Range and 0.055% Fixed-Pattern-Noise
Abstract:
This paper presents a 0.5 V operated pulse-width modulation (PWM) CMOS imager with threshold-variation canceling (TVC) and programmable current-controlled threshold (PCCT) schemes implemented in 0.18 µm CMOS technology. The proposed TVC scheme efficiently improves the fixed-pattern-noise (FPN) issue caused by process variation in conventional PWM sensors. The limited dynamic range in ultra-low-voltage operated sensor can be extended by 56.5 dB with the proposed PCCT operation. The measurement results of the prototype chip show an array FPN of 0.055%, a column FPN of 0.016%, a dark random noise of 0.65 LSB, and a dynamic range (DR)of 82 dB. The total chip consumes 4.95 uW and 29.6 µW at 11.8 fps and 78.5 fps, which achieves an iFOM of 163.9 pW/f-p and 147.3 pW/f-p, respectively.
Autors: Chung, M.-T.;Lee, C.-L.;Yin, C.;Hsieh, C.-C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2013, volume: 48, issue:10, pages: 2522 - 2530
Publisher: IEEE
 
» A 0.7-V 17.4- W 3-Lead Wireless ECG SoC
Abstract:
This paper presents a fully integrated sub-1 V 3-lead wireless ECG System-on-Chip (SoC) for wireless body sensor network applications. The SoC includes a two-channel ECG front-end with a driven-right-leg circuit, an 8-bit SAR ADC, a custom-designed 16-bit microcontroller, two banks of 16 kb SRAM, and a MICS band transceiver. The microcontroller and SRAM blocks are able to operate at sub-/near-threshold regime for the best energy consumption. The proposed SoC has been implemented in a standard 0.13- m CMOS process. Measurement results show the microcontroller consumes only 2.62 pJ per instruction at 0.35 V . Both microcontroller and memory blocks are functional down to 0.25 V. The entire SoC is capable of working at single 0.7-V supply. At the best case, it consumes 17.4 W in heart rate detection mode and 74.8 W in raw data acquisition mode under sampling rate of 500 Hz. This makes it one of the best ECG SoCs among state-of-the-art biomedical chips.
Autors: Khayatzadeh, M.;Zhang, X.;Tan, J.;Liew, W.-S.;Lian, Y.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Oct 2013, volume: 7, issue:5, pages: 583 - 592
Publisher: IEEE
 
» A 0.8-V 230- W 98-dB DR Inverter-Based Modulator for Audio Applications
Abstract:
This paper presents a modulator based on a gain-boost class-C inverter for audio applications. The gain-boost class-C inverter behaves as a low-voltage subthreshold amplifier and boosts its dc gain for the high-precision requirement. Meanwhile, an on-chip body bias is used to compensate the performance degradation of the inverter at a slow process corner or low supply voltage. The proposed inverter-based modulator is fabricated in a 65-nm mixed-signal CMOS process with a die area of 0.3 mm . The experimental chip achieves 91-dB peak signal-to-noise-plus-distortion ratio (SNDR), 94-dB signal-to-noise ratio (SNR) and 98-dB dynamic range (DR) over a 20-KHz audio band with a 5-MHz sampling frequency and a 0.8-V supply voltage consuming only 230- W power, which demonstrates that the gain-boost class-C inverter is particularly suitable for low-voltage micro-power high-resolution applications.
Autors: Luo, H.;Han, Y.;Cheung, R.C.C.;Liu, X.;Cao, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2013, volume: 48, issue:10, pages: 2430 - 2441
Publisher: IEEE
 
» A 1–3-GHz Digitally Controlled Dual-RF Input Power-Amplifier Design Based on a Doherty-Outphasing Continuum Analysis
Abstract:
Pub DtlThis paper presents a linear multi-harmonic analysis method to evaluate the performance of digitally controlled dual RF-input power amplifiers (PAs). The method enables, due to its low computational cost, optimization of PA efficiency and bandwidth in a complex design space involving two independent inputs. Under the idealized assumption of short-circuited higher harmonics, the analysis is used to prove the existence of a Doherty-outphasing continuum, featuring high average efficiency over 100% fractional bandwidth. With this result as a foundation, a combiner incorporating microwave transistor parasitics is analyzed without assuming short-circuited higher harmonics, showing that high average efficiencies are also achievable under more realistic conditions. A PA is straightforwardly designed from these calculation results using two 15-W GaN HEMTs. The simulated layout-ready (large-signal transistor model) PA average drain efficiency exceeds 50% over 1.1–3.7 GHz for a 6.7-dB peak-to-average power-ratio WCDMA signal. The measured PA has a maximum output power of dBm and a 6-dB output power back-off (OPBO) power-added efficiency (PAE) of 45% over 1–3 GHz. After applying digital pre-distortion, excellent linearity is demonstrated when transmitting the WCDMA signal, resulting in an adjacent channel leakage power ratio lower than dBc with corresponding average PAE of 50% and 40% at 1.2 and 2.3 GHz, respectively. This is, to the authors' knowledge, the most wideband OPBO efficiency enhanced PA reported to date, proving the effectiveness of employing linear multi-harmonic analysis in dual-input PA design.
Autors: Andersson, C.M.;Gustafsson, D.;Chani Cahuana, J.;Hellberg, R.;Fager, C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Oct 2013, volume: 61, issue:10, pages: 3743 - 3752
Publisher: IEEE
 
» A 1.2-V 8.3-nJ CMOS Humidity Sensor for RFID Applications
Abstract:
This paper presents a fully integrated CMOS humidity sensor for a smart RFID sensor platform. The sensing element is a CMOS-compatible capacitive humidity sensor, which consists of top-metal finger-structure electrodes covered by a humidity-sensitive polyimide layer. Its humidity-sensitive capacitance is digitized by an energy-efficient capacitance-to-digital converter (CDC) based on a third-order delta-sigma modulator. This CDC employs current-efficient operational transconductance amplifiers based on current-starved cascoded inverters, whose limited output swing is accommodated by employing a feedforward loop-filter topology. A programmable offset capacitor is included to remove the sensor's baseline capacitance and thus reduce the required dynamic range. To reduce offset errors due to charge injection of the switches, the entire system is auto-zeroed. The proposed humidity sensor has been realized in a 0.16- CMOS technology. Measurement results show that the CDC performs a 12.5-bit capacitance-to-digital conversion in a measurement time of 0.8 ms, while consuming only 8.6 from a 1.2-V supply. This corresponds to a state-of-the-art figure-of-merit of 1.4 pJ/conversion-step. Combined with the co-integrated humidity sensing element, it provides a resolution of 0.05% RH in the range from 30% RH to 100% RH while consuming only 8.3 nJ per measurement, which is an order-of-magnitude less energy than the state-of-the-art.
Autors: Tan, Z.;Daamen, R.;Humbert, A.;Ponomarev, Y.V.;Chae, Y.;Pertijs, M.A.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2013, volume: 48, issue:10, pages: 2469 - 2477
Publisher: IEEE
 
» A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings
Abstract:
This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended to be used in high speed bit-serial Low Voltage Differential Signaling (LVDS) Address Event Representation (AER) chip grids, where short (like 32-bit) sparse data packages are transmitted. Voltage-Mode drivers require intrinsically half the power of their Current-Mode counterparts and do not require Common-Mode Voltage Control. However, for fast ON/OFF switching a special high-speed voltage regulator is required which needs to be kept ON during data pauses, and hence its power consumption must be minimized, resulting in tight design constraints. A proof-of-concept chip test prototype has been designed and fabricated in low-cost standard 0.35 m CMOS. At mV voltage swing with 500 Mbps serial bit rate and 32 bit events, current consumption scales from 15.9 mA (7.7 mA for the driver and 8.2 mA for the receiver) at 10 Mevent/s rate to 406 A ( 343 A for the driver and 62.5 A for the receiver) for an event rate below 10 Kevent/s, therefore achieving a rate dependent power saving of up to 40 times, while keeping switching times at 1.5 ns. Maximum achievable event rate was 13.7 Meps at 638 Mbps serial bit rate. Additionally, differential voltage swing is tunable, thus allowing further power reductions.
Autors: Zamarreno-Ramos, C.;Kulkarni, R.;Silva-Martinez, J.;Serrano-Gotarredona, T.;Linares-Barranco, B.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Oct 2013, volume: 7, issue:5, pages: 722 - 731
Publisher: IEEE
 
» A 10 Watt S-Band MMIC Power Amplifier With Integrated 100 MHz Switch-Mode Power Supply and Control Circuitry for Active Electronically Scanned Arrays
Abstract:
The integration of a Switch-Mode Power Supply (SMPS) with a High Power Amplifier (HPA) offers various benefits for application in array antennas for radar purposes. Among the most distinct advantages are removal of a single point of failure from the antenna system, individual bias control for local efficiency optimization, the high switching frequency which separates the spurious contributions from the carrier and the improved control of the HPA supply voltage rise- and fall times. The latter provides the possibility to control the RF pulse shapes thereby reducing the temporal side lobes and enhancing the output signal spectrum. An S-band HPA with integrated SMPS is designed, fabricated and tested. The SMPS includes the control circuitry for the switches. The SMPS is optimized to operate at a switching frequency of 100 MHz. The MMIC delivers an output power of 10 W with an HPA efficiency of more than 40% and an SMPS efficiency of more than 75%. This paper presents an overview of the design aspects and the obtained results.
Autors: van der Bent, G.;de Hek, P.;Geurts, S.;Telli, A.;Brouzes, H.;Besselink, M.;van Vliet, F.E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2013, volume: 48, issue:10, pages: 2285 - 2295
Publisher: IEEE
 
» A 100-Channel 1-mW Implantable Neural Recording IC
Abstract:
Pub DtlThis paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18- standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.
Autors: Zou, X.;Liu, L.;Cheong, J.H.;Yao, L.;Li, P.;Cheng, M.-Y.;Goh, W.L.;Rajkumar, R.;Dawe, G.S.;Cheng, K.-W.;Je, M.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Oct 2013, volume: 60, issue:10, pages: 2584 - 2596
Publisher: IEEE
 
» A 155 W 88-dB DR Discrete-Time Modulator for Digital Hearing Aids Exploiting a Summing SAR ADC Quantizer
Abstract:
This paper presents a low-power switched-capacitor modulator for digital hearing-aid applications that features a novel summing successive approximation (SAR). The summing SAR performs multi-bit quantization together with the analog addition required in feed-forward (FF) modulator topologies, with no attenuation of the input signals and no need for amplifiers. The prototype is implemented in a 0.18- m CMOS technology and its measurements demonstrate a dynamic range of 88 dB in 10 kHz bandwidth while consuming 155 W from a 1.8 V supply. The combined use of passive addition and SAR quantization reduces the complexity and power consumption of the modulator. The summing SAR ADC quantizer results in a calculated power saving of 40% when compared to a multi-bit FF M using active addition and flash quantization.
Autors: Porrazzo, S.;Morgado, A.;San Segundo Bello, D.;Cannillo, F.;Van Hoof, C.;Yazicioglu, R.F.;van Roermund, A.H.M.;Cantatore, E.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Oct 2013, volume: 7, issue:5, pages: 573 - 582
Publisher: IEEE
 
» A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory
Abstract:
To improve the reliability of MLC NAND flash memory, this paper presents an energy-efficient high-throughput architecture for decoding concatenated-BCH (CBCH) codes. As the data read from the flash memory is hard-decided in practical applications, the proposed CBCH decoding method is a promising solution to achieve both high error-correction capability and energy efficiency. In the proposed CBCH decoding, the number of on-chip memory accesses consuming much energy is minimized by computing and updating syndromes two-dimensionally. To achieve an area-efficient hardware realization, row and column decoders are unified into one decoder and some syndromes are computed when they are needed. In addition, the decoding throughput is enhanced remarkably by skipping redundant decoding processes. Based on the proposed CBCH decoding architecture, a prototype chip is implemented in a 65-nm CMOS process to decode the (70528, 65536) CBCH code. The proposed decoder provides a decoding throughput of 17.7 Gb/s and an energy efficiency of 2.74 pJ/bit, being vastly superior to the state-of-the-art architectures.
Autors: Lee, Y.;Yoo, H.;Jung, J.;Jo, J.;Park, I.-C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2013, volume: 48, issue:10, pages: 2531 - 2540
Publisher: IEEE
 
» A 200-GHz Inductively Tuned VCO With 7-dBm Output Power in 130-nm SiGe BiCMOS
Abstract:
Pub DtlA highly efficient push–push voltage-controlled oscillator (VCO) with a new inductive frequency tuning topology for (sub) terahertz frequencies is presented. The tuning technique is based on a variable inductance seen at the emitter node of a base-degenerated transistor. The variable inductor exhibits high quality factor and high tuning range due to the tunable transistor transconductance via bias current. Fabricated in a 0.13- SiGe BiCMOS process, the VCO achieves a tuning range of 3.5% and an output power of 7.2 dBm at 201.5 GHz. The dc power consumption of the VCO is 30 mW, resulting in a high dc to RF power efficiency of 0.6% and a figure of merit of 165, which is the highest FoM for any silicon-based VCO reported to date at this frequency range. To demonstrate the functionality of the tuning technique, three VCO prototypes at different oscillation frequencies, including one operating in the 222.7–229-GHz range, are implemented and measured.
Autors: Chiang, P.-Y.;Momeni, O.;Heydari, P.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Oct 2013, volume: 61, issue:10, pages: 3666 - 3673
Publisher: IEEE
 
» A 252- , 16.7-Million-Frames-Per-Second 312-kpixel Back-Side-Illuminated Ultrahigh-Speed Charge-Coupled Device
Abstract:
We developed a 312-kpixel back-side-illuminated ultrahigh-speed charge-coupled device (CCD) that has a sensitivity of 252 and is capable of operating at 16.7 Mfps. The potential profile of the pixel was designed by using a 3-D semiconductor device simulator. The high sensitivity results from the unit having fill factor and time aperture ratios of 100% and a high optical utilization ratio. Its sensitivity is 12.7 times that of a front-side-illuminated image sensor. Ultrahigh-speed shooting was enabled by an in situ storage image sensor. By reducing the wiring resistance and dividing the image area into eight blocks, a maximum frame rate of 16.7 Mfps was attained. The total pixel count is 760 horizontally and 411 vertically. The burst capturing speed is thus 5.2 Tpixel/s, making it the fastest imaging device to date.
Autors: Arai, T.;Yonai, J.;Hayashida, T.;Ohtake, H.;van Kuijk, H.;Etoh, T.G.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Oct 2013, volume: 60, issue:10, pages: 3450 - 3458
Publisher: IEEE
 
» A 3-D Finite-Element Eigenvalue Analysis of Slow-Wave Structures of Traveling-Wave Tubes Without Matching Meshes
Abstract:
A novel 3-D finite-element modeling technique without matching meshes for the eigenvalue analysis of arbitrary lossy slow-wave structures (SWSs) of traveling-wave tubes is presented. By simulating two examples, it is shown that the cold parameters of SWSs can be accurately and quickly obtained without matching meshes when using this technique. Moreover, a new second-order transverse electric periodic boundary condition (PBC) is proposed to improve the modeling efficiency of lossy SWSs in the nonmatching meshes case, and this technique is very suitable for application of the rotated PBC. This technique would make the modeling of SWSs more flexible, cheaper, and more efficient.
Autors: Xu, L.;Yang, Z.-H.;Li, J.-Q.;Li, B.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Oct 2013, volume: 61, issue:10, pages: 3524 - 3528
Publisher: IEEE
 
» A 3-D Self-Organized Leader Propagation Model and Its Engineering Approximation for Lightning Protection Analysis
Abstract:
This paper presents a 3-D self-organized model of a downward stepped leader in negative cloud-to-ground lightning. In the model, the characteristic features of stepped leaders are generalized, so that parameters, such as the charge density along with the leader channel, leader corona sheath radius, leader step length, step time interval, and step advance speed, are calculated. Stepwise growth of the 3-D leader channel is developed stochastically. Parameters predicted by the model are qualitatively compatible with observation results, while the engineering approximation of the model for convenient lightning protection analysis is derived thereafter. The model is operated under various conditions at different leader initiation heights and electric potentials. Based on statistics of the simulation results, analytical relationships between the height and potential of leader initiation in the cloud and the charge distribution along the leader channel are approximated. Moreover, the lightning striking distance to flat ground is defined and calculated. Depending on the present model, the striking distance is found to be well associated with the charge density (or electrical potential) of the leader tip near to ground rather than the total charge in the leader channel. Based on appropriate physical understanding, the striking distance is connected to the return stroke peak current.
Autors: Xu, Y.;Chen, M.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Oct 2013, volume: 28, issue:4, pages: 2342 - 2355
Publisher: IEEE
 
» A 35-to-83 GHz Multiconductor-Lines Signal Combiner for High Linear and Wideband Mixer
Abstract:
This letter proposes a broadband and low-loss multiconductor-lines signal combiner in 90 nm CMOS. The signal combiner consists of one broadside-coupled balun, two broadband in-phase power dividers, one edge-coupled balun, and four impedance-transformation lines. By using thin-film microstrip lines to avoid the loss from silicon substrate, the signal combiner has a simulated insertion loss of 8.1 dB and port-to-port isolations better than 42 dB from 35 to 83 GHz. The signal combiner is then integrated into a source-pumped mixer, and a conversion gain and a 13 dBm average input IP3 at a 6.5 mW total dc power are achieved in measurements.
Autors: Chiou, H.-K.;Chou, H.-T.;Liang, C.-J.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Oct 2013, volume: 23, issue:10, pages: 548 - 550
Publisher: IEEE
 
» A 4-Gbps POF Receiver Using Linear Equalizer With Multi-Shunt-Shunt Feedbacks in 65-nm CMOS
Abstract:
This brief describes the design of a monolithic plastic optical fiber (POF) receiver with a pair of 250-by-250 m N-well/P-sub photodetectors (PDs). A two-stage continuous-time linear equalizer that utilizes multiple active shunt-shunt feedback networks has been proposed to compensate for the slow-rolling-off high-frequency losses of the PDs. A test chip has been implemented in a standard 65-nm CMOS process, and it consists of a transimpedance amplifier, a variable-gain amplifier, a linear equalizer, a limiting amplifier, and an output buffer. The receiver consumes an active chip area of 0.24 and a dc power of 46 mW (excluding auxiliary test circuits and the output buffer) from a 1-V power supply. The prototype POF receiver demonstrates a non-return-to-zero data rate of 4 Gbit/s with a bit error rate less than , at a peak-to-peak optical input power of 3.2 dBm p-p (average input power is kept at 3 dBm).
Autors: Dong, Y.;Martin, K.W.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Oct 2013, volume: 60, issue:10, pages: 617 - 621
Publisher: IEEE
 
» A 4-Path 42.8-to-49.5 GHz LO Generation With Automatic Phase Tuning for 60 GHz Phased-Array Receivers
Abstract:
This paper presents a 4-path LO generation system with automatic phase tuning for 60 GHz phased-array receivers. Each path employs a linear phase-shift generation chain composed of an injection-locked-oscillator-based phase shifter cascaded with an injection-locked frequency tripler. The frequency tripler with a proposed locking-range enhancement technique is employed to relax both the frequency and the phase shift of the phase shifter for high linearity and low power. Finally, a novel successive-approximation algorithm is proposed to perform automatic phase detection and tuning. Fabricated in a 65 nm CMOS process and occupying a core area of 1.4 2.0 mm², the proposed 4-path LO generation system measures linear phase shift range larger than ±90°, amplitude variation within ±0.4 dB, phase resolution of 22.5°, and maximum phase errors of 22.0° and 1.5° before and after automatic phase calibration while drawing a current of 85 mA from a 1-V supply.
Autors: Wu, L.;Li, A.;Luong, H.C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2013, volume: 48, issue:10, pages: 2309 - 2322
Publisher: IEEE
 
» A 4th Order 3.6 GS/s RF ADC With a FoM of 1 pJ/bit
Abstract:
Pub DtlA 4th order RF LC-based ADC clocked at 3.6 GHz and centered at 900 MHz is presented. A simple design methodology is used to derive a robust architecture with a minimum number of feedback coefficients. The simplicity of the ADC architecture results in a significant performance enhancement and power consumption reduction. An efficient algorithm for the tuning and calibration of the LC-based loop filter is also presented. The ADC, suitable for cognitive Software Defined Radio applications, is implemented in a standard 130 nm CMOS technology. It achieves a 52 dB SFDR and a 50 dB SNR in a 28 MHz BW and consumes only 15 mW from a 1.2 V supply. The Figure of Merit of the ADC is 1.0 pJ/bit, which is to date the best reported FoM for an RF ADC. The effect of the clock jitter on the ADC performance is also measured and presented.
Autors: Ashry, A.;Aboushady, H.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Oct 2013, volume: 60, issue:10, pages: 2606 - 2617
Publisher: IEEE
 
» A 4th-order band-pass filter using differential readout of two in-phase actuated contour-mode resonators
Abstract:
A 4th-order band-pass filter (BPF) based on the subtraction of two 2nd-order contour-mode Lamb-wave resonators is presented. The resonators have slightly different resonance frequencies around 380 MHz. Each resonator consists of a 500 nm pulsed-laser deposited lead zirconate titanate (PZT) thin-film on top of a 3 μm silicon (PZT-on-Si). The resonators are actuated in-phase, and their outputs are subtracted. Utilizing this technique, the feed-through signals are eliminated while the outputs of the resonators are added up constructively, due to the phase difference between the two output signals. The BPF is presented using 50 Ω termination with a bandwidth of approximately 3.9 MHz and 43 dB stopband rejection. This technique provides further opportunities for MEMS filter design in addition to existing methods, i.e., mechanical and/or electrical coupling. It also resolves the design issue associated with high feed-through when exploiting piezoelectric materials with high-dielectric constant like PZT.
Autors: Yagubizade, Hadi;Darvishi, Milad;Elwenspoek, Miko C.;Tas, Niels R.;
Appeared in: Applied Physics Letters
Publication date: Oct 2013, volume: 103, issue:17, pages: 173517 - 173517-4
Publisher: IEEE
 
» A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS
Abstract:
A 60-GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. To boost the amplifier performance at millimeter-wave (mmWave) frequencies, a new transistor layout is proposed to minimize the device and interconnect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve the power gain and stability. The transformer-based power-combining PA consists of two unit amplifiers, operating in Class AB for better back-off efficiency. To further reduce the power consumption and hence extend battery lifetime, one unit PA is tuned off in low-power mode. A switch is used to short the output of this non-operating unit PA to reduce the combiner loss and improve the efficiency. The PA achieves a measured saturated output power of 17.0 dBm (12.1 dBm) and 1-dB compressed power of 13.8 dBm (9.1 dBm) in the high-power (low-power) mode. The power-added efficiencies (PAEs) at and are 30.3% and 21.6% respectively for the high-power mode. Compared to Class A, the PA operating in Class AB shows 5.3% improvement in measured PAE at with no compromise in linearity. The PA with the power combiner only occupies an active area of 0.074 mm . The reliability measurements are also conducted and the PA has an estimated lifetime of 80613 hours.
Autors: Zhao, D.;Reynaert, P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2013, volume: 48, issue:10, pages: 2323 - 2337
Publisher: IEEE
 
» A 90–100-GHz Phased-Array Transmit/Receive Silicon RFIC Module With Built-In Self-Test
Abstract:
Pub DtlThis paper presents the first built-in self-test system (BIST) for -band transmit–receive phased-array modules. Low-loss high-isolation switches are attached to the RF input and output ports using transmission-line sections, which result in a high shunt impedance when the BIST is disabled and minimal penalty in additional loss. A -band in-phase/quadrature down-conversion mixer/receiver with 0.5-dB amplitude and 4 –5 phase imbalance at 90–100 GHz is also implemented on-chip and is used as an on-chip vector network analyzer. The BIST allows the measurement of the normalized in both transmit and receive modes with high accuracy (4-bit phase response, 0.5-dB amplitude variation) at 90–100 GHz without any external calibration. The BIST also results in a normalized frequency response that agrees well with the measured -parameters at 90–100 GHz.
Autors: Inac, O.;Golcuk, F.;Kanar, T.;Rebeiz, G.M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Oct 2013, volume: 61, issue:10, pages: 3774 - 3782
Publisher: IEEE
 
» A 0.5% Precision On-Chip Frequency Reference With Programmable Switch Array for Crystal-Less Applications
Abstract:
An on-chip frequency reference is designed for low-power, low-cost, and fully integrated system-on-chip designs. In this relaxation oscillator, pseudodifferential architecture is used to eliminate frequency variation caused by bias current, and interleaving capacitors are implemented to extend its discharge time. A low-leakage programmable switch array (PSA) trimming method is proposed to calibrate the first- and second-order temperature coefficients (TCs) of the composite resistor. The oscillator was fabricated in a 0.35- 2P4M CMOS process with an area of 0.162 . The oscillator operates at 130 kHz, and measurement results show that it achieves a frequency variation of less than 0.5% over a temperature range of –100 and less than 0.4% over a supply voltage range of 1–3 V.
Autors: Lu, Y.;Yuan, G.;Der, L.;Ki, W.-H.;Yue, C.P.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Oct 2013, volume: 60, issue:10, pages: 642 - 646
Publisher: IEEE
 
» A Beam Switching Quasi-Yagi Dipole Antenna
Abstract:
A high gain beam switching pattern reconfigurable quasi-Yagi dipole antenna is presented for wireless local area network (WLAN) systems at 5.2 GHz. The antenna consists of a microstrip-to-coplanar stripline (CPS) balun, the length of which can be controlled by using PIN diodes. The change of the length of the balun allows the currents on the two arms of the dipole to have different phase differences, thereby making the antenna operate at three states with the E-plane maximum beam direction towards 20 , , and 0 , respectively. In order to validate the design method, a prototype of the proposed antenna with a practical biasing network was fabricated and measured. Measured results on the reflection coefficients, radiation patterns, and realized gains for three operating states are provided, which agree well with the numerical simulations.
Autors: Qin, P.-Y.;Guo, Y.J.;Ding, C.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Oct 2013, volume: 61, issue:10, pages: 4891 - 4899
Publisher: IEEE
 
» A Bistable Electrostatic Silicon Nanofin Relay for Nonvolatile Memory Application
Abstract:
We present a nanoelectromechanical (NEM) relay that is capable of demonstrating two stable states without on-hold power due to the influence of van der Waals force. This is realized by leveraging a silicon nanofin (SiNF) as a relay that can switch between two lateral terminals. The smallest dimension of the SiNF is 80-nm width by 2- length. The SiNF is able to maintain its geometrical position even after the bias voltage is turned off. Bistable hysteresis behavior with pull-in voltage and reset voltage as low as 8.4 and 10.1 V is measured. The nanoscale footprint of this device shows great potential for high-density nonvolatile memory applications.
Autors: Soon, B.;Ng, E.J.;Singh, N.;Tsai, J.M.;Qian, Y.;Le, C.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Oct 2013, volume: 22, issue:5, pages: 1004 - 1006
Publisher: IEEE
 
» A Boundary Difference Method for Electromagnetic Scattering Problems With Perfect Conductors and Corners
Abstract:
Boundary integral equations (BIE) are widely used in applied electromagnetics, with the boundary element method (BEM) typically employed for numerical solution. The paper extends the recently proposed boundary difference method (BDM)—an alternative to BEM—to electromagnetic scattering problems with perfect conductors and with corners. BDM shares several key features and advantages of BEM but avoids the singular kernels inherent in BIE. Convergence rates of the method established via numerical experiments are in agreement with the theoretical predictions.
Autors: Alkhateeb, O.;Tsukerman, I.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Oct 2013, volume: 61, issue:10, pages: 5117 - 5126
Publisher: IEEE
 
» A bulge-induced dehydration failure mode of nanocomposite hydrogel
Abstract:
Since hydrogels are very soft and usually weak in swollen state, they pose unique challenges to traditional mechanical experiments. The mechanical property of nanocomposite poly(N-isopropylacrylamide) hydrogel was characterized by the bulge test in this investigation. A dehydration failure phenomenon of the hydrogel was found and the failure mechanism was presented. A criterion is proposed that when strain reaches the threshold, water molecules migrate out of the polymer networks and the dehydration failure occurs. The critical strain keeps constant for orifices with different diameters. This failure mode can be applied in the controllable release of drugs.
Autors: Tang, Jingda;Yu, Zejun;Sun, Youyi;Pei, Yongmao;Fang, Daining;
Appeared in: Applied Physics Letters
Publication date: Oct 2013, volume: 103, issue:16, pages: 161903 - 161903-4
Publisher: IEEE
 
» A Canonical UTD Solution for Electromagnetic Scattering by an Electrically Large Impedance Circular Cylinder Illuminated by an Obliquely Incident Plane Wave
Abstract:
A uniform geometrical theory of diffraction (UTD) solution is developed for the canonical problem of the electromagnetic (EM) scattering by an electrically large circular cylinder with a uniform impedance boundary condition (IBC), when it is illuminated by an obliquely incident high frequency plane wave. A solution to this canonical problem is first constructed in terms of an exact formulation involving a radially propagating eigenfunction expansion. The latter is converted into a circumferentially propagating eigenfunction expansion suited for large cylinders, via the Watson transform, which is expressed as an integral that is subsequently evaluated asymptotically, for high frequencies, in a uniform manner. The resulting solution is then expressed in the desired UTD ray form. This solution is uniform in the sense that it has the important property that it remains continuous across the transition region on either side of the surface shadow boundary. Outside the shadow boundary transition region it recovers the purely ray optical incident and reflected ray fields on the deep lit side of the shadow boundary and to the modal surface diffracted ray fields on the deep shadow side. The scattered field is seen to have a cross-polarized component due to the coupling between the and waves (where is the cylinder axis) resulting from the IBC. Such cross-polarization vanishes for normal incidence on the cylinder, and also in the deep lit region for oblique incidence where it properly reduces to the geometrical optics (GO) or ray optical solution. This UTD solution is shown to be very accurate by a numerical comparison with an exact reference solution.
Autors: Aguilar, A.G.;Pathak, P.H.;Sierra-Perez, M.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Oct 2013, volume: 61, issue:10, pages: 5144 - 5154
Publisher: IEEE
 
» A Chance Constrained Programming Approach to Determine the Optimal Disassembly Sequence
Abstract:
Disassembly planning is aimed to perform the optimal disassembly sequence given a used or obsolete product in terms of cost and environmental impact. However, the actual disassembly process of products can experience great uncertainty due to a variety of unpredictable factors. To deal with such uncertainty, this work presents some chance constrained programming models for disassembly cost from the perspective of stochastic planning. Moreover, two hybrid intelligent algorithms, namely, one integrating stochastic simulation and neural network (NN), and another integrating stochastic simulation, genetic algorithm (GA) and neural network (NN), are proposed to solve the proposed models, respectively. Some numerical examples are given to illustrate the proposed models and the effectiveness of proposed algorithms.
Autors: Tian, G.;Zhou, M.;Chu, J.;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Oct 2013, volume: 10, issue:4, pages: 1004 - 1013
Publisher: IEEE
 
» A Charge-Pump-Based Current Feedback Method for AMOLED Displays
Abstract:
This work presents a new external driving scheme that uses the current feedback method with a 3T1C pixel circuit. The proposed circuit provides a stable OLED driving current by compensating for the threshold voltage shift of amorphous-silicon thin-film transistors (a-Si TFTs). For fabricated a-Si TFTs and the 0.35 m CMOS process associated with the proposed driving scheme, measurements reveal that the normalized OLED current degradation is less than 5% after 60 hours of operation at 60 C. Moreover, for a data line load of 1.69 K /110 pF, the relative error rates between data currents and OLED currents are less than 4% within a settling time of 19 .
Autors: Lin, C.-L.;Chang, F.-C.;Lai, P.-C.;Chen, P.-S.;Chang, W.-Y.;
Appeared in: Journal of Display Technology
Publication date: Oct 2013, volume: 9, issue:10, pages: 783 - 786
Publisher: IEEE
 
» A Cloud-Oriented Content Delivery Network Paradigm: Modeling and Assessment
Abstract:
Cloud-oriented content delivery networks (CCDNs) constitute a promising alternative to traditional content delivery networks. Exploiting the advantages and principles of the cloud, such as the pay as you go business model and geographical dispersion of resources, CCDN can provide a viable and cost-effective solution for realizing content delivery networks and services. In this paper, a hierarchical framework is proposed and evaluated toward an efficient and scalable solution of content distribution over a multiprovider networked cloud environment, where inter and intra cloud communication resources are simultaneously considered along with traditional cloud computing resources. To efficiently deal with the CCDN deployment problem in this emerging and challenging computing paradigm, the problem is decomposed to graph partitioning and replica placement problems while appropriate cost models are introduced/adapted. Novel approaches on the replica placement problem within the cloud are proposed while the limitations of the physical substrate are taken into consideration. The performance of the proposed hierarchical CCDN framework is assessed via modeling and simulation, while appropriate metrics are defined/adopted associated with and reflecting the interests of the different identified involved key players.
Autors: Papagianni, C.;Leivadeas, A.;Papavassiliou, S.;
Appeared in: IEEE Transactions on Dependable and Secure Computing
Publication date: Oct 2013, volume: 10, issue:5, pages: 287 - 300
Publisher: IEEE
 
» A CMOS 77-GHz Receiver Front-End for Automotive Radar
Abstract:
Pub DtlThis paper presents the design of a receiver (Rx) front-end for automotive radar application operating at 76–77 GHz. The Rx employs a double conversion architecture, which consists of a five-stage low-noise amplifier (LNA), a sub-harmonic mixer (SHM), and a double-balanced passive mixer (PSM). By adopting this architecture, millimeter-wave frequency synthesizer design can be relaxed. In the LNA layout, the output of each stage is positioned close to the input of the follow stage, thus creating a resonance load. As a result, complex interstage matching networks is simplified. The SHM driven by a 38-GHz local oscillator (LO) is adopted to avoid push/pull effect and power consumption of the voltage-controlled oscillator. A PSM is utilized for the second conversion since it consumes no dc current and has low flickering noise. To connect the singled-ended LNA and SHM, a 77-GHz balun is designed; and for driving the SHM, two 38-GHz baluns and an in-phase/quadrature coupler to provide quadrature 38-GHz LO are designed. The proposed Rx is implemented in a 65-nm CMOS technology and measurement results show 16-dB voltage gain and 13-dB calculated noise figure while dissipating 23.5 mA from a black 1.2-V supply.
Autors: Le, V.H.;Duong, H.T.;Huynh, A.T.;Ta, C.M.;Zhang, F.;Evans, R.J.;Skafidas, E.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Oct 2013, volume: 61, issue:10, pages: 3783 - 3793
Publisher: IEEE
 
» A CMOS High Speed Multi-Modulus Divider With Retiming for Jitter Suppression
Abstract:
A new asynchronous high speed multi-modulus divider (MMD) architecture is presented in this letter. This new architecture significantly reduces the delay of the critical path, which not only pushes to ultra-high speed operation, but also allows retiming techniques to suppress jitter accumulation from the divider chain simultaneously. A prototype in a 65 nm CMOS technology has demonstrated an improved speed over three times compared with a conventional MMD and a reduced phase noise about 8.4 dB due to a retiming scheme. To the authors' best knowledge, this MMD has demonstrated to date the highest operating frequency static MMD with retiming function in CMOS. Due to its static implementation, this MMD can operate from 19 GHz down to close to dc with programmable division ratios from 16 to 31. This MMD consumes 39.8 mW power and occupies 0.011 chip area.
Autors: Gu, Q.J.;Gao, Z.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Oct 2013, volume: 23, issue:10, pages: 554 - 556
Publisher: IEEE
 
» A CMOS Wideband Highly Linear Low-Noise Amplifier for Digital TV Applications
Abstract:
Pub DtlThis paper presents a highly linear wideband differential low-noise amplifier (LNA) for digital TV applications. The proposed LNA is a modified version of the wideband LNA reported by Bruccoleri in 2004. In order to increase the linearity of Bruccoleri 's LNA, the Volterra series is adopted to identify the nonlinear components and the noise-cancelling circuit is modified to eliminate the whole nonlinear components. Implemented in 0.13- CMOS technology, the proposed wideband LNA has a gain of 12.4 dB and a noise figure of 1.6 dB, as determined from measurements, while drawing 18.45 mA from a 1.2-V supply. The proposed LNA has an of 16.6 dBm with 6-MHz frequency offset at 100 MHz, far exceeding the values of existing wideband LNAs.
Autors: Bae, J.-Y.;Kim, S.;Cho, H.-S.;Lee, I.-Y.;Ha, D.S.;Lee, S.-G.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Oct 2013, volume: 61, issue:10, pages: 3700 - 3711
Publisher: IEEE
 
» A Collusion-Resistant Conditional Access System for Flexible-Pay-Per-Channel Pay-TV Broadcasting
Abstract:
Pay-TV broadcasting system is an extensively deployed application that charges users based on their subscription. To ensure security for the Pay-TV broadcasting application, a conditional access system (CAS) is designed to control TV channel/program access to only the authorized subscribers. Several key management schemes with a four-level hierarchical key structure have been proposed. In this paper, we point out a severe security weakness of these schemes against collusion attacks. Then we propose a new CAS scheme with a three-level hierarchical key structure using ciphertext-policy attribute-set-based encryption (ASBE), an extension of ciphertext-policy attribute-based encryption (CP-ABE). Our scheme achieves scalable, flexible, fine-grained, and most importantly, collusion-resistant access control for Pay-TV broadcasting applications. The proposed scheme is designed to support all operations in Pay-TV applications. We then provide a detailed analysis on security and performance of our scheme. We also implement the scheme and it is showed to be both efficient and flexible for Pay-TV broadcasting applications.
Autors: Wan, Z.;Liu, J.;Zhang, R.;Deng, R.H.;
Appeared in: IEEE Transactions on Multimedia
Publication date: Oct 2013, volume: 15, issue:6, pages: 1353 - 1364
Publisher: IEEE
 
» A Combined Wavelet-Based Mesh-Free Method for Solving the Forward Problem in Electrical Impedance Tomography
Abstract:
In this paper, a combined wavelet-based mesh-free method is suggested to solve the forward problem in electrical impedance tomography (EIT). EIT is a noninvasive imaging modality based on the reconstruction of the conductivity profile inside a solution domain. The forward problem simulates measurement data for comparing with experimental data in the inverse problem. The forward problem can be solved by the finite element method (FEM) or the mesh-free method. Since the solution of the FEM depends on the mesh shape and boundary condition constraints are difficult to be applied to the mesh-free method, the combined wavelet-based mesh-free approach can resolve the disadvantages of both methods in the EIT forward problem. In order to apply interface conditions between different regions, slope jump functions are entered to the set of basis functions. Two different 2-D EIT problems are modeled. The simulation results obtained by the combined wavelet-based mesh-free method are compared with the FEM in terms of accuracy and computational cost. Moreover, the effects of object movement and deformation are investigated on the accuracy of the simulated electrode voltages using the standard FEM and combined wavelet-based mesh-free method.
Autors: Yousefi, M.R.;Jafari, R.;Moghaddam, H.A.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Oct 2013, volume: 62, issue:10, pages: 2629 - 2638
Publisher: IEEE
 
» A Compact 94 GHz Image Substrate Integrated Non-Radiative Dielectric (iSINRD) Waveguide Cruciform Coupler
Abstract:
Pub DtlThis letter presents a study of image substrate integrated dielectric (iSINRD) guide arms at 94 GHz, from which a cruciform 3 dB coupler is conceived by superimposing their respective reflection coefficients. Four configurations are analyzed by investigating the boundary value problem in light of the electric and magnetic symmetries of the iSINRD guide. Mode conversion, and thus double bends, is totally avoided thanks to the PEC image plane. Thus, in addition to being planar, the coupler is very compact which makes it easily integrable in millimeter-wave circuits. The lateral dimensions of each arm are 0.413 0.635 . Perforation is done using square air-vias, each having a side length of 0.35 mm. The total size of the circuit is 4.413 4.413 . Measured results agree well with simulated ones. A coupling level of 3.5 dB and isolation better than 17 dB are obtained for a bandwidth of 15%.
Autors: Attari, J.;Djerafi, T.;Wu, K.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Oct 2013, volume: 23, issue:10, pages: 533 - 535
Publisher: IEEE
 
» A compact rotating dilution refrigerator
Abstract:
We describe the design and performance of a new rotating dilution refrigerator that will primarily be used for investigating the dynamics of quantized vortices in superfluid 4He. All equipment required to operate the refrigerator and perform experimental measurements is mounted on two synchronously driven, but mechanically decoupled, rotating carousels. The design allows for relative simplicity of operation and maintenance and occupies a minimal amount of space in the laboratory. Only two connections between the laboratory and rotating frames are required for the transmission of electrical power and helium gas recovery. Measurements on the stability of rotation show that rotation is smooth to around 10-3 rad s-1 up to angular velocities in excess of 2.5 rad s-1. The behavior of a high-Q mechanical resonator during rapid changes in rotation has also been investigated.
Autors: Fear, M.J.;Walmsley, P.M.;Chorlton, D.A.;Zmeev, D.E.;Gillott, S.J.;Sellers, M.C.;Richardson, P.P.;Agrawal, H.;Batey, G.;Golov, A.I.;
Appeared in: Review of Scientific Instruments
Publication date: Oct 2013, volume: 84, issue:10, pages: 103905 - 103905-6
Publisher: IEEE
 
» A Compact, Low Input Capacitance Neural Recording Amplifier
Abstract:
Conventional capacitively coupled neural recording amplifiers often present a large input load capacitance to the neural signal source and hence take up large circuit area. They suffer due to the unavoidable trade-off between the input capacitance and chip area versus the amplifier gain. In this work, this trade-off is relaxed by replacing the single feedback capacitor with a clamped T-capacitor network. With this simple modification, the proposed amplifier can achieve the same mid-band gain with less input capacitance, resulting in a higher input impedance and a smaller silicon area. Prototype neural recording amplifiers based on this proposal were fabricated in 0.35 CMOS, and their performance is reported. The amplifiers occupy smaller area and have lower input loading capacitance compared to conventional neural amplifiers. One of the proposed amplifiers occupies merely 0.056 . It achieves 38.1-dB mid-band gain with 1.6 pF input capacitance, and hence has an effective feedback capacitance of 20 fF. Consuming 6 , it has an input referred noise of 13.3 over 8.5 kHz bandwidth and NEF of 7.87. In-vivo recordings from animal experiments are also demonstrated.
Autors: Ng, K.A.;Xu, Y.P.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Oct 2013, volume: 7, issue:5, pages: 610 - 620
Publisher: IEEE
 
» A Comparative Analysis of Low-Level Radio Frequency Interference in SMOS and Aquarius Microwave Radiometer Measurements
Abstract:
Measurements of both the Soil Moisture and Ocean Salinity (SMOS) and Aquarius L-band microwave radiometers show a significant presence of radio frequency interference (RFI), although they operate in a protected frequency band where transmission is prohibited. RFI detection and mitigation remain a challenging problem for both missions, especially for low or moderate (i.e., on the order of 10 K or less) amplitude contributions. An algorithm for low-level source detection and mitigation is already included in Aquarius data sets, and both Aquarius and SMOS have distinct attributes that can potentially enable further improvements in detection and mitigation of these sources to some degree. The combination of SMOS and Aquarius data sets may enable further future improvements as well. Initial efforts toward this goal are reported in this paper. Similarities and differences in RFI effects on SMOS and Aquarius are examined, with a particular focus on instrument properties that cause differences in received RFI power in SMOS and Aquarius observations of a specific source. A study is also performed of SMOS observations for regions reported by Aquarius to contain “low-level” RFI. It is shown that the detection of these sources in the SMOS data set is challenging and that the dependence of the SMOS third and fourth Stokes parameters on incidence angle makes the polarimetric features of SMOS difficult to utilize for low-level source detection. However, an angular fitting procedure suggested previously in the literature can, in some cases, detect such sources in horizontal and vertical polarizations.
Autors: Aksoy, M.;Johnson, J.T.;
Appeared in: IEEE Transactions on Geoscience and Remote Sensing
Publication date: Oct 2013, volume: 51, issue:10, pages: 4983 - 4992
Publisher: IEEE
 
» A comparative study of principal component analysis and independent component analysis in eddy current pulsed thermography data processing
Abstract:
Eddy Current Pulsed Thermography (ECPT), an emerging Non-Destructive Testing and Evaluation technique, has been applied for a wide range of materials. The lateral heat diffusion leads to decreasing of temperature contrast between defect and defect-free area. To enhance the flaw contrast, different statistical methods, such as Principal Component Analysis and Independent Component Analysis, have been proposed for thermography image sequences processing in recent years. However, there is lack of direct and detailed independent comparisons in both algorithm implementations. The aim of this article is to compare the two methods and to determine the optimized technique for flaw contrast enhancement in ECPT data. Verification experiments are conducted on artificial and thermal fatigue nature crack detection.
Autors: Bai, Libing;Gao, Bin;Tian, Shulin;Cheng, Yuhua;Chen, Yifan;Tian, Gui Yun;Woo, W.L.;
Appeared in: Review of Scientific Instruments
Publication date: Oct 2013, volume: 84, issue:10, pages: 104901 - 104901-11
Publisher: IEEE
 
» A Compiler Design Technique for Impulsive VDD Current Minimization
Abstract:
For electromagnet interference (EMI) optimization issues, different hardware-level techniques have been proposed. This paper focuses on an EMI optimization technique via a software-level technique. We propose a novel estimation and optimization tool for reducing conducted EMI at specified frequency by compiler technology. This study is not a research on compiler technique but an adaption of computer science-domain technology to EMI optimization research. The proposed tool can accept C language syntax and generate many versions of assembly programs. These assembly programs perform the same functionality defined by the input C program but with different conducted EMI behaviors when they are executed. The proposed tool can estimate, select, and generate the assembly program with the least amount of conducted EMI released during its execution. The experiment results show that the proposed tool can analyze test C-programs and generate lower EMI assembly programs. Currently, compared to a commercial compiler, the proposed technique can decrease conducted EMI by 2–5 dB at any specified frequency.
Autors: Yuan, S.-Y.;Su, W.-B.;Ni, G.-K.;Chi, T.-Y.;Kuo, S.-Y.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Oct 2013, volume: 55, issue:5, pages: 855 - 866
Publisher: IEEE
 
» A Computationally Efficient Iterative MLE for GPS AOA Estimation
Abstract:
This paper presents a computationally efficient algorithm for GPS signal angle of arrival (AOA) estimation based on an iterative maximum likelihood estimator (iMLE) operating on an antenna array output. The iMLE has global convergence and therefore can estimate the true AOA MLE, regardless of the initial value, and has a simple mathematical form without any derivative or matrix decomposition computation. Simulations are performed for signals with different antenna array parameters, and the performances are compared with that of conventional MUSIC and CAPON methods. The results demonstrate that the iMLE can achieve better noise performance even with a small number of antenna elements. The paper also presents a tracking mode for the iMLE that further improves its performance for signals with low signal-to-noise ratio (SNR) and greatly extends its application into weak GPS signal or multipath environments.
Autors: Chen, Xin;Morton, Yu;Dovis, Fabio;
Appeared in: IEEE Transactions on Aerospace and Electronic Systems
Publication date: Oct 2013, volume: 49, issue:4, pages: 2707 - 2716
Publisher: IEEE
 
» A Constrained Coding Approach to Error-Free Half-Duplex Relay Networks
Abstract:
We show that the broadcast capacity of an infinite-depth tree-structured network of error-free half-duplex-constrained relays can be achieved using constrained coding at the source and symbol forwarding at the relays.
Autors: Kschischang, F.R.;Lutz, T.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Oct 2013, volume: 59, issue:10, pages: 6258 - 6260
Publisher: IEEE
 
» A Current-Density Centric Logical Effort Delay and Power Model for High-Speed CML Gates
Abstract:
Pub DtlThis paper presents a logical effort delay and power model for high-speed current-mode logic (CML) circuits. Current density centric and voltage swing dependent logical effort parameters are defined in terms of the characteristic current density for peak transistor cutoff frequency, which remains relatively constant across different technology nodes. Based on this model, constant and non-constant current density biasing schemes in data-paths of CML circuits are investigated and optimized for delay, power, and energy-delay metrics. The proposed model is simple yet sufficiently accurate for technology nodes in the constant-field scaling regime.
Autors: Kapoor, A.;Hu, Y.;Bashirullah, R.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Oct 2013, volume: 60, issue:10, pages: 2618 - 2630
Publisher: IEEE
 
» A Cyberoperations Program
Abstract:
To conduct cyberoperations, not only must you understand computers, networks, and protocols, you must also determine what circumstances actions may be taken in and who can take them. In addition, you must consider strategies and policies as well as those actions' possible side effects, in both cyberspace and the natural world. At the US Naval Postgraduate School and elsewhere, educators are preparing computer science graduates to meet these challenges.
Autors: Irvine, Cynthia;
Appeared in: IEEE Security & Privacy
Publication date: Oct 2013, volume: 11, issue:5, pages: 66 - 69
Publisher: IEEE
 
» A Differential Evolution-Based Algorithm to Schedule Flexible Assembly Lines
Abstract:
Scheduling is key towards improving the performance of a Flexible Assembly Line (FAL). In this paper, a Bilevel Differential Evolution (BiDE) algorithm to solve a FAL scheduling problem is proposed. The BiDE algorithm optimizes the performance of the FAL with respect to two criteria: the weighted sum of Earliness/Tardiness (E/T) penalties and the balance of the FAL. The performance of BiDE is evaluated using the data sets available in the literature and an evolutionary heuristic algorithm published earlier called BiGA. The experimental results show that the BiDE algorithm can solve the FAL scheduling problem effectively and exhibits a superior performance over BiGA.
Autors: Vincent, L;Ponnambalam, S.G.;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Oct 2013, volume: 10, issue:4, pages: 1161 - 1165
Publisher: IEEE
 
» A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band
Abstract:
In this paper, a digital time domain equalizer (TDE) for 60 GHz radio frequency transmission systems is presented. Significantly, the TDE supports both single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) operation modes for digital baseband receiver. In order to improve the performance, the proposed TDE adopts Golay sequence aided one-shot channel estimation and modified multi-path interference cancellation (MPIC) equalization. Targeting on the line-of-sight (LOS) channel characteristic, MPIC is simplified with single-tap for complexity reduction. From the area efficiency point of view, both SC and OFDM modes are designed within a single hardware to yield 99% of area sharing. The Golay-MPIC TDE structure is realized as feed-forward data path with 8X-parallelism to achieve 2.64 GS/s at 330 MHz clock rate. The Golay-MPIC TDE is fabricated as a part of a digital baseband with 65 nm 1P9M general purpose process. The area of Golay-MPIC TDE occupies 1.05 with 405 K gate counts. Besides, the power dissipations for SC and ODFM modes are 56.71 mW@220 MHz (1 V) and 91.29 mW@330 MHz (1.1 V), respectively. Finally, the chip can provide the maximum throughput 15.84 Gb/s (2.64 GS/s with 64-QAM modulation).
Autors: Liu, W.-C.;Yeh, F.-C.;Wei, T.-C.;Chan, C.-D.;Jou, S.-J.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Oct 2013, volume: 60, issue:10, pages: 2730 - 2739
Publisher: IEEE
 
» A Digital Monolithic Active Pixel Sensor Chip in a Quadruple-Well CIS Process for Tracking Applications
Abstract:
A CMOS sensor chip for charged particle detection has been developed and submitted for fabrication in a 0.18 m Quadruple-Well (N&P-Wells, Deep N&P-Wells) CMOS Image Sensor (CIS) process. Improvement of the radiation hardness, the power dissipation and the readout speed of the mainstream CMOS sensors is expected with the exploration of this process. In order to ensure better charge collection and neutron tolerance, wafers with high-resistivity epitaxial layer have been chosen. In this paper a digital CMOS sensor prototype developed in order to validate the key analog blocks (from sensing element to 1-bit digital conversion) of a binary Monolithic Active Pixel Sensor (MAPS) in this process will be presented. The digital sensor prototype comprises four different sub-arrays of 20 m pitch 64 32 pixels, 128 column-level auto-zeroed discriminators, a sequencer and an output digital multiplexer. Laboratory tests results including the charge-to-voltage conversion factor, the charge collection efficiency, the temporal noise and the fixed-pattern noise are presented in details. Some irradiation results will also be given.
Autors: Degerli, Y.;Bertolone, G.;Claus, G.;Dorokhov, A.;Dulinski, W.;Goffe, M.;Guilloux, F.;Hu-Guo, Ch.;Jaaskelainen, K.;Morel, F.;Orsini, F.;Specht, M.;Winter, M.;
Appeared in: IEEE Transactions on Nuclear Science
Publication date: Oct 2013, volume: 60, issue:5, pages: 3899 - 3906
Publisher: IEEE
 
» A Direct 100 GHz Parametric CMOS Tripler
Abstract:
The first direct anti-series CMOS tripler is described in this letter. MOS varactors are arranged in a back-to-back configuration free of the self-bias problem that prevents standard Schottky varactors from employing such an arrangement. Implemented in 130 nm CMOS, the circuit achieves a 28 dB conversion loss at 102 GHz with an output power of .
Autors: Kabir, S.;Magierowski, S.;Messier, G.G.;Zhao, Z.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Oct 2013, volume: 23, issue:10, pages: 557 - 559
Publisher: IEEE
 
» A Direct Masking Approach to Robust ASR
Abstract:
Recently, much work has been devoted to the computation of binary masks for speech segregation. Conventional wisdom in the field of ASR holds that these binary masks cannot be used directly; the missing energy significantly affects the calculation of the cepstral features commonly used in ASR. We show that this commonly held belief may be a misconception; we demonstrate the effectiveness of directly using the masked data on both a small and large vocabulary dataset. In fact, this approach, which we term the direct masking approach, performs comparably to two previously proposed missing feature techniques. We also investigate the reasons why other researchers may have not come to this conclusion; variance normalization of the features is a significant factor in performance. This work suggests a much better baseline than unenhanced speech for future work in missing feature ASR.
Autors: Hartmann, W.;Narayanan, A.;Fosler-Lussier, E.;DeLiang Wang;
Appeared in: IEEE Transactions on Audio, Speech, and Language Processing
Publication date: Oct 2013, volume: 21, issue:10, pages: 1993 - 2005
Publisher: IEEE
 

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