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Electrical and Electronics Engineering publications abstract of: 10-2011 sorted by title, page: 0
» 1,3,6,8-Tetrakis[(triisopropylsilyl)ethynyl]pyrene: A highly efficient solid-state emitter for non-doped yellow electroluminescence devices
Abstract:
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Highlights

? A new pyrene derivative is facilely synthesised and fully characterized. It shows intense photoluminescence with unity emission efficiency in solid-state. Highly efficient non-doped organic light-emitting diodes are fabricated based on it.

Autors:

Graphical abstract

A new pyrene derivative exhibits unity solid-state fluorescence eff
Appeared in: Organic Electronics
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» 10 224-Gb/s POLMUX-16QAM Transmission Over 656 km of Large- PSCF With a Spectral Efficiency of 5.6 b/s/Hz
Abstract:
The authors demonstrate the successful transmission of 10 channels with 224-Gb/s POLMUX-16QAM modulation (28 GBaud) on a 37.5-GHz wavelength grid. Using large- pure-silica-core fibers they show a 656-km transmission distance with a spectral efficiency of 5.6 b/s/Hz. They report a back-to-back performance penalty of 3.5 dB compared to theoretical limits at the forward-error correction (FEC) limit (bit-error rate of ), and a margin of 0.5 dB in Q-factor with respect to the FEC limit after 656 km of transmission.
Autors: Sleiffer, V. A. J. M.;Alfiad, M. S.;van den Borne, D.;Kuschnerov, M.;Veljanovski, V.;Hirano, M.;Yamamoto, Y.;Sasaki, T.;Jansen, S. L.;Wuth, T.;de Waardt, H.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Oct 2011, volume: 23, issue:20, pages: 1427 - 1429
Publisher: IEEE
 
» 10 Lessons from 10 Years of Measuring and Modeling the Internet's Autonomous Systems
Abstract:
Formally, the Internet inter-domain routing system is a collection of networks, their policies, peering relationships and organizational affiliations, and the addresses they advertize. It also includes components like Internet exchange points. By its very definition, each and every aspect of this system is impacted by BGP, the de-facto standard inter-domain routing protocol. The element of this inter-domain routing system that has attracted the single-most attention within the research community has been the "inter-domain topology". Unfortunately, almost from the get go, the vast majority of studies of this topology, from definition, to measurement, to modeling and analysis, have ignored the central role of BGP in this problem. The legacy is a set of specious findings, unsubstantiated claims, and ill-conceived ideas about the Internet as a whole. By presenting a BGP-focused state-of-the-art treatment of the aspects that are critical for a rigorous study of this inter-domain topology, we demystify in this paper many "controversial" observations reported in the existing literature. At the same time, we illustrate the benefits and richness of new scientific approaches to measuring, modeling, and analyzing the inter-domain topology that are faithful to the BGP-specific nature of this problem domain.
Autors: Roughan, Matthew;Willinger, Walter;Maennel, Olaf;Perouli, Debbie;Bush, Randy;
Appeared in: IEEE Journal on Selected Areas in Communications
Publication date: Oct 2011, volume: 29, issue:9, pages: 1810 - 1821
Publisher: IEEE
 
» 10-Gb/s Ge/SiGe Multiple Quantum-Well Waveguide Photodetector
Abstract:
The authors report on high speed operation of a Ge/SiGe multiple quantum-well waveguide photodetector. At , 10 Gb/s operation is demonstrated at wavelengths of 1405 and 1420 nm with a responsivity as high as 0.8 A/W. The device, 3 wide and 80 long, exhibits a dark current of 474 nA at a reverse bias of . These results pave the way for the use of Ge/SiGe multiple quantum-well structures as efficient active waveguide devices in silicon compatible integrated circuits.
Autors: Chaisakul, P.;Marris-Morini, D.;Isella, G.;Chrastina, D.;Rouifed, M.-S.;Le Roux, X.;Edmond, S.;Cassan, E.;Coudevylle, J.-R.;Vivien, L.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Oct 2011, volume: 23, issue:20, pages: 1430 - 1432
Publisher: IEEE
 
» 10-Gb/s WDM-PON Based on Low-Bandwidth RSOA Using Partial Response Equalization
Abstract:
An extended reach 10-Gb/s wavelength division multiplexing passive optical network (WDM-PON) system based on a low-bandwidth reflective semiconductor optical amplifier (RSOA) is demonstrated using a novel partial response equalization (PRE) scheme. The proposed technique has good performance-complexity tradeoff compared to traditional equalization methods. The intrinsic feature of the signal directly modulated by RSOA and the impact of dispersion on the modulated signal are investigated. The result shows that the shape of the RF spectrum of the received signal can be predicted. Moreover, one target response can be applied for a wide range of transmission distances by properly setting the equalizer parameters. It is confirmed experimentally and via simulation that the proposed system can achieve good performance over 0 to 75 km fiber link using PRE with the same setup.
Autors: Guo, Q.;Tran, A. V.;Chae, C.-J.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Oct 2011, volume: 23, issue:20, pages: 1442 - 1444
Publisher: IEEE
 
» 1550-nm High-Speed Short-Cavity VCSELs
Abstract:
The latest advances in -nm high-speed short-cavity vertical-cavity surface-emitting lasers (VCSELs) are presented. The electrical, optical, and thermal design of these devices is discussed with respect to their high-speed modulation behavior. The implemented design improvements allow high output powers for ambient temperatures up to , high differential quantum efficiencies up to 40%, temperature-stable single-mode emission, low thermal resistances down to 1.6 K/mW, small-signal modulation bandwidths in excess of 17 GHz, and error-free data transmission at room temperature at data rates of 35 Gb/s in back-to-back configuration and up to 25 Gb/s over 4.2 km of single-mode fiber.
Autors: Muller , M.;Hofmann , W.;Grundl , T.;Horn, M.;Wolf, P.;Nagel, R. D.;Ronneberg, E.;Bohm, G.;Bimberg , D.;Amann, M-.C.;
Appeared in: IEEE Journal of Selected Topics in Quantum Electronics
Publication date: Oct 2011, volume: 17, issue:5, pages: 1158 - 1166
Publisher: IEEE
 
» 1D-Leaky Wave Antenna Employing Parallel-Plate Waveguide Loaded With PRS and HIS
Abstract:
A new type of one-dimensional leaky-wave antenna (LWA) with independent control of the beam-pointing angle and beamwidth is presented. The antenna is based on a simple structure composed of a bulk parallel-plate waveguide (PPW) loaded with two printed circuit boards (PCBs), each one consisting of an array of printed dipoles. One PCB acts as a partially reflective surface (PRS), and the other grounded PCB behaves as a high impedance surface (HIS). It is shown that an independent control of the leaky-mode phase and leakage rate can be achieved by changing the lengths of the PRS and HIS dipoles, thus resulting in a flexible adjustment of the LWA pointing direction and directivity. The leaky-mode dispersion curves are obtained with a simple Transverse Equivalent Network (TEN), and they are validated with three-dimensional full-wave simulations. Experimental results on fabricated prototypes operating at 15 GHz are reported, demonstrating the versatile and independent control of the LWA performance by changing the PRS and HIS parameters.
Autors: Garcia-Vigueras, M.;Gomez-Tornero, J. L.;Goussetis, G.;Weily, A. R.;Guo, Y. J.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Oct 2011, volume: 59, issue:10, pages: 3687 - 3694
Publisher: IEEE
 
» 2-D Digital Predistortion (2-D-DPD) Architecture for Concurrent Dual-Band Transmitters
Abstract:
This paper presents a novel 2-D digital-predistortion (2-D-DPD) technique that is applicable for linearization of concurrent dual-band transmitters. This technique uses a unique way for distortion compensation and linearization of dual-band transmitters by selecting, characterizing, and applying predistortion in each band separately. Compared to conventional linearization techniques, this 2-D-DPD method requires a lower sampling rate for digital-to-analog and analog-to-digital converters. The performance of the 2-D-DPD topology is evaluated using two modulated signals, Worldwide Interoperability for Microwave Access and wideband code-division multiple-access, separated in frequency by 100 MHz. The measurement results show an adjacent channel power ratio of less than 50 dBc and a normalized mean square error of less than 40 dB.
Autors: Bassam, S. A.;Helaoui, M.;Ghannouchi, F. M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Oct 2011, volume: 59, issue:10, pages: 2547 - 2553
Publisher: IEEE
 
» 2-D Inductor-Capacitor Lattice Synthesis
Abstract:
We consider a general class of 2-D passive propagation media, represented as a planar graph where nodes are capacitors connected to a common ground and edges are inductors. Capacitances and inductances are fixed in time but vary in space. Kirchhoff's laws give the time dynamics of voltage and current in the system. By harmonically forcing input nodes and collecting the resulting steady-state signal at output nodes, we obtain a linear, analog device that transforms the inputs to outputs. We pose the lattice synthesis problem: given a linear transformation, find the inductances and capacitances for an inductor-capacitor circuit that can perform this transformation. Formulating this as an optimization problem, we numerically demonstrate its solvability using gradient-based methods. By solving the lattice synthesis problem for various desired transformations, we design several devices that can be used for signal processing and filtering.
Autors: Bhat, H. S.;Osting, B.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Oct 2011, volume: 30, issue:10, pages: 1483 - 1492
Publisher: IEEE
 
» 2011 IEEE Wireless and Microwave Technology Conference [Conference Report]
Abstract:
Autors: Xun Gong;Johnson, W.J.D.;
Appeared in: IEEE Microwave Magazine
Publication date: Oct 2011, volume: 12, issue:6, pages: 152 - 154
Publisher: IEEE
 
» 3-D Analytical Calculation of the Torque Between Perpendicular Magnetized Magnets in Magnetic Suspensions
Abstract:
This paper presents novel equations that enable the direct analytical calculation of the interaction torque between perpendicularly magnetized cuboidal permanent magnets in free space. These expressions complement the expressions for the interaction force and stiffness that are already available in literature and are computationally inexpensive due to their analytical nature. They are suitable in the design and analysis of ironless structures such as certain types of magnetic bearings or for obtaining the peeling torque on the magnets in devices such as voice coil actuators or electron beam focusing devices.
Autors: Janssen, J. L. G.;Paulides, J. J. H.;Lomonova, E. A.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Oct 2011, volume: 47, issue:10, pages: 4286 - 4289
Publisher: IEEE
 
» 3-D Parallel Fault Simulation With GPGPU
Abstract:
General purpose computing on graphical processing units (GPGPU) is a paradigm shift in computing that promises a dramatic increase in performance. GPGPU also brings an unprecedented level of complexity in algorithmic design and software development. In this paper, we present an efficient parallel fault simulator, , that exploits the high degree of parallelism supported by a state-of-the-art graphic processing unit (GPU) with the NVIDIA compute unified device architecture. A novel 3-D parallel fault simulation technique is proposed to achieve extremely high computation efficiency on the GPU. Global communication is minimized by concentrating as much work as possible on the local device's memory. We present results on a GPU platform from NVIDIA (a GeForce GTX 285 graphics card) that demonstrate a speedup of up to and compared to two other GPU-based fault simulators and up to over a state-of-the-art algorithm on conventional processor architectures.
Autors: Li, M.;Hsiao, M. S.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Oct 2011, volume: 30, issue:10, pages: 1545 - 1555
Publisher: IEEE
 
» 30th anniversary of the PC and the post-PC era [Editor's Note]
Abstract:
Where has the time gone? It is the 30th anniversary of the IBM PC. Many of us might remember when IBM announced the PC (formally the Model 5150) on August 12, 1981. There were many computers at the time, but predominantly mainframes and minicomputers. Computers were largely seen as costly resources to be time-shared by large groups. The idea of a "personal" computer owned and used by one person was a relatively new notion for most people.
Autors: Chen, T.M.;
Appeared in: IEEE Network
Publication date: Oct 2011, volume: 25, issue:5, pages: 2 - 3
Publisher: IEEE
 
» 3D NOC for many-core processors
Abstract:
With an increasing number of processors forming many-core chip multiprocessors (CMP), there exists a need for easily scalable, high-performance and low-power intra-chip communication infrastructure for emerging systems. In CMPs with hundreds of processing elements, 3D integration can be utilized to shorten long wires forming communication links. In this paper, we propose a Clos network-on-chip (CNOC) in conjunction with 3D integration as a viable network topology for many core CMPs. The primary benefit of 3D CNOC is scalability and a clear upper bound on power dissipation. We present the architectural and physical design of 3D CNOC and compare its performance with several other topologies. Comparisons are made among several topologies (fat tree, flattened butterfly, mesh and Clos) showing the power consumption of a 3D CNOC increases only minimally as the network size is scaled from 64 to 512 nodes relative to the other topologies. Furthermore, in a 512-node system, 3D CNOC consumes about 15% less average power than any other topology. We also compare 3D partitioning strategies for these topologies and discuss their effect on wire delay and the number of through-silicon vias.
Autors: Aamir Zia, Sachhidh Kannan, H. Jonathan Chao, Garrett S. Rose
Appeared in: Microelectronics Journal
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» 3D-Antenna-in-Package Solution for Microwave Wireless Sensor Network Nodes
Abstract:
A three-dimensional packaging solution is introduced for wireless sensor network nodes at microwave frequencies. The package has a cubic geometry with radiating antennas on its surrounding faces. The cube which is called e-CUBE is designed in such a way that its radiation pattern resembles that of a simple dipole. The antenna is designed in a modular way and the final structure has a return loss better than 10 dB and a dipole-shape pattern at 17.2 GHz. Moreover, the measurement and simulation results show very good agreement.
Autors: Enayati, A.;Brebels, S.;De Raedt, W.;Vandenbosch, G. A. E.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Oct 2011, volume: 59, issue:10, pages: 3617 - 3623
Publisher: IEEE
 
» 40-Gb/s Operation of a 1.3-/1.55-μm InGaAlAs Electroabsorption Modulator Integrated With DFB Laser in Compact TO-CAN Package
Abstract:
We have developed compact, cost-effective transistor-outline (TO)-CAN modules based on a 1.3-/1.55-μm InGaAlAs electroabsorption modulator integrated with a distributed feedback laser (EML), and realized the 40-Gb/s operation of these modules for the first time. We propose a new method for connecting a straight RF substrate and a TO-CAN stem that minimizes the air gap between them, and that suppresses the impedance mismatch at the connection interface. We also employ a liquid crystal polymer as an RF-line substrate, and apply a borosilicate glass-based coaxial RF pin, which is compatible with K connector glass beads to the TO-CAN stem. By using these modules, we confirm experimentally that the impedance of the entire RF transmission line is approximately 50 Ω throughout the module, and achieve an electrical-to-optical 3-dB-down frequency bandwidth ( ) of over 33 GHz. We also achieve 40-Gb/s clear eye openings for both 1.3- and 1.55-μm EML-based modules.
Autors: Kobayashi, W.;Tsuzuki, K.;Tadokoro, T.;Fujisawa, T.;Fujiwara, N.;Yamanaka, T.;Kano, F.;
Appeared in: IEEE Journal of Selected Topics in Quantum Electronics
Publication date: Oct 2011, volume: 17, issue:5, pages: 1183 - 1190
Publisher: IEEE
 
» 5T SRAM With Asymmetric Sizing for Improved Read Stability
Abstract:
Conventional 6-transistor (6T) SRAM scaling to newer technologies and lower supply voltages is difficult due to a complex trade-off space involving stability, performance, power, and area. Local and global variation make SRAM design even more challenging. We present a 5-transistor (5T) bitcell that uses sizing asymmetry to improve read stability and to provide an efficient knob for trading off the aforementioned metrics. In this paper, we compare the 5T with the conventional 6T and the 8T and show how it can be a flexible, intermediate alternative between the two. We also investigate single-ended sensing for the 5T. Finally, we present measurement results in a 45 nm test chip that demonstrate the functionality of the 5T. Through a combination of write assists, the 5T can demonstrate comparable writability down to 0.7 V, while showing no read errors down to 0.5 V.
Autors: Nalam, S.;Calhoun, B. H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2011, volume: 46, issue:10, pages: 2431 - 2442
Publisher: IEEE
 
» 90 nm 32 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation
Abstract:
Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models developed from this group's Si/SiGe resonant interband tunnel diode experimental data. 1 T and 3 T- 2 tunnel diode memory cell configurations were evaluated. The memory array assigns 0.5 V as a logic “1” and 0 V as a logic “0”. Dual supply voltages of 1 and 0.5 V and dual threshold voltage design are used to ensure high sensing speed concurrently with low operating and standby power. Read access time of 1 ns and write access time of 2 ns is achieved for the 3 T memory cell. Write access time can be reduced to 0.5 ns for 32 bit write operations not requiring a preceding read operation. Standby power dissipation of per cell and dynamic power dissipation of per cell is obtained from the TSRAM memory array. This is the first report of TSRAM performance at the array level.
Autors: Ramesh, A.;Park, S.-Y.;Berger, P. R.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Oct 2011, volume: 58, issue:10, pages: 2432 - 2445
Publisher: IEEE
 
» 90 nm 32 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation
Abstract:
Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models developed from this group's Si/SiGe resonant interband tunnel diode experimental data. 1 T and 3 T- 2 tunnel diode memory cell configurations were evaluated. The memory array assigns 0.5 V as a logic “1” and 0 V as a logic “0”. Dual supply voltages of 1 and 0.5 V and dual threshold voltage design are used to ensure high sensing speed concurrently with low operating and standby power. Read access time of 1 ns and write access time of 2 ns is achieved for the 3 T memory cell. Write access time can be reduced to 0.5 ns for 32 bit write operations not requiring a preceding read operation. Standby power dissipation of per cell and dynamic power dissipation of per cell is obtained from the TSRAM memory array. This is the first report of TSRAM performance at the array level.
Autors: Ramesh, A.;Park, S.-Y.;Berger, P. R.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Oct 2011, volume: 58, issue:10, pages: 2432 - 2445
Publisher: IEEE
 
» A 0.5 V Operation Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems
Abstract:
A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. To realize the low power LSIs it is important to decrease the supply voltage ( ) to e.g., 0.5 V because the active power consumption of LSIs strongly depends on . When the 0.5 V is adopted, widely used RAM, SRAM is difficult to operate because the SRAM is sensitive to the variation. DRAM has a potential to operate at such low . As the key technology to realize 0.5 V operation DRAM, this paper proposes the word-line booster circuit. The theoretical equation of the output voltage and the energy consumption of the proposed booster is extensively investigated. The proposed booster outputs 1.4 V in 3 clock cycles, which is shorter than the DRAM access time and the power consumption is 60 pJ. 1.4 V is the required word-line voltage to successfully charge the DRAM cell capacitor. Compared with the conventional boosters, the rising time and the power consumption are decreased to 38% and 68%, respectively, with the same circuit area. The proposed circuit was fabricated with the 0.18 standard CMOS process and the high-speed boosting is experimentally demonstrated.
Autors: Tanakamaru, S.;Takeuchi, K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2011, volume: 46, issue:10, pages: 2406 - 2415
Publisher: IEEE
 
» A 0.5 V Operation Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems
Abstract:
A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. To realize the low power LSIs it is important to decrease the supply voltage ( ) to e.g., 0.5 V because the active power consumption of LSIs strongly depends on . When the 0.5 V is adopted, widely used RAM, SRAM is difficult to operate because the SRAM is sensitive to the variation. DRAM has a potential to operate at such low . As the key technology to realize 0.5 V operation DRAM, this paper proposes the word-line booster circuit. The theoretical equation of the output voltage and the energy consumption of the proposed booster is extensively investigated. The proposed booster outputs 1.4 V in 3 clock cycles, which is shorter than the DRAM access time and the power consumption is 60 pJ. 1.4 V is the required word-line voltage to successfully charge the DRAM cell capacitor. Compared with the conventional boosters, the rising time and the power consumption are decreased to 38% and 68%, respectively, with the same circuit area. The proposed circuit was fabricated with the 0.18 standard CMOS process and the high-speed boosting is experimentally demonstrated.
Autors: Tanakamaru, S.;Takeuchi, K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2011, volume: 46, issue:10, pages: 2406 - 2415
Publisher: IEEE
 
» A 0.6-V 82-dB 28.6- W Continuous-Time Audio Delta-Sigma Modulator
Abstract:
The design of a low-voltage low-power fourth-order single-bit continuous-time Delta-Sigma modulator is presented in this paper for audio applications. The modulator employs an input-feedforward topology in order to reduce internal signal swings, thus relaxes the linearity and slew rate requirements on amplifiers leading to low-voltage operation and low-power consumption. The energy efficiency is further improved by embedding the summation of feedforward paths into the quantizer. For low-voltage operation, a gain-enhanced fully-differential amplifier and a body-driven rail-to-rail input CMFB circuit are developed. The modulator, implemented in a 0.13- standard CMOS technology with a core area of 0.11 , achieves an 82-dB dynamic range (DR), and a 79.1-dB peak signal-to-noise and distortion ratio (SNDR) over a 20-kHz signal bandwidth. The power consumption of the modulator is 28.6 under a 0.6-V supply voltage. The achieved performance make it one of the best among state-of-the-art sub-1-V modulators in terms of two widely used figures of merit.
Autors: Zhang, J.;Lian, Y.;Yao, L.;Shi, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2011, volume: 46, issue:10, pages: 2326 - 2335
Publisher: IEEE
 
» A 0.6-V 82-dB 28.6- W Continuous-Time Audio Delta-Sigma Modulator
Abstract:
The design of a low-voltage low-power fourth-order single-bit continuous-time Delta-Sigma modulator is presented in this paper for audio applications. The modulator employs an input-feedforward topology in order to reduce internal signal swings, thus relaxes the linearity and slew rate requirements on amplifiers leading to low-voltage operation and low-power consumption. The energy efficiency is further improved by embedding the summation of feedforward paths into the quantizer. For low-voltage operation, a gain-enhanced fully-differential amplifier and a body-driven rail-to-rail input CMFB circuit are developed. The modulator, implemented in a 0.13- standard CMOS technology with a core area of 0.11 , achieves an 82-dB dynamic range (DR), and a 79.1-dB peak signal-to-noise and distortion ratio (SNDR) over a 20-kHz signal bandwidth. The power consumption of the modulator is 28.6 under a 0.6-V supply voltage. The achieved performance make it one of the best among state-of-the-art sub-1-V modulators in terms of two widely used figures of merit.
Autors: Zhang, J.;Lian, Y.;Yao, L.;Shi, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2011, volume: 46, issue:10, pages: 2326 - 2335
Publisher: IEEE
 
» A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications
Abstract:
A 10-bit 30-MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low-power sub-sampling applications, is presented. Bootstrapped switches are used to enhance the sampling linearity at the high input frequency. The proposed ADC adopts a binary-weighted split-capacitor array with the energy efficient switching procedure and includes an asynchronous clock scheme to yield more power and speed-efficiency. The ADC is fabricated in a 65 nm complementary metal-oxide-semiconductor technology and occupies an active area of 0.07 mm. The differential and integral nonlinearities of the ADC are less than 0.82 and 1.13 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 56.60 dB, a spurious free dynamic range of 73.35 dB, and an effective number of bits (ENOB) of 9.11-bits with a 2.5-MHz sinusoidal input at 30-MS/s. It exhibits higher than 8.86 ENOB for input frequencies up to 78-MHz. The ADC consumes 0.85 mW at a 1.1 V supply and achieves a figure-of-merit of 51 fJ/conversion-step.
Autors: Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon
Appeared in: Microelectronics Journal
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A 100–117 GHz W-Band CMOS Power Amplifier With On-Chip Adaptive Biasing
Abstract:
A W-band power amplifier (PA) has been realized in 65 nm bulk CMOS technology, which covers 100 to 117 GHz. It delivers up to 13.8 dBm saturated output power with up to 15 dB power gain and 10% PAE, which also achieves better than 10.1 dBm output P1 dB. The PA features compact realization with transformer-coupled three stages and on-chip input/output baluns to facilitate single-ended characterization. To ensure stability and boost efficiency, it adopts cascode structure in the first two stages and common source amplifier in the last stage. To improve the PAE and linearity, an adaptive biasing circuitry is incorporated inside the PA. The entire PA core occupies 0.041 die area and burns about 180 mW with the adaptive bias circuit consuming only 0.002 active chip area.
Autors: Xu, Z.;Gu, Q. J.;Chang, M.-C. F.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Oct 2011, volume: 21, issue:10, pages: 547 - 549
Publisher: IEEE
 
» A 12 GHz-Bandwidth CMOS Mixer With Variable Conversion Gain Capability
Abstract:
A broadband downconverter mixer using an operational transconductance amplifier (OTA) in the RF transconductor stage is presented in this paper. By changing the OTA's transconductance through a dc control voltage, the mixer's conversion gain is varied. Experimental results show that the mixer's conversion gain can vary from 17 dB down to 1.2 dB over a 12 GHz bandwidth. The maximum of the mixer is 3.7 dBm and its maximum IIP3 is 8.6 dBm. Meanwhile, the maximum is 7 dBm and the maximum OIP3 is 21 dBm. The circuit consumes a maximum of 5.9 mW of power from a 1.2 V supply. The chip occupies an area of 0.105 excluding bonding pads.
Autors: Xu, J.;Saavedra, C. E.;Chen, G.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Oct 2011, volume: 21, issue:10, pages: 565 - 567
Publisher: IEEE
 
» A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS
Abstract:
A phase-locked loop (PLL) with the proposed voltage-controlled oscillator (VCO) and a divide-by-2 injection-locked frequency divider (ILFD) is fabricated in 65-nm digital CMOS technology. The proposed VCO and the divide-by-two ILFD operate at the higher and lower poles, respectively, of two fourth-order LC ladders. The frequency ratio between the VCO and its first divide-by-2 ILFD is kept by scaling the inductances and the capacitances. The design considerations of this VCO and the locking range of this ILFD are discussed. The measured locking range of this PLL is 132.1–132.6 GHz. It consumes 120.8 mW from 1.35-V supply, excluding the output buffers. The chip area is .
Autors: Lin, B.-Y.;Liu, S.-I.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Oct 2011, volume: 58, issue:10, pages: 617 - 621
Publisher: IEEE
 
» A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL
Abstract:
A 2-Gb/s point-to-point intrapanel interface for thin-film-transistor liquid crystal display (TFT-LCD) is proposed by using only clock and data lines. Extra control lines are eliminated by sending the VSYNC code through the clock line at the start of the VBLANK time period and by sending the control commands through the data line at the end of the VBLANK time period. To reduce electromagnetic interference, the slew rate of the clock driver is reduced, and the frequency of clock signals is set to the subpixel (R/G/B) frequency (1/10 of the data rate). The clock line is cascaded between two adjacent receiver (RX) chips for a point-to-point interface. To generate an internal clock synchronized (deskewed) to the subpixel (R/G/B) boundary of incoming data at each RX, a single all-digital delay-locked loop (DLL) circuit is proposed to perform the combined operation of a DLL and a phase interpolator. This deskew operation is performed during the VBLANK period with periodic preamble data input (‘1111100000’). At the RX, a multiphase DLL follows the deskew DLL to generate 20-phase clocks for data sampling. 2-Gb/s data are transmitted through a series connection of a 100-cm-long flat flexible cable and a 50-cm-long FR4 microstrip line with a bit error rate less than 1e–12. The image test was successfully performed with a 42-in full-high definition 120-Hz LCD panel at 1.5 Gbps. The area and power consumption of RX chip is 0.35 and 52.4 mW at 2 Gbps with a 0.18- complementary metal–oxide–semiconductor process and a 1.8-V supply.
Autors: Chi, H.-J.;Choi, Y.-H.;Lee, S.-M.;Sim, J.-Y.;Park, H.-J.;Lim, J.-J.;Kang, P.-S.;Lee, B.-Y.;Hong, J.-C.;Lee, H.-S.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Oct 2011, volume: 58, issue:10, pages: 687 - 691
Publisher: IEEE
 
» A 2.4- 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies
Abstract:
The design of a 60-Gb/s CMOS driver with input signal retiming is analyzed theoretically and validated experimentally. The output stage employs a modified distributed amplifier (DA) architecture with summation of both low-pass and reactively coupled bandpass signal paths along a 50- output transmission line. The DA features digital variable gain amplifier (DVGA) cells to achieve broadband waveshape control with adjustable pre-emphasis at three different peaking frequencies. Binary-weighted MOSFET gate-finger groupings are employed in a Gilbert-cell based DVGA topology to minimize bit-dependent output impedance and group delay variations. -parameter measurements of the retimed driver show 54-dB gain, while the standalone DA exhibits approximately 10 dB of peaking control in each of the three frequency bands. Input and output return loss is better than up to 60 GHz. The circuit operates from 1.2- and 2-V supplies and achieves a throughput efficiency of 12.2 mW/Gb/s. Equalization experiments at 40 Gb/s demonstrate compensation of various channel characteristics, including over 12 feet of cascaded coaxial cables with 21 dB loss at 20 GHz.
Autors: Aroca, R. A.;Schvan, P.;Voinigescu, S. P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2011, volume: 46, issue:10, pages: 2226 - 2239
Publisher: IEEE
 
» A 2.4- 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies
Abstract:
The design of a 60-Gb/s CMOS driver with input signal retiming is analyzed theoretically and validated experimentally. The output stage employs a modified distributed amplifier (DA) architecture with summation of both low-pass and reactively coupled bandpass signal paths along a 50- output transmission line. The DA features digital variable gain amplifier (DVGA) cells to achieve broadband waveshape control with adjustable pre-emphasis at three different peaking frequencies. Binary-weighted MOSFET gate-finger groupings are employed in a Gilbert-cell based DVGA topology to minimize bit-dependent output impedance and group delay variations. -parameter measurements of the retimed driver show 54-dB gain, while the standalone DA exhibits approximately 10 dB of peaking control in each of the three frequency bands. Input and output return loss is better than up to 60 GHz. The circuit operates from 1.2- and 2-V supplies and achieves a throughput efficiency of 12.2 mW/Gb/s. Equalization experiments at 40 Gb/s demonstrate compensation of various channel characteristics, including over 12 feet of cascaded coaxial cables with 21 dB loss at 20 GHz.
Autors: Aroca, R. A.;Schvan, P.;Voinigescu, S. P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2011, volume: 46, issue:10, pages: 2226 - 2239
Publisher: IEEE
 
» A 23.4 mW 68 dB Dynamic Range Low Band CMOS Hybrid Tracking Filter for ATSC Digital TV Tuner Adopting RC and Gm-C Topology
Abstract:
In this paper, a 48–200 MHz CMOS hybrid tracking low-pass filter with low power and high dynamic range is presented to solve a local oscillator harmonic-mixing problem for Advanced Television Systems Committee terrestrial digital TV tuner integrated circuits. For low power consumption, the first-order passive RC filter and the second-order transconductor-C filter are combined to implement the third-order Chebyshev tracking low-pass filter. A transconductor linearization technique based on a method of multiple gated transistors is adopted to achieve high dynamic range. Fabricated in a 0.18 m CMOS process, it achieves a maximum in-band input-referred noise density of 5.1 and maximum in-band output-referred third-order intercept point of 17.3 dBm, while dissipating 23.4 mW with 1.8 V. The total chip area is 0.6 mm 0.4 mm.
Autors: Kwon, K.;Lee, K.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Oct 2011, volume: 58, issue:10, pages: 2346 - 2354
Publisher: IEEE
 
» A 3W network strategy for mobile data traffic offloading
Abstract:
This article presents a quantitative survey of mobile data traffic surge and a strategic solution to traffic offloading. As diverse mobile devices such as smartphones and tablet computers become ubiquitous, the explosive increase of data traffic in 3G cellular networks is a major concern for network operators. The rapid increase of mobile data traffic is unprecedented ?? a tenfold increase in a year is common. Thus, mobile data traffic offloading in 3G cellular networks is necessary. In this article we examine the effect of a network strategy deploying multiple wireless networks. We first discuss the relationship between the spread of smartphones and their contribution to the mobile data traffic surge. To see how mobile data traffic is transferred among different networks, we illustrate the traffic trend of the 3W (WCDMA, WIBRO, and WiFi) network in KT Corporation. Based on the composition of traffic, we also discuss functions and roles of the 3W networks in accessing mobile Internet. From these results, we show that deploying multiple wireless networks is an effective way of traffic offloading.
Autors: Yongmin Choi;Hyun Wook Ji;Jae-yoon Park;Hyun-chul Kim;Silvester, J.A.;
Appeared in: IEEE Communications Magazine
Publication date: Oct 2011, volume: 49, issue:10, pages: 118 - 123
Publisher: IEEE
 
» A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy
Abstract:
An ultra low energy, 128 kbit 6T SRAM in 90 nm LP CMOS with energy consumption of 4.4 pJ/access, operating at 80 MHz for the wireless sensor applications is developed. The variability resilient and low power techniques developed include innovation in the local architecture with the use of local read/write assist circuitry. The energy-efficient hierarchical bit-lines structure includes low swing global bit-lines and VDD/2 pre-charged short local bit-lines. The innovative Multi-Sized SA redundancy (MS-SA-R) calibration technique for the global read sense amplifiers of the SRAM not only adds to the variability resilience but also yields maximum energy reduction compared with existing calibration techniques.
Autors: Sharma, V.;Cosemans, S.;Ashouei, M.;Huisken, J.;Catthoor, F.;Dehaene, W.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2011, volume: 46, issue:10, pages: 2416 - 2430
Publisher: IEEE
 
» A 4.8-mW 4-GHz CMOS Class-B-Like Down-Converter for Harmonic Mixing Rejection
Abstract:
In a wideband receiver, higher frequency channels may be converted to the frequency of a desired signal by a harmonic mixing mechanism. To alleviate this issue, this paper proposes a topology, called the classBlike converter, to achieve high harmonic mixing rejection in frequency translation without any filtering. The converter is based on a linear commutation with a sinusoidal local oscillator for a small harmonic mixing, while its gain and noise performances are comparable to that of a switching-type converter. Most important, the circuitry of the proposed converter is simple and can be incorporated with other harmonic rejection techniques. The circuit is implemented with a 0.18- m 1.8-V CMOS technology and the power consumption is 4.8 mW. Measurement results indicate that the third- to ninth-order harmonic rejections are more than 45 dB in average within a 4-GHz frequency range. A polyphase prototype with the proposed converter achieves higher than 70-dB third-order harmonic rejection even under a 2 phase and 2% gain mismatch.
Autors: Li, C.-F.;Huang, P.-C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Oct 2011, volume: 59, issue:10, pages: 2504 - 2512
Publisher: IEEE
 
» A 6-DOF adaptive parallel manipulator with large tilting capacity
Abstract:

Highlights

? A novel 6-DOF adaptive parallel manipulator with large tilting capacity is presented. ? The doubly actuated center limb is used to solve the nonholonomic problem. ? The detailed kinematic analysis of the manipulator is developed.


Autors: In this paper, a novel 6 degrees of freedom (DOFs) adaptive parallel manipulator with large tilting capacity is presented. The manipulator consists of four identical peripheral limbs and one center limb connecting the base and the moving platform. Du
Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A 60 GHz Sub-Harmonic Resistive FET Mixer Using 0.13 CMOS Technology
Abstract:
A 56 to 66 GHz sub-harmonic resistive mixer using 0.13 CMOS technology is presented in this letter. This mixer exhibits a flat conversion loss of about 12 and 13 dB and good isolations between ports from 56 to 66 GHz for both down and up-conversion with a lowest LO power of 0 and 1 dBm. The 2LO-RF isolation is more than 27 dB even if IF input power exceeds 4 dBm, which results from the mechanism of connecting drain and body of the device. Besides, this mixer has a relatively high input and a 3 GHz IF bandwidth in each band defined in IEEE 802.15.3c standard.
Autors: Lin, S.-K.;Kuo, J.-L.;Wang, H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Oct 2011, volume: 21, issue:10, pages: 562 - 564
Publisher: IEEE
 
» A 70- m Pitch 8- W Self-Biased Charge-Integration Active Pixel for Digital Mammography
Abstract:
This paper presents a new low-power compact CMOS active pixel circuit specifically optimized for full-field digital mammography. The proposed digital pixel sensor (DPS) architecture includes self-bias capability at 10% accuracy, up to 15 nA of dark-current autocalibration, built-in test mechanisms, selectable collection, 10-b lossless charge-integration analog–to-digital conversion, more than 1 decade of individual gain tuning for fixed pattern noise cancellation, and a 50-Mb/s digital-only input/output interface. Experimental results for a 70- m pitch 8- W DPS cell example are reported in 0.18- m CMOS 1-polySi 6-metal technology.
Autors: Figueras, R.;Sabadell, J.;Teres, L.;Serra-Graells, F.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Oct 2011, volume: 5, issue:5, pages: 481 - 489
Publisher: IEEE
 
» A 70- m Pitch 8- W Self-Biased Charge-Integration Active Pixel for Digital Mammography
Abstract:
This paper presents a new low-power compact CMOS active pixel circuit specifically optimized for full-field digital mammography. The proposed digital pixel sensor (DPS) architecture includes self-bias capability at 10% accuracy, up to 15 nA of dark-current autocalibration, built-in test mechanisms, selectable collection, 10-b lossless charge-integration analog–to-digital conversion, more than 1 decade of individual gain tuning for fixed pattern noise cancellation, and a 50-Mb/s digital-only input/output interface. Experimental results for a 70- m pitch 8- W DPS cell example are reported in 0.18- m CMOS 1-polySi 6-metal technology.
Autors: Figueras, R.;Sabadell, J.;Teres, L.;Serra-Graells, F.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Oct 2011, volume: 5, issue:5, pages: 481 - 489
Publisher: IEEE
 
» A 96% Efficient High-Frequency DC–DC Converter Using E-Mode GaN DHFETs on Si
Abstract:
III-Nitride materials are very promising to be used in next-generation high-frequency power switching applications. In this letter, we demonstrate the performance of normally off AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs) using a boost-converter circuit. The figures of merit of our large (57.6-mm gate width) GaN transistor are presented: of 2.5 is obtained at . The switching performance of the GaN DHFET is studied in a dedicated high-frequency boost converter: both the switching times and power losses are characterized. We show converter efficiency values up to 96.1% at 500 kHz and 93.9% at 850 kHz at output power of 100 W.
Autors: Das, J.;Everts, J.;Van Den Keybus, J.;Van Hove, M.;Visalli, D.;Srivastava, P.;Marcon, D.;Cheng, K.;Leys, M.;Decoutere, S.;Driesen, J.;Borghs, G.;
Appeared in: IEEE Electron Device Letters
Publication date: Oct 2011, volume: 32, issue:10, pages: 1370 - 1372
Publisher: IEEE
 
» A Battery-Aware Scheme for Routing in Wireless Ad Hoc Networks
Abstract:
Wireless ad hoc networks have played an increasingly important role in a wide range of applications. A key challenge in such networks is to achieve maximum lifetime for battery-powered mobile devices with dynamic energy-efficient algorithms. Recent studies in battery technology have revealed that the behavior of battery discharging is more complex than we used to know. Battery-powered devices might waste a huge amount of energy if their battery discharging is not carefully scheduled and budgeted. In this paper, we introduce a novel energy model for batteries and study the effect of battery behavior on routing in wireless ad hoc networks. We first propose an online computable discrete-time mathematical model to capture battery discharging behavior. The model has low computational complexity and data storage requirement. It is therefore suitable for online battery capacity computation in routing. Our evaluations indicate that the model can accurately capture the behavior of battery discharging. Based on this battery model, we then propose a battery-aware routing (BAR) scheme for wireless ad hoc networks. BAR is a generic scheme that implements battery awareness in routing protocols and is independent of any specific routing protocol. By dynamically choosing the devices with well-recovered batteries as routers and leaving the “fatigue” batteries for recovery, the BAR scheme can effectively recover the device's battery capacity to achieve higher energy efficiency. Our simulation results demonstrate that, by adopting the BAR scheme, network lifetime and data throughput can be increased by up to 28% and 24%, respectively. The results also show that BAR achieves good performance in various networks composed of different devices, batteries, and node densities. Finally, we also propose an enhanced prioritized BAR (PBAR) scheme for time-sensitive applications in wireless ad hoc networks. Our simulation results illustrate that PBAR achieves good performance in- - terms of end-to-end delay and data throughput.
Autors: Ma, C.;Yang, Y.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Oct 2011, volume: 60, issue:8, pages: 3919 - 3932
Publisher: IEEE
 
» A Bayesian Passive Islanding Detection Method for Inverter-Based Distributed Generation Using ESPRIT
Abstract:
In this paper, a new passive islanding detection method for grid-connected inverter-based distributed-generation (DG) systems is proposed. A statistical signal-processing algorithm known as estimation of signal parameters via rotational invariance techniques is used to extract new features from measurements of the voltage and frequency at the point of common coupling as islanding indicators. The new features are defined based on a damped-sinusoid model for power system voltage and frequency waveforms, and include modal initial amplitudes, oscillation frequencies, damping factors, and initial phases. A set of training cases generated on the IEEE 34-bus system was used to train a naïve-Bayes classifier that discriminates islanding and nonislanding events. Cross-validation was used to evaluate the performance of the proposed islanding detection method. The results show that by using the new features extracted from ESPRIT, the classifier is capable of discriminating islanding and nonislanding events with an accuracy close to 100%.
Autors: Najy, W. K. A.;Zeineldin, H. H.;Alaboudy, A. H. K.;Woon, W. L.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Oct 2011, volume: 26, issue:4, pages: 2687 - 2696
Publisher: IEEE
 
» A Bayesian-Compressive-Sampling-Based Inversion for Imaging Sparse Scatterers
Abstract:
In this paper, a new approach based on the Bayesian compressive sampling (BCS ) and within the contrast source formulation of an inverse scattering problem is proposed for imaging sparse scatterers. By enforcing a probabilistic hierarchical prior as a sparsity regularization constraint, the problem is solved by means of a fast relevance vector machine. The effectiveness and robustness of the BCS-based approach are assessed through a set of numerical experiments concerned with various scatterer configurations and different noisy conditions.
Autors: Oliveri, G.;Rocca, P.;Massa, A.;
Appeared in: IEEE Transactions on Geoscience and Remote Sensing
Publication date: Oct 2011, volume: 49, issue:10, pages: 3993 - 4006
Publisher: IEEE
 
» A Brushless Permanent Magnet Machine With Integrated Differential
Abstract:
Road vehicles are equipped with at least one differential which enables torque to be transmitted to the driving wheels while still being able to rotate at different speeds. The paper presents a brushless permanent magnet machine with integrated differential, where the torque is transmitted to the wheels/axles through two permanent magnet eddy current couplings. Simulation studies have shown that such differential would exhibit the characteristics of limited-slip mechanical differential and the permanent magnet eddy current couplings can transmit the torque of the traction machine with efficiencies in excess of 99%.
Autors: Atallah, K.;Wang, J.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Oct 2011, volume: 47, issue:10, pages: 4246 - 4249
Publisher: IEEE
 
» A Bus-Based Smart Myoelectric Electrode/Amplifier—System Requirements
Abstract:
The evaluation of a bus-based smart myoelectric electrode/amplifier is described that is to be used in conjunction with a multi-function prosthetic hand controller. The smart electrode/amplifier was designed to meet power consumption and size specifications of commercially available myoelectric amplifiers used for prosthetic control applications while providing a number of additional features. This paper investigates the electrode/amplifier requirements for a pattern classifier system and compares them to those currently accepted within a clinical setting. System testing and evaluation was performed with both normally limbed subjects and traumatic amputees.
Autors: Wilson, A. W.;Losier, Y. G.;Parker, P. A.;Lovely, D. F.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Oct 2011, volume: 60, issue:10, pages: 3290 - 3299
Publisher: IEEE
 
» A century of development in applied electrostatics; nothing static here
Abstract:
Although the topic of electrostatics is well known as the earliest of the electrical sciences, it is mainly in the twentieth century that real engineering applications have developed. Today, electrostatic processes are the basis of many important industries in fields as diverse as air pollution control, printing and copying, painting, material??s separation and even sandpaper manufacture. Worldwide these applications account for many billions of dollars in annual business. In this paper the meaning of the term electrostatics is discussed and the fundamental properties that lead to these applications reviewed. The important advancements of the past century are highlighted by describing the development of three key processes; electrostatic precipitation, electrostatic painting and coating, and electrophotography. The continuing evolution of the field is put in context by summarizing the fundamental properties of the electrostatic forces and new applications in the fields of MEMS, biotechnology and nanotechnology are suggested.
Autors: Castle, G.S.P.;
Appeared in: IEEE Transactions on Dielectrics and Electrical Insulation
Publication date: Oct 2011, volume: 18, issue:5, pages: 1361 - 1365
Publisher: IEEE
 
» A Circuit Model for Spherical Wheeler Cap Measurements
Abstract:
The efficiency of an electrically-small antenna may be measured conveniently by placing it in a conducting Wheeler Cap. This paper presents a composite equivalent circuit that models an antenna both inside a spherical cap and also radiating into free space. The circuit is used to show how the measurements are affected by the antenna size, efficiency, and polarization (TE or TM), the cap radius, and experimental errors. Methods for using a single cap or multiple caps are analyzed and compared. Antennas with typical properties are represented in a general form rather than by either series or parallel circuits as is commonly done. Loops and spherical dipoles are used as examples.
Autors: Thal, H. L.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Oct 2011, volume: 59, issue:10, pages: 3638 - 3645
Publisher: IEEE
 
» A Class of Scaled Bessel Sampling Theorems
Abstract:
Sampling theorems for a class of scaled Bessel unitary transforms are presented. The derivations are based on the properties of the generalized Laguerre functions. This class of scaled Bessel unitary transforms includes the classical sine and cosine transforms, but also novel chirp sine and modified Hankel transforms. The results for the sine and cosine transform can also be utilized to yield a sampling theorem, different from Shannon's, for the Fourier transform.
Autors: Knockaert, L.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Oct 2011, volume: 59, issue:10, pages: 5082 - 5086
Publisher: IEEE
 
» A Classification Framework for Software Component Models
Abstract:
In the last decade, a large number of different software component models have been developed, with different aims and using different principles and technologies. This has resulted in a number of models which have many similarities, but also principal differences, and in many cases unclear concepts. Component-based development has not succeeded in providing standard principles, as has, for example, object-oriented development. In order to increase the understanding of the concepts and to differentiate component models more easily, this paper identifies, discusses, and characterizes fundamental principles of component models and provides a Component Model Classification Framework based on these principles. Further, the paper classifies a large number of component models using this framework.
Autors: Crnkovic, Ivica;Sentilles, Severine;Aneta, Vulgarakis;Chaudron, Michel R.V.;
Appeared in: IEEE Transactions on Software Engineering
Publication date: Oct 2011, volume: 37, issue:5, pages: 593 - 615
Publisher: IEEE
 
» A closed-form expanded autocorrelation method for frequency estimation of a sinusoid
Abstract:

Highlights

? Our estimator is closer to CRB than several existing time-domain estimators. ? Our estimator is more computational efficient than two-stage autocorrelation method. ? Our estimator has a closed-form. ? A closed-form expression of the MSE of our estimator is derived.


Autors: A closed-form expanded autocorrelation method for real single-tone frequency estimation is proposed. Firstly, the modified covariance (MC) method based on multiple autocorrelation lags is applied to provide a coarse frequency estimate. Then, a closed
Appeared in: Signal Processing
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A CMOS Hall-Effect Sensor for the Characterization and Detection of Magnetic Nanoparticles for Biomedical Applications
Abstract:
A CMOS Hall-effect sensor chip designed for the characterization and detection of magnetic nanoparticles (MNPs) achieves over three orders of magnitude better temporal resolution than prior solutions based on superconducting quantum interference devices and fluxgate sensors. The sensor relies on wires embedded in the chip to generate a local magnetizing field that is switched OFF rapidly to observe the relaxation field of the MNPs. The CMOS sensor chip, with integrated high-speed readout electronics, occupies 6.25 . It can be easily integrated with microfluidics and is suitable for lab-on-a-chip and point-of-care applications.
Autors: Liu, P.;Skucha, K.;Megens, M.;Boser, B.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Oct 2011, volume: 47, issue:10, pages: 3449 - 3451
Publisher: IEEE
 
» A CMOS In-Pixel CTIA High-Sensitivity Fluorescence Imager
Abstract:
Traditionally, charge-coupled device (CCD)-based image sensors have held sway over the field of biomedical imaging. Complementary metal–oxide semiconductor (CMOS)-based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility, and compactness of CMOS imagers. We present a 132 124 high sensitivity imager array with a 20.1- m pixel pitch fabricated in a standard 0.5- m CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA)-based in-pixel amplification, pixel scanners, and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 frames/s, the array has a minimum detectable signal of 4 nW/cm at a wavelength of 450 nm while consuming 718 A from a 3.3-V supply. The peak signal-to-noise ratio (SNR) was 44 dB at an incident intensity of 1 . Implementing 4 4 binning allowed the frame rate to be increased to 675 frames/s. Alternately, sensitivity could be increased to detect about 0.8 nW/cm while maintaining 70 frames/s. The chip was used to image single-cell fluorescence at 28 frames/s with an average SNR of 32 dB. For comparison, a - - cooled CCD camera imaged the same cell at 20 frames/s with an average SNR of 33.2 dB under the same illumination while consuming more than a watt.
Autors: Murari, K.;Etienne-Cummings, R.;Thakor, N. V.;Cauwenberghs, G.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Oct 2011, volume: 5, issue:5, pages: 449 - 458
Publisher: IEEE
 
» A combined impedance and traveling wave based fault location method for multi-terminal transmission lines
Abstract:

Highlights

? We have proposed a combined impedance and TW based fault location method suitable for multi-terminal lines. ? The impedance based method is used to identify the faulted half of the line. ? The TW based method is employed to compute the fault location accurately. ? Regardless of the fault type and fault resistance the fault location is computed accurately.


Autors: A new fault location method suitable for multi-terminal transmission lines that combines the advantages of both impedance and traveling wave based methods has been developed and presented in this paper. The proposed method first determines whether th
Appeared in: International Journal of Electrical Power & Energy Systems
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A common gate thin film transistor on poly(ethylene naphthalate) foil using step-and-flash imprint lithography
Abstract:
image

Highlights

? We have fabricated thin film transistors (TFTs) on PEN foil by imprint lithography. ? A high mobility and a near-zero threshold voltage have been obtained. ? Our TFTs perform equally well as photolithographically patterned devices. ? Imprint lithography is suitable for the fabrication of electronic devices on foil.

Autors:

Graphical abstract

Appeared in: Organic Electronics
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A compact CPW fed slot antenna for ultra wide band applications
Abstract:
A printed compact coplanar waveguide fed triangular slot antenna for ultra wide band (UWB) communication systems is presented. The antenna comprises of a triangular slot loaded ground plane with a T shaped strip radiator to enhance the bandwidth and radiation. This compact antenna has a dimension of 26 mm × 26 mm when printed on a substrate of dielectric constant 4.4 and thickness 1.6 mm. Design equations are implemented and validated for different substrates. The pulse distortion is insignificant and is verified by the measured antenna performance with high signal fidelity and virtually steady group delay. The simulation and experiment reveal that the proposed antenna exhibits good impedance match, stable radiation patterns and constant gain and group delay over the entire operating band.
Autors: V.A. Shameena, S. Mridula, Anju Pradeep, Sarah Jacob, A.O. Lindo, ...
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A Compact EADFB Laser Array Module for a Future 100-Gb/s Ethernet Transceiver
Abstract:
A compact electroabsorption modulators integrated distributed feedback (EADFB) laser array module has been developed for 100-Gb/s Ethernet. Four 25-Gb/s EADFB lasers and an optical multiplexer are monolithically integrated on one chip in an area of only 2 mm × 2.6 mm. As a result, a compact 12 mm × 20 mm EADFB laser array module is achieved. A bridge-type RF circuit board is employed to transmit high-frequency, 4 × 25-Gb/s, electrical signals effectively in a narrow package and improve the electrical/optical response of the module. The module has a 3-dB frequency bandwidth of 20 GHz for the four lanes assigned in 100-Gb/s Ethernet. Furthermore, the possibility of realizing low-driving voltage operation is investigated to reduce the power consumption of the module. An error-free transmission through 10 km of single-mode fiber at 100 Gb/s with a modulation voltage of only 1 V is demonstrated.
Autors: Kanazawa, S.;Fujisawa, T.;Ohki, A.;Ishii, H.;Nunoya, N.;Kawaguchi, Y.;Fujiwara, N.;Takahata, K.;Iga, R.;Kano, F.;Oohashi, H.;
Appeared in: IEEE Journal of Selected Topics in Quantum Electronics
Publication date: Oct 2011, volume: 17, issue:5, pages: 1191 - 1197
Publisher: IEEE
 
» A Compact Printed Filtering Antenna Using a Ground-Intruded Coupled Line Resonator
Abstract:
A compact printed filtering antenna with high band-edge gain selectivity is presented. Occupying about the same substrate area as a conventional antenna, the proposed structure not only serves as a radiator but also a second-order bandpass filter, with one filter pole provided by a -shaped antenna and the other by a newly proposed coupled line resonator. High band-edge selectivity is achieved due to two additional stop-band transmission zeros provided by the coupled line resonator. To minimize the required area and reduce the spurious radiation, a coupled line structure composed of a microstrip line and a coplanar waveguide by broadside coupling is adopted and intruded into the -shaped antenna area. According to the filter specifications, a design procedure for the proposed filtering antenna is depicted in detail. One example at 2.45 GHz with a second-order Chebyshev bandpass filter of 0.1 dB equal-ripple response is tackled. As compared to the conventional -shaped antenna, the proposed filtering antenna not only possesses a similar antenna gain but also provides better band-edge gain selectivity and flat passband gain response. The measured results, including the S-parameters, total radiated power, and antenna gains versus frequency, have good agreement with the designed ones.
Autors: Chuang, C.-T.;Chung, S.-J.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Oct 2011, volume: 59, issue:10, pages: 3630 - 3637
Publisher: IEEE
 
» A Compact V-Band Bandpass Filter in IPD Technology
Abstract:
This work presents a miniaturized bandpass filter in V-band using integrated passive device (IPD) technology with thick metal layers and Benzocyclobutene (BCB) dielectric on a glass substrate. The proposed filter, comprised of two stepped-impedance resonators with quarter-wave short-circuited stubs and floating pads, has low passband insertion loss and high stopband attenuation in a compact size. The fabricated filter has an insertion loss of 2.46 dB at the center frequency of 59 GHz, and a 3 dB bandwidth from 55.7 to 62.2 GHz. The core size of this filter is only 0.32 0.4 mm .
Autors: Hsiao, C.-Y.;Hsu, S. S. H.;Chang, D.-C.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Oct 2011, volume: 21, issue:10, pages: 531 - 533
Publisher: IEEE
 
» A comparative study of physicochemical, dielectric and thermal properties of pressboard insulation impregnated with natural ester and mineral oil
Abstract:
Natural ester is considered to be a substitute of mineral oil in the future. To apply natural ester in large transformers safely, natural ester impregnated solid insulation should be proved to have comparable dielectric strength and thermal stability to mineral oil impregnated solid insulation. This paper mainly focuses on a comparative study of physicochemical, ac breakdown strength and thermal stability behavior of BIOTEMP natural ester/pressboard insulation and Karamay 25# naphthenic mineral oil/pressboard insulation after long term thermal ageing. The physicochemical and dielectric parameters including moisture, acids and the ac breakdown strength of these two oil/pressboard insulation systems at different ageing status were compared. The permittivity and ac breakdown strength of these two oil/pressboard insulation systems at different temperatures were also investigated. And a comparative result of the thermal stability behavior of these two oil/pressboard insulation systems with different ageing status was provided at last. Results show that though natural ester has higher absolute humidity and acidity during the long ageing period, the lower relative humidity of natural ester helps to keep its ac breakdown strength higher than mineral oil. The pressboard aged in natural ester also has higher ac breakdown strength than that aged in mineral oil. The lower relative permittivity ratio of natural ester impregnated paper to natural ester is beneficial to its dielectric strength. Using natural ester in transformer, the resistance to thermal decomposition of the oil/pressboard insulation system could be also effectively improved.
Autors: Liao, R.;Hao, J.;Chen, G.;Ma, Z.;Yang, L.;
Appeared in: IEEE Transactions on Dielectrics and Electrical Insulation
Publication date: Oct 2011, volume: 18, issue:5, pages: 1626 - 1637
Publisher: IEEE
 
» A Comparison of Magnetic Domain Images Using a Modified Bitter Pattern Technique and the Kerr Method on Grain-Oriented Electrical Steel
Abstract:
Differences in the magnetic domain patterns of high permeability grain-oriented (HGO) electrical steel have been compared using a modified Bitter technique and the magneto-optical Kerr method. Distinct differences in the domain images were observed which have been attributed to the greater sensitivity of the Bitter technique to the degree of misorientation of the crystal grains. Electron backscatter diffraction (EBSD) analysis was also carried out to confirm the degree of crystal misorientation for the area under investigation. The results show that the Bitter technique is most effective in detecting the presence of low angle grain boundaries but less accurate than the Kerr method for determining the absolute direction of magnetization.
Autors: Xu, X. T.;Moses, A. J.;Hall, J. P.;Williams, P. I.;Jenkins, K.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Oct 2011, volume: 47, issue:10, pages: 3531 - 3534
Publisher: IEEE
 
» A Comparison of Tabular Expression-Based Testing Strategies
Abstract:
Tabular expressions have been proposed as a notation to document mathematically precise but readable software specifications. One of the many roles of such documentation is to guide testers. This paper 1) explores the application of four testing strategies (the partition strategy, decision table-based testing, the basic meaningful impact strategy, and fault-based testing) to tabular expression-based specifications, and 2) compares the strategies on a mathematical basis through formal and precise definitions of the subsumption relationship. We also compare these strategies through experimental studies. These results will help researchers improve current methods and will enable testers to select appropriate testing strategies for tabular expression-based specifications.
Autors: Feng, Xin;Parnas, David Lorge;Tse, T.H.;O'Callaghan, Tony;
Appeared in: IEEE Transactions on Software Engineering
Publication date: Oct 2011, volume: 37, issue:5, pages: 616 - 634
Publisher: IEEE
 
» A comparison study of pattern recognition algorithms implemented on a microcontroller for use in an electronic tongue for monitoring drinking waters.
Abstract:
A portable electronic tongue has been developed using an array of eighteen thick-film electrodes of different materials forming a multi-electrode array. A microcontroller is used to implement the pattern recognition. The classification of drinking waters is carried out by a Microchip PIC18F4550 micro-controller and is based on neural networks algorithms. These algorithm are initially trained with the multi-electrode array on a Personal Computer (PC) using several samples of waters (still, sparkling and tap) to obtain the optimum architecture of the networks. Once it is trained, the computed data are programmed into the microcontroller, which then gives the water classification directly for new unknown water samples. A comparative study between a Fuzzy ARTMAP, a Multi-Layer Feed-Forward network (MLFF) and a Linear Discriminant Analysis (LDA) has been done in order to obtain the best implementation on a microcontroller.
Autors: Eduardo Garcia-Breijo, John Atkinson, Luis Gil-Sanchez, Rafael Masot, Javier Ibañez, ...
Appeared in: Sensors and Actuators A: Physical
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A Comprehensive Investigation of Four-Switch Three-Phase Voltage Source Inverter Based on Double Fourier Integral Analysis
Abstract:
This paper presents a comprehensive analytical investigation of the four-switch three-phase (B4) voltage source inverter. The double Fourier integral analysis is used as an analytical approach to determine the phase-leg switched voltage spectrum under condition of natural sampling. The performance of two proposed switching sequences are subsequently evaluated when the harmonic copper losses are chosen as performance criterion. For a clear identification of dc-link voltage, the spectrum of dc-link current is characterized by convolution of switching function spectrum and corresponding phase current spectrum, in which fundamental component appears causing offset and fluctuation in dc-link two-capacitor voltages. The offset can be suppressed by certain switching states, whereas the effect of fluctuation must be neutralized through analytical compensation for modulating waveforms. Otherwise, symmetry of three-phase output currents and reliable operation of the system will not be retained. Finally, the analytically calculated spectrum of output voltage and dc-link current are demonstrated by comparing with those obtained by fast Fourier transform (FFT) analysis of simulated waveforms in MATLAB/SIMULINK. The capacitor voltage offset suppression and fluctuation effect neutralization are carried out by simulations and experiments, in which the results confirm the validity of the analytical investigation.
Autors: Wang, R.;Zhao, J.;Liu, Y.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Oct 2011, volume: 26, issue:10, pages: 2774 - 2787
Publisher: IEEE
 
» A Construction of Quantum Stabilizer Codes Based on Syndrome Assignment by Classical Parity-Check Matrices
Abstract:
In this paper, a new but simple construction of stabilizer codes and related entanglement-assisted quantum error-correcting codes is proposed based on syndrome assignment by classical parity-check matrices. This method turns the construction of quantum stabilizer codes to the construction of classical parity-check matrices satisfying a specific commutative condition. The designed minimum distance of the constructed quantum stabilizer codes can be achieved by a commutative classical parity-check matrix with classical minimum distance , where the parameter , depends on a property of the parity-check matrix. As decreases, there is an increasing set of additional correctable error operators beyond the designed error correcting capability . The (asymptotic) coding efficiency is at least comparable to that of CSS codes. A class of quantum Reed–Muller codes is constructed and codes in this class have a larger set of correctable error operators than that of the quantum Reed–Muller codes previously developed in the literature. Quantum circulant codes are also constructed and many of them are optimal in terms of their coding parameters.
Autors: Lai, C.-Y.;Lu, C.-C.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Oct 2011, volume: 57, issue:10, pages: 7163 - 7179
Publisher: IEEE
 
» A customer service assurance platform for mobile broadband networks
Abstract:
In this article, we discuss trends, issues, requirements and solutions for customer service assurance (CSA) platforms for mobile broadband networks. We propose a distributed probe-based architecture called intelligent CSA (iCSA), and demonstrate how it is a key component of an advanced OSS. iCSA provides support to OSSs, addressing a number of important issues: increased bit rate, joint analysis of control and user plane, multidimensional analysis, root cause analysis, and so forth. To provide real evidence of the benefits of our proposals on a real mobile broadband network, we also illustrate experimental results on two hot topics: mobility and session management and root cause analysis of TCP connections.
Autors: Botta, A.;Pescape, A.;Guerrini, C.;Mangri, M.;
Appeared in: IEEE Communications Magazine
Publication date: Oct 2011, volume: 49, issue:10, pages: 101 - 109
Publisher: IEEE
 
» A DC Offset Current Compensation Strategy in Transformerless Grid-Connected Power Converters
Abstract:
A line frequency transformer is usually employed in grid-connected power converters, from both renewable and traditional energy sources, in order to suppress the DC current component and the ground leakage current. Solutions employing a high frequency transformer or employing no transformer at all have recently been investigated in order to reduce size, weight and cost. As a consequence, unless a suitable remedy is adopted, a DC current component exceeding the limits enforced by international standards may be injected into the grid. This paper proposes a simple and cheap solution to reduce the DC current component injected into the grid in the case of a full-bridge, single-phase, transformerless converter. The proposed strategy is intrinsically insensitive to offset measurement errors and can be utilized as a robust and dynamic offset compensator for the current transducer. The simulation results have confirmed the theoretical behavior of the proposed solution, while the experimental ones, performed for different values of output power and for different current control architectures, have shown its effectiveness.
Autors: Buticchi, G.;Lorenzani, E.;Franceschini, G.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Oct 2011, volume: 26, issue:4, pages: 2743 - 2751
Publisher: IEEE
 
» A decoupled inversion-based iterative control approach to multi-axis precision positioning: 3D nanopositioning example
Abstract:
System inversion provides a nature avenue to utilize the priori knowledge of system dynamics in iterative learning control, resulting in rapid convergence and exact tracking (for nonminimum-phase systems). The benefits of system inversion, however, are not fully exploited in the time-domain ILC approach due to the lack of uncertainty quantification. This critical limit was alleviated in the frequency-domain formulated inversion-based iterative control (IIC) techniques. The existing IIC techniques, however, are for single-input-single-output (SISO) systems only, and the time-domain properties of the IIC techniques are unclear. The contributions of the proposed multi-axis inversion-based iterative control (MAIIC) approach are twofold: First, the IIC technique is extended from SISO systems to multi-input-multi-output systems and is easy to implement in practice. The iterative control law is optimized by using the quantification of the system uncertainty. Secondly, the time-domain properties of the MAIIC law are discussed. The proposed MAIIC technique is illustrated through 3D nanopositioning experiments using piezoelectric actuators. The experimental results clearly demonstrated that by using the proposed technique, precision tracking in all 3D axes can be achieved in the presence of a pronounced cross-axis dynamics coupling effect.
Autors: Yan Yan, Haiming Wang, Qingze Zou
Appeared in: Automatica
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A design algorithm using external perturbation to improve Iterative Feedback Tuning convergence
Abstract:
Iterative Feedback Tuning constitutes an attractive control loop tuning method for processes in the absence of process insight. It is a purely data driven approach for optimization of the loop performance. The standard formulation ensures an unbiased estimate of the loop performance cost function gradient, which is used in a search algorithm for minimizing the performance cost. A slow rate of convergence of the tuning method is often experienced when tuning for disturbance rejection. This is due to a poor signal to noise ratio in the process data. A method is proposed for increasing the data information content by introducing an optimal perturbation signal in the tuning algorithm. The theoretical analysis is supported by a simulation example where the proposed method is compared to an existing method for acceleration of the convergence by use of optimal prefilters.
Autors: Jakob K. Huusom, Håkan Hjalmarsson, Niels K. Poulsen, Sten B. Jørgensen
Appeared in: Automatica
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A Design Method of Magnetically Resonanting Wireless Power Delivery Systems for Bio-Implantable Devices
Abstract:
Magnetic resonant wireless power transfer (MRWPT) technology has great potential in delivering power to bio-implantable devices as it obviates the need to have expensive battery replacement surgery. However, no systematic design method has been reported in this important area. In this paper, a design method of MRWPT system for bio-implantable devices, including detailed procedures, is proposed to realize maximum power transfer efficiency. Considerations on the basic dimensions of the system are outlined, and ways to express the impedance coefficients matrix of equivalent circuit model as functions of system variables are given. Experiment is carried out to verify the validity and effectiveness of the proposed design method.
Autors: Luo, X.;Niu, S.;Ho, S. L.;Fu, W. N.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Oct 2011, volume: 47, issue:10, pages: 3833 - 3836
Publisher: IEEE
 
» A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity
Abstract:
This brief presents a wide frequency range digitally controlled oscillator (DCO) with low supply sensitivity and low power consumption. We propose a compensation scheme employing feedforward inverters to suppress supply noise. Both wide frequency range and fine resolution are obtained using a hierarchical architecture consisting of a coarse delay chain and an interpolator. The proposed DCO was fabricated in a 0.13- CMOS process. It successfully eliminates noise components due to supply variation. The phase noise at 1-MHz frequency offset from the carrier frequency of 700 MHz is 106.3 dBc/Hz. The frequency range of the DCO is measured from 320 MHz to 1.25 GHz.
Autors: Seo, S.-Y.;Chun, J.-H.;Jun, Y.-H.;Kim, S.;Kwon, K.-W.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Oct 2011, volume: 58, issue:10, pages: 632 - 636
Publisher: IEEE
 
» A Distributed Control Strategy Based on DC Bus Signaling for Modular Photovoltaic Generation Systems With Battery Energy Storage
Abstract:
Modular generation system, which consists of modular power conditioning converters, is an effective solution to integrate renewable energy sources with conventional utility grid to improve reliability and efficiency, especially for photovoltaic generation. A distributed control strategy based on improved dc bus signaling is proposed for a modular photovoltaic (PV) generation system with battery energy storage elements. In this paper, the modular PV generation system is composed of three modular dc/dc converters for PV arrays, two grid-connected dc/ac converters, and one dc/dc converter for battery charging/discharging and local loads, which is available of either grid-connected operation or islanding operation. By using the proposed control strategy, the operations of a modular PV generation system are categorized into four modes: islanding with battery discharging, grid-connected rectification, grid-connected inversion, and islanding with constant voltage (CV) generation. The power balance of the system under extreme conditions such as the islanding operation with a full-charged battery is taken into account in this control strategy. The dc bus voltage level is employed as an information carrier to distinguish different modes and determine mode switching. Control methods of modular dc/dc converters, battery converter, and grid-connected converter are addressed. An autonomous control method for modular dc/dc converters is proposed to realize smooth switching between CV operation and maximum power point tracking operation, which enables the dc bus voltage regulation capability of modular dc/dc converters. Seamless switching of a battery converter between charging and discharging and that of a grid-connected converter between rectification and inversion are ensured by the proposed control methods. Experiments verify the practical feasibility and the effectiveness of the proposed control strategies.
Autors: Sun, K.;Zhang, L.;Xing, Y.;Guerrero, J. M.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Oct 2011, volume: 26, issue:10, pages: 3032 - 3045
Publisher: IEEE
 
» A driver's sixth sense
Abstract:
To find out what driving's like when you have a sixth sense, I took a radar-equipped Audi A8 around the highways and byways of Stuttgart, Germany. It was great. I couldn't help but smile when I pulled behind a huge truck and, resisting the temptation to hit the brakes, focused on steering. The adaptive cruise-control system, which uses a new radar from Robert Bosch that can see hundreds of meters ahead, did the rest. The system gently nestled the car behind the juggernaut and accelerated at my command, so I was able to pull out into the passing lane, all the while getting the most out of the 4.2-liter diesel, which rapidly
Autors: Stevenson, R.;
Appeared in: IEEE Spectrum
Publication date: Oct 2011, volume: 48, issue:10, pages: 50 - 55
Publisher: IEEE
 
» A dynamic gravimetric standard for trace water
Abstract:
A system for generating traceable reference standards of water vapor at trace levels between 5 and 2000 nmol/mol has been developed. It can provide different amount fractions of trace water vapor by using continuous accurate measurements of mass loss from a permeation device coupled with a dilution system based on an array of critical flow orifices. An estimated relative expanded uncertainty of ±2% has been achieved for most amount fractions generated. The system has been used in an international comparison and demonstrates excellent comparability with National Metrology Institutes maintaining standards of water vapor in this range using other methods.
Autors: Brewer, P. J.;Goody, B. A.;Woods, P. T.;Milton, M. J. T.;
Appeared in: Review of Scientific Instruments
Publication date: Oct 2011, volume: 82, issue:10, pages: 105102 - 105102-5
Publisher: IEEE
 
» A Eureka Moment [Microwave Surfing]
Abstract:
Five years ago, while I was in China (accompanying my younger daughter on a high-school field trip), I had the opportunity to experience the magnetic levitation technology firsthand when our group boarded the Shanghai Maglev Train [1] on the way to the Pudong International airport. Although the ride lasted only around seven minutes, the 267 mi/h top speed certainly provided an exhilarating experience.
Autors: Bansal, R.;
Appeared in: IEEE Microwave Magazine
Publication date: Oct 2011, volume: 12, issue:6, pages: 38 - 40
Publisher: IEEE
 
» A Facile Fabrication of Fe O /ZnO Core-Shell Submicron Particles With Controlled Size
Abstract:
Monodispersed superparamagnetic magnetite submicron particles were synthesized by using a one-step solvothermal method. Increasing the volume ratio of ethylene glycol/diethylene glycol (EG/DEG) shows a gradual increase in the size of primary nanograin and secondary Fe3O4 submicroparticles. To induce the photo-magnetic functionality, we have successfully synthesized the multifunctional core-shell (Fe3O4/ZnO) submicron particles by atomic layer deposition (ALD) method. Microstructure and magnetic properties of the multifunctional core/shell submicron particles are investigated by field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), vibrating sample magnetometry (VSM), and photoluminescence spectroscopy.
Autors: Kyong-Hoon Choi;Weon-Sik Chae;Eun-Mee Kim;Jong-Ho Jun;Jong-Hyung Jung;Yong-Rok Kim;Jin-Seung Jung;
Appeared in: IEEE Transactions on Magnetics
Publication date: Oct 2011, volume: 47, issue:10, pages: 3369 - 3372
Publisher: IEEE
 
» A Fast and Effective Control Scheme for the Dynamic Voltage Restorer
Abstract:
A novel control scheme for the dynamic voltage restorer (DVR) is proposed to achieve fast response and effective sag compensation capabilities. The proposed method controls the magnitude and phase angle of the injected voltage for each phase separately. Fast least error squares digital filters are used to estimate the magnitude and phase of the measured voltages. The utilized least error squares estimated filters considerably reduce the effects of noise, harmonics, and disturbances on the estimated phasor parameters. This enables the DVR to detect and compensate voltage sags accurately, under linear and nonlinear load conditions. The proposed control system does not need any phase-locked loops. It also effectively limits the magnitudes of the modulating signals to prevent overmodulation. Besides, separately controlling the injected voltage in each phase enables the DVR to regulate the negative- and zero-sequence components of the load voltage as well as the positive-sequence component. Results of the simulation studies in the PSCAD/EMTDC software environment indicate that the proposed control scheme 1) compensates balanced and unbalanced voltage sags in a very short time period, without phase jump and 2) performs satisfactorily under linear and nonlinear load conditions.
Autors: Ajaei, F. B.;Afsharnia, S.;Kahrobaeian, A.;Farhangi, S.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Oct 2011, volume: 26, issue:4, pages: 2398 - 2406
Publisher: IEEE
 
» A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology
Abstract:
A phase-locked loop (PLL) for analog video RGB signal acquisition interface requires precise clock generation from a very noisy and low-frequency horizontal synchronization signal (HSYNC). In such applications, the frequency multiplication ratio is always larger than 800 and can be up to over 2600. The output pixel clock has to be phase aligned to the HSYNC. Otherwise, the displayed image will become blurry. A fast phase tracking all-digital PLL (ADPLL) for video pixel clock generation in a 65 nm CMOS technology is presented in this paper. In the proposed ADPLL, the digital loop filter eliminates the reference clock jitter effects and then the period jitter of the output pixel clock can be reduced. A time-to-digital converter (TDC) and a delta-sigma modulator (DSM) are used to perform the fast phase tracking, and the tracking jitter is controlled at less than one-third of the output pixel clock period. As compared to prior studies, the proposed ADPLL does not require an extra external oscillator to overcome the reference clock jitter effects. Thus, it has a small chip area and low power consumption, and is well-suited to video pixel clock generation applications in 65 nm CMOS process.
Autors: Chung, C.-C.;Ko, C.-Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Oct 2011, volume: 46, issue:10, pages: 2300 - 2311
Publisher: IEEE
 
» A Feature Scale Greenwood-Williamson Model Predicting Pattern-Size Effects In CMP
Abstract:
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Autors:

Graphical abstract

Appeared in: Microelectronic Engineering
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A feedback-based-norm limiter for periodic signals
Abstract:
Limiting the rms value (norm) of periodic signals can be a necessity in some controllers for power electronic devices. The prevailing existing solution is simply to compute, off-line, thenorm and then to multiply the signal by the factor that ensures the desired bound is achieved. This feedforward procedure could yield unsatisfactory results during the transients of the system. In this paper, a feedback-based algorithm that carries out the computations on-line is proposed. Besides the on-line computation of thenorm, the second component of the algorithm is a classical proportional-integral loop with an anti-windup mechanism. Although the overall algorithm is described by complicated nonlinear, non-autonomous, delay-differential equations, a detailed stability analysis is carried out, proving its robust performance. Simulation results, that confirm the theoretical results, are presented.
Autors: Robert Griñó, Romeo Ortega, Enric Fossas
Appeared in: Automatica
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A Fiber Bragg Grating Tension and Tilt Sensor Applied to Icing Monitoring on Overhead Transmission Lines
Abstract:
A novel ice monitoring system for the overhead transmission lines based on fiber Bragg grating (FBG) sensing is proposed in this paper. Compared to the existing systems, this system has several unique advantages, such as unnecessary power supply onsite, excellent ability for avoiding electromagnetic interference, and long lifespan. First, two near-elliptical-shaped concavities with FBG in each side are designed on the column structure to improve accuracy in measuring eccentric load. Then, a high reliability and high resolution tilt sensing section is developed based on a beam of uniform strength where an FBG is fixed on. Finally, an unforced FBG is placed in the sensor to solve the cross-sensitivity of strain and temperature in FBG sensing. Tension and angle experiments are conducted in our laboratory to calibrate the sensor. The tension experiment results indicate that the sensor is sensitive to tension, and the sensitivity and resolution of the sensor are 0.0413 pm/N and 24.21 N. The results of the tilt angle experiment show that the sensitivity and resolution of the sensor is 16.17 pm and 0.0619 . The temperature effect on the tension and angle measurement, evaluated by putting the sensor in an oven, is less than 0.3% and 0.38% separately. A 250-h outdoor experiment was carried out in the testing field, and the results prove the sensor can work properly in harsh environments and no creep is observed during the experiment.
Autors: Ma, G.;Li, C.;Quan, J.;Jiang, J.;Cheng, Y.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Oct 2011, volume: 26, issue:4, pages: 2163 - 2170
Publisher: IEEE
 
» A finite weakest-link model of lifetime distribution of high-kgate dielectrics under unipolar AC voltage stress
Abstract:
This paper presents a new probability distribution function for the breakdown lifetime of high-kgate dielectrics under unipolar AC voltage stress. This function is derived from a finite weakest-link model, where the gate oxide layer is considered to consist of many potential breakdown cells. Each potential breakdown cell is modeled as a series coupling of several subcells, which is analogous to the fiber-bundle model for the strength statistics of structures. The present model indicates that the type of lifetime distribution varies with the gate area and the dependence of the mean lifetime on the gate area deviates from the classical Weibull scaling law. It is shown that the model agrees well with the observed lifetime histograms of HfO2based gate dielectrics under unipolar AC voltage stress.
Autors: Jia-Liang Le
Appeared in: Microelectronics Reliability
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A Five-/Nine-Level Twelve-Switch Neutral-Point-Clamped Inverter for High-Speed Electric Drives
Abstract:
A five-/nine-level twelve-switch inverter is described for three-phase high-speed electric machines having a low per-unit leakage reactance. By reducing the voltage blocking requirement of the semiconductors, the neutral-point-clamped (NPC) variant of the coupled inductor (CI) inverter topology (NPC-CI) is more suited to high dc bus voltages than the six-switch alternative (six-switch CI). Operational and design details are described for the NPC-CI inverter using a three-limb inductor core, including practical considerations for the inverter construction and operation, 480 V/208 V inductor mass comparison between six- and twelve-switch topologies, natural voltage balancing of the split-capacitor dc link, and voltage stresses of the freewheel diodes. Improvements in machine performance are illustrated using two experimental test rigs: an unloaded 18 000-r/min 15-hp induction machine to illustrate improved harmonic quality when operating with a limited switching frequency and a high fundamental output frequency, and a loaded 2-hp utility speed induction machine to demonstrate transient performance.
Autors: Ewanchuk, J.;Salmon, J.;Vafakhah, B.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Oct 2011, volume: 47, issue:5, pages: 2145 - 2153
Publisher: IEEE
 
» A Focused Asymmetric Metal–Insulator–Metal Tunneling Diode: Fabrication, DC Characteristics and RF Rectification Analysis
Abstract:
Asymmetric thin-film metal–insulator–metal (MIM) tunneling diodes have been demonstrated using the geometric field enhancement (GFE) technique in a Ni/NiO/Ni structure. The GFE technique provides several benefits: generating asymmetric tunneling currents, lowering tunneling resistance, increasing nonlinearity, enhancing the effective ac signal amplitude, and improving zero-bias rectifying performance. The GFE technique can be merged with a dissimilar electrode method and use surface plamon resonances for further performance improvement. In this paper, we disclose techniques for fully exploiting all these advantages. Detailed descriptions of process flows are provided. Performance improvements are experimentally verified by measuring the static current–voltage and dynamic (6.4 GHz) response of the developed Ni/NiO/Ni tunnel diodes.
Autors: Choi, K.;Yesilkoy, F.;Ryu, G.;Cho, S. H.;Goldsman, N.;Dagenais, M.;Peckerar, M.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Oct 2011, volume: 58, issue:10, pages: 3519 - 3528
Publisher: IEEE
 
» A framework for authentication in NBD tactical Ad Hoc networks
Abstract:
Network-based defense (NBD) and the all-IP network make authentication ever more important. However, a generally accepted and comprehensive authentication suite is lacking. This work is a step toward filling the gap. The article proposes a three-level framework for authentication in NBD tactical ad hoc networks. Hop-by-hop network-level authentication provides basic protection. End-to-end application-level authentication is included only when finer resolution is needed. The third level of authentication relates to physical node access. The framework may serve as a reference for authentication in other networks as well. An additional contribution is the approach used to derive the authentication framework, which has general relevance.
Autors: Hegland, A.M.;Winjum, E.;Hedenstad, O.-E.;
Appeared in: IEEE Communications Magazine
Publication date: Oct 2011, volume: 49, issue:10, pages: 64 - 71
Publisher: IEEE
 
» A framework for real-time implementation of low-dimensional parameterized NMPC
Abstract:
In this paper, a novel approach is proposed to implement low-dimensional parameterized Nonlinear Model Predictive Control (NMPC) schemes for systems showing fast dynamics. The proposed scheme is based on distributing the reconstruction of the cost function over the real lifetime of the controlled system. The framework is particularly suitable for NMPC formulations that use low dimensional control parametrization. The concrete example of a Planar Vertical Take-Off and Landing (PVTOL) aircraft stabilization problem is used to illustrate the efficiency of the proposed formulation.
Autors: Mazen Alamir
Appeared in: Automatica
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A Framework to Quantify the Pitfalls of Using Traceroute in AS-Level Topology Measurement
Abstract:
Although traceroute has the potential to discover AS links that are invisible to existing BGP monitors, it is well known that the common approach for mapping router IP addresses to AS numbers based on BGP routing tables is highly error-prone. We develop a systematic framework to quantify the potential errors of traceroute measurement in AS-level topology inference. In comparing traceroute-derived AS paths with BGP AS paths, we take a novel approach to identifying mismatched path segments and then inferring the causes of these mismatches through a set of tests. Our results show that about 60% of mismatches are due to routers using IP addresses belonging to peering neighbors. This result helps settle a debate in previous works regarding the major cause of errors in traceroute measurement. With the approximate ground truth of the ASes with BGP monitors inside, we identify the inaccuracy of publicly available traceroute-derived topology datasets and find that between 8% and 42% of AS adjacencies on the monitored ASes are false. With a new method to characterize AS links, we show that the derived (false) links between Tier-1/large ISPs and their customers' customers appear more frequently than real links do.
Autors: Zhang, Yu;Oliveira, Ricardo;Wang, Yangyang;Su, Shen;Zhang, Baobao;Bi, Jun;Zhang, Hongli;Zhang, Lixia;
Appeared in: IEEE Journal on Selected Areas in Communications
Publication date: Oct 2011, volume: 29, issue:9, pages: 1822 - 1836
Publisher: IEEE
 
» A Fully Analytical Model for the Series Impedance of Through-Silicon Vias With Consideration of Substrate Effects and Coupling With Horizontal Interconnects
Abstract:
This paper introduces a fully analytical and physical model capable of extracting high-frequency series impedance of through-silicon vias (TSVs) in 3-D integrated chips with consideration of the eddy currents in the surrounding Si substrate and coupling with horizontal interconnects. The model employs the vertical-to-vertical and horizontal-to-vertical 3D vector potential Green's function in layered media and is concise and sufficiently accurate in the entire range of interest for both the frequency and the center-to-center distance between TSVs. Along with the series impedances between horizontal wires, which are extracted from the discrete complex image method, as well as the TSV and horizontal wire capacitance values, the total loop impedance can be obtained. Our approach is verified against a full-wave finite- element-method electromagnetic solver High Frequency Structure Simulator, and it shows good accuracy ( 7% error) in the entire frequency range examined (up to 100 GHz). Given the fact that the formulated TSV series impedance model is purely analytical, the model could be efficiently used for system-level interconnect impedance extraction in emerging 3-D integrated systems.
Autors: Xu, C.;Kourkoulos, V.;Suaya, R.;Banerjee, K.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Oct 2011, volume: 58, issue:10, pages: 3529 - 3540
Publisher: IEEE
 
» A Fully Passive Wireless Microsystem for Recording of Neuropotentials Using RF Backscattering Methods
Abstract:
The ability to safely monitor neuropotentials is essential in establishing methods to study the brain. Current research focuses on the wireless telemetry aspect of implantable sensors in order to make these devices ubiquitous and safe. Chronic implants necessitate superior reliability and durability of the integrated electronics. The power consumption of implanted electronics must also be limited to within several milliwatts to microwatts to minimize heat trauma in the human body. In order to address these severe requirements, we developed an entirely passive and wireless microsystem for recording neuropotentials. An external interrogator supplies a fundamental microwave carrier to the microsystem. The microsystem comprises varactors that perform nonlinear mixing of neuropotential and fundamental carrier signals. The varactors generate third-order mixing products that are wirelessly backscattered to the external interrogator where the original neuropotential signals are recovered. Performance of the neurorecording microsystem was demonstrated by wireless recording of emulated and in vivo neuropotentials. The obtained results were wireless recovery of neuropotentials as low as approximately 500 microvolts peak-to-peak ( ) with a bandwidth of 10 Hz to 3 kHz (for emulated signals) and with 128 epoch signal averaging of repetitive signals (for in vivo signals). [2010-0338]
Autors: Schwerdt, H. N.;Xu, W.;Shekhar, S.;Abbaspour-Tamijani, A.;Towe, B. C.;Miranda, F. A.;Chae, J.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Oct 2011, volume: 20, issue:5, pages: 1119 - 1130
Publisher: IEEE
 
» A fuzzy adaptive chaotic ant swarm optimization for economic dispatch
Abstract:

Highlights

? A FCASO algorithm is developed for solving the ED problems. ? The FCASO algorithm embeds a fuzzy system to dynamically tune the parameters of CASO. ? The application of the proposed method demonstrates its effectiveness to the ED problems.


Autors: This paper developed a fuzzy adaptive chaotic ant swarm optimization (FCASO) algorithm for solving the economic dispatch (ED) problems of thermal generators in power systems. The FCASO algorithm introduces a fuzzy system to dynamically tune the chara
Appeared in: International Journal of Electrical Power & Energy Systems
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A Fuzzy Association Rule-Based Classification Model for High-Dimensional Problems With Genetic Rule Selection and Lateral Tuning
Abstract:
The inductive learning of fuzzy rule-based classification systems suffers from exponential growth of the fuzzy rule search space when the number of patterns and/or variables becomes high. This growth makes the learning process more difficult and, in most cases, it leads to problems of scalability (in terms of the time and memory consumed) and/or complexity (with respect to the number of rules obtained and the number of variables included in each rule). In this paper, we propose a fuzzy association rule-based classification method for high-dimensional problems, which is based on three stages to obtain an accurate and compact fuzzy rule-based classifier with a low computational cost. This method limits the order of the associations in the association rule extraction and considers the use of subgroup discovery, which is based on an improved weighted relative accuracy measure to preselect the most interesting rules before a genetic postprocessing process for rule selection and parameter tuning. The results that are obtained more than 26 real-world datasets of different sizes and with different numbers of variables demonstrate the effectiveness of the proposed approach.
Autors: Alcala-Fdez, J.;Alcala, R.;Herrera , F.;
Appeared in: IEEE Transactions on Fuzzy Systems
Publication date: Oct 2011, volume: 19, issue:5, pages: 857 - 872
Publisher: IEEE
 
» A General Resource Allocation Algorithm with Fairness for SDMA/MISO/OFDMA Systems
Abstract:
This paper considers the resource allocation problem of Space Division Multiple Access (SDMA)/ Multiple Input Single Output (MISO)/Orthogonal Frequency Division Multiple Access (OFDMA) systems. Equal power allocation (EPA) is used among subcarriers to reduce the complexity of the problem. Furthermore, a novel algorithm called proportional rate greedy (PRG) is proposed to choose users and allocate powers among selected users for each subcarrier. Such EPA-PRG algorithm can be applied to different fairness issues. From simulation, it can both achieve high throughput and ensure the fairness among users without increasing the complexity.
Autors: Lu, Weishan;Ji, Fei;Yu, Hua;
Appeared in: IEEE Communications Letters
Publication date: Oct 2011, volume: 15, issue:10, pages: 1072 - 1074
Publisher: IEEE
 
» A Generalized Accelerated Proximal Gradient Approach for Total-Variation-Based Image Restorationquery valign="-12pt" COPYEDITED FILE
Abstract:
This paper proposes a generalized accelerated proximal gradient (GAPG) approach for solving total variation (TV)-based image restoration problems. The GAPG algorithm generalizes the original APG algorithm by replacing the Lipschitz constant with an appropriate positive-definite matrix, resulting in faster convergence. For TV-based image restoration problems, we further introduce two auxiliary variables that approximate the partial derivatives. Constraints on the variables can easily be imposed without modifying the algorithm much, and the TV regularization can be either isotropic or anisotropic. As compared with the recently developed APG-based methods for TV-based image restoration, i.e., monotone version of the two-step iterative shrinkage/thresholding algorithm (MTwIST) and monotone version of the fast IST algorithm (MFISTA), our GAPG is much simpler as it does not require to solve an image denoising subproblem. Moreover, the convergence rate of is maintained by our GAPG, where is the number of iterations; the cost of each iteration in GAPG is also lower. As a result, in our experiments, our GAPG approach can be much faster than MTwIST and MFISTA. The experiments also verify that our GAPG converges faster than the original APG and MTwIST when they solve identical problems.
Autors: Zuo, W.;Lin, Z.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Oct 2011, volume: 20, issue:10, pages: 2748 - 2759
Publisher: IEEE
 
» A Generalized Prefix Construction for OFDM Systems Over Quasi-Static Channels
Abstract:
All practical orthogonal frequency-division multiplexing (OFDM) systems require a prefix to eliminate intersymbol interference (ISI) at the receiver. Cyclic prefix (CP) and zero padding are well-known prefix construction methods, with the former being the most employed technique in practice due to its lower complexity. In this paper, we construct an OFDM system with a generalized CP. It is shown that the proposed generalized prefix effectively makes the channel experienced by the packet different from the actual channel. Using an optimization procedure, lower bit error rates (BERs) can be achieved, outperforming other prefix construction techniques. At the same time, the complexity of the technique is comparable with the CP method. The presented simulation results show that the proposed technique not only outperforms the CP method but is more robust in the presence of channel estimation errors and mobility as well. Therefore, the proposed method is appropriate for practical OFDM systems.
Autors: Cooklev, T.;Dogan, H.;Cintra, R. J.;Yildiz, H.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Oct 2011, volume: 60, issue:8, pages: 3684 - 3693
Publisher: IEEE
 
» A Generalized Rotate-and-Fire Digital Spiking Neuron Model and Its On-FPGA Learning
Abstract:
A generalized rotate-and-fire digital spiking neuron model that can be implemented by a simple asynchronous sequential logic circuit is proposed. The model can exhibit various nonlinear phenomena and responses to stimulation inputs. It is shown that the model can reproduce five types of inhibitory responses of Izhikevich's simplified ordinary differential equation neuron model. In addition, field programmable gate array experiments show that a learning algorithm enables the model to automatically reproduce nonlinear responses of a biological neuron and neuron models in the neuron simulator.
Autors: Matsubara, T.;Torikai, H.;Hishiki, T.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Oct 2011, volume: 58, issue:10, pages: 677 - 681
Publisher: IEEE
 
» A gradient-based alternating minimization approach for optimization of the measurement matrix in compressive sensing
Abstract:

Highlights

? An alternate minimization method proposed to reduce coherence in measurement matrix. ? A gradient-based technique with both fixed and adaptive stepsizes was proposed. ? Extensive experiments conducted to assess different aspects of the proposed method. ? Optimization of measurement matrix improves the performance of sparse recovery. ? The proposed method is superior to other existing methods.


Autors: In this paper the problem of optimization of the measurement matrix in compressive (also called compressed) sensing framework is addressed. In compressed sensing a measurement matrix that has a smallcoherencewith the sparsifying dictionary (or basis)
Appeared in: Signal Processing
Publication date: Oct 2011
Publisher: Elsevier B.V.
 
» A Halting Algorithm to Determine the Existence of the Decoder
Abstract:
Complementary synthesis automatically synthesizes the decoder circuit of an encoder. It determines the existence of the decoder by checking whether the encoder's input can be uniquely determined by its output. However, this algorithm will not halt if the decoder does not exist. To solve this problem, a novel halting algorithm is proposed. For every path of the encoder, this algorithm first checks whether the encoder's input can be uniquely determined by its output. If yes, the decoder exists; otherwise, this algorithm checks if this path contains loops, which can be further unfolded to prove the non-existence of the decoder for all those longer paths. To illustrate its usefulness and efficiency, this algorithm has been run on several complex encoders, including PCI-E and Ethernet. Experimental results indicate that this algorithm always halts properly by distinguishing correct encoders from incorrect ones, and it is more than three times faster than previous ones.
Autors: Shen, S.;Qin, Y.;Xiao, L.;Wang, K.;Zhang, J.;Li, S.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Oct 2011, volume: 30, issue:10, pages: 1556 - 1563
Publisher: IEEE
 

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