Electrical and Electronics Engineering publications abstract of: 09-2015 sorted by title, page: 0

» "Let's Share a Story"': Socially Enhanced Multimedia Storytelling
Abstract:
User-generated audio-visual content is becoming the most popular medium for information sharing and social storytelling around live events. In this article, the authors introduce an online multimedia storytelling ecosystem comprised of purpose-built user applications, a collaborative story-authoring engine, social context integration, and socially aware media services. As their event-based user experiments illustrate, the system enables online collaborative story coauthoring and provides an ideal platform to study the synergy between social networks and networked media in enhancing the user experience of storytelling. This article is part of a special issue on social multimedia and storytelling.
Autors: Mu Mu;Simpson, S.;Race, N.;Niamut, O.;Koot, G.;Kaptein, R.;Taal, J.;Mori, L.;
Appeared in: IEEE Multimedia
Publication date: Sep 2015, volume: 22, issue:3, pages: 54 - 65
Publisher: IEEE
 
» “Arc Flash” Hazards, Incident Energy, PPE Ratings, and Thermal Burn Injury—A Deeper Look
Abstract:
Tremendous resources are being invested in arc flash studies and personal protective equipment (PPE) to protect workers from “arc flash” hazards. In the flurry to comply with OSHA regulations and NFPA 70 and 70E standards, the real understanding of the arc hazard and incident energy may be lagging behind. The term “arc flash” does not adequately convey the range of potential arc hazards—light, pressure, and heat transmission, as well as others. The term “arc flash” also fails to emphasize that arc flash injuries primarily arise from thermal burns and that the risk of a potentially severe or fatal arc burn is often present when performing electrical work. Worker risk assessment and the appropriate PPE are represented as definitive quantities in “cal/cm 2;” however, the quantitative potential heat exposure and heat protection afforded by PPE are usually less precise than what concrete numerical values imply. Basic concepts of incident energy, PPE ratings, and burn injury are also explored in this paper to help identify factors influencing the burn hazards posed by arcing faults in electrical power systems.
Autors: Gammon, T.;Lee, W.;Zhang, Z.;Johnson, B.C.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Sep 2015, volume: 51, issue:5, pages: 4275 - 4283
Publisher: IEEE
 
» (InP) HEMT Small-Signal Equivalent-Circuit Extraction as a Function of Temperature
Abstract:
HEMT small-signal equivalent-circuit (SSEC) extractions are of great utility in device characterization, as well as in the design of low-noise amplifiers. Despite the importance of low-noise HEMTs in cryogenic applications, the literature shows little or no work on the temperature dependence of SSEC extractions. This work addresses the question in detail. We recently reported a robust nondestructive accurate room-temperature extraction procedure that we presently apply to InP HEMTs between 5 and 350 K. The extracted SSEC reproduces measured S-parameters well as a function of temperature without the need for optimization. As well, extrinsic resistance and inductive element values exhibit physically correct temperature variations and thereby support the suitability of the present procedure down to cryogenic temperatures. Our work provides a detailed characterization of HEMT SSEC extractions over the broadest temperature range published to date.
Autors: Alt, A.R.;Bolognesi, C.R.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Sep 2015, volume: 63, issue:9, pages: 2751 - 2755
Publisher: IEEE
 
» 1.2 V–0.18- CMOS Temperature Sensors With Quasi-Digital Output for Portable Systems
Abstract:
This paper presents two compact frequency-output temperature sensors based on a multivibrator current-to-frequency converter to improve sensor linearity over a wide temperature range featuring low-voltage low-power operation. Both sensors have been fabricated in a low-cost 0.18-μm CMOS technology with a single 1.2 V supply voltage. They show high linearity over a temperature range of -40°C to +120°C, achieving an inaccuracy of ±1°C, with sensitivities of 335 Hz/°C and 460 Hz/°C, a power consumption below 3 μW, and an area below 0.025 mm2. These features make them a highly suitable solution in the case of portable applications.
Autors: Azcona, C.;Calvo, B.;Medrano, N.;Celma, S.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Sep 2015, volume: 64, issue:9, pages: 2565 - 2573
Publisher: IEEE
 
» 1.2 V–0.18- CMOS Temperature Sensors With Quasi-Digital Output for Portable Systems
Abstract:
This paper presents two compact frequency-output temperature sensors based on a multivibrator current-to-frequency converter to improve sensor linearity over a wide temperature range featuring low-voltage low-power operation. Both sensors have been fabricated in a low-cost 0.18-μm CMOS technology with a single 1.2 V supply voltage. They show high linearity over a temperature range of -40°C to +120°C, achieving an inaccuracy of ±1°C, with sensitivities of 335 Hz/°C and 460 Hz/°C, a power consumption below 3 μW, and an area below 0.025 mm2. These features make them a highly suitable solution in the case of portable applications.
Autors: Azcona, C.;Calvo, B.;Medrano, N.;Celma, S.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Sep 2015, volume: 64, issue:9, pages: 2565 - 2573
Publisher: IEEE
 
» 11th WFCS 2015 on a Mediterranean Island [Society News]
Abstract:
Presents information on the 11th WFCS 2015.
Autors: Proenza, J.;Sauter, T.;
Appeared in: IEEE Industrial Electronics Magazine
Publication date: Sep 2015, volume: 9, issue:3, pages: 51 - 52
Publisher: IEEE
 
» 150–850 MHz High-Linearity Sine-wave Synthesizer Architecture Based on FIR Filter Approach and SFDR Optimization
Abstract:
A low distortion sinusoidal waveform synthesizer architecture is proposed. The synthesizer utilizes 50% duty cycle and differential-mode circuitry to eliminate the even order harmonics, and it also implements a 5-phase 3-amplitude harmonic cancellation technique to suppress the 3rd, 5th, 7th, and 9th order harmonics. The compact system architecture consists of a 12-phase ring oscillator, a weighted resistor summing network, and an RC output filter. Phase shifters are adopted in the ring oscillator to enable the control of an external harmonic cancellation optimization algorithm. The proposed application of the optimization algorithm compensates the errors in the circuit and further improves the linearity of the output waveforms. This synthesizer is fabricated in 180 nm standard CMOS technology, occupies a 0.08 silicon area and achieves the spur-free dynamic range (SFDR) of 59 to 70 dBc from 150 to 850 MHz after the optimization procedure. It can operate from a 1 to 1.8 V supply voltage and achieve a power consumption from 9.11 to 57 mW.
Autors: Shi, C.;Sanchez-Sinencio, E.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Sep 2015, volume: 62, issue:9, pages: 2227 - 2237
Publisher: IEEE
 
» 2015 Humanitarian Robotics and Automation Technology Challenge [Humanitarian Technology]
Abstract:
Presents information on the RASS 2015 Humanitarian Robotics and Automation Technology Challenge.
Autors: Madhavan, R.;Marques, L.;Prestes, E.;Maffei, R.;Jorge, V.;Gil, B.;Dogru, S.;Cabrita, G.;Neuland, R.;Dasgupta, P.;
Appeared in: IEEE Robotics & Automation Magazine
Publication date: Sep 2015, volume: 22, issue:3, pages: 182 - 184
Publisher: IEEE
 
» 2015 IERA Award Joint Winners, Seattle [Industrial Activities]
Abstract:
Presents the recipients of the RAS Society 2015 IERA Award Joint Winners.
Autors: Madhavan, R.;
Appeared in: IEEE Robotics & Automation Magazine
Publication date: Sep 2015, volume: 22, issue:3, pages: 17 - 18
Publisher: IEEE
 
» 2015 Industrial Electronics Society Awards [Society News]
Abstract:
Presents a listing of the recipients of select 2015 Industrial Electronics Society Awards.
Autors: Sauter, T.;
Appeared in: IEEE Industrial Electronics Magazine
Publication date: Sep 2015, volume: 9, issue:3, pages: 56 - 56
Publisher: IEEE
 
» 2015 Joint Rail Conference [Conference Report]
Abstract:
Autors: Ku, B.;
Appeared in: IEEE Vehicular Technology Magazine
Publication date: Sep 2015, volume: 10, issue:3, pages: 92 - 94
Publisher: IEEE
 
» 21CW: Norbert Wiener in the 21st Century [Guest Editorial]
Abstract:
The articles in this special section focus on the work and life of Dr. Norbert Wiener (1894???1964), who is considered one of the quintessential multi-disciplinarians of our time. He is considered the "Father of Cybernetics." During his life, Wiener influenced mathematics, philosophy, science, technology, ethics, biology, prosthesis, education, manufacturing, and many other fields. He was an early practitioner of diversity and social inclusion, and an advocate of social responsibility in the development of technology. He predicted the social impact of robotic, cybernetic, and other technologies on the future of society, and after several decades his writings retain their relevance.
Autors: Hall, P.;Love, H.;Uesugi, S.;
Appeared in: IEEE Technology and Society Magazine
Publication date: Sep 2015, volume: 34, issue:3, pages: 33 - 34
Publisher: IEEE
 
» 3-D Cameras: A Novel Method and Device for 3-D Imaging Using Light Detection and Ranging [From Mind to Market]
Abstract:
In this column, we provide a method and device for measuring the distance of a targeted object (pixels in this case) based on a number of reflected light signals with low cost and high resolution. The distance is obtained by the phase difference between the transmitted and received signals. Consequently, the technology provides the high-resolution three-dimensional (3-D) image beyond the two-dimensional (2-D) image. This invention can be used in many industrial products, e.g., an examination device for sorting out defective goods. We expect that this technology will contribute to the development of the next generation of digital cameras in the near future.
Autors: Lim, J.;Kim, T.;
Appeared in: IEEE Industrial Electronics Magazine
Publication date: Sep 2015, volume: 9, issue:3, pages: 6 - 8
Publisher: IEEE
 
» 3-D Fourier Series Based Digital Predistortion Technique for Concurrent Dual-Band Envelope Tracking With Reduced Envelope Bandwidth
Abstract:
In this paper, the design, implementation, and measurement results of a new digital predistortion (DPD) method for a concurrent dual-band envelope tracking (ET) power amplifier (PA) system is presented. The PA gain is represented using a set of 3-D orthogonal Fourier series basis functions, which accounts for the distortions introduced by the two signal bands, as well as the supply modulation voltage. Here, the new Fourier series basis is shown to substantially outperform the traditional memory polynomial approach in terms of its linearization capability for subsequent data for which it was not trained for (prediction) due to its well-defined numerical rank and stability. The new DPD system was implemented using a 10-W peak gallium–nitride (GaN) ET PA operating with a dual-band input based on long-term evolution and WCDMA signals center frequency (1.89 and 2.2 GHz) spaced by 310 MHz. The linearization results are compared to the 3-D memory polynomial in two steps: extraction and prediction. In the DPD coefficient extraction phase, tested under the same signal, the traditional memory polynomial and the Fouries series reach close results in both normalized mean square error (NMSE) and adjacent channel power ratio (ACPR). In the prediction phase, however, the proposed method provides a significant performance improvement. A performance improvement as high as 17 dB in terms of NMSE and 4.6 dB in terms of ACPR in comparison to the conventional dual-band 3-D memory polynomial method implementing ET. Furthermore, the well-defined numerical rank of the Fourier series approach allows for a substantial reduction in coefficients using principal component analysis without detrimenting performance.
Autors: Lin, Y.;Quindroit, C.;Jang, H.;Roblin, P.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Sep 2015, volume: 63, issue:9, pages: 2764 - 2775
Publisher: IEEE
 
» 3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability
Abstract:
The 3-D integrated dynamic random-access memory (DRAM) structure with a processor is being widely studied due to advantages, such as a large band-width and data communication power reduction. In these structures, the massive heat generation of the processor results in a high operating temperature and a high refresh rate of the DRAM. Thus, in the 3-D DRAM over processor architecture, temperature-aware refresh management is necessary. However, temperature determination is difficult, because in the 3-D DRAM, the temperature changes dynamically and temperature variation in a DRAM die is complicated. In this paper, a thermal guard-band set-up method for 3-D stacked DRAM is proposed. It considers the latency of the temperature data and the position difference between the temperature sensor and the DRAM cell. With this method, the data reliability of the on-chip temperature sensor-dependent adaptive refresh control is guaranteed. In addition, an efficient temperature sensor built-in and refresh control method is analyzed. The expected refresh power reduction is examined through a simulation.
Autors: Lim, J.;Lim, H.;Kang, S.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Sep 2015, volume: 34, issue:9, pages: 1455 - 1466
Publisher: IEEE
 
» 60 GHz CMOS Wideband Differential Driving Amplifier Using Multi-Section Coupled Lines
Abstract:
This letter presents a 60 GHz wideband differential driving amplifier based on multi-section coupled lines (MSCL) matching network for the first time. The impedance transforming of the proposed two-port matching network is realized in a single structure. It is suitable for millimeter wave CMOS integrated circuit design since the proposed matching network eliminates the self-resonant and defected-ground problems which exist in the traditional transformer or inductor based matching networks. It provides an inherent DC-block function and is compact in size compared with the conventional transmission line based matching technique. Using the proposed network, a differential amplifier in 65 nm CMOS is designed, measured and discussed. Wideband and high gain performance is achieved.
Autors: Zhang, H.;Xue, Q.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Sep 2015, volume: 25, issue:9, pages: 600 - 602
Publisher: IEEE
 
» Filtering for Discrete-Time Switched Systems With Known Sojourn Probabilities
Abstract:
This technical note deals with the design of mode-dependent H filters for a class of discrete-time switched systems with nonlinearities. In this class of systems, when the system mode changes, the filter designed for the specific subsystem also switches accordingly. The main contribution is on the use of the information of the sojourn probability-the probability of the switched system staying in each subsystem-to build new kind of switched system model when this additional information is available. Sojourn probabilities are easier to obtain than the transition probabilities commonly used in Markovian jump systems. Applying the Lyapunov functional method, the bounded real lemma (BRL) for the resulting filtering error system is obtained in Theorem 1. The filter parameters are designed in Theorem 2 by solving a set of linear matrix inequalities. Finally, two illustrative examples are given to demonstrate the effectiveness and potential of the proposed approach.
Autors: Engang Tian;Wong, W.K.;Dong Yue;Tai-Cheng Yang;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Sep 2015, volume: 60, issue:9, pages: 2446 - 2451
Publisher: IEEE
 
» Filtering for Discrete-Time Switched Systems With Known Sojourn Probabilities
Abstract:
This technical note deals with the design of mode-dependent filters for a class of discrete-time switched systems with nonlinearities. In this class of systems, when the system mode changes, the filter designed for the specific subsystem also switches accordingly. The main contribution is on the use of the information of the sojourn probability—the probability of the switched system staying in each subsystem—to build new kind of switched system model when this additional information is available. Sojourn probabilities are easier to obtain than the transition probabilities commonly used in Markovian jump systems. Applying the Lyapunov functional method, the bounded real lemma (BRL) for the resulting filtering error system is obtained in Theorem 1. The filter parameters are designed in Theorem 2 by solving a set of linear matrix inequalities. Finally, two illustrative examples are given to demonstrate the effectiveness and potential of the proposed approach.
Autors: Tian, E.;Wong, W.K.;Yue, D.;Yang, T.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Sep 2015, volume: 60, issue:9, pages: 2446 - 2451
Publisher: IEEE
 
» In Situ Process Control of Trilayer Gate-Stacks on p-Germanium With 0.85-nm EOT
Abstract:
In situ spectroscopic ellipsometry was utilized in an atomic-layer-deposition (ALD) reactor for rapid and rational gate stack process optimization of the trilayer dielectric HfO2/Al2O3/GeOx on Ge. The benefit of this approach was demonstrated by developing an entire process in situ: 1) native oxide removal by hydrogen plasma; 2) controlled reoxidation for Ge surface passivation; and 3) deposition of Al2O3 and HfO2 using thermal ALD. The low- layer thicknesses were scaled down without losing their respective functions, i.e., GeOx to form an electrically well behaved interface with Ge and Al2O3 to thermodynamically stabilize the GeOx /Ge interface. Aggressive equivalent-oxide-thickness scaling of the trilayer stack down to 0.85 nm with a low gate leakage of 0.15 mA/cm2 at –1 V was achieved, while preserving a high-quality dielectric-semiconductor interface.
Autors: Zheng, Y.X.;Agrawal, A.;Rayner, G.B.;Barth, M.J.;Ahmed, K.;Datta, S.;Engel-Herbert, R.;
Appeared in: IEEE Electron Device Letters
Publication date: Sep 2015, volume: 36, issue:9, pages: 881 - 883
Publisher: IEEE
 
» Cina: Suppressing the Detection of Unstable Context Inconsistency
Abstract:
Context-aware applications adapt their behavior based on contexts. Contexts can, however, be incorrect. A popular means to build dependable applications is to augment them with a set of constraints to govern the consistency of context values. These constraints are evaluated upon context changes to detect inconsistencies so that they can be timely handled. However, we observe that many context inconsistencies are unstable. They vanish by themselves and do not require handling. Such inconsistencies are detected due to misaligned sensor sampling or improper inconsistency detection scheduling. We call them unstable context inconsistencies (or STINs). STINs should be avoided to prevent unnecessary inconsistency handling and unstable behavioral adaptation to applications. In this article, we study STINs systematically, from examples to theoretical analysis, and present algorithms to suppress their detection. Our key insight is that only certain patterns of context changes can make a consistency constraint subject to the detection of STINs. We derive such patterns and proactively use them to suppress the detection of STINs. We implemented our idea and applied it to real-world applications. Experimental results confirmed its effectiveness in suppressing the detection of numerous STINs with negligible overhead, while preserving the detection of stable context inconsistencies that require inconsistency handling.
Autors: Xu, C.;Xi, W.;Cheung, S.;Ma, X.;Cao, C.;Lu, J.;
Appeared in: IEEE Transactions on Software Engineering
Publication date: Sep 2015, volume: 41, issue:9, pages: 842 - 865
Publisher: IEEE
 
» ???New Japan??? at 70 [Numbers Don???t Lie]
Abstract:
On 2 September 1945, representatives of the Japanese government signed the instrument of surrender on the deck of the USS Missouri, anchored in Tokyo Bay. So ended perhaps the most reckless of all modern wars, the outcome of which was decided by U.S. technical superiority even before it started. Japan lost in material terms even before it attacked Pearl Harbor: In 1940 the United States produced roughly 10 times as much steel as Japan did, and during the war the difference grew further. ??? The devastated Japanese economy did not surpass its prewar peak until 1953. But by then the foundations had been laid for the country???s spectacular rise. Soon its fast-selling exports ranged from the first transistor radios (Sony) to the first giant crude-oil tankers ( Sumitomo). The first Honda Civic arrived in the United States in 1973, and by 1980, Japanese cars claimed 30 percent of the U.S. market. Japan, totally dependent on crude-oil imports, was hit hard by the OPEC oil price rises of the 1970s, but it adjusted rapidly by pursuing energy efficiency, and in 1978 it became the world???s second largest economy. By 1985 the yen was so strong that the United States, feeling threatened by Japanese imports, forced its devaluation through the Plaza Accord. But even afterward the economy soared: In the five years following January 1985 the Nikkei index rose more than threefold. ??? It was too good to be true; indeed, the success reflected the working of an enormous bubble economy driven by inflated stock and real estate prices. In January 2000, ten years after its peak, the Nikkei was still at only half its 1990 value, and only recently has it risen above even that low mark.
Autors: Smil, V.;
Appeared in: IEEE Spectrum
Publication date: Sep 2015, volume: 52, issue:9, pages: 28 - 28
Publisher: IEEE
 
» A 0.02 mm 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad
Abstract:
This paper reports a switched-capacitor (SC)-buffer Biquad that can be recycled efficiently as an ultra-compact low-pass filter (LPF) in nanoscale CMOS. It incorporates only passive-SC networks and open-loop unity-gain buffers; both are friendlier to technology downscaling than most conventional Biquads that use high-gain amplifiers and closed-loop negative feedback. Complex-pole pairs with independent Q factors are recursively realized in one clock period, while ensuring low crosstalk effect between the formations of each pole. Nonlinearity and parasitic effects are inherently low due to no internal gain. The fabricated 65 nm CMOS prototype is a 1x-recycling SC-buffer Biquad that is equivalent to a 4th-order Butterworth LPF with 75% buffer utilization. It occupies a die size of only 0.02 mm and exhibits 20x bandwidth tunability (0.5 to 10 MHz), linear with the clock rate. At 10 MHz bandwidth, the in-band IIP3 is +17.6 dBm and input-referred noise is 19.5 nV/ Hz; they correspond to 59.2 dB SFDR and 0.013 fJ figure-of-merit which are favorably comparable with the recent art. The 1 dB compression point conforms to the out-of-band blocker profile of the LTE standard at a 20 dB front-end gain.
Autors: Zhao, Y.;Mak, P.-I.;Martins, R.P.;Maloberti, F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 1988 - 2001
Publisher: IEEE
 
» A 0.02 mm 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad
Abstract:
This paper reports a switched-capacitor (SC)-buffer Biquad that can be recycled efficiently as an ultra-compact low-pass filter (LPF) in nanoscale CMOS. It incorporates only passive-SC networks and open-loop unity-gain buffers; both are friendlier to technology downscaling than most conventional Biquads that use high-gain amplifiers and closed-loop negative feedback. Complex-pole pairs with independent Q factors are recursively realized in one clock period, while ensuring low crosstalk effect between the formations of each pole. Nonlinearity and parasitic effects are inherently low due to no internal gain. The fabricated 65 nm CMOS prototype is a 1x-recycling SC-buffer Biquad that is equivalent to a 4th-order Butterworth LPF with 75% buffer utilization. It occupies a die size of only 0.02 mm and exhibits 20x bandwidth tunability (0.5 to 10 MHz), linear with the clock rate. At 10 MHz bandwidth, the in-band IIP3 is +17.6 dBm and input-referred noise is 19.5 nV/ Hz; they correspond to 59.2 dB SFDR and 0.013 fJ figure-of-merit which are favorably comparable with the recent art. The 1 dB compression point conforms to the out-of-band blocker profile of the LTE standard at a 20 dB front-end gain.
Autors: Zhao, Y.;Mak, P.-I.;Martins, R.P.;Maloberti, F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 1988 - 2001
Publisher: IEEE
 
» A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- CMOS for Medical Implant Devices
Abstract:
This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the offset performance of the comparator working under low supply voltage, a detailed theoretical analysis of comparator offset voltages is made. Based on the analysis, the comparator is optimized by only adjusting transistor sizes without any particular offset cancellation. As a result, when the common-mode input voltage varies from 300 mV to 450 mV at a 0.6 V supply, the 3×σ offset voltage is optimized to be about 6 mV with a fluctuation of only 0.15 mV, as revealed by Monte Carlo simulations. A prototype of the proposed ADC was fabricated in 0.18 μm 1P6M CMOS technology, which occupies an active area of only 380×430 μm2. At a 0.6-V supply and 20 kS/s sampling rate, the ADC achieves an SNDR of 58.3 dB and a power consumption of 38 nW, resulting in a figure of merit (FOM) of 2.8 fJ/conversion-step.
Autors: Zhangming Zhu;Yuhua Liang;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Sep 2015, volume: 62, issue:9, pages: 2167 - 2176
Publisher: IEEE
 
» A 1 kHz a-scan rate pump-probe laser-ultrasound system for robust inspection of composites
Abstract:
We recently built a fiber-optic laser-ultrasound (LU) scanner for nondestructive evaluation (NDE) of aircraft composites and demonstrated its greatly improved sensitivity and stability compared with current noncontact systems. It is also very attractive in terms of cost, stability to environmental noise and surface roughness, simplicity in adjustment, footprint, and flexibility. A new type of a balanced fiber-optic Sagnac interferometer is a key component of this all-optical LU pump-probe system. Very high A-scan rates can be achieved because no reference arm or stabilization feedback are needed. Here, we demonstrate LU system performance at 1000 A-scans/s combined with a fast 2-D translator operating at a scanning speed of 100 mm/s with a peak acceleration of 10 m/s2 in both lateral directions to produce parallel B-scans at high rates. The fast scanning strategy is described in detail. The sensitivity of this system, in terms of noise equivalent pressure, was further improved to be only 8.3 dB above the Nyquist thermal noise limit. To our knowledge, this is the best reported sensitivity for a noncontact ultrasonic detector of this dimension used to inspect aircraft composites.
Autors: Pelivanov, I.;Shtokolov, A.;Chen-Wei Wei;O???donnell, M.;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Sep 2015, volume: 62, issue:9, pages: 1696 - 1703
Publisher: IEEE
 
» A 100-MHz Breakdown-Resilient Power Converter With Fully Monolithic Implementation on Nanoscale CMOS Process
Abstract:
A monolithic switched-capacitor power converter is designed in the nanoscale CMOS technology, employing a two-stage system architecture to mitigate overvoltage breakdown risk. The efficiency impact of various parasitic components is analyzed for design optimization on both the topology level and the device level. An external capacitorless low-dropout regulator with a wide bandwidth and a high power supply rejection ratio is introduced, removing high-frequency ripples and enabling a fast load transient response. The proposed design was implemented with the 180-nm CMOS process. At a switching frequency of 100 MHz, it regulates Vout at 0.8 Vout with a maximum power efficiency of 60%. When the load current switches between 1.5 and 15 mA, Vout responds within 45 ns, with a voltage droop below 45 mV.
Autors: Yongtao Geng;Dongsheng Ma;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Sep 2015, volume: 62, issue:9, pages: 5529 - 5538
Publisher: IEEE
 
» A 110–170-GHz Multi-Mode Transconductance Mixer in 250-nm InP DHBT Technology
Abstract:
A novel full D-band (110–170 GHz) multi-mode transconductance down-converter mixer is realized in a 250-nm indium–phosphide double heterojunction bipolar transistor technology. A single-balanced topology is chosen and an active power combiner for the RF and the local oscillator (LO) signals’ combination is used. The designed mixer is feasible to work at 1, 2, 3, 4 subharmonically LO-pumped mixing modes with relatively low LO powers of 0, , 5, and 6 dBm, respectively. The measured conversion gain achieves typical values of , , , and dB over the full D-band while the best noise figures of 12, 13.5, 18.5, and 19 dB are obtained, respectively. Through the multi-mode operation in terms of subharmonic LO-pump-frequency, the designer can make a tradeoff between LO frequency, LO power, and noise figure.
Autors: Yan, Y.;Bao, M.;Gunnarsson, S.E.;Vassilev, V.;Zirath, H.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Sep 2015, volume: 63, issue:9, pages: 2897 - 2904
Publisher: IEEE
 
» A 130.3 mW 16-Core Mobile GPU With Power-Aware Pixel Approximation Techniques
Abstract:
Intensive pixel shading dominates the power dissipation of the graphics pipeline as the screen resolution grows. In this work, we propose a 130.3 mW 16-core mobile GPU with three pixel approximation techniques and a corresponding tile-based rasterization architecture. The proposed architecture can trade-off between power consumption and visual quality to provide power-aware capability, and is fabricated with TSMC 45 nm technology. The feasibility and effectiveness of these techniques are verified in this chip prototype. The implementation results show that, with satisfactory visual quality, 52.32% of the power consumption of the shader processors can be empirically reduced with an experimental Approximated Precision Shader architecture and a Screen-space Approximated Lighting technique. Furthermore, the Approximated Texturing technique can reduce 24.57% of L1 cache updates in our evaluation.
Autors: Chen, Y.-J.;Hsu, C.-H.;Hung, C.-Y.;Chang, C.-M.;Chuang, S.-Y.;Chen, L.-G.;Chien, S.-Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 2212 - 2223
Publisher: IEEE
 
» A 15-Channel Digital Active Electrode System for Multi-Parameter Biopotential Measurement
Abstract:
This paper presents a digital active electrode (DAE) system for multi-parameter biopotential signal acquisition in portable and wearable devices. It is built around an IC that performs analog signal processing and digitization with the help of on-chip instrumentation amplifiers, a 12 bit ADC and a digital interface. Via a standard bus, up to 16 digital active electrodes (15-channels) can be connected to a commercially available microcontroller, thus significantly reducing system complexity and cost. In addition, the DAE utilizes an innovative functionally DC-coupled amplifier to preserve input DC signal, while still achieving state-of-the-art performance: 60 nV/sqrt(Hz) input-referred noise and 350 mV electrode-offset tolerance. A common-mode feedforward scheme improves the CMRR of an AE pair from 40 dB to maximum 102 dB.
Autors: Xu, J.;Busze, B.;Van Hoof, C.;Makinwa, K.A.A.;Yazicioglu, R.F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 2090 - 2100
Publisher: IEEE
 
» A 183 GHz Metamorphic HEMT Low-Noise Amplifier With 3.5 dB Noise Figure
Abstract:
This letter presents a 183 GHz low-noise amplifier (LNA), designed primarily for water vapor detection in atmosphere. The LNA requirements were defined by MetOp Second Generation (MetOp-SG) Microwave Sounder, Microwave Imager and Ice Cloud Imager instruments. MetOp-SG is the European contribution to operational meteorological observations from polar orbit. This LNA advances the current state-of-the-art for the InGaAs metamorphic high electron mobility transistor (mHEMT) technology. The five-stage common-source MMIC amplifier utilizes transistors with a gate length of 50 nm. On-wafer measurements show a noise figure of 3.5 dB at the operative frequency, about 1 dB lower than previously reported mHEMT LNAs, and a gain of over the bandwidth 160-200 GHz. The input and output matching are and , respectively. Moreover, the dc power dissipation at the optimal bias for noise is as low as 24 mW.
Autors: Moschetti, G.;Leuther, A.;Massler, H.;Aja, B.;Rosch, M.;Schlechtweg, M.;Ambacher, O.;Kangas, V.;Genevieve-Perichaud, M.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Sep 2015, volume: 25, issue:9, pages: 618 - 620
Publisher: IEEE
 
» A 2-W W-Band GaN Traveling-Wave Amplifier With 25-GHz Bandwidth
Abstract:
A high-power gallium–nitride (GaN) monolithic microwave integrated circuit (MMIC) operating over the 75–100-GHz band is reported. Using an on-chip traveling-wave power-combining network, it achieves a continuous wave output power level of 34 dBm (2.5 W) 1 dB over the 75–100-GHz bandwidth and a peak power of 3 W at 84 GHz. Operating in a pulsed mode (10% duty), the MMIC chip produces a peak power of 3.6 W at 83 GHz. This work establishes new levels of performance for GaN MMICs at these frequencies. In comparison to the previous work, these results represent improvements in output power, bandwidth, and gain/power flatness with frequency across the full 75–100-GHz band. This paper also presents design details on the combining network and the MMIC not previously reported.
Autors: Schellenberg, J.M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Sep 2015, volume: 63, issue:9, pages: 2833 - 2840
Publisher: IEEE
 
» A 26 W 97%-Efficiency Fast-Settling Dimmable LED Driver With Dual-nMOS-Sensing Based Glitch-Tolerant Synchronous Current Control for High-Brightness Solid-State Lighting Applications
Abstract:
This paper presents an integrated buck-type dimmable synchronous LED driver for high-brightness solid-state lighting applications. A glitch-tolerant synchronous current control (GT-SCC) scheme is proposed to regulate the average LED current. The GT-SCC enables fast settling time of the LED current upon start-up or PWM dimming condition, and provides reliable operation under high dV/dt slewing during switching transitions of the LED driver. The proposed LED driver consists of a high-speed low-power HV synchronous gate driver to enable on-chip synchronous rectification with a dual-nMOS power train under different input voltages for the conduction power loss reduction. Two on-chip senseFET peak and valley current sensors are also developed to offer low-power and reliable current sensing under high input voltages. Implemented in a 0.35 m 50 V CMOS process, the proposed LED driver supports a wide input range from 5 V to 45 V, operates up to 4 MHz with a small-value inductor of 8.2 H, handles a high PWM dimming frequency of 20 kHz with a wide duty-ratio range from 0.1 to 1, and delivers an average LED current of 700 mA for driving up to 12 series-connected HB-LEDs (with the maximum output power of 26 W). The proposed LED driver achieves a peak power efficiency of 97.2% and the current deviation 3.3% of the average LED current under different conditions. The worst-case settling time achieves 3.2 s that is at least 2.7 times improvement over state-of-the-art counterparts.
Autors: Liu, Z.;Lee, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 2174 - 2187
Publisher: IEEE
 
» A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz
Abstract:
This brief presents a 7-GS/s 6-bit current-steering digital-to-analog converter (DAC) in 28-nm CMOS for VLSI System On Chip I/O embedding with an on-chip memory and clock generation circuits for wafer-sort testing. It demonstrates how Spurious Free Dynamic Range >50 dB can be maintained up to 1 GHz, while keeping the DAC footprint small −0.035 mm . Several linearization techniques, such as current source cascodes with local biasing, thick-oxide output cascodes, bleeding currents, and 50% level of segmentation are validated for the first time at such very high frequencies. Testing is facilitated by means of integrating a digital front-end design-for-test scheme in 0.048 mm . It uses a 5-kb 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7-GHz Current Mode Logic ring oscillator-type clock generator and a serial data interface enable simple testing of the DAC at reduced cost.
Autors: Radulov, G.I.;Quinn, P.J.;van Roermund, A.H.M.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Sep 2015, volume: 23, issue:9, pages: 1941 - 1945
Publisher: IEEE
 
» A 3-D Electromagnetic-Model-Based Algorithm for Absolute Attitude Measurement Using Wideband Radar
Abstract:
In this letter, a novel algorithm for attitude measurement based on a 3-D electromagnetic model (3-D em-model) is proposed. The 3-D em-model is established offline based on the geometric structure of the target, and it can be used to predict the scattering features at different target attitudes. In order to measure the attitude of the air target, we design a bistatic step frequency radar system. The directions of the two radars' lines of sight (LOSs) relative to the target are acquired by matching the high-resolution range profiles (HRRPs) from the target echoes to the HRRPs generated from the 3-D em-model. Since the directions of two radars' LOSs relative to the Earth are already known, the absolute attitude of the target can be acquired. The innovative contributions of this letter are as follows: 1) A comprehensive theoretical analysis of air target attitude measurement based on its own 3-D em-model is proposed; 2) the method can be applied to different kinds of air targets such as aircraft, satellite, missile, etc.; 3) the proposed attitude measurement method does not require target motion model in advance; and 4) the proposed algorithm can be applied to any kind of step frequency waveforms. Experiments using both data predicted by a high-frequency electromagnetic code and data measured in the chamber verify the validity of the method.
Autors: XiaoLiang Yang;GongJian Wen;JinRong Zhong;BingWei Hui;CongHui Ma;
Appeared in: IEEE Geoscience and Remote Sensing Letters
Publication date: Sep 2015, volume: 12, issue:9, pages: 1878 - 1882
Publisher: IEEE
 
» A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS
Abstract:
Spread-spectrum clocking is an established approach to mitigate electromagnetic interference (EMI) of digital circuits, by intentionally sweeping the clock frequency. In this way, the energy of each clock harmonic is spread over a larger bandwidth, thereby reducing the peak of the interfering spectrum. This paper describes an highly flexible all-digital spread-spectrum clock generator (SSCG) realized with a standard-cells design flow. The developed circuit supports discontinuous frequency modulation profiles (with improved EMI reduction capability) and features reduced output jitter, due to delay interpolators and digital compensation of delay path asymmetries. The proposed SSCG is ideally suited for complex system on chips applications, having programmable spreading parameters, frequency synthesis capability and reduced recovery time to support local standby modes. The SSCG is implemented in bulk 28 nm CMOS technology, presents a maximum working frequency of 3.3 GHz and less than 3.2 ps output jitter. The measured peak level reduction of the clock power spectrum, at 1.0 GHz output frequency, is 27.0 dB with a 10% modulation depth. The power dissipation is 29.3 mW @ 3.3 GHz and the area occupation is 0.031 mm.
Autors: De Caro, D.;Tessitore, F.;Vai, G.;Imperato, N.;Petra, N.;Napoli, E.;Parrella, C.;Strollo, A.G.M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 2074 - 2089
Publisher: IEEE
 
» A 30 µW 30 fps 110 × 110 Pixels Vision Sensor Embedding Local Binary Patterns
Abstract:
We present a 110 × 110 pixel vision sensor that computes the Local Binary Patterns (LBPs) of an imaged scene with a power consumption of 30 µW at 30 fps. The LBP of a given pixel is a binary vector, encoding the direction and sign of image contrast with respect to its neighbors. Each LBP provides a visual description of an image's local structure that is widely used for texture and object recognition. In the sensor proposed here, each pixel detects its corresponding LBP with respect to its four neighboring pixels and saves this information into a digital map using 6 bits to encode each pixel. The operation is executed during the exposure time and requires 83 pW/pixel frame to be computed. The chip is implemented in a 0.35 µm CMOS featuring 34 T square pixels with 26 µm pitch. We illustrate some examples of image description based on the LBPs output by the sensor.
Autors: Berkovich, A.;Lecca, M.;Gasparini, L.;Abshire, P.A.;Gottardi, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 2138 - 2148
Publisher: IEEE
 
» A 350-MS/s Continuous-Time Delta–Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS
Abstract:
Two techniques to improve the performance of continuous-time delta–sigma (CTDS) modulators are presented. A digital calibration technique is introduced to enable the use of binary current digital-to-analog converters (DACs) without dynamic element matching. Furthermore, a high-speed two-step analog-to-digital data converter quantizer is introduced to efficiently increase the resolution of the quantizer in CTDS modulators with high-sampling rates. A proof-of-concept prototype implemented in 130-nm CMOS shows that the proposed calibration technique can compensate for up to 5% of mismatch in the DAC elements. The modulator has a measured SNDR/SFDR of 60.3/74 dB for a sampling rate of 350 MS/s and oversampling ratio of 20, translating to an 8.75-MHz bandwidth. The total power consumption is 5.5 mW from a 1.6 V supply.
Autors: Taherzadeh-Sani, M.;Nabki, F.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Sep 2015, volume: 23, issue:9, pages: 1914 - 1919
Publisher: IEEE
 
» A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS
Abstract:
A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divide-by-two. Thanks to the lower frequency of operation, the effect of non-zero sampling aperture of the switch is minimized. A dummy divider of the quadrature PLL is utilized for the sub-sampling loop to avoid extra loading in the 60 GHz path. A 53.8–63.3 GHz QVCO uses super-harmonic coupling at 120 GHz for relaxed headroom at a 0.9 V supply and achieves a free-running phase noise down to 94.5 dBc/Hz at 1 MHz offset. The millimeter-wave sub-sampling PLL achieves an RMS jitter, integrated from 1 kHz to 100 MHz, of 200 fs at a power consumption of 42 mW, compared to 210 fs for the PFD/CP PLL at 75 mW. Reference spurs in both modes are below 40 dBc.
Autors: Szortyka, V.;Shi, Q.;Raczkowski, K.;Parvais, B.;Kuijk, M.;Wambacq, P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 2025 - 2036
Publisher: IEEE
 
» A 50 to 146 GHz Power Amplifier Based on Magnetic Transformers and Distributed Gain Cells
Abstract:
A monolithic millimeter-wave integrated circuit power amplifier covering the entire V-, W- and F-band is presented. The amplifier applies magnetic distributed transformers in combination with traveling wave gain cells to achieve a bandwidth that spans from 50 to 146 GHz, 12 dB gain and a maximum measured output power of 15 dBm. With a relative bandwidth of 98.3% the PA achieves the highest bandwidth reported for power amplifiers operating at around 100 GHz to date.
Autors: Pahl, P.;Wagner, S.;Massler, H.;Diebold, S.;Leuther, A.;Kallfass, I.;Zwick, T.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Sep 2015, volume: 25, issue:9, pages: 615 - 617
Publisher: IEEE
 
» A 6–10 mW Power Amplifier at 290–307.5 GHz in 250 nm InP HBT
Abstract:
A 290–307.5 GHz solid-state power-amplifier MMIC is presented demonstrating 6–10 mW for mW. is 848 mW. This represents 10–12 dB of large-signal gain across 18 GHz of high-power bandwidth. This 3-stage amplifier has peak 23.5 dB gain at 299 GHz, a 1 dB bandwidth from 292–303 GHz, and a 3 dB bandwidth from 285–306 GHz. A power-cascode cell topology is used for the PA unit cell and 2:1 Wilkinson power combining of these cells (32 um HBT output periphery) achieves the RF powers claimed. The insertion loss demonstrated by the combiner is 0.45–0.5 dB from 255–330 GHz—this improves upon state-of-the-art for on-wafer 2:1 combining at these frequencies by 0.3–0.7 dB. This work represents the first demonstration of a 300 GHz power cascode cell topology with output power and output power density (W/mm) competitive with state-of-the-art PAs with 10 mW .
Autors: Griffith, Z.;Urteaga, M.;Rowell, P.;Pierson, R.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Sep 2015, volume: 25, issue:9, pages: 597 - 599
Publisher: IEEE
 
» A 60 dB SNDR 35 MS/s SAR ADC With Pub _newline Comparator-Noise-Based Stochastic Residue Estimation
Abstract:
We present a SAR ADC with comparator-noise-based stochastic residue estimation. The circuit uses a 9 cycle SAR converter to generate a residue, which is then quantized by clocking 16 noisy comparators four times each and digitally calculating the most likely input voltage for the obtained distribution of zeros and ones. The ADC achieves a 60.9 dB SNDR for a near-Nyquist input at 35 MS/s for a purely dynamic power consumption of 12 µW/MHz.
Autors: Verbruggen, B.;Tsouhlarakis, J.;Yamamoto, T.;Iriguchi, M.;Martens, E.;Craninckx, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 2002 - 2011
Publisher: IEEE
 
» A 60 GHz CMOS VCO Using a Fourth-Order Resonator
Abstract:
In this letter, a 60 GHz voltage-controlled oscillator (VCO) implemented in the 90 nm CMOS process is presented. By using a fourth-order resonator, the proposed VCO oscillates at its second pole frequency to achieve high speed operation with fully differential output phases and a wide tuning range with a larger size of varactors. The measured oscillation frequencies of the proposed VCO are from 58.76 to 63.94 GHz corresponding to an 8.44% tuning range. The measured phase noise is 91.53 dBc/Hz at 1 MHz frequency offset for the highest output frequency. The core circuit consumes 7.2 mW power from a 1.2 V dc supply.
Autors: Chiang, Y.-C.;Chang, Y.-H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Sep 2015, volume: 25, issue:9, pages: 609 - 611
Publisher: IEEE
 
» A 75 dB SNDR 10-MHz Signal Bandwidth Gm-C-Based Sigma-Delta Modulator With a Nonlinear Feedback Compensation Technique
Abstract:
Wideband ( 10 MHz) continuous-time (CT) sigma-delta modulators generally use active-RC filters. On the other hand, Gm-C-filters avoid the need of a power-hungry driving stage due to their small loading. At the moment, the major challenge for designing Gm-C-based modulator is the narrow linear input range due to the nonlinear Gm amplifier, which leads to low SNDR. This work develops a nonlinearity compensation technique for Gm-C-based modulator. This technique designs a nonlinear feedback DAC which has matched V-I transfer curve as the first Gm amplifier (Gm1). As a result, the distortions of Gm1 are significantly suppressed at the modulator output. This method is prototyped in a 640 MS/s Gm-C-based modulator with 10 MHz signal bandwidth in a 0.18- CMOS process. With this technique, the linear input range of the modulator is greatly enlarged. Consequently, the peak SNDR of the modulator is improved by about 8 dB to 75 dB. This 12-bit ENOB is achieved for the first time for wide-band Gm-C-based modulators.
Autors: Huang, J.;Yang, S.;Yuan, J.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Sep 2015, volume: 62, issue:9, pages: 2216 - 2226
Publisher: IEEE
 
» A Balanced-to-Balanced Power Divider With Wide Bandwidth
Abstract:
In this letter, a balanced-to-balanced power divider (PD) is proposed. By etching both slot and aperture on the common ground of the back-to-back microstrip Wilkinson PD, the proposed balanced-to-balanced PD can achieve wide and high common-mode (CM) suppression while keeping the PD function for differential-mode signals. Compared with previous technologies of CM suppression for back-to-back microstrip balanced circuits, the proposed one has the advantage of compact size. Furthermore, the proposed PD shows enhanced bandwidth for matching and isolation. A prototype is realized with the size of . The measured results show relative frequency bandwidth for dB of 85%. The fractional bandwidths for and under dB are 44%, 44% and 55%, respectively.
Autors: Shi, J.;Wang, J.;Xu, K.;Chen, J.-X.;Liu, W.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Sep 2015, volume: 25, issue:9, pages: 573 - 575
Publisher: IEEE
 
» A Bode-Like Integral for Discrete Linear Time-Periodic Systems
Abstract:
We present a generalization of the Bode integral formula for discrete-time linear periodic systems. It is shown that similar to the classical Bode integral formula, the sensitivity integral for a discrete-time linear periodic system depends only on the open-loop dynamics of the system; in particular, on the open-loop characteristic multipliers outside the unit circle in the complex plane. The integral is derived by using an asymptotic eigenvalue distribution theorem for block Toeplitz matrices, which does not require the open loop system to be stable or the disturbance to be Gaussian. The result is demonstrated through application to a class of multi-rate sampled data systems with commensurate rates.
Autors: Zhao, Y.;Gupta, V.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Sep 2015, volume: 60, issue:9, pages: 2494 - 2499
Publisher: IEEE
 
» A Calibration Technique for Pipelined ADCs Using Self-Measurement and Histogram-Based Test Methods
Abstract:
This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs) to correct the capacitor mismatch, finite dc gain, and nonlinearity of residue amplifiers. It estimates the calibration coefficients at start-up by a modified self-measurement method with low-precision stimulation signals in the multistage calibration. Then, during the ADC normal operation, a sliding histogram in the vicinity of the decision boundaries of stage comparators is utilized to adjust the calibration coefficients in order to follow the variation of errors. To do so, the ratio of information achieved from the initial and new histograms is used to update the calibration coefficients. Behavioral simulation results of a 12-bit pipelined ADC show that the proposed calibration technique improves the ADC linearity by more than 4 bits and it is robust against the variation of errors.
Autors: Moosazadeh, T.;Yavari, M.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Sep 2015, volume: 62, issue:9, pages: 826 - 830
Publisher: IEEE
 
» A Class of Adaptive Extended State Observers for Nonlinear Disturbed Systems
Abstract:
This paper proposes a novel class of adaptive extended state observers (AESOs) that significantly expand the applications of extended state observers (ESOs) to nonlinear disturbed systems. An AESO is designed as a linear time-varying form that, as a result, combines both the advantages of theoretical completeness in a conventional linear ESO (LESO) and good practical performance in a conventional nonlinear ESO (NESO). To tune the time-varying observer gains, AESO error dynamics is first transformed into a canonical (phase-variable) form. Then, time-varying PD-eigenvalues are assigned for the canonical system based on differential algebraic spectral theory. Theorems for stability and estimate error bounds of the AESO are given in the presence of unknown disturbances. These theorems also offer some important guidelines for assigning the PD-eigenvalues. To demonstrate the effectiveness of this new observer, two representative applications, including a numerical single-input-single-output example and a practical multiple-input-multiple-output hypersonic vehicle application, are exemplified, and comparison simulations are conducted among AESO, LESO, and NESO. Future work is pointed out in the end.
Autors: Zhiqiang Pu;Ruyi Yuan;Jianqiang Yi;Xiangmin Tan;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Sep 2015, volume: 62, issue:9, pages: 5858 - 5869
Publisher: IEEE
 
» A Class of Binary Linear Codes With at Most Three Weights
Abstract:
In this letter, we use Gauss sums of index 2 to construct a class of new binary linear codes with at most three weights. In special cases, they are optimal or near optimal codes. These codes can be used in authentication codes and secret sharing schemes.
Autors: Heng, Z.;Yue, Q.;
Appeared in: IEEE Communications Letters
Publication date: Sep 2015, volume: 19, issue:9, pages: 1488 - 1491
Publisher: IEEE
 
» A Classification Framework for Predicting Components' Remaining Useful Life Based on Discrete-Event Diagnostic Data
Abstract:
In this paper, we propose to define the problem of predicting the remaining useful life of a component as a binary classification task. This approach is particularly useful for problems in which the evolution of the system condition is described by a combination of a large number of discrete-event diagnostic data, and for which alternative approaches are either not applicable, or are only applicable with significant limitations or with a large computational burden. The proposed approach is demonstrated with a case study of real discrete-event data for predicting the occurrence of railway operation disruptions. For the classification task, Extreme Learning Machine (ELM) has been chosen because of its good generalization ability, computational efficiency, and low requirements on parameter tuning.
Autors: Fink, O.;Zio, E.;Weidmann, U.;
Appeared in: IEEE Transactions on Reliability
Publication date: Sep 2015, volume: 64, issue:3, pages: 1049 - 1056
Publisher: IEEE
 
» A Closed-Loop Interface for a High-Q Micromechanical Capacitive Accelerometer With 200 ng/ Hz Input Noise Density
Abstract:
In this paper, a fully-differential high-order switched-capacitor (SC) sigma-delta interface in a standard 0.5 CMOS technology for a micromechanical capacitive accelerometer is presented. A 1 bit digital output is attained by the interface circuit based on a low-noise front-end and a back-end third-order SC modulator, avoiding the use of a separate high-resolution converter to digitize the analog feedback signal. In addition, a micromechanical capacitive sensor element with a high quality factor (high-Q) is used to achieve high-resolution. Furthermore, closed-loop operation and electrical compensation are employed for damping the high-Q to ensure the stability of the high-order system. The sensor consumes 23 mW of power from a single 7 V supply at a sampling clock of 250 kHz. Meanwhile, a sensitivity of 1.896 V/g is achieved with a noise floor of lower than 200 ng Hz in low-frequency. The sensor has a nonlinearity of 0.15% with an input range of 1.2g. The bandwidth (BW) is 300 Hz and the bias instability is 18 .
Autors: Xu, H.;Liu, X.;Yin, L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 2101 - 2112
Publisher: IEEE
 
» A Closed-Loop Interface for a High-Q Micromechanical Capacitive Accelerometer With 200 ng/ Hz Input Noise Density
Abstract:
In this paper, a fully-differential high-order switched-capacitor (SC) sigma-delta interface in a standard 0.5 CMOS technology for a micromechanical capacitive accelerometer is presented. A 1 bit digital output is attained by the interface circuit based on a low-noise front-end and a back-end third-order SC modulator, avoiding the use of a separate high-resolution converter to digitize the analog feedback signal. In addition, a micromechanical capacitive sensor element with a high quality factor (high-Q) is used to achieve high-resolution. Furthermore, closed-loop operation and electrical compensation are employed for damping the high-Q to ensure the stability of the high-order system. The sensor consumes 23 mW of power from a single 7 V supply at a sampling clock of 250 kHz. Meanwhile, a sensitivity of 1.896 V/g is achieved with a noise floor of lower than 200 ng Hz in low-frequency. The sensor has a nonlinearity of 0.15% with an input range of 1.2g. The bandwidth (BW) is 300 Hz and the bias instability is 18 .
Autors: Xu, H.;Liu, X.;Yin, L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 2101 - 2112
Publisher: IEEE
 
» A Collaborative Design of Aggregated Residential Appliances and Renewable Energy for Demand Response Participation
Abstract:
Although the locational marginal price may change dramatically within a single day in competitive wholesale electricity markets, most end users are charged monthly electricity bills over flat rates. Without financial incentives, the customers are lacking of motivation to respond to the price signals, which may result in inefficient energy consumption. In Texas, Senate Bill 1125 encourages qualified residential and commercial customer classes to participate in demand response (DR) programs. This paper proposes an idea to aggregate a number of residential customers to participate in residential DR program by employing smart appliances and a home area network to shift the coincidental peak load to off-peak hours to reap financial benefits. The operation strategies for the most representative residential load types are discussed. To further reduce electricity purchase and cut electricity bills, a solar farm with energy storage system is proposed, and the control algorithm is designed accordingly. The operation strategies are simulated for a whole year, and the annual costs are calculated and compared in this paper. The results show that, by doing load control and utilizing renewable resources, the total operation cost can be reduced significantly.
Autors: Liu, M.;Quilumba, F.;Lee, W.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Sep 2015, volume: 51, issue:5, pages: 3561 - 3569
Publisher: IEEE
 
» A Collision and Reaction Model of Feature Fusion: Mechanism and Realization
Abstract:
Duplicate data must be properly handled in the process of intelligent search, surveillance, and tracking. To better detect and fuse this data, the authors take a new perspective on feature fusion based on the "collision and reaction"' mechanism of data objects. This mechanism can greatly facilitate differentiating duplicate and nonduplicate data in the fusion (reaction) probability. With this perspective, the fusion probability of a feature sample in a dataset is the cumulative effect of the microscopic collision (interaction) results between this sample and other samples. The operations on duplicate detection and feature fusion depend on the fusion probability and are finally realized when the collision process is finished. This new quantum-inspired feature fusion model gives interesting experimental results and could have great implications for some intelligent systems.
Autors: Peng, Weimin;Deng, Huifang;
Appeared in: IEEE Intelligent Systems
Publication date: Sep 2015, volume: 30, issue:5, pages: 56 - 65
Publisher: IEEE
 
» A Comment on “A Similarity Measure for Text Classification and Clustering”
Abstract:
Presents comments on the paper, "A similarity measure for text classification and clustering??? (Lin, Y.-S., et al; IEEE Trans. Knowl. Data Eng., vol. 26, no. 7, pp. 1575??? 1590, Jul. 2014).
Autors: Kumar Nagwani, N.;
Appeared in: IEEE Transactions on Knowledge and Data Engineering
Publication date: Sep 2015, volume: 27, issue:9, pages: 2589 - 2590
Publisher: IEEE
 
» A Compact and High-Performance Eddy-Current Sensor Based on Meander-Spiral Coil
Abstract:
In this paper, a novel meander–spiral coil (MSC) was designed as an eddy-current sensor (ECS) probe, which has small sensing area and spot size, nearly no limitation of mounting space, and can perform better than the regular-spiral coil (RSC). The results of the finite-element analysis show that the MSC has a magnetic active area that was only a quarter of that of the RSC. The MSC has much smaller inductance and resistance than the RSC, though the former has high sensitivity similar to the latter. These types of spiral coils were manufactured by printed circuit board technology and tested, which proves that the MSC has a small sensing range. Owing to MSC’s small magnetic active area and high performance, this type of spiral coil is suitable for applications in sensor arrays and micro-electromechanical systems. Furthermore, using the MSC, ECSs have the potential to be used for micro-gap measurement, accelerometers, and pressure measurement applications, as in the case of capacitive sensors. Moreover, ECSs are inherently immune to environmental contaminations.
Autors: Wang, H.;Li, W.;Feng, Z.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Sep 2015, volume: 51, issue:9, pages: 1 - 6
Publisher: IEEE
 
» A Compact Multiband Printed Dipole Antenna Loaded With Two Unequal Parallel NRI-TL Metamaterial Unit Cells
Abstract:
A negative-refractive-index transmission-line (NRI-TL) metamaterial-loaded dipole antenna is proposed, which has a fully printed configuration and exhibits multiband performance. The antenna consists of a conventional dipole antenna loaded with two unequal parallel NRI-TL metamaterial unit cells which have the same electrical length, but each is loaded with a thin inductive strip that has a different length and therefore a different effective shunt inductance. An equivalent circuit is extracted to investigate the performance of the proposed metamaterial-loaded dipole antenna by modeling each of the dipole arms as a transmission line. This circuit is then used to verify that the resonant behavior of the proposed antenna can be altered by simply adjusting the lengths of the thin inductive strips. A fabricated prototype has compact dimensions of , and exhibits good agreement between the measured and simulated results.
Autors: Jamilan, S.;Antoniades, M.A.;Nourinia, J.;Azarmanesh, M.N.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Sep 2015, volume: 63, issue:9, pages: 4244 - 4250
Publisher: IEEE
 
» A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements
Abstract:
We present a data-calibrated compact model of carbon nanotube (CNT) FETs (CNTFETs) based on the virtual-source (VS) approach, describing the intrinsic current–voltage and charge–voltage characteristics. The features of the model include: 1) carrier VS velocity extracted from experimental devices with gate lengths down to 15 nm; 2) carrier effective mobility and velocity depending on the CNT diameter; 3) short channel effect such as inverse subthreshold slope degradation and drain-induced barrier lowering depending on the device dimensions; and 4) small-signal capacitances including the CNT quantum capacitance effect to account for the decreasing gate capacitance at high gate bias. The CNTFET model captures the dimensional scaling effects and is suitable for technology benchmarking and performance projection at the sub-10-nm technology nodes.
Autors: Lee, C.;Pop, E.;Franklin, A.D.;Haensch, W.;Wong, H.P.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Sep 2015, volume: 62, issue:9, pages: 3061 - 3069
Publisher: IEEE
 
» A Compact, Wideband Circularly Polarized Co-designed Filtering Antenna and Its Application for Wearable Devices With Low SAR
Abstract:
A compact circularly polarized (CP) co-designed filtering antenna is reported. The device is based on a patch radiator seamlessly integrated with a bandpass filter composed of coupled stripline open-loop resonators, which are designed together as a system. In the proposed design, the patch functions simultaneously as the radiator and the last stage resonator of the filter, resulting in a low-profile integrated radiating and filtering module with a small overall form factor of . It is shown that the filtering circuit not only ensures frequency selectivity but also provides impedance matching functionality, which serves to broaden both the impedance and axial ratio bandwidths. The designed filtering antenna was fabricated and measured, experimentally achieving an , an axial ratio of less than 3 dB and a gain higher than 5.2 dBi over a bandwidth from 3.77 to 4.26 GHz, i.e., around 12.2%, which makes it an excellent candidate for integration into a variety of wireless systems. A linearly polarized version of the integrated filtering antenna was also demonstrated. In addition, further full-wave simulations and experiments were carried out to verify that the designed CP filtering antenna maintains its properties even when mounted on different positions of the human body with various body gestures. The stable impedance and radiation properties also make it a suitable candidate as a wearable antenna for off-body wireless communications.
Autors: Jiang, Z.H.;Werner, D.H.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Sep 2015, volume: 63, issue:9, pages: 3808 - 3818
Publisher: IEEE
 
» A Comparison of Graphene and Noble Metals as Conductors for Plasmonic One-Dimensional Waveguides
Abstract:
This study presents the propagation properties of plasmonic slab waveguides based on graphene compared with noble metals. Transfer matrix theory as an analytical method and finite-element method as a numerical approach are applied for analysis of one-dimensional plasmonic structures. Calculating the guided mode propagation constants of the waveguides, characteristics of the waveguides are compared by three factors: propagation length, spatial length, and electromagnetic field profile. The results obtained here are very helpful to the guided-wave applications in terahertz and infrared frequencies.
Autors: Hosseininejad, S.E.;Komjani, N.;Talafi Noghani, M.;
Appeared in: IEEE Transactions on Nanotechnology
Publication date: Sep 2015, volume: 14, issue:5, pages: 829 - 836
Publisher: IEEE
 
» A Computational Framework for Electrical Stimulation of Vestibular Nerve
Abstract:
The vestibular organs are very important to generate reflexes critical for stabilizing gaze and body posture. Vestibular diseases significantly reduce the quality of life of people who are affected by them. Some research groups have recently started developing vestibular neuroprostheses to mitigate these symptoms. However, many scientific and technological issues need to be addressed to optimise their use in clinical trials. We developed a computational model able to mimic the response of human vestibular nerves and which can be exploited for “in-silico” testing of new strategies to design implantable vestibular prostheses. First, a digital model of the vestibular system was reconstructed from anatomical data. Monopolar stimulation was delivered at different positions and distances from ampullary nerves. The electrical potential induced by the injected current was computed through finite-element methods and drove extra-cellular stimulation of fibers in the vestibular, facial, and cochlear nerves. The electrical activity of vestibular nerves and the resulting eye movements elicited by different stimulation protocols were investigated. A set of electrode configurations was analyzed in terms of selectivity at increasing injected current. Electrode position along the nerve plays a major role in producing undesired activity in other nontargeted nerves, whereas distance from the fiber does not significantly affect selectivity. Indications are provided to minimize misalignment in nonoptimal electrode locations. Eye movements elicited by the different stimulation protocols are calculated and compared to experimental values, for the purpose of model validation.
Autors: Marianelli, P.;Capogrosso, M.;Bassi Luciani, L.;Panarese, A.;Micera, S.;
Appeared in: IEEE Transactions on Neural Systems and Rehabilitation Engineering
Publication date: Sep 2015, volume: 23, issue:5, pages: 897 - 909
Publisher: IEEE
 
» A Condition-Based Maintenance Model for Assets With Accelerated Deterioration Due to Fault Propagation
Abstract:
Complex industrial assets such as power transformers are subject to accelerated deterioration when one of its constituent component malfunctions, affecting the condition of other components, which is a phenomenon called fault propagation. In this paper, we present a novel approach for optimizing condition-based maintenance policies for such assets by modelling their deterioration as a multiple dependent deterioration path process. The aim of the policy is to replace the malfunctioned component and mitigate accelerated deterioration at minimal impact to the business. The maintenance model provides guidance on determining inspection and maintenance strategies to optimize asset availability and operational cost.
Autors: Liang, Z.;Parlikad, A.K.;
Appeared in: IEEE Transactions on Reliability
Publication date: Sep 2015, volume: 64, issue:3, pages: 972 - 982
Publisher: IEEE
 
» A Construction of Physical-Layer Systematic Raptor Codes Based on Protographs
Abstract:
A construction of physical-layer Raptor (PLR) codes based on protographs is proposed. We first set up a sequence of signal-to-noise ratios (SNRs). For each SNR, we employ a modified protograph EXIT analysis to find the extra check nodes in addition to the existing check nodes so as to meet the threshold required by the outer low-density parity check code. PLR codes which are capacity-approaching for a wide SNR range can be obtained using the proposed construction.
Autors: Kuo, S.;Lee, H.;Ueng, Y.;Lin, M.;
Appeared in: IEEE Communications Letters
Publication date: Sep 2015, volume: 19, issue:9, pages: 1476 - 1479
Publisher: IEEE
 
» A Conversation with Lazar Puhalo [Interview]
Abstract:
On December 17, 2014, T&S Editor-in-Chief Katina Michael interviewed Archbishop of Ottawa (Ret.) Lazar Puhalo, of the Orthodox Church in America. Their discussion focused broadly on transhumanism.
Autors: Puhalo, A.;
Appeared in: IEEE Technology and Society Magazine
Publication date: Sep 2015, volume: 34, issue:3, pages: 25 - 28
Publisher: IEEE
 
» A DC-100 GHz Active Frequency Doubler With a Low-Voltage Multiplier Core
Abstract:
Cross-coupled differential pairs implement an even-order active frequency multiplier in 90 nm SiGe-BiCMOS. The multiplier core uses asymmetric biasing to realize an even-order transfer function. Wideband (WB) and narrowband doublers built around the active core are proposed, and their relative performance is compared from simulation. Measurement of a WB prototype consisting of the doubler, active load with feedback regulation of bias, and 50 input and output buffers validates the circuit concepts. Conversion gain (CG) for the WB doubler peaks at low frequency (e.g., 12 dB at 10 GHz) and rolls off to 0 dB at 100 GHz. For 25 GHz output, significant spurs are: 25 dBc at 12.5 GHz (input tone) and 28 dBc at 50 GHz (4th harmonic). The 0.37 mm WB testchip consumes 55.5 mA from a 4.5 V supply.
Autors: Vera, L.;Long, J.R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 1963 - 1973
Publisher: IEEE
 
» A Dichotomy of Functions in Distributed Coding: An Information Spectral Approach
Abstract:
The problem of distributed data compression for function computation is considered, where: 1) the function to be computed is not necessarily symbolwise function and 2) the information source has memory and may not be stationary nor ergodic. We introduce the class of smooth sources and give a sufficient condition on functions so that the achievable rate region for computing coincides with the Slepian-Wolf region (i.e., the rate region for reproducing the entire source) for any smooth sources. Moreover, for symbolwise functions, the necessary and sufficient condition for the coincidence is established. Our result for the full side-information case is a generalization of the result by Ahlswede and Csiszár to sources with memory; our dichotomy theorem is different from Han and Kobayashi's dichotomy theorem, which reveals an effect of memory in distributed function computation. All results are given not only for fixed-length coding but also for variable-length coding in a unified manner. Furthermore, for the full side-information case, the error probability in the moderate deviation regime is also investigated.
Autors: Kuzuoka, S.;Watanabe, S.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Sep 2015, volume: 61, issue:9, pages: 5028 - 5041
Publisher: IEEE
 
» A Directional Interstitial Antenna for Microwave Tissue Ablation: Theoretical and Experimental Investigation
Abstract:
Microwave ablation (MWA) is a minimally invasive thermal therapy modality increasingly employed for the treatment of tumors and benign disease. For successful treatment, complete thermal coverage of the tumor and margin of surrounding healthy tissue must be achieved. Currently available interstitial antennas for MWA have cylindrically symmetric radiation patterns. Thus, when treating targets in proximity to critical structures, caution must be taken to prevent unintended thermal damage. A novel coaxial antenna design for MWA with an asymmetrical cylindrical heating pattern is presented in this paper. This radiation pattern is achieved by employing a hemicylindrical reflector positioned at a critical distance from a conventional coaxial monopole antenna. Finite-element method simulations were employed to optimize the geometric dimensions of the antenna with the objective of minimizing the antenna reflection coefficient at the 2.45-GHz operating frequency, and maximizing volume of the ablation zone. Prototype antennas were fabricated and experimentally evaluated. Simulations indicated an optimal S11 of –32 dB at 2.45 GHz in close agreement with experimental measurements of –29 dB. Ex vivo experiments were performed to validate simulations and observe effects to the antennas’ heating pattern with the varying input power and geometry of the reflector. Ablation zones up to 20 mm radially were observed in the forward direction, with minimal heating (less than 4 mm) behind the reflector.
Autors: McWilliams, B.T.;Schnell, E.E.;Curto, S.;Fahrbach, T.M.;Prakash, P.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Sep 2015, volume: 62, issue:9, pages: 2144 - 2150
Publisher: IEEE
 
» A DSP-Based Control Method For a Nonlinear Mach–Zehnder Interferometer DPSK Regenerator
Abstract:
A frequency offset and phase control method is described for a differential-phase-shift-keying (DPSK) 2R (reamplification and reshaping) regenerator based on a nonlinear Mach–Zehnder interferometer. The controller is comprised of a coherent receiver, analog-to-digital converters (ADCs), a digital signal processor, and an optical frequency/phase shifter. For a 40 Gb/s DPSK signal, simulation results demonstrate that an ADC sampling rate of only 335.94 MSa/s is needed to adequately estimate the frequency offset and phase noise, and adjust the pump signal accordingly. The cascadability of the 2R regenerator is evaluated in recirculating loop simulations for different regenerator spacings, using both ideal DPSK signals and captured experimental DPSK signals. The influence of residual span dispersion on the performance is investigated.
Autors: Zhang, S.;Cartledge, J.C.;
Appeared in: Journal of Lightwave Technology
Publication date: Sep 2015, volume: 33, issue:18, pages: 3788 - 3795
Publisher: IEEE
 
» A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis
Abstract:
Goal: The existing ISFET-based DNA sequencing detects hydrogen ions released during the polymerization of DNA strands on microbeads, which are scattered into microwell array above the ISFET sensor with unknown distribution. However, false pH detection happens at empty microwells due to crosstalk from neighboring microbeads. In this paper, a dual-mode CMOS ISFET sensor is proposed to have accurate pH detection toward DNA sequencing. Methods: Dual-mode sensing, optical and chemical modes, is realized by integrating a CMOS image sensor (CIS) with ISFET pH sensor, and is fabricated in a standard 0.18-μm CIS process. With accurate determination of microbead physical locations with CIS pixel by contact imaging, the dual-mode sensor can correlate local pH for one DNA slice at one location-determined microbead, which can result in improved pH detection accuracy. Moreover, toward a high-throughput DNA sequencing, a correlated-double-sampling readout that supports large array for both modes is deployed to reduce pixel-to-pixel nonuniformity such as threshold voltage mismatch. Results: The proposed CMOS dual-mode sensor is experimentally examined to show a well correlated pH map and optical image for microbeads with a pH sensitivity of 26.2 mV/pH, a fixed pattern noise (FPN) reduction from 4% to 0.3%, and a readout speed of 1200 frames/s. Conclusion: A dual-mode CMOS ISFET sensor with suppressed FPN for accurate large-arrayed pH sensing is proposed and demonstrated with state-of-the-art measured results toward accurate and high-throughput DNA sequencing. Significance: The developed dual-mode CMOS ISFET sensor has great potential for future personal genome diagnostics with high accuracy and low cost.
Autors: Huang, X.;Yu, H.;Liu, X.;Jiang, Y.;Yan, M.;Wu, D.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Sep 2015, volume: 62, issue:9, pages: 2224 - 2233
Publisher: IEEE
 
» A Dual-Mode Substrate Integrated Waveguide Filter With Controllable Transmission Zeros
Abstract:
In this letter, a circular dual-mode substrate integrated waveguide (SIW) filter with two controllable transmission zeros is proposed. Two vias situated on a diameter line are employed to perturb two modes in a circular substrate integrated waveguide resonator. Taking advantage of the modal orthogonality of multiple cavity modes, transmission zeros are created. By moving the vias along the diameter line, the transmission zeros can be adjusted. The coupling matrix is employed to analyze the design concept. A three-pole filter with the center frequency at 8 GHz and two transmission zeros at 8.6 and 9.2 GHz is designed and fabricated. Experimental and simulated results are presented which validate the design concept of the proposed filter.
Autors: Cheng, F.;Lin, X.Q.;Lancaster, M.;Song, K.;Fan, Y.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Sep 2015, volume: 25, issue:9, pages: 576 - 578
Publisher: IEEE
 
» A Dynamic Vision Sensor With 1% Temporal Contrast Sensitivity and In-Pixel Asynchronous Delta Modulator for Event Encoding
Abstract:
A dynamic vision sensor (DVS) encodes temporal contrast (TC) of light intensity into address-events that are asynchronously transmitted for subsequent processing. This paper describes a DVS with improved TC sensitivity and event encoding. To enhance the TC sensitivity, each pixel employs a common-gate photoreceptor for low output noise and a capacitively-coupled programmable gain amplifier for continuous-time signal amplification without sacrificing the intra-scene dynamic range. A proposed in-pixel asynchronous delta modulator (ADM) better preserves signal integrity in event encoding compared with self-timed reset (STR) used in previous DVSs. A 60 30 prototype sensor array with a 31.2 pixel pitch was fabricated in a 1P6M 0.18 CMOS technology. It consumes 720 at a 100k event/s output rate. Measurements show that a 1% TC sensitivity with a 35% relative standard deviation is achieved and that the in-pixel ADM is up to 3.5 times less susceptible to signal loss than STR in terms of event number. These improvements can facilitate the application of DVSs in areas like optical neuroimaging which is demonstrated in a simulated experiment.
Autors: Yang, M.;Liu, S.-C.;Delbruck, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Sep 2015, volume: 50, issue:9, pages: 2149 - 2160
Publisher: IEEE
 
» A Family of Bit-Representation-Optimized Formats for Fast Sparse Matrix-Vector Multiplication on the GPU
Abstract:
Sparse matrix-vector multiplication (SpMV) is an important kernel that is used in many iterative algorithms for solving scientific and engineering problems. One of the main challenges of SpMV is its memory-boundedness due to the low arithmetic intensity of the kernel. Although compression has been proposed previously to improve SpMV performance on CPUs, its use has not been demonstrated on the GPU because of the serial nature of many compression and decompression schemes. In this paper, we introduce a family of bit-representation-optimized (BRO) compression formats for representing sparse matrices on GPUs. The proposed formats – BRO-CSR, BRO-ELL and BRO-HYB, perform compression on index data and help to speed up SpMV on GPUs through the reduction of memory traffic. We also propose two other hybrid BRO formats which can potentially perform better than both HYB and BRO-HYB formats. Experimental results demonstrate that compared to uncompressed CSR and ELLPACK formats, our proposed compressed BRO-CSR and BRO-ELL formats are able to achieve average speedups of 2 and 1.4 respectively. Furthermore, we demonstrate that by using BRO-ELL, the preconditioned conjugate gradient method is able to achieve an average speedup of 1.3 over ELLPACK.
Autors: Tang, W.T.;Tan, W.J.;Goh, R.S.M.;Turner, S.J.;Wong, W.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Sep 2015, volume: 26, issue:9, pages: 2373 - 2385
Publisher: IEEE
 
» A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation
Abstract:
Analog layout generation in the advanced CMOS design is challenging by its increasing layout constraints and performance requirements. This situation becomes more intricate by the growing parasitic variability and manufacturing reliability. To facilitate the feasibility of template-based layout migration, this paper first introduces a layout preservation, which extracts placement and routing behaviors from an existing layout into a crossing graph via constrained Delaunay triangulation. And later this crossing graph can be migrated into multiple layouts with placement and routing reconnection. The proposed approach also provides a refinement for wire to optimize the performance metrics. This approach is applied to a variable-gain amplifier, a folded-cascode operational amplifier, and a low dropout regulator. The experimental results demonstrate more possibility on layout migration, such that averagely more than 75% routing of migrated layout is generated by our approach. Additionally, it exhibits the productivity with qualified performance on different designs.
Autors: Pan, P.;Chin, C.;Chen, H.;Chen, T.;Lee, C.;Lin, J.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Sep 2015, volume: 34, issue:9, pages: 1373 - 1386
Publisher: IEEE
 
» A Flexible and Configurable Architecture for Automatic Control Remote Laboratories
Abstract:
In this paper, we propose a novel approach in hardware and software architecture design for implementation of remote laboratories for automatic control. In our contribution, we show the solution with flexible connectivity at back-end, providing features of multipurpose usage with different types of experimental devices, and fully configurable client side application at front-end. The physical setup and communication principles of hardware architecture are based on two types of devices: the programmable logic controllers and industrial network routers. The user interface of client application is designed as a Web page, powered by optimized JavaScript, using the sophisticated on-the-fly content generation. To prove the suitability of the architecture, we compare it with other existing approaches of remote laboratory design. We evaluate their benefits and weaknesses, especially in terms of expense, implementation difficulty, and versatility of usage. In this paper, we also show a detailed example of remote laboratory implementation based on new architecture for thermo-optical educational system and provide three other examples of developed remote laboratories. Evaluation of remote laboratory usage and its benefits is provided to demonstrate the learning value of proposed architecture in education process.
Autors: Kaluz, M.;Garcia-Zubia, J.;Fikar, M.;Cirka, L.;
Appeared in: IEEE Transactions on Learning Technologies
Publication date: Sep 2015, volume: 8, issue:3, pages: 299 - 310
Publisher: IEEE
 
» A Focus on Key Areas: Updates from IEEE Board of Directors Meetings [Leader's Corner]
Abstract:
Presents information on upcoming IEEE Board of Directors meetings.
Autors: Reder, W.;
Appeared in: IEEE Power and Energy Magazine
Publication date: Sep 2015, volume: 13, issue:5, pages: 6 - 8
Publisher: IEEE
 
» A Formal Verification Methodology for FPGA-Based Stepper Motor Control
Abstract:
Stepper motors are electric motors that are used extensively in safety-critical applications such as auto, medical devices, and surgical robots. A popular trend is the use of FPGA-based digital control for stepper motors. We present a formal verification methodology for 6 types of stepper motor (SM) control. Our methodology is based on the theory of Well-Founded Equivalence Bisimulation refinement , where both formal specifications and implementations are treated as transition systems. We define formal specifications for six types of Stepper Motor control. We also develop correctness proof obligations for FPGA implementations of stepper motor control. The methods are demonstrated using six case studies. The specifications are simple, with less than 50 transitions. We have used our methodology to verify FPGA controllers with millions of transitions against these simple specifications.
Autors: Jabeen, S.;Srinivasan, S.K.;Shuja, S.;Dubasi, M.A.L.;
Appeared in: IEEE Embedded Systems Letters
Publication date: Sep 2015, volume: 7, issue:3, pages: 85 - 88
Publisher: IEEE
 
» A Four-Element Array of Wideband Low-Profile H-Plane Horns
Abstract:
A wideband wide-coverage H-plane horn array with vertical polarization is proposed. Due to its light weight and low profile, the designed array is suitable for applications in spectrum monitoring systems on moving platforms. The switched-beam symmetrical array consists of four identical short H-plane horns. Pattern deterioration occurring in a high-frequency range is solved by inserting two pins in each horn. The measured impedance bandwidth is almost 100% for owing to its fed structure with a thick-cylinder-loaded probe. The measured azimuth-plane beamwidth is about 90 over the entire frequency range from 860 to 2500 MHz. Moreover, the measured results with the corresponding simulated results are presented and discussed in this paper.
Autors: Yang, L.;Shen, Z.;Wu, W.;Zhang, J.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Sep 2015, volume: 64, issue:9, pages: 4356 - 4359
Publisher: IEEE
 
» A Framework for Composition and Enforcement of Privacy-Aware and Context-Driven Authorization Mechanism for Multimedia Big Data
Abstract:
The proliferation of multimedia big data for dissemination and sharing of massive amounts of information raises important security and privacy concerns. One such concern is the composition and enforcement of privacy policies in order to securely manage access of multimedia big data. Several researchers have pointed out that for proper enforcement of privacy policies, the privacy requirements should be captured in access control systems. In this paper, we propose a hybrid approach where privacy requirements are captured in an access control system and present a framework for composition and enforcement of privacy policies. The focus is to allow a user, not a system or security administrator to compose conflict free policies for their online multimedia data. An additional requirement is that such a policy be context-aware. We also present a methodology for verifying the privacy policy in order to ensure correctness and logical consistency. The verification process is also used to ensure that sensitive security requirements are not violated when privacy rules are enforced. A prototype, named Intelligent Privacy Manager (iPM), has been implemented for sharing of multimedia big data in a secure and private manner.
Autors: Samuel, A.;Sarfraz, M.I.;Haseeb, H.;Basalamah, S.;Ghafoor, A.;
Appeared in: IEEE Transactions on Multimedia
Publication date: Sep 2015, volume: 17, issue:9, pages: 1484 - 1494
Publisher: IEEE
 
» A Framework of Reconfigurable Transducer Nodes for Smart Home Environments
Abstract:
This letter presents a transducer network framework that supports the amalgamation of multiple transducers into single wireless nodes. This approach is aimed at decreasing energy consumption by reducing the number of wireless transceivers involved in such networks. To make wireless nodes easily reconfigurable, a plug and play mechanism is applied to enable the clustering of any number of transducers. Furthermore, an algorithm is proposed to dynamically detect added and removed transducers from a node. Lastly, an XML based protocol is devised to allow nodes to communicate a description of their layout, measured data and control information. To verify the proposed framework, multiple reconfigurable wireless nodes are used to monitor the dynamic condition of a multiple rooms during a period of 24 hours in order to emulate a smart home scenario.
Autors: Hafidh, B.;Al Osman, H.;Dong, H.;El Saddik, A.;
Appeared in: IEEE Embedded Systems Letters
Publication date: Sep 2015, volume: 7, issue:3, pages: 81 - 84
Publisher: IEEE
 
» A Fully On-Chip PT-Invariant Transconductor
Abstract:
This brief presents a novel process and temperature (PT)-invariant transconductor, fabricated and tested in 180-nm CMOS technology. It uses a novel bias circuit for implementing a PT-invariant transconductor using a MOSFET in triode region. Measurements show that the transconductance varies only by ±3.4% across 18 fabricated chips and over temperatures ranging from 25 °C to 100 °C. Simulations show that variation of the transconductance across process corners is ±6.7% and across temperature range of 0 °C to 100 °C is ±1.6%. The proposed PT-invariant transconductor has the minimum variation among the fully on-chip transconductors reported so far. The proposed circuit consumes 136 W of power.
Autors: Amaravati, A.;Dave, M.;Baghini, M.S.;Sharma, D.K.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Sep 2015, volume: 23, issue:9, pages: 1961 - 1964
Publisher: IEEE
 
» A General Formula for the Mismatch Capacity
Abstract:
The fundamental limits of channels with mismatched decoding are addressed. A general formula is established for the mismatch capacity of a general channel, defined as a sequence of conditional distributions with a general decoding metrics sequence. We deduce an identity between the Verdú–Han general channel capacity formula, and the mismatch capacity formula applied to maximum likelihood decoding metric. Furthermore, several upper bounds on the capacity are provided, and a simpler expression for a lower bound is derived for the case of a non-negative decoding metric. The general formula is specialized to the case of finite input and output alphabet channels with a type-dependent metric. The closely related problem of threshold mismatched decoding is also studied, and a general expression for the threshold mismatch capacity is obtained. As an example of threshold mismatch capacity, we state a general expression for the erasures-only capacity of the finite input and output alphabet channel. We observe that for every channel, there exists a (matched) threshold decoder, which is capacity achieving. In addition, necessary and sufficient conditions are stated for a channel to have a strong converse.
Autors: Somekh-Baruch, A.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Sep 2015, volume: 61, issue:9, pages: 4554 - 4568
Publisher: IEEE
 
» A Generalized Likelihood Ratio Test for Coherent Change Detection in Polarimetric SAR
Abstract:
Several detection statistics have been proposed for detecting fine ground disturbances between two synthetic aperture radar (SAR) images, such as vehicle tracks. The standard method involves estimating a local correlation coefficient between images. Other methods have been proposed using various statistical hypothesis tests. One of these alternative methods is a generalized likelihood ratio test (GLRT), which compares a full-correlation image model to a no-correlation image model. In this letter, we expand the GLRT to polarimetric SAR data and derive the appropriate GLRT detection statistics. Additionally, we explore relaxing the equal variance/equal polarimetric covariance assumptions used in previous results and find improved performance on macroscopic scene changes.
Autors: Barber, J.;
Appeared in: IEEE Geoscience and Remote Sensing Letters
Publication date: Sep 2015, volume: 12, issue:9, pages: 1873 - 1877
Publisher: IEEE
 
» A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure
Abstract:
A general potential model is proposed for all types of double-gate junctionless FETs (DGJL-FETs), i.e., the symmetric versus asymmetric DG structures and the tied versus untied DG structures. The potential model is obtained with a simple form through a 2-D Poisson’s equation based on the assumption that the vertical channel potential is approximated to a cubic function of the position in order to consider all types of DGJL-FETs. An analytical threshold voltage ( equation via the potential model is derived with the gate voltage when the sum of the depletion widths from the front-gate and the back-gate equals the body thickness. The analytic solution of shows good agreement with the simulation results down to a channel length <20 nm. The variability of is analyzed for various device parameters. The back-gate effect of the untied DG structure is also investigated.
Autors: Hur, J.;Choi, J.;Woo, J.;Jang, H.;Choi, Y.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Sep 2015, volume: 62, issue:9, pages: 2710 - 2716
Publisher: IEEE
 
» A High Efficiency Input/Output Magnetically Coupled Interleaved Buck–Boost Converter With Low Internal Oscillation for Fuel-Cell Applications: CCM Steady-State Analysis
Abstract:
The performance of dc-dc converters plays a vital role in the exploitation of renewable energy sources such as solar and fuel cell (FC). This paper demonstrates the feasibility of using the input/output (I/O) magnetically coupled interleaved buck-boost converter, improving the conventional interleaved cascaded buck-boost converter in FC applications. While keeping the same step-up/step-down voltage transfer ratio, the proposed topology facilitates operating conditions with its nonpulsating I/O currents and high efficiency using interleaved technique and reducing switches' voltage stresses, respectively. The steady-state operation of the converter is analyzed based on the state-space-averaging method and supported with simulation results. The prototype setup of 360-W and 36-V output voltage for an FC with a brand of “FCgen 1020ACS” Ballard Power Systems, Inc. was implemented. Experimental results are presented to verify the theoretical expected merits of the converter, including high efficiency and nonpulsating I/O currents.
Autors: Samavatian, V.;Radan, A.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Sep 2015, volume: 62, issue:9, pages: 5560 - 5568
Publisher: IEEE
 
» A High-Performance 2×27 MVA Machine Test Bench Based on Multilevel IGCT Converters
Abstract:
In this paper, a high-performance 22 MW/27 MVA test bench using a pumpback topology is introduced for testing electrical machines. It proposes a cost-effective concept that works reliably even with a weak grid. A paralleling concept of two three-level integrated gate-commutated thyristor (IGCT) converters is presented. I generates a five-level pulse pattern with low harmonic distortion at 600-Hz carrier frequency and 80-Hz load frequency. The selected magnetic device minimizes the circulating current, which ensures the full power utilization of IGCT converters. Moreover, the control concept works reliably at 7.5 times of the carrier-to-load frequency ratio while there is a sine filter and a variable-frequency transformer between the converter and load machines. This test bench has been experimentally validated at the customer site.
Autors: Shen, J.;Schroder, S.;Qu, B.;Zhang, Y.;Chen, K.;Zhang, F.;Li, Y.;Liu, Y.;Dai, P.;Zhang, R.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Sep 2015, volume: 51, issue:5, pages: 3877 - 3889
Publisher: IEEE
 
» A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels
Abstract:
With the development of parallel computing, the compute-intensive part of an application could be accelerated so dramatically that the control intensive part, usually processed by a sequential processor, is becoming more and more critical in terms of performance and power consumption. To address this problem, this paper proposes a novel reconfigurable architecture to execute control-intensive kernels efficiently. The architecture applies three key design methods. The first one, parallel condition, exploits the instruction level parallelism of conditional branches with hardware design. The second one, configuration branch, enables the architecture to independently execute an entire application that has loops and other control flows. The third one, compound configuration, combines multiple configurations of low hardware utilization, which are common in sequential codes particularly, and thus reduces the reconfiguring times. Therefore, to offload control-intensive kernels onto the proposed architecture will speed up these workloads and boost the overall performance. The experiments were conducted on a benchmark that contains various branches, loops, and sequential codes. The results showed that the proposed architecture alone could implement the benchmark correctly. In addition, the proposed methods can improve performance by over 40% compared with the conventional techniques. The power efficiency is two orders larger than general purpose processors.
Autors: Zhu, J.;Liu, L.;Yin, S.;Yang, X.;Wei, S.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Sep 2015, volume: 23, issue:9, pages: 1700 - 1709
Publisher: IEEE
 
» A Hybrid Scheme With Nyström Discretization for Solving Transient Electromagnetic Scattering by Conducting Objects
Abstract:
The interaction of transient electromagnetic (EM) waves with objects can be formulated by the integral equation approach in time domain. For conducting objects or homogeneous penetrable objects, the time-domain surface integral equations (TDSIEs) can be applied. Traditionally, the TDSIEs are solved by combining the method of moments (MoM) in spatial domain and a march-on-in-time (MoT) scheme in temporal domain. The MoM usually requires conforming meshes with a well-designed basis function and the MoT may suffer from a stability problem. In this work, we propose a hybrid scheme in which the Nyström method is used in spatial domain while the MoM with Laguerre function as basis and testing functions is employed with a march-on-in-degree (MoD) manner in the temporal domain. The Nyström method does not require any basis and testing functions and can use nonconforming meshes in spatial domain, whereas the MoM with Laguerre function as basis and testing functions can fully eliminate the stability problem in temporal domain. Numerical examples for EM scattering by typical conducting objects are presented to demonstrate the scheme and its merits have been verified.
Autors: Tong, M.S.;Chen, W.J.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Sep 2015, volume: 63, issue:9, pages: 4219 - 4224
Publisher: IEEE
 
» A Hybrid Wedge-To-Wedge Plasmonic Waveguide With Low Loss Propagation and Ultra-Deep-Nanoscale Mode Confinement
Abstract:
The well-known tradeoff between the propagation loss and mode confinement is a critical consideration for the plasmonic waveguide structures. Aiming to overcome this limitation, in this paper, we propose a compact plasmonic waveguide consisting of two identical dielectric wedge waveguides symmetrically placed on each side of a nanowedge-patterned thin metal film. The systematical analysis has demonstrated that the light can be confined to approximate 3000th of the diffraction spot size (ranging from λ2/10 604 to λ2 /972) without sacrificing the propagation length (ranging from 1680 to 4724 μm). Compared to the recent published structure which achieved the best tradeoff, to the best of our knowledge, the proposed waveguide could achieve a 9-fold enhanced mode confinement for the same propagation length and a 2.4-fold outspread propagation length for the same mode confinement.
Autors: Ma, Y.;Farrell, G.;Semenova, Y.;Wu, Q.;
Appeared in: Journal of Lightwave Technology
Publication date: Sep 2015, volume: 33, issue:18, pages: 3827 - 3835
Publisher: IEEE
 
» A kit for the internet of things [Resources_Hands On]
Abstract:
Just like pretty much every other tech outlet, IEEE Spectrum has been nattering on for a while now about the coming Internet of Things (IoT). This is the vision of a world where not only our PCs and smartphones are connected to the Internet but where nearly every device that runs on electricity???fridges, scales, lightbulbs???has sensors, a small glob of processing power, and a network connection. ??? Makers have been building IoT-style gadgets for some time, but it can be quite fiddly to glue together all the required bits of hardware and software. In a bid to make it easier for developers to get their feet wet and start experimenting with the concepts behind the IoT, IBM and ARM have teamed up to create the US $120 Mbed IoT Starter Kit, intended to be ???a slick experience???particularly suitable for developers with no specific experience in embedded or web development.??? ??? On the hardware side, the Starter Kit consists of an FRDM???K64F microcontroller and an application shield that fits on top. Pin-compatible with Arduino boards, the FRDM-K64F has an Ethernet interface built in and is based on a chip with an ARM Cortex-M4 core that???s capable of running at up to 120 megahertz (in comparison, the Arduino Mega clocks in at 16 MHz). The application shield is equipped with a temperature sensor, three-axis accelerometer, RGB LED, five-way joystick, two potentiometers, a loudspeaker, and a small 128- by 32-pixel LCD. ??? On the software side is IBM???s Internet of Things Foundation and its Bluemix service, which lets you build and deploy apps for IoT devices.
Autors: Cass, S.;
Appeared in: IEEE Spectrum
Publication date: Sep 2015, volume: 52, issue:9, pages: 23 - 24
Publisher: IEEE
 
» A Linewidth-Tolerant Two-Stage CPE Using a New QPSK-Partitioning Approach and an Enhanced Maximum Likelihood Detection for 64-QAM Coherent Optical Systems
Abstract:
We propose a novel two-stage carrier phase estimation (CPE) algorithm for 64-ary quadrature amplitude modulation (64-QAM) coherent optical systems. It makes use of a new quadrature phase shift keying partitioning (QPSK-partitioning) approach and an enhanced maximum likelihood (ML) detection. 36/64 of the 64-QAM symbols are statistically employed by the modified QPSK-partitioning approach to estimate phase noise in the first stage. The proposed enhanced ML detection is used in the second stage to improve linewidth tolerance performance. The simulation results show that, our proposed VVPEc1&c2 + EML algorithm can achieve much higher linewidth tolerance performance than the modified V&V + MLE algorithm at high laser linewidth level. A combined laser linewidth symbol duration product as high as is achieved by the proposed two-stage CPE algorithm at a target BER of with 1 dB SNR sensitivity penalty.
Autors: Chen, Y.;Huang, X.G.;
Appeared in: Journal of Lightwave Technology
Publication date: Sep 2015, volume: 33, issue:18, pages: 3883 - 3889
Publisher: IEEE
 
» A Low Power LNA-Phase Shifter With Vector Sum Method for 60 GHz Beamforming Receiver
Abstract:
Taking into consideration the limitations of the conventional vector sum phase shifter (VSPS), a low power LNA-PS is proposed for a 60 GHz beamforming receiver using a 65 nm CMOS process. By developing a low loss 90 ° PS that integrates the HPF into the LPF with a low loss SPST switch and a power efficient vector adder using a current reuse structure, the proposed LNA-PS shows the gain of 24 dB, the highest among the LNA-PSs developed to date, with very small power consumption of 16 mW. The total size including the pads is only 1.3 mm2.
Autors: In Sang Song;Joong Geun Lee;Giwan Yoon;Chul Soon Park;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Sep 2015, volume: 25, issue:9, pages: 612 - 614
Publisher: IEEE
 
» A Low-Complexity Detection Scheme for Differential Spatial Modulation
Abstract:
Differential spatial modulation (DSM), which does not require the channel state information at the receiver, is an attractive alternative to its coherent counterpart. The optimal maximum-likelihood (ML) detector of the DSM system employs the classic block-by-block method for jointly detecting the activated antenna matrix (AM) and the modulation symbols, resulting in high computational complexity. In this letter, a low-complexity near-ML detector, which operates on a symbol-by-symbol basis, is proposed for the DSM scheme. Specifically, in each block, the index of the activated transmit antenna and modulation symbol in each time slot are first obtained, and then, these antenna indices are utilized to simply determine the index of the activated AM. Simulation results show that the proposed algorithm is capable of offering almost the same performance as that of the ML detector with more than 90% reduction in complexity.
Autors: Xiao, L.;Yang, P.;Lei, X.;Xiao, Y.;Fan, S.;Li, S.;Xiang, W.;
Appeared in: IEEE Communications Letters
Publication date: Sep 2015, volume: 19, issue:9, pages: 1516 - 1519
Publisher: IEEE
 
» A low-cost desktop software defined radio design environment using MATLAB, simulink, and the RTL-SDR
Abstract:
In the last five years, the availability of powerful DSP and communications design software, and the emergence of relatively affordable devices that receive and digitize RF signals, has brought SDR to the desktops of many communications engineers. However, the more recent availability of very low cost SDR devices such as the RTL-SDR, costing less than $20, has brought SDR to the home desktops of undergraduate and graduate students, as well as professional engineers and the maker communities. Since the release of the various open source drivers for the RTL-SDR, many in the digital communications community have used this device to scan the RF spectrum and digitize I/Q signals that are being transmitted in the range 25 MHz to 1.75 GHz. This wide operating range enables the sampling of frequency bands containing signals such as FM radio, ISM signals, GSM, 3G and LTE mobile radio, GPS, and so on. In this article we will describe the opportunity and operation of the RTL-SDR, and the development of a handson, open-courseware for SDR. These educational materials can be integrated into core curriculum undergraduate and graduate courses, and will greatly enhance the teaching of DSP and communications theory, principles, and applications. The lab and teaching materials have recently been used in senior (fourth year undergraduate) courses and are available as open course materials for all to access, use, and evolve.
Autors: Stewart, R.W.;Crockett, L.;Atkinson, D.;Barlee, K.;Crawford, D.;Chalmers, I.;Mclernon, M.;Sozer, E.;
Appeared in: IEEE Communications Magazine
Publication date: Sep 2015, volume: 53, issue:9, pages: 64 - 71
Publisher: IEEE
 
» A Low-Power Broadband 200 GHz Down-Conversion Mixer with Integrated LO-Driver in 0.13 m SiGe BiCMOS
Abstract:
This letter presents an active 200 GHz fundamental down-conversion mixer based on the Micromixer topology for low-power high data-rate wireless communications. The mixer-core operation requires a 5 dBm LO-signal, which is generated on-chip from an external single-ended source of only 20 dBm by means of a power-efficient LO-driver and a passive balun. Mixer, LO-driver and balun have been implemented together in a 450 GHz SiGe BiCMOS technology occupying a circuit core area of 0.21 mm . For a 200 GHz LO-signal, the characterized circuit exhibits a maximum conversion gain of 5.5 dB over a 3 dB RF-bandwidth of 30 GHz, requiring only 17.4 and 22.5 mW of DC-power in the mixer core and in the LO-driver, respectively.
Autors: Fritsche, D.;Leufker, J.D.;Tretter, G.;Carta, C.;Ellinger, F.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Sep 2015, volume: 25, issue:9, pages: 594 - 596
Publisher: IEEE
 

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