Log in
Register

Electrical and Electronics Engineering publications abstract of: 08-2016 sorted by title, page: 0

» (Continuous) Phase Modulation on the Hypersphere
Abstract:
We introduce phase modulation on the hypersphere (PMH) for load-modulated multiple-input multiple-output (MIMO) transmitters with a single central power amplifier. In PMH, the peak to average ratio of the sum power before pulse shaping is 1; thus, the central power amplifier of load-modulated MIMO transmitters does not require any back-off. We derive the capacity of PMH on an additive white Gaussian noise channel and show that the input signal should be uniformly distributed on a hypersphere. The mutual information of uniformly distributed PMH input is derived in an uplink multiple-access independent identically distributed Gaussian MIMO channel using the replica method from statistical physics. Furthermore, discrete PMH is introduced using spherical codes and also generalizing minimum shift keying from the complex unit circle to the hypersphere. We investigate different pulse shaping methods for PMH including a novel spherical filtering. Using spherical pulse shaping, the signal stays on the hypersphere. Various filters are investigated, and a tradeoff between spectral shape and peak-to-average-sum-power ratio (PASPR) is found. For as few as four antennas, good spectral properties (similar to root-raised cosine pulses) can be achieved at very low PASPR. Both former and latter further improve with increasing the number of antennas.
Autors: Mohammad Ali Sedaghat;Ralf R. Müller;Christoph Rachinger;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Aug 2016, volume: 15, issue:8, pages: 5763 - 5774
Publisher: IEEE
 
» 13th International Bhurban Conference on Applied Sciences and Technology Held in January in Islamabad [Meeting Reports]
Abstract:
Presents information on the 13th International Bhurban Conference on Applied Sciences and Technology.
Autors: Levent Sevgi;
Appeared in: IEEE Antennas and Propagation Magazine
Publication date: Aug 2016, volume: 58, issue:4, pages: 18 - 18
Publisher: IEEE
 
» 2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D Integration
Abstract:
This paper introduces a hybrid capacitive coupling interconnects (CCIs) array suitable for bumpless flip-chip 3-D integration. Inside the hybrid array, both single-ended and common-centroid differential CCIs are interleaved together to cancel the crosstalk among them. The crosstalk cancellation capability of its own allows CCIs to be placed closer and thus improves the area efficiency. A high gain and high common-mode-rejection ratio receiver is also presented to minimize the jitter caused by the common-mode noise. The process variation track biasing circuit is also proposed for the receiver. The measurement verifies that the proposed transceiver in a pseudohybrid CCIs array produces only 84 ps or 0.2 unit interval crosstalk related jitter under the worst case crosstalk condition. A total of nine transceivers in the array achieve the data rate of 20.79 Gb/s and consume only /Gb/s. The chip was fabricated in 65-nm CMOS technology.
Autors: Aung, M.-T.-L.;Lim, T.H.;Yoshikawa, T.;Kim, T.T.-H.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Aug 2016, volume: 24, issue:8, pages: 2703 - 2711
Publisher: IEEE
 
» 25-Gb/s OOK Transmission Using 1.5- 10G-Class VCSEL for Optical Access Network
Abstract:
We explore the possibility of transmitting 25-Gb/s on-off keying (OOK) signals generated by using a 1.5-μm 10G-class vertical-cavity surface-emitting laser (VCSEL) over standard single-mode fiber (SSMF) for optical access applications. A transistor-outline-can packaged VCSEL having a 3-dB modulation bandwidth of 7 GHz is utilized to transmit the 25-Gb/s signals. We experimentally investigate the transmission performances of OOK signals obtained from two different transmitter schemes: with and without a delay interferometer (DI) at the output of the directly modulated VCSEL. In order to maximize the transmission distance without using bulky and lossy dispersion compensation modules, we optimize the extinction ratio of the signals and apply the electrical equalization at the receiver. Also optimized is the free-spectral range (FSR) of the DI when it is utilized. The experimental results show that we can successfully transmit the 25-Gb/s OOK signals over 33- and 45-km long SSMF with and without the DI, respectively. The use of DI not only alleviates the band limitation of the VCSEL but also significantly improves the receiver sensitivity of the 25-Gb/s OOK signal up to 30 km. Moreover, a larger power budget is achieved for transmission distances shorter than 25 km when a DI having an FSR of 25 GHz is utilized at the output of the VCSEL.
Autors: Jingjing Zhou;Changyuan Yu;Gurusamy Mohan;Hoon Kim;
Appeared in: Journal of Lightwave Technology
Publication date: Aug 2016, volume: 34, issue:16, pages: 3790 - 3795
Publisher: IEEE
 
» 3-D Integration of MEMS and CMOS Using Electroless Plated Nickel Through-MEMS-Vias
Abstract:
Three-dimensional integration of microelectromechanical systems (MEMS) and CMOS is able to achieve hetero-integrated microsystems with high performance, small size, low cost, and multiple functions. This paper reports a 3-D integration method using wafer transfer technology and electroless Ni plating with a noncontact induction (ENPNI) technique. Wafer transfer technology based on adhesive bonding and wafer thinning allows stacked integration of MEMS on top of CMOS. To address the challenge in fabricating through-MEMS-vias (TMVs) with small diameters, ENPNI has been developed to fabricate Ni TMVs as both the mechanical supports for suspended MEMS and the electrical connects between MEMS and CMOS. High-density MEMS arrays and CMOS circuits are integrated to demonstrate the feasibility of the 3-D integration method, and thermal cycling and mechanical vibration are performed to evaluate the reliability. Experimental results show that the 3-D integration processes do not exert distinct influences on MEMS arrays and CMOS circuits, and the integrated systems have good yield, uniformity, and reliability. The capability of ENPNI in the fabrication of small TMVs enables 3-D integration of high-density MEMS arrays and CMOS circuits, such as micromirror arrays, infrared focal planes, acoustic sensor arrays, radiation sensor arrays, and so on.
Autors: Yuxin Du;Dong Wu;Zhen Song;Miao Liu;Sujie Yang;Zheyao Wang;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Aug 2016, volume: 25, issue:4, pages: 770 - 779
Publisher: IEEE
 
» 3-D Printing as an Effective Educational Tool for MEMS Design and Fabrication
Abstract:
This paper presents a series of course modules developed as a high-impact and cost-effective learning tool for modeling and simulating the microfabrication process and design of microelectromechanical systems (MEMS) devices using three-dimensional (3-D) printing. Microfabrication technology is an established fabrication technique for small and high-precision MEMS devices; these processes typically take place in a cleanroom with the use of expensive high-vacuum equipment. These course modules were developed to provide engineering educators a more affordable and effective method for teaching MEMS modeling in settings without a cleanroom, as is the case in many undergraduate institutions. Feedback from student evaluations as well as course grades all support the efficacy of these course modules. In these hands-on modules, by designing and building the MEMS prototypes, the students learn by experiencing the process of building a MEMS device from the specifications given. The results are also compared to similar assessments made in the course before the introduction of these course modules to verify success. The detailed description of the modules, the evaluation methodologies adopted, and reflections on the implementation are discussed.
Autors: Dahle, R.;Rasel, R.;
Appeared in: IEEE Transactions on Education
Publication date: Aug 2016, volume: 59, issue:3, pages: 210 - 215
Publisher: IEEE
 
» 40th Anniversary of COMPSAC: Highlights
Abstract:
The 40th IEEE Computer Society International Conference on Computers, Software & Applications was held in 2016 in Atlanta, Georgia, from June 10-14. The author reviews this year's conference theme, keynote addresses, and significant panels and how they relate to IT professionals.
Autors: Sorel Reisman;
Appeared in: IT Professional
Publication date: Aug 2016, volume: 18, issue:4, pages: 4 - 6
Publisher: IEEE
 
» 5-GHz Vehicle-to-Vehicle Channel Characterization for Example Overpass Channels
Abstract:
The overpass is a special over-road structure for vehicular travel, constituting one type of roadway intersection. Real-time communications between on- and under-overpass vehicles can contribute to effective vehicle-to-vehicle (V2V) communications, including, for example, optimal route selection and overpass accident warning messaging. Ensuring effective communication requires a quantitative characterization of the overpass propagation channel. In this paper, we provide measurement and analytical results for V2V propagation path loss and root-mean-square delay spread, and from these results, we develop tapped-delay line channel models that are applicable to the 5-GHz band for two example overpasses. These two example overpasses are termed i) one-lane metal-bottom overpass and ii) two-lane metal-bottom overpass. Due to the unique structure of the overpasses, we divide the radio propagation space around the overpass into four different areas: a two-ray area, a short-term partial-shadowing area, a (full) shadowing area, and a long-term partial-shadowing area. In the two-ray area, a line-of-sight (LOS) path and a ground-reflected path are the dominant propagation mechanisms, whereas in the other areas, the overpass body (floor, walls, and columns) attenuates the LOS signal. The accuracy of our measurement results and the developed channel model are verified by a geometry-based stochastic channel modeling approach, in which the height dimension is first introduced to characterize the diffraction phenomenon in V2V communication. The actual measurement and simulation results show good consistency.
Autors: Liu, P.;Ai, B.;Matolak, D.;Sun, R.;Li, Y.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Aug 2016, volume: 65, issue:8, pages: 5862 - 5873
Publisher: IEEE
 
» 6.3 mW 94 GHz CMOS Down-Conversion Mixer With 11.6 dB Gain and 54 dB LO-RF Isolation
Abstract:
A 94 GHz CMOS down-conversion mixer is reported. RF negative resistance compensation (NRC) technique, i.e., PMOS LC-oscillator-based RF transconductance (GM) stage load, is used to increase the output impedance and suppress the feedback capacitance Cgd of RF GM stage. As a result, conversion gain (CG), noise figure (NF) and LO-RF isolation of the mixer are enhanced. For frequencies of 80~110 GHz, the mixer consumes 6.3 mW and achieves excellent RF-port input reflection coefficient (S11) of -8.7~ -22 dB and LO-port input reflection coefficient (S22) of -10.3~-19.4 dB. In addition, the mixer achieves excellent CG of 4.1~11.6 dB, NF of 15.8~18.1 dB, and LO-RF isolation of 42.1~54 dB for frequencies of 80~110 GHz, one of the best CG, NF and LO-RF isolation results ever reported for a W-band CMOS down-conversion mixer.
Autors: Yo-Sheng Lin;Kai-Siang Lan;Chien-Chin Wang;Chien-Chu Chi;Shey-Shi Lu;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2016, volume: 26, issue:8, pages: 604 - 606
Publisher: IEEE
 
» 7-Bit SiGe-BiCMOS Step Attenuator for X-Band Phased-Array RADAR Applications
Abstract:
This letter presents a 7-bit CMOS step attenuator for the first time in the literature, designed with isolated NMOS (iNMOS) using IHP 0.25 μm SiGe BiCMOS process technology. INMOS' are utilized to decrease the insertion loss (IL) caused by internal parasitic capacitances, which is especially important when cascading 7 attenuation stages. The attenuator has a measured maximum relative attenuation of 16.51 dB with an increment of 0.13 dB while exhibiting a root mean square (RMS) amplitude error of less than 0.13 dB, the lowest error ever reported. In addition, the attenuator exhibits an RMS phase error of 2.7° at 10 GHz. The measured input referred 1 dB compression point (IP1 dB) of the attenuator is 12.5 dBm at 10 GHz. Moreover, the attenuator demonstrates an IL of less than 12.5 dB in X-band (8-12 GHz). The total chip area excluding pads is 0.29 mm2.
Autors: Murat Davulcu;Can Caliskan;Ilker Kalyoncu;Mehmet Kaynak;Yasar Gurbuz;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2016, volume: 26, issue:8, pages: 598 - 600
Publisher: IEEE
 
» -NET: A Network for Molecular Biology Applications in Microfluidic Chips
Abstract:
This paper introduces -NET, a microfluidic LAN that supports the exchange of both digital information and biochemical information carried by droplets moving across molecular processors in a microfluidic chip. The -NET can be used to support molecular biology applications like DNA, RNA, and protein biosynthesis. The -NET is the first realization of a microfluidic networking paradigm that controls movements of droplets in microfluidic chips by exploiting hydrodynamic phenomena only and builds on recent solutions to achieve communications in the microfluidic domain. The -NET integrates techniques to represent addressing information, as well as switching and medium access control solutions. In fact, in -NET, the address of the molecular processor where a droplet should be sent to is encoded into the distance between droplets; switching is executed to steer the droplets inside the microfluidic device; medium access control is applied to avoid collisions between droplets that may result in their fusion and, thus, loss of the biochemical information. In this paper, the design of -NET is presented in detail, and simulation results validating -NET operations are shown.
Autors: Donvito, L.;Galluccio, L.;Lombardo, A.;Morabito, G.;
Appeared in: IEEE/ACM Transactions on Networking
Publication date: Aug 2016, volume: 24, issue:4, pages: 2525 - 2538
Publisher: IEEE
 
» Multiple Kernel Fuzzy SVM-Based Data Fusion for Improving Peptide Identification
Abstract:
SEQUEST is a database-searching engine, which calculates the correlation score between observed spectrum and theoretical spectrum deduced from protein sequences stored in a flat text file, even though it is not a relational and object-oriental repository. Nevertheless, the SEQUEST score functions fail to discriminate between true and false PSMs accurately. Some approaches, such as PeptideProphet and Percolator, have been proposed to address the task of distinguishing true and false PSMs. However, most of these methods employ time-consuming learning algorithms to validate peptide assignments [1] . In this paper, we propose a fast algorithm for validating peptide identification by incorporating heterogeneous information from SEQUEST scores and peptide digested knowledge. To automate the peptide identification process and incorporate additional information, we employ multiple kernel learning (MKL) to implement the current peptide identification task. Results on experimental datasets indicate that compared with state-of-the-art methods, i.e., PeptideProphet and Percolator, our data fusing strategy has comparable performance but reduces the running time significantly.
Autors: Jian, L.;Xia, Z.;Niu, X.;Liang, X.;Samir, P.;Link, A.J.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Aug 2016, volume: 13, issue:4, pages: 804 - 809
Publisher: IEEE
 
» -Band Relativistic Traveling Wave Oscillator Based on a Circular Corrugated Waveguide
Abstract:
A coupling impedance () between a relativistic electron beam and a fundamental harmonic of a TM01 wave slowed down to the speed of light in a circular corrugated waveguide is calculated. The geometry of a relativistic ( keV) traveling wave oscillator (TWO) with an operating frequency of 1.25 GHz is optimized using this calculations by the fully electromagnetic particle-in-cell (PIC) code KARAT. The transient time obtained in PIC simulations is ns. A microwave power of 340 MW is also obtained in PIC simulations at an electron beam current of 3.0 kA in strong ( T) and weak ( T) guiding magnetic fields, which corresponds to the oscillator efficiency %.
Autors: Totmeninov, E.M.;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Aug 2016, volume: 44, issue:8, pages: 1276 - 1279
Publisher: IEEE
 
» -Band Waveguide Filters Fabricated by Laser Micromachining and 3-D Printing
Abstract:
This paper presents two W-band waveguide bandpass filters, one fabricated using laser micromachining and the other 3-D printing. Both filters are based on coupled resonators and are designed to have a Chebyshev response. The first filter is for laser micromachining and it is designed to have a compact structure allowing the whole filter to be made from a single metal workpiece. This eliminates the need to split the filter into several layers and therefore yields an enhanced performance in terms of low insertion loss and good durability. The second filter is produced from polymer resin using a stereolithography 3-D printing technique and the whole filter is plated with copper. To facilitate the plating process, the waveguide filter consists of slots on both the broadside and narrow side walls. Such slots also reduce the weight of the filter while still retaining the filter's performance in terms of insertion loss. Both filters are fabricated and tested and have good agreement between measurements and simulations.
Autors: Xiaobang Shang;Pavel Penchev;Cheng Guo;Michael J. Lancaster;Stefan Dimov;Yuliang Dong;Mirko Favre;Mathieu Billod;Emile de Rijk;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Aug 2016, volume: 64, issue:8, pages: 2572 - 2580
Publisher: IEEE
 
» Multiple Kernel Fuzzy SVM-Based Data Fusion for Improving Peptide Identification
Abstract:
SEQUEST is a database-searching engine, which calculates the correlation score between observed spectrum and theoretical spectrum deduced from protein sequences stored in a flat text file, even though it is not a relational and object-oriental repository. Nevertheless, the SEQUEST score functions fail to discriminate between true and false PSMs accurately. Some approaches, such as PeptideProphet and Percolator, have been proposed to address the task of distinguishing true and false PSMs. However, most of these methods employ time-consuming learning algorithms to validate peptide assignments [1] . In this paper, we propose a fast algorithm for validating peptide identification by incorporating heterogeneous information from SEQUEST scores and peptide digested knowledge. To automate the peptide identification process and incorporate additional information, we employ multiple kernel learning (MKL) to implement the current peptide identification task. Results on experimental datasets indicate that compared with state-of-the-art methods, i.e., PeptideProphet and Percolator, our data fusing strategy has comparable performance but reduces the running time significantly.
Autors: Jian, L.;Xia, Z.;Niu, X.;Liang, X.;Samir, P.;Link, A.J.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Aug 2016, volume: 13, issue:4, pages: 804 - 809
Publisher: IEEE
 
» iCrowd: Near-Optimal Task Allocation for Piggyback Crowdsensing
Abstract:
This paper first defines a novel spatial-temporal coverage metric, k-depth coverage, for mobile crowdsensing (MCS) problems. This metric considers both the fraction of subareas covered by sensor readings and the number of sensor readings collected in each covered subarea. Then iCrowd, a generic MCS task allocation framework operating with the energy-efficient Piggyback Crowdsensing task model, is proposed to optimize the MCS task allocation with different incentives and k-depth coverage objectives/ constraints. iCrowd first predicts the call and mobility of mobile users based on their historical records, then it selects a set of users in each sensing cycle for sensing task participation, so that the resulting solution achieves two dual optimal MCS data collection goals-i.e., Goal. 1 near-maximal k-depth coverage without exceeding a given incentive budget or Goal. 2 near-minimal incentive payment while meeting a predefined k-depth coverage goal. We evaluated iCrowd extensively using a large-scale real-world dataset for these two data collection goals. The results show that: for Goal.1, iCrowd significantly outperformed three baseline approaches by achieving 3-60 percent higher k-depth coverage; for Goal.2, iCrowd required 10.0-73.5 percent less incentives compared to three baselines under the same k-depth coverage constraint.
Autors: Xiong, H.;Zhang, D.;Chen, G.;Wang, L.;Gauthier, V.;Barnes, L.E.;
Appeared in: IEEE Transactions on Mobile Computing
Publication date: Aug 2016, volume: 15, issue:8, pages: 2010 - 2022
Publisher: IEEE
 
» A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications
Abstract:
This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.
Autors: Harikumar, P.;Wikner, J.J.;Alvandpour, A.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2016, volume: 63, issue:8, pages: 743 - 747
Publisher: IEEE
 
» A 0.45-V Low-Power OOK/FSK RF Receiver in 0.18 CMOS Technology for Implantable Medical Applications
Abstract:
A 0.45-V low-power 0.18 μm CMOS OOK/FSK RF receiver for implantable medical applications is proposed. The receiver utilizes a wake-up mechanism to adjust its power consumption automatically by reading the amplitude of the input wireless OOK/FSK modulated RF signal directly. No additional wireless wake-up commands are required. Such a normally-off and instanton scheme reduces the power consumption of this receiver significantly. The power consumption is 129 μW in sleep mode and 352 μW in wake-up mode. Other techniques, such as third-orderharmonic cancellation, subharmonic mixing, and forward body biasing are also adopted for better linearity, higher LO-to-RF isolation, and lower VDD, respectively. The measurement results show that the proposed receiver consumes only 2.6 nJ/bit (OOK) and 1 nJ/bit (FSK) to achieve the sensitivities of -55 dBm (OOK) and -53.5 dBm (FSK) in BER <; 10-3 constraint. The proposed receiver is designed for low-power and short-distance MICS band applications.
Autors: Jian-Yu Hsieh;Yi-Chun Huang;Po-Hung Kuo;Tao Wang;Shey-Shi Lu;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2016, volume: 63, issue:8, pages: 1123 - 1130
Publisher: IEEE
 
» A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
Abstract:
This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-but-low-quality clock for low-frequency operation. With the dual-mode clock generator enabled, a prototype 65 nm CMOS 0.6 V 12 b 10 MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24 LSB and 0.45 LSB, respectively. The FoM is 6.2 fJ/conversion-step with a power consumption of 83 μW. The ADC operates under the lowest supply voltage of 0.6 V among comparable designs with ENOBs over 10 and conversion rates over 1 MS/s.
Autors: Wan Kim;Hyeok-Ki Hong;Yi-Ju Roh;Hyun-Wook Kang;Sun-Il Hwang;Dong-Shin Jo;Dong-Jin Chang;Min-Jae Seo;Seung-Tak Ryu;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2016, volume: 51, issue:8, pages: 1826 - 1839
Publisher: IEEE
 
» A 0.67- 177-ppm/°C All-MOS Current Reference Circuit in a 0.18- CMOS Technology
Abstract:
This brief describes a nanopower current reference circuit that has been fabricated in a standard 0.18- CMOS technology. The proposed circuit is an extension of the resistorless current reference circuit suggested by Oguey and Aebischer. This extension is a simple circuit arrangement that is capable of reducing the temperature coefficient (TC) of Oguey's circuit. The measurements have been done on ten prototypes in the temperature range of −40 °C to +85 °C. The measured average reference current is 92.2 nA with the average TC value of 177 ppm/°C. The measured average reduction of ≈68% has been achieved in TC value of Oguey's circuit after implementing the proposed arrangement. The operating supply voltage for the proposed circuit ranges from 1.25 to 1.8 V with the line sensitivity of 7.5%/V. The measured maximum average power dissipation of the proposed current reference circuit is 0.67 at the supply voltage of 1.8 V.
Autors: Chouhan, S.S.;Halonen, K.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2016, volume: 63, issue:8, pages: 723 - 727
Publisher: IEEE
 
» A 0.67- 177-ppm/°C All-MOS Current Reference Circuit in a 0.18- CMOS Technology
Abstract:
This brief describes a nanopower current reference circuit that has been fabricated in a standard 0.18- CMOS technology. The proposed circuit is an extension of the resistorless current reference circuit suggested by Oguey and Aebischer. This extension is a simple circuit arrangement that is capable of reducing the temperature coefficient (TC) of Oguey's circuit. The measurements have been done on ten prototypes in the temperature range of −40 °C to +85 °C. The measured average reference current is 92.2 nA with the average TC value of 177 ppm/°C. The measured average reduction of ≈68% has been achieved in TC value of Oguey's circuit after implementing the proposed arrangement. The operating supply voltage for the proposed circuit ranges from 1.25 to 1.8 V with the line sensitivity of 7.5%/V. The measured maximum average power dissipation of the proposed current reference circuit is 0.67 at the supply voltage of 1.8 V.
Autors: Chouhan, S.S.;Halonen, K.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2016, volume: 63, issue:8, pages: 723 - 727
Publisher: IEEE
 
» A 1.8 pJ/bit Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration
Abstract:
A source-synchronous I/O architecture is reported that includes redundant receiver lanes to enable lane recalibration with reduced power and area overhead. Key features and considerations of the proposed architecture are described. A proof-of-concept 16 lane, 16 Gb/s per lane source-synchronous I/O test chip was designed and fabricated in a 32 nm SOI CMOS technology. Several circuit techniques employed in the design of this test chip are described. These include a phase rotator based on current-integrating phase interpolator cores with architecture and circuit improvements to performance as compared to prior art, an active-inductor-based RX CTLE, and an 8:1 TX serializer with 8-phase clocking. Measurements demonstrate the operation of the test chip over ultra-short-reach channels with up to 10 dB of loss with greater than 30% timing margin. The I/O circuitry operates from 1 V supplies and achieves a power efficiency of better than 2 pJ/bit, making the proposed architecture suitable for use in high-density interconnect applications required for high-performance computing systems.
Autors: Timothy O. Dickson;Yong Liu;Ankur Agrawal;John F. Bulzacchelli;Herschel A. Ainspan;Zeynep Toprak-Deniz;Benjamin D. Parker;Michael P. Beakes;Mounir Meghelli;Daniel J. Friedman;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2016, volume: 51, issue:8, pages: 1744 - 1755
Publisher: IEEE
 
» A 12-m 2.5-Gb/s Lighting Compatible Integrated Receiver for OOK Visible Light Communication Links
Abstract:
This paper presents a visible light communication (VLC) system for indoor applications. The system employs a high-sensitivity integrated circuit (IC) receiver with detection levels in the microwatts range. The proposed link is a lighting compatible VLC system enabled by the low noise floor of the IC receiver and capable of establishing a VLC link in the gigabit-per-second range with only 250 lux illuminance or 600-μW transmitted optical power from a high-speed 680-nm laser diode source. Dedicated optics is used for light steering and for focusing the transmitted power toward the receiver to maximize the collected optical power. The receiver is implemented in AMS 0.35 μm CMOS technology with integrated photodiodes. An error-free VLC link with a bit error rate (BER) <;10-9 is measured up to 1.8 Gb/s and a VLC-compliant BER below 10-3 is measured up to 2.5 Gb/s with on-off-keying modulation over 12 m link distance. To our knowledge, this is the first reported IC receiver-based VLC link in the Gb/s range.
Autors: Bassem Fahs;Asif Jahangir Chowdhury;Mona Mostafa Hella;
Appeared in: Journal of Lightwave Technology
Publication date: Aug 2016, volume: 34, issue:16, pages: 3768 - 3775
Publisher: IEEE
 
» A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator
Abstract:
Binary image descriptors, which derive image feature description from the local image patches directly, are widely adopted in the mobile and embedded applications due to lower computational complexity and memory requirement. With the aim of improving the computation efficiency without degrading recognition performance, a lightweight binary robust descriptor is proposed based on the analysis of the state-of-the-art binary descriptors in this paper. A directional edge detection and optimized keypoint score function are developed to refine the keypoints. In addition, rotation invariance is achieved by executing circular symmetric-based descriptor generation and a coarse-grained orientation calculation method concurrently. The experimental results demonstrate that the proposed keypoint detector and binary descriptor achieve more than two times speedup and at least 23.6% improvement in processing speed with comparable performance, respectively. Furthermore, a very large scale integration architecture is also designed based on in-depth exploration of bit-level and task-level parallelism. Based on the postlayout simulation in a TSMC 65-nm CMOS process, the accelerator can achieve 135 frames/s on 1080p image while only consuming 87.5 mW at a 200-MHz operating frequency.
Autors: Zhu, W.;Liu, L.;Jiang, G.;Yin, S.;Wei, S.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Aug 2016, volume: 26, issue:8, pages: 1532 - 1543
Publisher: IEEE
 
» A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider
Abstract:
Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit (FoMJ) that quantifies the power-jitter tradeoff is at least 25 dB worse than their LC-oscillator-based FNPLL counterparts. This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. Fabricated in 65 nm CMOS process, the proposed FNPLL operates over a wide frequency range of 2.0-5.5 GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9 psrms integrated jitter while consuming only 4 mW at 5 GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1 MHz offset. The proposed FNPLL achieves wide BW up to 6 MHz using a 50 MHz reference and its FoMJ is -228.5 dB, which is the best among all reported ring-based FNPLLs.
Autors: Ahmed Elkholy;Saurabh Saxena;Romesh Kumar Nandwana;Amr Elshazly;Pavan Kumar Hanumolu;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2016, volume: 51, issue:8, pages: 1771 - 1784
Publisher: IEEE
 
» A 2016 National Radio Science Conference of Firsts in Upper Egypt [Meeting Reports]
Abstract:
Presents informaiton on the 2016 National Radio Science Conference.
Autors: Said E. El-Khamy;Mahmoud El-Hadidi;
Appeared in: IEEE Antennas and Propagation Magazine
Publication date: Aug 2016, volume: 58, issue:4, pages: 14 - 16
Publisher: IEEE
 
» A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector
Abstract:
This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW.
Autors: Lee, D.;Lee, T.;Kim, Young-Ju;Kim, Lee-Sup;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2016, volume: 63, issue:8, pages: 733 - 737
Publisher: IEEE
 
» A 3-D Micromechanical Multi-Loop Magnetometer Driven Off-Resonance by an On-Chip Resonator
Abstract:
This paper presents the principle and complete characterization of a single-chip unit formed by microelectromechanical system magnetometers to sense the 3-D magnetic field vector and a Tang resonator. The three sensors, nominally with the same resonance frequency, are operated 200-Hz off-resonance through an ac current whose reference frequency is provided by the resonator embedded in an oscillating circuit. The sensors gain is increased by adopting a current recirculation strategy using metal strips directly deposited on the structural polysilicon. At a driving value of 100 μArms flowing in series through the three devices, the magnetometers show a sub-185 nT/√Hz resolution with a selectable bandwidth up to 50 Hz. Over a ±5-mT full-scale range, the sensitivity curves show linearity errors lower than 0.2%, with high cross-axis rejection and immunity to external accelerations. Under temperature changes, the stability of the 200-Hz difference between the magnetometers and the resonator frequency is within 55 ppm/K. Offset is trimmed down to the microtesla range, with an overall measured Allan stability of about 100 nT at 20-s observation time.
Autors: Giacomo Laghi;Cristiano R. Marra;Paolo Minotti;Alessandro Tocchio;Giacomo Langfelder;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Aug 2016, volume: 25, issue:4, pages: 637 - 651
Publisher: IEEE
 
» A 40-Gb/s 211-1 PRBS With Distributed Clocking and a Trigger Countdown Output
Abstract:
A 211-1 pseudo-random binary sequence (PRBS) generator with trigger synchronization output (9.77-MHz rate) is implemented using synthetic transmission lines for the clock distribution. The full-rate data sequence is sourced from a 2:1 multiplex of dual shift register outputs synchronized to a half-rate clock. Quadrature half-rate clocks generated by a dual-mode (Dynastat) divide-by-2 are distributed via the synthetic lines to optimize power–speed tradeoffs in the design. The PRBS designed in 130-nm SiGe BiCMOS (200/280 GHz ) consumes 250 mA at 2.5 V (i.e., 625 mW).
Autors: Vera, L.;Long, J.R.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2016, volume: 63, issue:8, pages: 758 - 762
Publisher: IEEE
 
» A 50–60 GHz mm-Wave Rectifier With Bulk Voltage Bias in 65-nm CMOS
Abstract:
This letter presents a 50~60 GHz fully integrated 3-stage rectifier with bulk voltage bias for threshold voltage modulation in a 65-nm CMOS technology, which can be integrated in a mm-wave hybrid rectifier structure as the main rectifier. In this letter, the new technique of bulk voltage bias is proposed and implemented. In this method, the threshold voltage of MOSFETs in the main rectifier is modulated by biasing their bulk voltage, which improves the rectifier sensitivity and efficiency. Compared to the inductor peaking method [1] or local threshold voltage modulation technique [2] in CMOS technology, the circuit proposed in this letter achieves better sensitivity and efficiency while maintaining a compact size. The work achieves -10 dBm input sensitivity at 52 GHz with 1 V DC output voltage. The maximum efficiency at 52 GHz is 13%. The overall sensitivity over the 50~60 GHz band is better than -5 dBm.
Autors: Hao Gao;Marion Matters-Kammerer;Pieter Harpe;Peter Baltus;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2016, volume: 26, issue:8, pages: 631 - 633
Publisher: IEEE
 
» A 500-MHz, 0.76-W/mm Power Density and 76.2% Power Efficiency, Fully Integrated Digital Buck Converter in 65-nm CMOS
Abstract:
In this paper, we propose a 500-MHz ON-chip digitally controlled buck converter in which active and passive components are fully integrated on a single CMOS chip. To achieve high-power density, a two-phase interleaving buck converter with negatively coupled inductors is adopted to reduce the silicon area for both inductors and output capacitors. In addition, the proposed ON-chip stacked L/C structure can achieve 20% area saving. Furthermore, to support a 500-Hz switching frequency, we present a low-power digital pulsewidth modulation (PWM) controller that includes a 9-bit time-based analog-to-digital converter and a 15%-90% wide-range digital pulsewidth modulator (DPWM), which occupies only 0.075 mm2 and dissipation of 3 mW. The prototype IC fabricated in 65-nm CMOS can convert a 2.2-V input to a 1.2-V output and achieve a peak power efficiency of 76.2% and maximum power density of 0.76 W/mm2. Simultaneously, it can deliver 0.84 W and occupy 1.1 mm2 of effective area that includes a pair of 1.54-nH ON-chip inductors and 2.63-nF ON-chip capacitors.
Autors: Minbok Lee;Yunju Choi;Jaeha Kim;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Aug 2016, volume: 52, issue:4, pages: 3315 - 3323
Publisher: IEEE
 
» A 540- Duty Controlled RSSI With Current Reusing Technique for Human Body Communication
Abstract:
An ultra-low-power duty controlled received signal strength indicator (RSSI) is implemented for human body communication (HBC) in 180 nm CMOS technology under 1.5 V supply. The proposed RSSI adopted 3 following key features for low-power consumption; 1) current reusing technique (CR-RSSI) with replica bias circuit and calibration unit, 2) duty controller, and 3) reconfigurable gm-boosting LNA. The CR-RSSI utilizes stacked amplifier-rectifier-cell (AR-cell) to reuse the supply current of each blocks. As a result, the power consumption becomes 540 μW with +/-2 dB accuracy and 75 dB dynamic range. The replica bias circuit and calibration unit are adopted to increase the reliability of CR-RSSI. In addition, the duty controller turns off the RSSI when it is not required, and this function leads 70% power reduction. At last, the gm-boosting reconfigurable LNA can adaptively vary its noise and linearity performance with respect to input signal strength. Fro current reusing technique m this feature, we achieve 62% power reduction in the LNA. Thanks to these schemes, compared to the previous works, we can save 70% of power in RSSI and LNA.
Autors: Jaeeun Jang;Yongsu Lee;Hyunwoo Cho;Hoi-Jun Yoo;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Aug 2016, volume: 10, issue:4, pages: 893 - 901
Publisher: IEEE
 
» A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator
Abstract:
This paper presents a continuous-time (CT) delta-sigma modulator using a Gm-C based noise-shaped integrating quantizer (NSIQ) with a digital back-end integrator. By incorporating the digital back-end integrator, the tradeoff between resolution and speed for a conventional time-based NSIQ is alleviated. Using only three clock edges and a low-power Gm-C, effective 4-bit quantization with an additional first order noise-shaping is achieved. Also, the linearity requirement of the quantizer is relaxed by employing the digital back-end integrator. The proposed modulator was fabricated in a 0.13 CMOS process with an active area of 0.08 . It operates at 640 MHz and achieves a peak SNDR of 75.3 dB and a peak SFDR of 94.1 dB in a 10 MHz bandwidth while consuming 7.2 mW from a 1.2 V power supply.
Autors: Taewook Kim;Changsok Han;Nima Maghari;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2016, volume: 51, issue:8, pages: 1840 - 1850
Publisher: IEEE
 
» A -Gb/s 1.12- Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels
Abstract:
A -Gb/s reference-less receiver is proposed in a 0.13- CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12- locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 , and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.
Autors: Song, J.;Hwang, S.;Kim, C.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Aug 2016, volume: 24, issue:8, pages: 2768 - 2777
Publisher: IEEE
 
» A -Gb/s 1.12- Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels
Abstract:
A 4×5-Gb/s reference-less receiver is proposed in a 0.13-μm CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12-μs locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 psrms, and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.
Autors: Song, J.;Hwang, S.;Kim, C.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Aug 2016, volume: 24, issue:8, pages: 2768 - 2777
Publisher: IEEE
 
» A Bi-Level Program for the Planning of an Islanded Microgrid Including CAES
Abstract:
Compressed air energy storage (CAES) can mitigate fluctuations of renewable-energy output due to its large-scale storage capacities, high ramp rate, and quick start-up time. It has become a novel choice for energy storage in microgrids. An islanded microgrid, which consists of wind turbines (WTs), photovoltaic (PV) array, diesel generators, and CAES, is investigated in this paper. The constant-pressure CAES is modeled in terms of its power capacity and energy capacity. A bi-level program (BLP) is proposed for the microgrid planning problem. It considers optimization of operation at the design stage of microgrids. The sizing problem is formulated on the upper level (UL), while the unit commitment (UC) problem with spinning-reserve requirement for the microgrid is described on the lower level (LL). The effectiveness of the approach is validated by case studies where the proposed methodology is compared to other similar ones.
Autors: Jun Zhang;Ke-Jun Li;Mingqiang Wang;Wei-Jen Lee;Hongxia Gao;Chenghui Zhang;Ke Li;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Aug 2016, volume: 52, issue:4, pages: 2768 - 2777
Publisher: IEEE
 
» A Bioimpedance Analysis Platform for Amputee Residual Limb Assessment
Abstract:
Objective: The objective of this research was to develop a bioimpedance platform for monitoring fluid volume in residual limbs of people with trans-tibial limb loss using prostheses. Methods: A customized multifrequency current stimulus profile was sent to thin flat electrodes positioned on the thigh and distal residual limb. The applied current signal and sensed voltage signals from four pairs of electrodes located on the anterior and posterior surfaces were demodulated into resistive and reactive components. An established electrical model (Cole) and segmental limb geometry model were used to convert results to extracellular and intracellular fluid volumes. Bench tests and testing on amputee participants were conducted to optimize the stimulus profile and electrode design and layout. Results: The proximal current injection electrode needed to be at least 25 cm from the proximal voltage sensing electrode. A thin layer of hydrogel needed to be present during testing to ensure good electrical coupling. Using a burst duration of 2.0 ms, intermission interval of 100 μs, and sampling delay of 10 μs at each of 24 frequencies except 5 kHz, which required a 200-μs sampling delay, the system achieved a sampling rate of 19.7 Hz. Conclusion: The designed bioimpedance platform allowed system settings and electrode layouts and positions to be optimized for amputee limb fluid volume measurement. Significance: The system will be useful toward identifying and ranking prosthetic design features and participant characteristics that impact residual limb fluid volume.
Autors: Sanders, J.E.;Moehring, M.;Rothlisberger, T.;Phillips, R.;Hartley, T.;Dietrich, C.;Redd, C.B.;Gardner, D.W.;Cagle, J.C.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Aug 2016, volume: 63, issue:8, pages: 1760 - 1770
Publisher: IEEE
 
» A Bistable Comb-Drive Electrostatic Actuator Biased by the Built-In Potential of Potassium Ion Electret
Abstract:
A new bistable micro-electro-mechanical systems actuator functioned by the potassium ion electret technique is presented. We utilize a three-terminal comb-drive actuator with a built-in electret potential. We first describe the operation principle of the bistable device that is driven by a pulse and/or step-function voltage. We next explain the fabrication results and the procedure of the electret polarization. Device operation is demonstrated to determine the switching characteristics from one stable state to another with a 12 V pulse voltage of 300 μs duration. We also establish bistable switching operation with a step voltage of 5 V or less, which is manageable by a battery for portable equipment. Discrepancy of switching characteristics between the theory and the experiments is discussed from a point of view on the fringe electrical fields between the comb electrodes.
Autors: Masato Suzuki;Hisayuki Ashizawa;Yasuhide Fujita;Hiroyuki Mitsuya;Tatsuhiko Sugiyama;Manabu Ataka;Hiroshi Toshiyoshi;Gen Hashiguchi;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Aug 2016, volume: 25, issue:4, pages: 652 - 661
Publisher: IEEE
 
» A Bounded Model of the Communication Delay for System Integrity Protection Schemes
Abstract:
This paper investigates the latency of system integrity protection schemes (SIPSs) and proposes a bounded model of the communication delay. To be specific, SIPSs can be divided into wide-area protection and substation-area protection. For the former, the data buffering of phasor data concentrators and the automatic protection switching of synchronous optical network/synchronous digital hierarchy are utilized to limit the latency of regional and backbone networks, respectively; then, the communication delay is modeled as bounded, instead of average or stochastic in the literature. For the latter, the network calculus theory is used to restrict the latency in switched Ethernet networks, and the communication delay is modeled as bounded. In practice, SIPSs need to preprogram the time delay of protective relays and expect the communication delay as predictable or predetermined. Hence, the proposed bounded model is more realistic than the average or stochastic model. Further, the bounded model suggests the network dynamics and worst-case performances. It can be a useful tool in the relay setting as well as in the planning, design, and assessment of SIPS networks.
Autors: Huang, C.;Li, F.;Ding, T.;Jiang, Y.;Guo, J.;Liu, Y.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Aug 2016, volume: 31, issue:4, pages: 1921 - 1933
Publisher: IEEE
 
» A Broadband Active Quasi Circulator for UHF and L Band Applications
Abstract:
This letter presents a compact, broadband three-port MMIC-based quasi circulator for UHF and L bands. As a motivation and application, the use of this circuit in a network analyzer is presented. The circuit is designed using differential amplifier and lossy broadband combiner to obtain effective phase cancellation for high directivity. The designed quasi circulator has return losses at all ports better than 10 dB and reverse isolation above 30 dB in the frequency range from 0.2 to 2.5 GHz. The quasi circulator has directivity of 15 to 52 dB and load dynamic range of 10 to 49 dB, over the 0.2 to 1.7 GHz band. The proposed circuit thus can be used in portable network analyzers and other applications designed for the UHF and L bands.
Autors: Debapratim Ghosh;Girish Kumar;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2016, volume: 26, issue:8, pages: 601 - 603
Publisher: IEEE
 
» A Cable-Suspended Intelligent Crane Assist Device for the Intuitive Manipulation of Large Payloads
Abstract:
This paper presents a cable-suspended crane system to assist operators in moving and lifting large payloads. The main objective of this work is to develop a simple and reliable system to help operators in industry to be more productive while preventing injuries. The system is based on the development of a precise and reliable cable angle sensor and a complete dynamic model of the system. Adaptive horizontal and vertical controllers designed for direct physical human-robot interaction are then proposed. Different techniques are then proposed to estimate the payload acceleration in order to increase the controller performances. Finally, experiments performed on a full-scale industrial system are presented.
Autors: Campeau-Lecours, A.;Foucault, S.;Laliberte, T.;Mayer-St-Onge, B.;Gosselin, C.;
Appeared in: IEEE/ASME Transactions on Mechatronics
Publication date: Aug 2016, volume: 21, issue:4, pages: 2073 - 2084
Publisher: IEEE
 
» A Characterization of the Minimal Average Data Rate That Guarantees a Given Closed-Loop Performance Level
Abstract:
This paper studies networked control systems closed over noiseless digital channels. We focus on noisy linear time-invariant (LTI) plants with stationary Gaussian disturbances, Gaussian initial state, scalar-valued control inputs and sensor outputs. For this set-up, we show that the absolute minimal directed information rate that allows one to achieve a prescribed level of performance (not necessarily stationary), over all combinations of encoder-controller-decoder, is achieved when the decoder output is jointly Gaussian with the other signals in the system. This directed information rate lower bounds the achievable operational data rates. When restricting our attention to encoder-controller-decoders which make the random processes in the loop (strongly) asymptotically wide-sense stationary, this bound can be expressed in terms of their asymptotic power spectral densities. Then we show that the directed information rate and stationary performance of any such scheme can be achieved when the concatenated encoder, channel, controller and decoder behave as an AWGN channel with LTI filters. We also present a simple coding scheme that allows one to achieve (operational) average data rates that are at most (approximately) 1.254 bits away from the derived lower bound, while satisfying the performance constraint. A numerical example is presented to illustrate our findings.
Autors: Silva, E.I.;Derpich, M.S.;Ostergaard, J.;Encina, M.A.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Aug 2016, volume: 61, issue:8, pages: 2171 - 2186
Publisher: IEEE
 
» A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design
Abstract:
This paper presents a novel charge-recycling SRAM assist circuit to reduce the dynamic power consumption of SRAM assist technique. By collaboratively combining the read and write assist schemes, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist technique. In order to compare the dynamic power consumption at ISO minimum operating voltage (VMIN) condition, the most probable failure point (MPFP) simulations are performed using 14 nm FinFET technology model. Compared to the conventional assist schemes, thanks to the charge-recycling, 41% power saving, and 2.3% area reduction can be achieved by using the proposed SRAM assist circuit.
Autors: Woong Choi;Jongsun Park;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2016, volume: 63, issue:8, pages: 1164 - 1175
Publisher: IEEE
 
» A Class of Binary Locally Repairable Codes
Abstract:
An (n, k) erasure code that can recover any coded symbol by at most r other coded symbols is called a locally repairable code (LRC) with locality r. LRCs have been recently implemented in distributed storage systems. Coding complexity reduction can be significantly decreased by using binary LRCs (BLRCs) as they eliminate costly multiplication calculation. In this paper, motivated by the recently erasure codes with d = 4 used in practice, we propose BLRCs when (r + 1) | n and d = 4. We prove that our proposed binary codes are optimal for r ∈ {1, 3}, meaning that neither their locality nor their minimum distance can be improved by non-binary codes. For r ≥ 4, our proposed binary codes offer near-optimal code rate, with a rate gap of O(log r/n) compared with optimal nonbinary codes. While keeping the bulk of code structure binary, we eliminate this rate gap by using fields with sizes as small as r + 2 for only two redundant symbols. These non-binary codes still eliminate the need for costly multiplications in many operations including a single failure repair (a dominant repair scenario). Using the construction of spanning BLRC with d = 4 as a backbone, we also construct LRCs with minimum distance d ≥ 6. Furthermore, we obtain a closed-form equation for the mean-time to data-loss of arbitrary erasure codes.
Autors: Mostafa Shahabinejad;Majid Khabbazian;Masoud Ardakani;
Appeared in: IEEE Transactions on Communications
Publication date: Aug 2016, volume: 64, issue:8, pages: 3182 - 3193
Publisher: IEEE
 
» A Closed-Form Approximate BEP Expression for Cooperative IDMA Systems over Multipath Nakagami- Fading Channels
Abstract:
In this letter, a closed-form approximate bit error probability (BEP) expression is derived for cooperative interleave-division multiple access systems with decode-and forward relaying subject to multipath Nakagami-m fading channels. The BEP expression is obtained by using the exponential-type approximation of Gaussian Q-function. Then, the derived expression is used to analyze system performance for different parameters, such as number of relays and Nakagami-m fading parameter. The accuracy of theoretical derivation is extensively validated through comprehensive computer simulations. It is shown that the results obtained by the proposed expression are in well agreement with the simulation results.
Autors: Mehmet Bilim;Nuri Kapucu;Ibrahim Develi;
Appeared in: IEEE Communications Letters
Publication date: Aug 2016, volume: 20, issue:8, pages: 1599 - 1602
Publisher: IEEE
 
» A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement
Abstract:
This paper proposes a new feed-forward equalizing (FFE) transmitter (Tx) for a massively parallel I/Os to reduce calibration circuits and to save power consumption. The proposed FFE Tx improves its robustness to a coefficient error and its power efficiency by utilizing a high-pass digital difference filter and a channel loss to attenuate the effects of the coefficient errors. To verify the proposed FFE architecture, we fabricated the conventional and the proposed FFEs in 65 nm CMOS technology and tested eye sensitivity and eye variation at 8 Gb/s on 25 dB, 13.2 dB, and 9.6 dB PCB traces. Compared to the conventional FFE Tx, the proposed FFE Tx improves the eye sensitivity and the eye variation by about 230% on a 25 dB lossy channel without calibration. In addition, this improvement increases as the channel loss increases. The proposed FFE Tx also improves the power efficiency by 230% at 25% utilization on a 25 dB lossy channel. These results imply that the proposed FFE Tx can reduce calibration circuits in a massively parallel I/Os and the power consumption.
Autors: Seungho Han;Sooeun Lee;Minsoo Choi;Jae-Yoon Sim;Hong-June Park;Byungsub Kim;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2016, volume: 51, issue:8, pages: 1902 - 1914
Publisher: IEEE
 
» A Comment on “Process Placement in Multicore Clusters: Algorithmic Issues and Practical Techniques”
Abstract:
In “Process placement in multicore clusters: Algorithmic issues and practical techniques,” Jeannot, Mercier, and Tessier presented an algorithm called TreeMatch for determining the best placement of a set of communicating processes on a hierarchically structured computing architecture, described by a tree. In order to speed up the algorithm, it was suggested to decompose levels of the tree with high arity into several levels of smaller arity. The authors conjectured what the optimal strategy for decomposition is. In this contribution, we prove that their conjecture was right.
Autors: Mann, Z.A.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Aug 2016, volume: 27, issue:8, pages: 2475 - 2476
Publisher: IEEE
 
» A Compact 57–67 GHz Bidirectional LNAPA in 65-nm CMOS Technology
Abstract:
The letter reports a 57-67 GHz bidirectional low-noise amplifier power amplifier (LNAPA) design. To eliminate the use of T/R switches, the bidirectional matching networks are introduced to connect LNA and PA core circuits in parallel and satisfy the isolation requirements with full consideration of input/output matching of the LNA and PA. Thus, the operation modes are simply selected by gate biasing of the LNA and PA core circuits. Fabricated in a commercial 65-nm CMOS technology, the Rx mode features peak gain of 21.5 dB with gain of > 17 dB over 57-67 GHz, NF of 6.7 dB with PDC of 39.6 mW, while Tx mode achieves peak gain of 24.5 dB with gain of > 17 dB over 57-65 GHz, PSAT of 8.4 dBm, PAE of 8.7% with PDC of 71.1 mW. The reverse isolation in both modes is better than 43 dB. The circuit occupies a compact size of 0.22 mm2.
Autors: Fanyi Meng;Kaixue Ma;Kiat Seng Yeo;Chirn Chye Boon;Xiang Yi;Junyi Sun;Guangyin Feng;Shanshan Xu;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2016, volume: 26, issue:8, pages: 628 - 630
Publisher: IEEE
 
» A Compact 60-GHz Wireless Power Transfer System
Abstract:
The first reported full-system 60-GHz wireless power transfer (WPT) solution that can power batteryless and charge coil-free compact WPT devices is presented. The system is fabricated in a 40-nm digital CMOS process and an inexpensive packaging material. In the rectenna (RX), a grid antenna is integrated with a complementary cross-coupled oscillator-like rectifier. At a 4-cm spacing from the transmitter (TX), the RX harvests energy at a rate of 1.22 mW with a 32.8% efficiency, which is significantly higher than the prior state of the art. A novel theoretical analysis of the rectifier operation is presented that formulates all key specifications. The TX is equipped with a quad-core PA that produces a saturated output power (Psat) of 24.6 dBm, which is the highest power delivery in digital CMOS at millimeter-wave bands. The TX peak power-added efficiency is 9.4%. In the TX, a 4 × 8-way differential power combining and a binary-tree architecture are implemented. The designed 2 × 2 grid array antenna helps the TX produce 35.3-dBm peak equivalent isotropically radiated power. The results of the performance characterizations of the full-system and all individually fabricated blocks are reported. The quadcore PA supports power control and beam steering. A four-port TX antenna is designed that shows a 70° steering range in simulations.
Autors: Med Nariman;Farid Shirinfar;Anna Papió Toda;Sudhakar Pamarti;Ahmadreza Rofougaran;Franco De Flaviis;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Aug 2016, volume: 64, issue:8, pages: 2664 - 2677
Publisher: IEEE
 
» A Compact Filtering Dielectric Resonator Antenna With Wide Bandwidth and High Gain
Abstract:
A rectangular filtering dielectric resonator antenna (FDRA) with low profile, wide bandwidth, and high gain is first investigated in this communication. It is fed by a microstrip-coupled slot from bottom, with open stub of the microstrip feedline elaborately designed to provide two radiation nulls at band edges for a filtering function. A separation is introduced in the slot to provide a good suppression level in lower stopband, while two parasitic strips are parallelly added to the microstrip feedline to offer good suppression in the upper stopband, and consequently, a compact FDRA with a quasi-elliptic bandpass response is obtained without involving specific filtering circuits. Based on the design, a modified DRA fed by a pair of separated slots is proposed to further enhance the gain by ~4 dB. A prototype operating at 5 GHz has been fabricated and measured for demonstration. The reflection coefficient, the radiation pattern, and the antenna gain are studied, and reasonable agreement between the measured and simulated results is observed. The prototype has a 10-dB impedance bandwidth of 20.3%, an average gain of 9.05 dBi within passband, and an out-of-band suppression level of more than 25 dB within a wide stopband.
Autors: P. F. Hu;Y. M. Pan;X. Y. Zhang;S. Y. Zheng;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2016, volume: 64, issue:8, pages: 3645 - 3651
Publisher: IEEE
 
» A Compact, Wideband Lumped-Element Wilkinson Power Divider/Combiner Using Symmetric Inductors with Embedded Capacitors
Abstract:
A compact, wideband, and low loss multi-section lumped-element Wilkinson power divider/combiner (WPDC) is reported in this letter. The cascade of four λ/16 LC π-networks for a λ/4 transformer of WPDC, realized by a symmetric inductor with an embedded capacitor technique, can achieve broadband operation and low insertion loss (IL) while saving Si die area. The measured results show a minimum IL of 0.45 dB at 10 GHz. In addition, the IL lower than 1 dB, the isolation (ISO) better than 10 dB, and return losses (RL) higher than 10 dB are satisfied from 5.2 GHz to 18.8 GHz, demonstrating the proposed scheme is applicable to wideband operation. The measured amplitude and phase error are within 0.06 dB and 1.0 degree from DC to 20 GHz, respectively. The core chip size is 0.32 × 0.34 mm2. To the authors' best knowledge, the proposed WPDC shows the lowest IL and widest band operational capability for all published Si-based WPDCs, and thus proves useful for low-cost, highly-integrated phased array and wireless communications systems.
Autors: Inchan Ju;Moon-Kyu Cho;Ickhyun Song;John D. Cressler;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2016, volume: 26, issue:8, pages: 595 - 597
Publisher: IEEE
 
» A Comparative Study of Output Metrics for an MEMS Resonant Sensor Consisting of Three Weakly Coupled Resonators
Abstract:
This paper systematically investigates the characteristics of different output metrics for a weakly coupled three degree-of-freedom microelectromechanical systems resonant sensor. The key figures-of-merit examined are sensitivity and linear range. The four main output metrics investigated are mode frequency shift, amplitude difference, amplitude ratio, and eigenstate shift. It is shown from theoretical considerations, equivalent RLC circuit model simulations and electrical measurements, that there is a strong tradeoff between sensitivity and linear range. For instance, the amplitude difference has the best sensitivity but the worst linear range, whereas frequency shift has the widest linear range but the lowest sensitivity. We also show that using the vibrational amplitude ratio as an output metric provides the best balance between sensitivity and linear range. [2016-0077].
Autors: Chun Zhao;Graham S. Wood;Jianbing Xie;Honglong Chang;Suan Hui Pu;Michael Kraft;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Aug 2016, volume: 25, issue:4, pages: 626 - 636
Publisher: IEEE
 
» A Comparison of Health Visualization Evaluation Techniques with Older Adults
Abstract:
Aging-associated changes in visual acuity, cognition, and motor control in addition to attitudinal and affective perceptions of technology impact the design of information systems for older adults. Although design guidelines and cognitive theories on information visualization exist, they are often understudied for use with older adults. In an effort to evaluate interactive health visualizations with older adults, the authors applied and compared a benchmark evaluation, an insight-based evaluation, and a subjective usability questionnaire. They were unable to identify statistically significant differences between visualizations using the benchmark evaluation, but found moderate differences with the perceived usability scale and more granular differences through the insight evaluation.
Autors: Le, T.;Thompson, H.;Demiris, G.;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Aug 2016, volume: 36, issue:4, pages: 67 - 77
Publisher: IEEE
 
» A Comparison of LQR Optimal Performance in the Decentralized and Centralized Settings
Abstract:
Here we consider the problem of LQR optimal control in the context of decentralized systems. It has been proven that if the system is centrally controllable and observable and the graph associated with the system is strongly connected, then there exists a linear periodic controller which provide LQR performance as close as desired to the optimal centralized performance. Here we demonstrate, via an example, that if the strongly connected assumption is violated then the optimal decentralized performance can be arbitrarily bad in comparison to the optimal centralized performance.
Autors: Miller, D.E.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Aug 2016, volume: 61, issue:8, pages: 2308 - 2311
Publisher: IEEE
 
» A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability
Abstract:
Reconfigurable digital filter is being widely used in applications such as communication and signal processing. Its performance, power consumption, and logic resource utilization are the major factors to be taken into consideration when designing the filters. This paper proposes a concise canonic signed digit coefficient grouping method aiming at reducing the number of common subexpressions (CSs). Further, we statistically analyze every CS occurance for numerous sorts of the finite-impulse response (FIR) filters and obtain characterization of the distribution behavior for all the possible CS patterns in a 16-bit coefficient. Thus, a novel processing element structure is proposed to form a medium-grain array for computationally efficient realization of reconfigurable FIR filter. The experiment results suggest such design implementations typically achieve 21% reduction in silicon area, 20% decrease in power consumption, and 14% improvement in operation speed in comparison to other conventional FIR architectures.
Autors: Jia, R.;Yang, H.;Lin, Y.;Chen, R.;Wang, X.;Guo, Z.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Aug 2016, volume: 35, issue:8, pages: 1297 - 1308
Publisher: IEEE
 
» A Continuous Wavelet Transform Based Time Delay Estimation Method for Long Range Fiber Interferometric Vibration Sensor
Abstract:
We propose a time delay estimation (TDE) method based on a continuous wavelet transform (CWT), which can be applied to the different-wavelength-based fiber interferometric vibration sensors. Using a CWT-based characteristic extraction algorithm, we successfully eliminate the asymmetry of the interference outputs that would seriously deteriorate the positioning accuracy of the sensor. A positioning measurement experiment using an asymmetric dual Mach-Zehnder interferometric sensor was carried out to verify the effectiveness of the proposed method. The experiment achieved a positioning accuracy of 0.029% at the sensing length of 85 km, with a mean processing time of 591.2 ms.
Autors: Chunyu Ma;Tiegen Liu;Kun Liu;Junfeng Jiang;Zhenyang Ding;Xiangdong Huang;Liang Pan;Miao Tian;Zhichen Li;
Appeared in: Journal of Lightwave Technology
Publication date: Aug 2016, volume: 34, issue:16, pages: 3785 - 3789
Publisher: IEEE
 
» A Contract-Based Incentive Mechanism for Delayed Traffic Offloading in Cellular Networks
Abstract:
Delayed traffic offloading is a promising paradigm to alleviate the cellular network congestion caused by explosive traffic demands. As we all know, in mobile networks, the delay profile for traffic is remarkable due to users' mobility. How to exploit user delay tolerance to improve the profit of operator as well as mobile users becomes a big challenge. In this paper, we model this delayed offloading process as a monopoly market based on contract theory, where operator acts as the monopolist setting up the optimal contract by statistical information on user satisfaction. We propose an incentive mechanism to motivate users to leverage their delay and price sensitivity in exchange for service cost. To capture the heterogeneity of user satisfaction, we classify users into different types. Each user chooses a proper quality-price contract item according to its type. More specifically, we investigate this delayed offloading scheme under strongly incomplete information scenario, where user type is private information. We derive an optimal contract, which maximizes operator's profit for both the continuous-user-type model and the discrete-user-type model. Numerical results validate the effectiveness of our incentive mechanism for delayed traffic offloading in cellular networks.
Autors: Yuqing Li;Jinbei Zhang;Xiaoying Gan;Luoyi Fu;Hui Yu;Xinbing Wang;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Aug 2016, volume: 15, issue:8, pages: 5314 - 5327
Publisher: IEEE
 
» A control plane architecture for multi-domain elastic optical networks: the view of the IDEALIST project
Abstract:
A key objective of the IDEALIST project included the design and implementation of a GMPLS and PCE-based control plane for multi-vendor and multi-domain flexi-grid EON, leveraging the project advances in optical switching and transmission technology, an enabling interoperable deployment. A control plane, relying on a set of entities, interfaces, and protocols, provides the automation of the provisioning, recovery, and monitoring of end-to-end optical connections. This article provides an overview of the implemented architecture. We present the macroscopic system along with the core functional blocks, control procedures, message flows, and protocol extensions. The implemented end-toend architecture adopted active stateful hierarchical PCE, under the control and orchestration of an adaptive network manager, interacting with a parent PCE, which first coordinates the selection of domains and the end-to-end provisioning using an abstracted view of the topology, and second, delegates the actual computation and intra-domain provisioning to the corresponding children PCEs. End-to-end connectivity is obtained by either a single LSP, or by the concatenation of multiple LSP segments, which are set up independently by the underlying GMPLS control plane at each domain. The architecture and protocol extensions have been implemented by several partners, assessing interoperability in a multi-partner testbed and adoption by the relevant Internet SDO (standards development organization).
Autors: Ramon Casellas;Oscar Gonzalez;Francesco Paolucci;Roberto Morro;Victor Lopez;Daniel King;Ricardo Martinez;Filippo Cugini;Ral Munoz;Adrian Farrel;Ricard Vilalta;Juan-Pedro Fernandez-Palacios;
Appeared in: IEEE Communications Magazine
Publication date: Aug 2016, volume: 54, issue:8, pages: 136 - 143
Publisher: IEEE
 
» A Decision Framework to Mitigate Supply Chain Risks: An Application in the Offshore-Wind Industry
Abstract:
Decision support systems (DSSs) for supply chain risk management benefit from a holistic approach for mitigating risks, which include identification and assessment of risks and evaluation and selection of measures to appease risks. However, previous studies in this area overlooked probability estimation, measure selection, and assessment of interdependence of risks and measures. We aim to fill these gaps in the literature by proposing a two-stage DSSs that will assist managers in not only select mitigation strategies for supply chain risks, but also mitigation tactics when risks occur. Our DSS employs a novel matrix formulation for decision-tree analysis, which integrates expert judgments. We applied our models to the supply chain of a fast-expanding offshore-wind industry, which faces high levels of exposure to risks because of the associated complexities in this domain. The results demonstrate how to select mitigation strategies and mitigation tactics for managing supply chain risks within the offshore-wind industry.
Autors: Riccardo Mogre;Srinivas (Sri) Talluri;Federico D'Amico;
Appeared in: IEEE Transactions on Engineering Management
Publication date: Aug 2016, volume: 63, issue:3, pages: 316 - 325
Publisher: IEEE
 
» A Decomposition Method for the Total Leakage Current of MOA Based on Multiple Linear Regression
Abstract:
A new current decomposition method based on multiple linear regression is presented. The time-domain equations of every current component on the applied voltage are deduced based on an improved equivalent model of the metal–oxide surge arrester (MOA). The capacitive current compensation method and the proposed method are used to decompose the total leakage current and to study the influence of the nonlinearity of MOA model, third harmonic voltage, and white noise on the decomposition accuracy. The simulation results show that the proposed method can exactly decompose the resistive current and the capacitive current if the applied voltage and the total leakage current are noiseless. The proposed method is more accurate than the capacitive current compensation method. The total leakage current of an MOA varistor is measured and is then decomposed by both methods. The experimental results verify the effectiveness of the proposed method.
Autors: Han, Y.;Li, Z.;Zheng, H.;Guo, W.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Aug 2016, volume: 31, issue:4, pages: 1422 - 1428
Publisher: IEEE
 
» A Design Approach for Tapered Waveguide to Substrate-Integrated Waveguide Transitions
Abstract:
A design approach for substrate-integrated waveguide (SIW) to rectangular waveguide (RWG) transitions based on the synthesis of antipodal finline tapers is proposed. The taper is designed using a reflection-based impedance definition as no suitable model is available for antipodal finlines. The characteristics of the finline are determined from full-wave simulation. To demonstrate the proposed method, two SIW-to-RWG transitions are designed and characterized at the K-band. The measured back-to-back transitions exhibit a return loss above 15 dB and an insertion loss below 1 dB between 16.7 and 20.5 GHz and between 21.1 and more than 31 GHz, respectively. A good agreement between the synthesis model and full-wave simulation of the taper on one hand and between simulation and measurements of back-to-back transitions on the other hand is demonstrated.
Autors: Christian Rave;Arne F. Jacob;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Aug 2016, volume: 64, issue:8, pages: 2502 - 2510
Publisher: IEEE
 
» A Differential-Fed UWB Antenna Element With Unidirectional Radiation
Abstract:
A new differential-fed broadband antenna element with unidirectional radiation is proposed. This antenna is composed of a folded bowtie, a center-fed loop, and a box-shaped reflector. A pair of differential feeds is developed to excite the antenna and provide an ultrawideband (UWB) impedance matching. The box-shaped reflector is used for the reduction of the gain fluctuation across the operating frequency band. An antenna prototype for UWB applications is fabricated and measured, exhibiting an impedance bandwidth of 132% with standing wave ratio ≤ 2 from 2.48 to 12.12 GHz, over which the gain varies between 7.2 and 14.1 dBi at boresight. The proposed antenna radiates unidirectionally with low cross polarization and low back radiation. Furthermore, the time-domain characteristic of the proposed antenna is evaluated. In addition, a 2 × 2 element array using the proposed element is also investigated in this communication.
Autors: Mingjian Li;Kwai-Man Luk;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2016, volume: 64, issue:8, pages: 3651 - 3656
Publisher: IEEE
 
» A Disparity-Based Adaptive Multihomography Method for Moving Target Detection Based on Global Motion Compensation
Abstract:
Moving target detection is an important technique in visual surveillance systems. If a camera is freely moving, it becomes more difficult to detect a moving target, especially in the environment of a wide-range background. To compensate for the global motion of a wide-range background, a disparity-based adaptive multi-homography method is proposed. The proposed method comprises four steps: 1) feature point extraction; 2) generation of adaptive multi-homography matrices using motion grouping; 3) generation of background model and detection of background; and 4) target detection. Experimental results show that the proposed method can robustly detect moving targets in sequences taken by a freely moving camera.
Autors: Kim, S.;Yang, D.W.;Park, H.W.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Aug 2016, volume: 26, issue:8, pages: 1407 - 1420
Publisher: IEEE
 
» A Dual-Band, Inductively Coupled Miniaturized-Element Frequency Selective Surface With Higher Order Bandpass Response
Abstract:
We present a new approach for designing dual-band miniaturized-element frequency selective surfaces (MEFSSs) with independent control of the frequencies of operation of each band. The proposed device is composed of 2-D periodic arrays of subwavelength inductive wire grids and capacitive patches separated by dielectric substrates. The structure is built on an inductively coupled MEFSS that uses capacitively loaded dielectric spacers as its main resonators. The two operating bands of this MEFSS correspond to the first and second resonant frequencies of its constituting resonators. By judiciously choosing the locations where the resonators are loaded and the load values, the frequencies of the first and second resonances can be controlled individually. In this way, a dual-band MEFSS with independent frequency bands of operation can be obtained. Using the equivalent circuit model of this MEFSS, a synthesis procedure is developed that can be used to synthesize the dual-band MEFSS from its system-level performance indicators. A prototype of the proposed dual-band MEFSS with second-order bandpass response at each band is designed, fabricated, and experimentally characterized. The measurement results of this device show a stable frequency response with respect to the angle of incidence up to ±45° for both the TE and TM polarizations of incidence.
Autors: Meng Gao;Seyed Mohamad Amin Momeni Hasan Abadi;Nader Behdad;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2016, volume: 64, issue:8, pages: 3729 - 3734
Publisher: IEEE
 
» A Dual-Output Thermoelectric Energy Harvesting Interface With 86.6% Peak Efficiency at 30 and Total Control Power of 160 nW
Abstract:
A thermoelectric energy harvesting interface based on a single-inductor dual-output (SIDO) boost converter is presented. A system-level design methodology combined with ultra-low-power circuit techniques reduce the power consumption and minimize the losses within the converter. Additionally, accurate zero-current switching (ZCS) and zero-voltage switching (ZVS) techniques are employed in the control circuit to ensure high conversion efficiency at μW input power levels. The proposed SIDO boost converter is implemented in a 0.18 μm CMOS process and can operate from input voltages as low as 15 mV. The measurement results show that the converter achieves a peak conversion efficiency of 86.6% at 30 μW input power.
Autors: Janko Katic;Saul Rodriguez;Ana Rusu;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2016, volume: 51, issue:8, pages: 1928 - 1937
Publisher: IEEE
 
» A Dual-Polarized Leaky Lens Antenna for Wideband Focal Plane Arrays
Abstract:
This paper presents the design and measurements of a wideband dual polarized leaky lens antenna suitable for tightly spaced focal plane arrays. The antenna is composed of two crossed leaky slots fed by two orthogonal microstrips to realize the dual-polarization operation. The crossed microstrips are fed differentially in order to couple the radiation into the slots. The slots are then coupled to a dielectric lens to achieve directive patterns suited for feeding large Focal distance to Diameter ratio reflectors. In this paper, the proposed leaky lens antenna is optimized to achieve high aperture efficiency with clean symmetric patterns in both polarizations exceeding an octave bandwidth. The concept is validated by the measurements of the primary fields inside the lens and with GRASP simulations of the focal plane array.
Autors: Ozan Yurduseven;Nuria Llombart Juan;Andrea Neto;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2016, volume: 64, issue:8, pages: 3330 - 3337
Publisher: IEEE
 
» A Factor Graph Approach to Iterative Channel Estimation, Detection, and Decoding for Two-Path Successive Relay Networks
Abstract:
We consider cooperative communications between a source node and a destination node with the help of two relays. In order to overcome the half-duplex constraint, the amplify-and-forward two-path relaying protocol is used. We adopt orthogonal frequency-division multiplexing modulation to combat frequency-selective channels and asynchronous reception at the destination node. In this paper, we develop a coherent receiver architecture suitable for unknown block fading channels. A factor graph representing the joint a posteriori probability of the coded symbols and the channels in the frequency domain is introduced. Then, we derive a Bayesian inference algorithm based on message passing over the factor graph. The resulting iterative receiver maintains low-complexity, based on the interaction between an off-the-shelf soft-input soft-output decoder and a newly introduced per-subcarrier processor for two-path relaying channel estimation and symbol detection. Simulation results show that the proposed solution maintains the full diversity order, even with a limited number of training blocks.
Autors: Frederic Lehmann;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Aug 2016, volume: 15, issue:8, pages: 5414 - 5429
Publisher: IEEE
 
» A Fast Mechanical Switch for Medium-Voltage Hybrid DC and AC Circuit Breakers
Abstract:
This paper presents the design and experimental results of a Thomson coil-based fast mechanical switch for hybrid ac and dc circuit breakers rated at 30-kV voltage and 630-A current. The compact design with optimized circuit parameters and geometric dimensions of components targets 2-mm travel within 1 ms when driven by a 2-mF capacitor bank precharged to 500 V. The use and design of a disc spring as the damping and holding mechanism is presented. Structural design of a complete switch assembly rather than just the actuator is given. Experimental results show that the switch can travel 1.3 mm in the first 1 ms and 3.1 mm in the first 2 ms when driven by a 360-V 2-mF capacitor bank. Such fast mechanical switches facilitate hybrid circuit breaker interruptions within 2 or 3 ms for ultra-fast and highly efficient protections in 5-35 kV medium-voltage dc as well as ac systems.
Autors: Chang Peng;Iqbal Husain;Alex Q. Huang;Bruno Lequesne;Roger Briggs;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Aug 2016, volume: 52, issue:4, pages: 2911 - 2918
Publisher: IEEE
 
» A Feature-Based Framework for Developing and Provisioning Customizable Web Services
Abstract:
A customizable web service is a service that enables service consumers to dynamically determine variants of the service they receive. Provisioning customizable services helps to efficiently address functional variability in customer requirements. However, this is challenging due to: i) the complexity in deriving the right subset of service capabilities for a service variant and ii) the existence of a large number of variants and their dependencies. We propose a feature-based framework to tackle this challenge. In our framework, a feature model is used to capture functional variability in customer requirements at a high-level of abstraction and to provide customers with a much simpler way to customize an atomic service. A service engineering process is designed to facilitate the systematic identification and implementation of variability during service development, and to maintain the mapping between variabilities at the feature modeling level and the service implementation level. We define a generative middleware that supports service deployment and exploits the mapping to enable runtime service customization. A large scale case study based on the Amazon web services is used for evaluation. In addition to addressing the challenge in provisioning customizable services, our experiments show that the generative middleware helps to reduce runtime resource consumption.
Autors: Nguyen, T.;Colman, A.;Han, J.;
Appeared in: IEEE Transactions on Services Computing
Publication date: Aug 2016, volume: 9, issue:4, pages: 496 - 510
Publisher: IEEE
 
» A first look at mobile cloud storage services: architecture, experimentation, and challenges
Abstract:
Mobile cloud storage services provide users a convenient and reliable way to store and share data on mobile devices. Despite increasing popularity, little work has focused on their architecture and internal sync protocol. In this article, we present a thorough architecture of mobile cloud storage services including sync protocols and key capabilities for speeding up transmission. Furthermore, we conduct a series of experiments to evaluate the sync performance of four popular commercial mobile cloud storage services. Our results show that the concrete deployment of capabilities has a strong impact on the performance of mobile cloud storage services. There is no clear winner, with all services suffering from some limitations or having potential for improvement. We pose issues and challenges to advance the topic area, and hope to pave a way for the forthcoming.
Autors: Yong Cui;Zeqi Lai;Ningwei Dai;
Appeared in: IEEE Network
Publication date: Aug 2016, volume: 30, issue:4, pages: 16 - 21
Publisher: IEEE
 
» A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme
Abstract:
This paper proposes a fractional-N digital phase locked loop (DPLL) architecture with calibration-free multi-phase injection-locked time-to-digital converter (TDC) and gradient-based adaptive single-tone spur cancellation scheme. By using the injection-locked ring oscillator, the TDC quantization step is automatically tracked with the period of the digitally controlled oscillator (DCO) over PVT, and hence is free of calibration. The multi-phase TDC further achieves a fine resolution of 7 to 12 ps, depending on the DPLL's operating frequency. The proposed single-tone spur cancellation scheme achieves more than 40 dB spur suppression. The proof-of-concept DPLL prototype is implemented in 65 nm CMOS technology and synthesizes frequencies from 2.7 to 4.8 GHz with a 1V supply, consuming 21.2 mW. The measured in-band phase noise is -92 dBc/Hz at 40 kHz offset, the far out phase noise is -130 dBc/Hz at 3 MHz offset, with a reference spur of -86.5 dBc.
Autors: Cheng-Ru Ho;Mike Shuo-Wei Chen;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2016, volume: 63, issue:8, pages: 1111 - 1122
Publisher: IEEE
 
» A Framework of Price Bidding Configurations for Resource Usage in Cloud Computing
Abstract:
In this paper, we focus on price bidding strategies of multiple users competition for resource usage in cloud computing. We consider the problem from a game theoretic perspective and formulate it into a non-cooperative game among the multiple cloud users, in which each cloud user is informed with incomplete information of other users. For each user, we design a utility function which combines the net profit with time efficiency and try to maximize its value. We design a mechanism for the multiple users to evaluate their utilities and decide whether to use the cloud service. Furthermore, we propose a framework for each cloud user to compute an appropriate bidding price. At the beginning, by relaxing the condition that the allocated number of servers can be fractional, we prove the existence of Nash equilibrium solution set for the formulated game. Then, we propose an iterative algorithm (), which is designed to compute a Nash equilibrium solution. The convergency of the proposed algorithm is also analyzed and we find that it converges to a Nash equilibrium if several conditions are satisfied. Finally, we revise the obtained solution and propose a near-equilibrium price bidding algorithm ( ) to characterize the whole process of our proposed framework. The experimental results show that the obtained near-equilibrium solution is close to the equilibrium one.
Autors: Li, K.;Liu, C.;Li, K.;Zomaya, A.Y.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Aug 2016, volume: 27, issue:8, pages: 2168 - 2181
Publisher: IEEE
 
» A Fully Integrated Wireless Compressed Sensing Neural Signal Acquisition System for Chronic Recording and Brain Machine Interface
Abstract:
Reliable, multi-channel neural recording is critical to the neuroscience research and clinical treatment. However, most hardware development of fully integrated, multi-channel wireless neural recorders to-date, is still in the proof-of-concept stage. To be ready for practical use, the trade-offs between performance, power consumption, device size, robustness, and compatibility need to be carefully taken into account. This paper presents an optimized wireless compressed sensing neural signal recording system. The system takes advantages of both custom integrated circuits and universal compatible wireless solutions. The proposed system includes an implantable wireless system-on-chip (SoC) and an external wireless relay. The SoC integrates 16-channel low-noise neural amplifiers, programmable filters and gain stages, a SAR ADC, a real-time compressed sensing module, and a near field wireless power and data transmission link. The external relay integrates a 32 bit low-power microcontroller with Bluetooth 4.0 wireless module, a programming interface, and an inductive charging unit. The SoC achieves high signal recording quality with minimized power consumption, while reducing the risk of infection from through-skin connectors. The external relay maximizes the compatibility and programmability. The proposed compressed sensing module is highly configurable, featuring a SNDR of 9.78 dB with a compression ratio of 8×. The SoC has been fabricated in a 180 nm standard CMOS technology, occupying 2.1 mm × 0.6 mm silicon area. A pre-implantable system has been assembled to demonstrate the proposed paradigm. The developed system has been successfully used for long-term wireless neural recording in freely behaving rhesus monkey.
Autors: Xilin Liu;Milin Zhang;Tao Xiong;Andrew G. Richardson;Timothy H. Lucas;Peter S. Chin;Ralph Etienne-Cummings;Trac D. Tran;Jan Van der Spiegel;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Aug 2016, volume: 10, issue:4, pages: 874 - 883
Publisher: IEEE
 
» A Game Theoretical Incentive Scheme for Relay Selection Services in Mobile Social Networks
Abstract:
Rapid developments in mobile services and wireless technologies have prompted users to form mobile social networks (MSNs), where bundles can be delivered via opportunistic peer-to-peer links in a store–carry–forward mode. This mode needs all nodes to work in a cooperative way. However, mobile nodes may be selfish and might not be willing to forward data to others due to the limited resources (e.g., buffer and energy), resulting in degraded system performance. To tackle the aforementioned problem, this paper proposes a novel incentive scheme to stimulate selfish nodes to participate in bundle delivery in MSNs. At first, a virtual currency is introduced to pay for the relay service. Then, a bundle carrier selects a relay node from its friends or other strangers based on its status. Next, a bargain game is employed to model the transaction pricing for relay service. In addition, the simulation results show that the proposal can improve the performance of the existing schemes significantly.
Autors: Xu, Q.;Su, Z.;Guo, S.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Aug 2016, volume: 65, issue:8, pages: 6692 - 6702
Publisher: IEEE
 
» A Gamut-Mapping Framework for Color-Accurate Reproduction of HDR Images
Abstract:
Few tone mapping operators (TMOs) take color management into consideration, limiting compression to luminance values only. This could lead to changes in image chroma and hues, which are typically managed with a post-processing step. However, current post-processing techniques for tone reproduction do not explicitly consider the target display gamut. Gamut mapping, on the other hand, deals with mapping images from one color gamut to another, usually smaller, gamut but has traditionally focused on smaller scale, chromatic changes. The authors present a combined gamut- and tone-management framework for color-accurate reproduction of high dynamic range images that can prevent hue and luminance shifts while taking gamut boundaries into consideration. Their approach is conceptually and computationally simple, parameter-free, and compatible with existing TMOs.
Autors: Sikudova, E.;Pouli, T.;Artusi, A.;Akyuz, O.;Banterle, F.;Reinhard, E.;Mazlumoglu, Z.;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Aug 2016, volume: 36, issue:4, pages: 78 - 90
Publisher: IEEE
 
» A General Approach to Scalable Buffer Pool Management
Abstract:
In high-end data processing systems, such as databases, the execution concurrency level rises continuously since the introduction of multicore processors. This happens both on premises and in the cloud. For these systems, a buffer pool management of high scalability plays an important role on overall system performance. The scalability of buffer pool management is largely determined by its data replacement algorithm, which is a major component in the buffer pool management. It can seriously degrade the scalability if not designed and implemented properly. The root cause is its use of lock-protected data structures that incurs high contention with concurrent accesses. A common practice is to modify the replacement algorithm to reduce the contention on the lock(s), such as approximating the LRU replacement with the CLOCK algorithm or partitioning the data structures and using distributed locks. Unfortunately, the modification usually compromises the algorithm's hit ratio, a major performance goal. It may also involve significant effort on overhauling the original algorithm design and implementation. This paper provides a general solution to improve the scalability of a buffer pool management using any replacement algorithms for the data processing systems on physical on-premises machines and virtual machines in the cloud. Instead of making a difficult trade-off between the high hit ratio of a replacement algorithm and the low lock contention of its approximation, we design a system framework, called BP-Wrapper, that eliminates almost all lock contention without requiring any changes to an existing algorithm. In BP-Wrapper, we use a dynamic batching technique and a prefetching technique to reduce lock contention and to retain high hit ratio. The implementation of BP-Wrapper in PostgreSQL adds only about 300 lines of C code. It can increase the throughput by up to two folds compared with the replacement algorithms with lock contention when runni- g TPC-C-like and TPC-W-like workloads.
Autors: Ding, X.;Shan, J.;Jiang, S.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Aug 2016, volume: 27, issue:8, pages: 2182 - 2195
Publisher: IEEE
 
» A General Framework for Robust Output Synchronization of Heterogeneous Nonlinear Networked Systems
Abstract:
The paper aims to establish a general framework for robust output synchronization of a group of networked agents. The agents under investigation have nonlinear, uncertain and heterogeneous dynamics. Output synchronization denotes that all agents, through collaborative control, achieve output agreement and follow a desired pattern. In particular, the agreed trajectory is not defined by nor known to any agent in advance. Collaborative control is achieved using only output information from neighboring agents. Two concurrent actions are revealed in the proposed synchronization framework. This framework involves design strategies for both perturbed consensus and perturbed regulation problems, subject to a class of small gain conditions. The success of the framework is verified by constructive proof and numerical simulation.
Autors: Zhu, L.;Chen, Z.;Middleton, R.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Aug 2016, volume: 61, issue:8, pages: 2092 - 2107
Publisher: IEEE
 
» A Generalized Cross-Connected Submodule Structure for Hybrid Multilevel Converters
Abstract:
The fault-tolerant multilevel converters are gaining increased interests for high-voltage direct current (HVDC) applications due to their ability to suppress the fault current during dc-side faults. However, most of these topologies use full-bridge submodules (FBSMs) resulting in the requirement of a large number of semiconductor switches. In this paper, a new generalized cross-connected SM (GX-SM) structure is presented, which requires lesser number of switching devices and provides the same functionality as the FBSM. A comparison of the switches required in the different converter topologies using FBSMs and GX-SMs is performed. The performance evaluation of two of the dc-side fault-tolerant converter topologies, namely alternate arm modular multilevel converter (AAMMC) and hybrid cascaded modular multilevel converter (HCMC) with the GX-SM, is performed using simulation studies done in PSCAD/EMTDC. The modulation and control schemes for these GX-SMs-based converters are presented. A new mixed-SM configuration of AAMMC is proposed which utilizes an optimal combination of GX-SMs and half-bridge SMs. The study results demonstrate the effectiveness of the proposed GX-SM structure, and satisfactory responses of the GX-SMs-based AAMMC and HCMC systems controlled using the presented modulation and control strategies under various system conditions.
Autors: Ebin Cherian Mathew;Mahendra B. Ghat;Anshuman Shukla;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Aug 2016, volume: 52, issue:4, pages: 3159 - 3170
Publisher: IEEE
 
» A Global-Shutter Centroiding Measurement CMOS Image Sensor With Star Region SNR Improvement for Star Trackers
Abstract:
A star tracker is a critical sensor for determining and controlling the attitude of a satellite. It utilizes a complementary metal–oxide–semiconductor (CMOS)-active pixel sensor to map the star field onto the focal plane. Starlight is measured and star centroids are calculated to estimate attitude knowledge. In this paper, we present a CMOS image sensor for star centroid measurement in star trackers. To improve sensitivity to low-level starlight, the capacitive transimpedance amplifier pixel is used as the detector. To improve centroiding accuracy, the proposed sensor architecture allows star pixels, pixels that are above a star threshold, to cluster together. The mean value of all the pixels in this cluster is calculated. The star signals are then amplified in relation to this mean value. This increases the signal-to-noise ratio in star regions in line with their starlight intensity. An adaptive region-of-interest readout architecture is also proposed, which reports only star regions instead of the entire frame. The proof-of-concept chip, containing a pixel array, was fabricated using AMS 0.35- CMOS Opto process. Each pixel has a size of . The measurement results show that centroiding accuracy increases with higher centroiding gain. Within a limited exposure time, the relative centroiding accuracy can surpass that of a commercial image sensor by more than 1%.
Autors: Qian, X.;Yu, H.;Chen, S.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Aug 2016, volume: 26, issue:8, pages: 1555 - 1562
Publisher: IEEE
 
» A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers
Abstract:
This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 μA from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 μW of power from a 1.8 V supply and occupies 0.017 mm2 of chip area realized in a 0.18 μm standard CMOS process.
Autors: Khandaker A. Al Mamun;Syed K. Islam;Dale K. Hensley;Nicole McFarlane;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Aug 2016, volume: 10, issue:4, pages: 807 - 816
Publisher: IEEE
 
» A Graph-Based Satellite Handover Framework for LEO Satellite Communication Networks
Abstract:
This letter proposes a graph-based satellite handover framework for the low earth orbit (LEO) satellite communication networks. In order to maintain the connection with the communicating counterpart, the user has to switch between consecutive satellites covering the very user. A directed graph with covering period of the satellite as its node, and the link representing the possible handover between two overlapping periods, is calculated in advance, and then, the satellite handover process can be viewed as finding a path in the directed graph. By setting the link weight according to different handover criterions, the graph-based framework can support a variety of satellite handover strategies, which shows the improved flexibility over the existing research. The application of the framework to find the shortest handover path conducted on two typical LEO satellite networks, viz., Iridium and Globalstar, also corroborates the effectiveness of the proposed handover framework.
Autors: Zhaofeng Wu;Fenglin Jin;Jianxin Luo;Yinjin Fu;Jinsong Shan;Guyu Hu;
Appeared in: IEEE Communications Letters
Publication date: Aug 2016, volume: 20, issue:8, pages: 1547 - 1550
Publisher: IEEE
 
» A green perspective on Wi-Fi offloading
Abstract:
Due to increased energy consumption and carbon emissions of the ICT industry, operators worldwide are focusing on reducing energy consumption of their networks from the financial as well as corporate responsibility perspectives. The subject of green or energy-efficient operation of the cellular access network has attracted a lot of attention in the research community recently. In this regard, dynamically powering down radio network equipment has emerged as a promising solution. In the literature, research around such techniques has mainly focused on quantifying the energy saving potential. However, few efforts have been made toward practical realization of these energy saving concepts. On the other hand, Wi-Fi networks are undergoing a paradigm shift toward ubiquity. The main objective of this article is to provide novel mechanisms for practically realizing the concept of improving power efficiency in the cellular access network through opportunistically offloading users to Wi-Fi networks. These mechanisms are based on the principles of cognitive network management. Performance evaluation shows the potential of the proposed mechanisms as a viable solution for achieving energy efficiency in the cellular access network.
Autors: Adnan Aijaz;A. Hamid Aghvami;
Appeared in: IEEE Wireless Communications
Publication date: Aug 2016, volume: 23, issue:4, pages: 112 - 119
Publisher: IEEE
 
» A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications
Abstract:
Integrity assurance of configuration data has a significant impact on microcontroller-based systems reliability. This is especially true when running applications driven by events which behavior is tightly coupled to this kind of data. This work proposes a new hybrid technique that combines hardware and software resources for detecting and recovering soft-errors in system configuration data. Our approach is based on the utilization of a common built-in microcontroller resource (timer) that works jointly with a software-based technique, which is responsible to periodically refresh the configuration data. The experiments demonstrate that non-destructive single event effects can be effectively mitigated with reduced overheads. Results show an important increase in fault coverage for SEUs and SETs, about one order of magnitude.
Autors: Martinez-Alvarez, A.;Restrepo-Calle, F.;Cuenca-Asensi, S.;Reyneri, L.M.;Lindoso, A.;Entrena, L.;
Appeared in: IEEE Transactions on Dependable and Secure Computing
Publication date: Aug 2016, volume: 13, issue:4, pages: 502 - 508
Publisher: IEEE
 
» A Hierarchical Model Predictive Control Approach for Signal Splits Optimization in Large-Scale Urban Road Networks
Abstract:
In this paper, we propose a hierarchical model predictive control (MPC) approach for signal split optimization in large-scale urban road networks. To reduce the computational complexity, a large-scale urban road network is first divided into several subnetworks using a network decomposition method. Second, the MPC optimization problem of the large-scale urban road network is presented, in which the interactions between neighboring subnetworks are described with interconnecting constraints. To coordinate the subnetworks, Lagrange multipliers are introduced to deal with interconnecting constraints among subnetworks, and an augmented Lagrange function is constructed. Then, based on dual optimization theory and a decomposition strategy, the dual optimization problem of the original MPC problem is divided into several new subproblems. In addition, we develop a coordination algorithm based on an interaction prediction approach to coordinate the resulted subproblems with a two-level hierarchical structure. Finally, experimental results by means of simulation on a benchmark road network are presented, which illustrate the performance of the proposed approach.
Autors: Ye, B.;Wu, W.;Li, L.;Mao, W.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Aug 2016, volume: 17, issue:8, pages: 2182 - 2192
Publisher: IEEE
 
» A High Performance Parallel and Heterogeneous Approach to Narrowband Beamforming
Abstract:
This paper describes a high performing, hybrid parallel, and heterogeneous algorithmic approach to narrowband Delay-Sum Beamforming (DSB) in the frequency domain using a Just-In-Time Asynchronous Data Method (JIT-ADM) parallel pattern. JIT-ADM is a novel asynchronous parallel programming pattern that unifies various levels of asynchronous concurrency available with distributed heterogeneous computing. The computational performance of this DSB algorithm was analyzed on a 50 node Cray XC30 with a single 10-core Intel Xeon E5-2670 v2 and NVIDIA Tesla K20X general purpose Graphics Processing Unit (GPU) on each node. The algorithm exhibits well behaved weak scalability with 92.7 percent parallel efficiency at 50 nodes compared to maximum performance observed. It is also shown that the algorithm efficiently utilizes a large portion of the available hardware. During beamforming the GPU is utilized at 51.8 percent of its maximum double precision floating point throughput whereas a comparable Central Processing Unit (CPU) version utilizes 60.0 percent of its maximum expected floating point throughput. Across the weak scalability study, utilizing GPUs for processing, a 2-5x performance gain is achieved compared to using CPUs. A brief derivation and validation of the implemented DSB is also presented.
Autors: Sarofeen, C.;Gillett, P.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Aug 2016, volume: 27, issue:8, pages: 2196 - 2207
Publisher: IEEE
 
» A High Power Density Micro-Thermoelectric Generator Fabricated by an Integrated Bottom-Up Approach
Abstract:
In this paper, we report a high power density cross-plane micro-thermoelectric generator (TEG) fabricated by integrating pulsed electroplating with micro-fabrication processes. The TEG consists of a total of 127 pairs of n-type Bi2Te3 and p-type Sb2Te3 thermoelectric pillars embedded in a SU-8 matrix in order to enhance the overall mechanical strength of the device. Both bottom and top electrical connections are formed by electroplating, which is advantageous because of facile and low cost fabrication and low parasitic electrical resistances. The device demonstrates a maximum power of 2990 μW at a temperature difference of 52.5 K, corresponding to a power density as high as 9.2 mW · cm-2. The power density of our device is more than two times the highest value reported for the electroplated micro-TEGs in the literature, which can be attributed to the low internal resistance and high packing density of thermoelectric pillars.
Autors: Wenhua Zhang;Juekuan Yang;Dongyan Xu;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Aug 2016, volume: 25, issue:4, pages: 744 - 749
Publisher: IEEE
 
» A High-Order Markov-Chain-Based Scheduling Algorithm for Low Delay in CSMA Networks
Abstract:
Recently, several CSMA algorithms based on the Glauber dynamics model have been proposed for wireless link scheduling, as viable solutions to achieve the throughput optimality, yet simple to implement. However, their delay performance still remains unsatisfactory, mainly due to the nature of the underlying Markov chains that imposes a fundamental constraint on how the link state can evolve over time. In this paper, we propose a new approach toward better queueing delay performance, based on our observation that the algorithm needs not be Markovian, as long as it can be implemented in a distributed manner. Our approach hinges upon utilizing past state information observed by local link and then constructing a high-order Markov chain for the evolution of the feasible link schedules. We show that our proposed algorithm, named delayed CSMA, achieves the throughput optimality, and also provides much better delay performance by effectively “decorrelating” the link state process (and thus resolves link starvation). Our simulation results demonstrate that the delay under our algorithm can be reduced by a factor of 20 in some cases, compared to the standard Glauber-dynamics-based CSMA algorithm.
Autors: Kwak, J.;Lee, C.-H.;Eun, D.Y.;
Appeared in: IEEE/ACM Transactions on Networking
Publication date: Aug 2016, volume: 24, issue:4, pages: 2278 - 2290
Publisher: IEEE
 
» A Highly Accurate Prediction Algorithm for Unknown Web Service QoS Values
Abstract:
Quality of service (QoS) guarantee is an important component of service recommendation. Generally, some QoS values of a service are unknown to its users who has never invoked it before, and therefore the accurate prediction of unknown QoS values is significant for the successful deployment of web service-based applications. Collaborative filtering is an important method for predicting missing values, and has thus been widely adopted in the prediction of unknown QoS values. However, collaborative filtering originated from the processing of subjective data, such as movie scores. The QoS data of web services are usually objective, meaning that existing collaborative filtering-based approaches are not always applicable for unknown QoS values. Based on real world web service QoS data and a number of experiments, in this paper, we determine some important characteristics of objective QoS datasets that have never been found before. We propose a prediction algorithm to realize these characteristics, allowing the unknown QoS values to be predicted accurately. Experimental results show that the proposed algorithm predicts unknown web service QoS values more accurately than other existing approaches.
Autors: Ma, Y.;Wang, S.;Hung, P.;Hsu, C.;Sun, Q.;Yang, F.;
Appeared in: IEEE Transactions on Services Computing
Publication date: Aug 2016, volume: 9, issue:4, pages: 511 - 523
Publisher: IEEE
 
» A Highly Linear Dual-Band Mixed-Mode Polar Power Amplifier in CMOS with An Ultra-Compact Output Network
Abstract:
This paper presents a highly linear dual-band mixed-mode polar power amplifier (PA) fully integrated in a standard 65 nm bulk CMOS process. An ultra-compact single-transformer-based passive network provides optimum load impedance transformations simultaneously at two operating frequencies, parallel power combining, and even-harmonic rejection without any tuning elements or band selection switches. The mixed-mode PA architecture leverages both digital and analog techniques to dynamically suppress the AM-AM and AM-PM distortions, achieving high linearity. As a proof-of-concept design, a dual-band mixed-mode polar PA is implemented in a standard 65 nm CMOS process. It demonstrates a peak output power of +28.1 dBm/+26.0 dBm with a PA drain efficiency of 40.7%/27.0% at 2.6 GHz/4.5 GHz, respectively. The measured 2nd harmonic rejection for the 2.35 GHz signal is 36 dB. Modulation tests with 8 MSym/s 256-QAM signals achieve the measured rms EVM of 1.53%/1.87% with the average output power of +20.37 dBm/+18.53 dBm and the PA drain efficiency of 16.26%/13.42% at 2.35 GHz/4.7 GHz, demonstrating a highly linear and efficient dual-band mixed-mode polar PA.
Autors: Jong Seok Park;Song Hu;Yanjie Wang;Hua Wang;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2016, volume: 51, issue:8, pages: 1756 - 1770
Publisher: IEEE
 

Publication archives by date

  2017:   January     February     March     April     May     June     July     August     September     October     November     December    

  2016:   January     February     March     April     May     June     July     August     September     October     November     December    

  2015:   January     February     March     April     May     June     July     August     September     October     November     December    

  2014:   January     February     March     April     May     June     July     August     September     October     November     December    

  2013:   January     February     March     April     May     June     July     August     September     October     November     December    

  2012:   January     February     March     April     May     June     July     August     September     October     November     December    

  2011:   January     February     March     April     May     June     July     August     September     October     November     December    

  2010:   January     February     March     April     May     June     July     August     September     October     November     December    

  2009:   January     February     March     April     May     June     July     August     September     October     November     December    

 
0-C     D-L     M-R     S-Z