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Electrical and Electronics Engineering publications abstract of: 08-2014 sorted by title, page: 0
» 100 Gb/s Intensity Modulation and Direct Detection
Abstract:
Recent advances in short reach 100 Gb/s intensity modulation and directed detection systems are briefly reviewed. As an illustrative example of using digital signal processing enabled transmitters and receivers to allow relatively modest symbol rates, the generation and detection of 112 Gb/s 16-QAM half-cycle Nyquist subcarrier modulation are considered using dual-polarization, single-carrier and single-polarization, dual-carrier implementations. High bandwidth directly modulated passive feedback lasers are used to generate the optical signals and pre-amplified receivers are used to detect the received signals in a back-to-back system and after transmission over 4 km of single-mode fiber.
Autors: Cartledge, J.C.;Karar, A.S.;
Appeared in: Journal of Lightwave Technology
Publication date: Aug 2014, volume: 32, issue:16, pages: 2809 - 2814
Publisher: IEEE
 
» 100 Gbit/s optical wireless communication system link throughput
Abstract:
Novel results on the link layer protocol performance of future infrared personal communication links at a line rate of 100 Gbit/s are presented. The discussion aims to demonstrate the shortcomings of the currently standardised half-duplex mode of communications in the physical layer and details its negative impact on the link layer efficiency. Results of a non-standardised full-duplex mode of operation that is however suitable for application in future high capacity infrared links are also presented. The results predict that the migration to this full-duplex mode can prove advantageous for the link layer performance, as it not only yields a higher efficiency, but also requires significantly smaller frame and window sizes.
Autors: Boucouvalas, A.C.;Yiannopoulos, K.;Ghassemlooy, Z.;
Appeared in: Electronics Letters
Publication date: Aug 2014, volume: 50, issue:17, pages: 1220 - 1222
Publisher: IEEE
 
» 2-Bit, 1–4 GHz Reconfigurable Frequency Measurement Device
Abstract:
A reconfigurable frequency measurement (RFM) device operating from 1 to 4 GHz has been designed, simulated, fabricated and tested. The RFM device can identify an unknown signal by assigning it to one of the four sub-bands defined by a switched circuit. The 2-bit design is formed by switching between two branches, where each branch corresponds to one bit. The RFM device is made using PIN diodes and other surface mounted components, integrated on the same dielectric substrate in microstrip technology. Simulated and measured results are shown with a very good agreement.
Autors: Espinosa-Espinosa, M.;de Oliveira, B.G.M.;Llamas-Garro, I.;de Melo, M.T.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2014, volume: 24, issue:8, pages: 569 - 571
Publisher: IEEE
 
» 2014 MTT-S Graduate Student Fellowship Awards [Education News]
Abstract:
Autors: Crupi, G.;Kaul, R.;Li, C.;Brazil, T.;Gupta, R.;
Appeared in: IEEE Microwave Magazine
Publication date: Aug 2014, volume: 15, issue:5, pages: 118 - 121
Publisher: IEEE
 
» 3-D Silicon-on-Insulator Integrated Circuits With NFET and PFET on Separate Layers Using Au/SiO2 Hybrid Bonding
Abstract:
We report the first demonstration of 3-D integrated circuits (3-D ICs) through the low-temperature (200 °C) hybrid bonding of 3- m-diameter gold (Au) contacts embedded in a polished silicon oxide (SiO2) surface. N-type field-effect transistors (NFETs) and p-type FETs (PFETs) prepared on separate silicon-on-insulator wafers are vertically connected after the completion of the FET process including metal wires. Ultrahigh-density integration is possible because the developed technology requires no additional area for electrical interconnect sites. At the same time, the overall IC performance can be improved because the process and design for the NFETs and PFETs are independently optimized before bonding. The reliability of the hybrid electrical connection is confirmed using a daisy-chain test device of more than 23000 electrodes. Feasibility tests are also performed by developing 3-D-CMOS inverters and 3-D-ring oscillators (ROs) with 101 stages. The experimental results indicate that the developed technology is promising for high-performance 3-D ICs.
Autors: Goto, M.;Hagiwara, K.;Iguchi, Y.;Ohtake, H.;Saraya, T.;Higurashi, E.;Toshiyoshi, H.;Hiramoto, T.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Aug 2014, volume: 61, issue:8, pages: 2886 - 2892
Publisher: IEEE
 
» 3-D Vibration Measurement Using a Single Laser Scanning Vibrometer by Moving to Three Different Locations
Abstract:
3-D vibration measurement is achieved using a single laser scanning vibrometer (LSV) and laser scanner (LS) by moving them to three arbitrarily different locations from the principle that vibration analysis based on the frequency domain is independent of the vibration signal based on time domain. The proposed system has the same effect as using three sets of LSVs, and has an advantage of reducing equipment costs. Analytical approach of obtaining in-plane and out-of-plane vibration of surface is introduced using geometrical relations between three LSV coordinates and vibrations measured at three different locations. The proposed algorithm is verified by comparing the experimental results obtained by a three-axis accelerometer and a developed optical system with an LSV and an LS combined together.
Autors: Dongkyu Kim;Hajun Song;Khalil, H.;Jongsuh Lee;Semyung Wang;Kyihwan Park;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Aug 2014, volume: 63, issue:8, pages: 2028 - 2033
Publisher: IEEE
 
» 400-Gb/s Transmission Over 10-km SSMF Using Discrete Multitone and 1.3- m EMLs
Abstract:
We experimentally demonstrated 400-Gb/s transmission over 10-km standard single-mode using discrete multi-tone (DMT) and four 1.3- m local-area-network wavelength-division-multiplexed externally modulated lasers. A reasonably good system margin has been obtained. We have also investigated the fundamental limitations of using semiconductor optical amplifiers for DMT-based systems.
Autors: Chan, T.;Lu, I.;Chen, J.;Way, W.I.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Aug 2014, volume: 26, issue:16, pages: 1657 - 1660
Publisher: IEEE
 
» 4W1H in mobile crowd sensing
Abstract:
With the rapid proliferation of sensor-rich smartphones, mobile crowd sensing has become a popular research field. In this article, we propose a four-stage life cycle (i.e., task creation, task assignment, individual task execution, and crowd data integration) to characterize the mobile crowd sensing process, and use 4W1H (i.e., what, when, where, who, and how) to sort out the research problems in the mobile crowd sensing domain. Furthermore, we attempt to foresee some new research directions in future mobile crowd sensing research.
Autors: Zhang, D.;Wang, L.;Xiong, H.;Guo, B.;
Appeared in: IEEE Communications Magazine
Publication date: Aug 2014, volume: 52, issue:8, pages: 42 - 48
Publisher: IEEE
 
» 50% continuous-wave wallplug efficiency from 1.53μm-emitting broad-area diode lasers
Abstract:
Long-wavelength InP-based diode lasers emitting at 1.53 μm have been optimized for maximum continuous-wave (CW) electrical-to-optical power conversion efficiency, so-called wallplug efficiency (WPE). Efficient electron and hole capture into a single-quantum-well (SQW) active region as well as suppression of electron and hole leakage out of the SQW result in high values for the internal differential efficiency: ∼97% for long-cavity (≥2 mm) uncoated-facet devices and ∼85%–89% for short-cavity (1.5 mm) optimized facet-coated devices. The characteristic temperature of the slope efficiency, T1, reaches a high value of 323 K. Doping-level optimization of the p-cladding layer and the use of the SQW result in low values for the internal loss coefficient: ∼1.1 cm−1 for long-cavity (≥2 mm) uncoated-facet devices and ∼1.5–2.0 cm−1 for short-cavity (1.5 mm) optimized facet-coated devices. In turn, a maximum CW WPE value of 50% is achieved at room temperature and ∼1 W output power from conductively-cooled 100 μm-wide-aperture devices. The maximum CW power is 2.5 W. One beneficial byproduct of the CW-WPE maximization process is a large transverse spot size which, in turn, provides a very narrow transverse beamwidth: 26° full width half maximum. Reliability tests show no degradation when devices are run CW at high currents (4–5 A) and high temperatures (40–50 °C) for over 4000 h, at ∼2 W output power.
Autors: Garrod, T.;Olson, D.;Klaus, M.;Zenner, C.;Galstad, C.;Mawst, L.;Botez, D.;
Appeared in: Applied Physics Letters
Publication date: Aug 2014, volume: 105, issue:7, pages: 071101 - 071101-5
Publisher: IEEE
 
» 60 GHz to E-Band Switchable Bandpass Filter
Abstract:
A novel reconfigurable millimeter-wave bandpass filter (BPF) capable of operating between 60 GHz and the E-band, with a good channel isolation, is presented. This fully integrated filter is designed with all reconfigurable elements embedded for compactness. A new method that increases fractional bandwidths is introduced. It uses inductively coupled invertersbut does not require tuning. New circuit models are provided for these inverters, reconfigurable resonators, and the reconfigurable bandstop stubs. The compact BPF achieved a footprint of only 4.75 mm 3.75 mm. Measurements for the filters show good agreement with the simulation results.
Autors: Chan, K.Y.;Ramer, R.;Mansour, R.R.;Guo, Y.J.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2014, volume: 24, issue:8, pages: 545 - 547
Publisher: IEEE
 
» 7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter
Abstract:
In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse–fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35- CMOS process occupies 0.09 and consumes a total of 153 from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step.
Autors: Omran, H.;Arsalan, M.;Salama, K.N.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2014, volume: 61, issue:8, pages: 589 - 593
Publisher: IEEE
 
» 700-kW-Peak-Power Monolithic Nanosecond Pulsed Fiber Laser
Abstract:
We report a high-pulse energy, high-peak power, and monolithic nanosecond pulsed fiber laser source at nm in master oscillator-power amplifier configuration. The seed source is a directly modulated laser diode, producing nanosecond pulses as short as ns with -W peak power and a tunable repetition rate. Three core-pumped fiber amplifier stages and two double-cladding fiber amplifier stages were built to boost the peak power and the pulse energy of the -ns seed pulses to kW and mJ, respectively. The all-fiber construction of the whole laser system enables compact size, maintenance-free, and robust operation.
Autors: Fang, Q.;Shi, W.;Fan, J.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Aug 2014, volume: 26, issue:16, pages: 1676 - 1678
Publisher: IEEE
 
» 71% PAE C-band GaN power amplifier using harmonic tuning technology
Abstract:
A high-efficiency C-band internally matched power amplifier, developed with 12 mm AlGaN/GaN high-electron mobility transistors is described. The second-harmonic frequency (2f0) tuning network is applied to confine the impedance at 2f0 in safe efficiency regions. The packaged power amplifier achieves 71% power-added efficiency (PAE) and 102 W output power, associated with 17 dB power gain. The PAE is believed to be the highest of the C-band GaN power amplifiers reported to date.
Autors: Yang Lu;Mengyi Cao;Jiaxing Wei;Bochao Zhao;Xiaohua Ma;Yue Hao;
Appeared in: Electronics Letters
Publication date: Aug 2014, volume: 50, issue:17, pages: 1207 - 1209
Publisher: IEEE
 
» 77 GHz Radar Transmitter With PLL Based on a Sub-Harmonic Gilbert Frequency Doubler
Abstract:
This contribution highlights the usage of a high-quality voltage controlled oscillator (VCO) at 19.25 GHz fundamental frequency with a succeeding times four frequency multiplication scheme facilitating a 77 GHz output frequency. Signal tapping at the VCO's common emitter node allows obtaining the second-order harmonic tone that drives a single Gilbert frequency doubler. Beneficial to the PLL implementation is a reduced overall prescaler ratio allowing faster frequency ramps.
Autors: Starzer, F.;Forstner, H.-P.;Maurer, L.;Stelzer, A.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2014, volume: 24, issue:8, pages: 539 - 541
Publisher: IEEE
 
» Suppression of Limit Cycles in Interfered Two-Dimensional Digital Filters: A Fornasini–Marchesini Model Case
Abstract:
Recently, Ahn proposed an stability criterion for interfered two-dimensional (2-D) digital filters described by the Roesser model. However, until now, no criteria for interfered 2-D digital filters in the Fornasini–Marchesini (FM) model have been studied. As a continuation of the results, this brief proposes a new criterion for the suppression of limit cycles in interfered 2-D digital filters in the FM model. The proposed criterion ensures the asymptotic stability and performance of 2-D digital filters. The effectiveness of the proposed criterion is demonstrated using numerical examples. The work in this brief and that of the Roesser model provide, as an integrity, systematic results on limit cycle suppression for 2-D digital filters in the sense.
Autors: Ahn, C.K.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2014, volume: 61, issue:8, pages: 614 - 618
Publisher: IEEE
 
» iCloudAccess: Cost-Effective Streaming of Video Games From the Cloud With Low Latency
Abstract:
As a new paradigm, cloud gaming allows users to play high-end video games instantly without downloading or installing the original game software. In this paper, we first conduct a series of well-designed active and passive measurements on a large-scale cloud gaming platform and identify the significant diversity in the queueing delay and response delay among users. We note that the latency problem largely results from user-specified request routing and inelastic server provisioning. To address latency problem of the cloud gaming platform, we further propose an online control algorithm called iCloudAccess to perform intelligent request dispatching and server provisioning. Our main objective is to cut down the provisioning cost of cloud gaming service providers while still ensuring the user quality-of-experience requirements. We formulate the problem as a constrained stochastic optimization problem and apply the Lyapunov optimization theory to derive the online control algorithm with provable upper bounds. We also conduct extensive trace-driven simulations to evaluate the effectiveness of our algorithm, and our results show that our proposed algorithm achieves significant gain over other alternative approaches.
Autors: Wu, D.;Xue, Z.;He, J.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Aug 2014, volume: 24, issue:8, pages: 1405 - 1416
Publisher: IEEE
 
» In-Situ Metallic Oxide Capping for High Mobility Solution-Processed Metal-Oxide TFTs
Abstract:
Transparent and highly conductive indium-zinc oxide (IZO) was utilized as a metallic capping layer in solution-processed indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) to enhance their electrical performance. By applying an in-situ metallic oxide (IZO) as a capping layer, which can be monolithically patterned with source/drain electrodes, the IGZO TFTs have shown enhanced mobility as high as cm2/V-s, subthreshold slope of <0.1 V/decade, and threshold voltage of V. We found that metallic capping layers having work function lower than that of the channel material can induce a significant reduction in series resistance and enhance the apparent field-effect mobility of the device.
Autors: Kim, K.T.;Kim, J.;Kim, Y.;Park, S.K.;
Appeared in: IEEE Electron Device Letters
Publication date: Aug 2014, volume: 35, issue:8, pages: 850 - 852
Publisher: IEEE
 
» A 0.42-V Input Boost dc–dc Converter With Pseudo-Digital Pulsewidth Modulation
Abstract:
A pseudo-digital pulsewidth modulation (P-DPWM) controlled boost direct current-direct current converter is presented in this brief. By applying low-voltage analog design techniques into the traditional digital pulsewidth modulation (DPWM) structure, the proposed P-DPWM achieves new features of high resolution, low power, and small area while retaining the low-supply feature of the DPWM. A test chip has been designed and fabricated in a 65-nm CMOS process with an area of 1.44 to validate its performance. A peak efficiency of 86% is achieved. The correct functionality is also demonstrated with the controller supply as low as 0.42 V, which is ideal for sub-1 V low-supply applications.
Autors: Sun, Z.;Chew, K.W.R.;Tang, H.;Yu, G.;Siek, L.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2014, volume: 61, issue:8, pages: 634 - 638
Publisher: IEEE
 
» A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration
Abstract:
Pub DtlA software-defined radio receiver is presented, operating from 400 MHz to 6 GHz. The split front-end architecture has a low-band RF path (0.4–3 GHz) using 8-phase passive mixers and a high-band RF path (3–6 GHz) using 4-phase passive mixers. DC-offset, IIP 2 , and harmonic recombination for harmonic rejection may be calibrated to achieve true wideband specifications. A 0.5–50 MHz tunable baseband bandwidth implies compliance with LTE and future standards. Despite having a 0.9 V supply, the receiver architecture ensures high out-of-band linearity. The 0.6 mm 2 , 28 nm CMOS receiver achieves down to 1.8 dB NF, +3 dBm out-of-band IIP3, 70 dB calibrated HR3/5 and +80 dBm calibrated IIP2. It tolerates 0 dBm blockers at 80 MHz offset with a blocker NF of 10 dB for a power consumption of 20–40 mW.
Autors: van Liempd, B.;Borremans, J.;Martens, E.;Cha, S.;Suys, H.;Verbruggen, B.;Craninckx, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1815 - 1826
Publisher: IEEE
 
» A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes
Abstract:
This study demonstrates a wide frequency tuning range voltage-controlled oscillator ( -VCO) with an active inductor in a 90-nm CMOS process. As the proposed -VCO is intended to be extremely flexible without redesign for several new-generation SerDes interfaces, a wide operating frequency makes the phase-locked loop (PLL) applicable to the multistandards. To demonstrate a highly competitive design, a quality factor enhancement technique has been also demonstrated to reduce the loss from the active inductor, leading to an appropriate phase noise over the entire tuning range. At a supply of 1.2 V, the fabricated -VCO provides a frequency tuning range of 0.9–8 GHz (160%) with power consumption of 3.2–19.1 mW. The measured phase noise is from 105 to 118 dBc/Hz at a 1-MHz offset. Realized in a fully integrated PLL chip, it occupies an active area of .
Autors: Cheng, K.;Hung, C.;Alex Gong, C.;Liu, J.;Jiang, B.;Sun, S.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2014, volume: 61, issue:8, pages: 559 - 563
Publisher: IEEE
 
» A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation
Abstract:
Dynamic adaptation using Razor-based detection and correction of timing errors has demonstrated substantial improvements in performance and energy-efficiency in microprocessors. In this work, we apply Razor to hardware accelerators that find increasing application in System-on-Chip designs with high-performance requirements that must be delivered under stringent power budgets. We describe the implementation and silicon measurement results from a Razor-based hardware loop-accelerator (RZLA), implementing the Sobel edge-detection algorithm. Unlike in microprocessors, the RZLA pipeline is datapath-dominated with statically-scheduled control that has queue-based storage structures which are simply extended to support check-pointing and recovery. We exploit these characteristics typical of DSP and image-processing accelerators to implement Razor recovery in manner that is amenable to RTL validation and verification. We show a low-overhead pulsed-latch based Razor Flip-flop (RFF) architecture that adds only a single extra transistor on clock to minimize clock power overhead. The RFF is deployed in conjunction with a level-sensitive latch-insertion based algorithm to address the minimum-delay constraint present in all Razor systems. This algorithm enables the use of 50% of the clock period for timing speculation leading to robust error detection and correction across a wide dynamic voltage- and frequency-scaling range. Fabricated in 65 nm CMOS, the RZLA reclaims voltage margins to demonstrate 34% energy-efficiency improvements on a per-device basis and 33% overall, for the entire batch of devices at 1 GHz operation.
Autors: Das, S.;Dasika, G.S.;Shivashankar, K.;Bull, D.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2014, volume: 61, issue:8, pages: 2290 - 2298
Publisher: IEEE
 
» A 10 GS/s 6 b Time-Interleaved Partially Active Flash ADC
Abstract:
This paper presents a new ADC architecture called partially active flash ADC. A 10 GS/s 6 b four-way time-interleaved ADC prototype in 65 nm CMOS demonstrated that this new ADC architecture offers better power efficiency than traditional ADC architectures in the 10 GS/s speed range. Various considerations towards high-speed ADC designs are discussed including a proposed source-follower based boot-strap track-and-hold circuit to reduce input kickback and improve the ADC bandwidth. Also discussed is the generation and skew calibration of the four-phase clocks for the interleaved channels to improve the ADC effective resolution at high input frequencies. By deriving the four-phase clocks from a Nyquist frequency input clock through pass gates, accurate timing skew calibration is achieved through a simple duty-cycle correction. Measured SNDR is 34.3 dB at low input frequencies and 32.0 dB at the Nyquist input frequency. The ADC including the input clock buffer consumes 83 mW with a FOM of 197 fJ/cs.
Autors: Yang, X.;Liu, J.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2014, volume: 61, issue:8, pages: 2272 - 2280
Publisher: IEEE
 
» A 10-bit 110 kS/s 1.16 SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications
Abstract:
A 10-bit 110-kS/s successive-approximation analog-to-digital converter (ADC) for multichannel biomedical applications is presented. In order to achieve low-power operation, the ADC utilizes a reduced-speed dynamic comparator, a low-complexity calibration technique, a hybrid single/differential digital-to-analog converter architecture, and an attenuation capacitor with low sensitivity to mismatch errors. Fabricated in 180-nm CMOS, this ADC consumes a total power of 1.16 from 1.5 V/1.2 V analog/digital power supplies. The integral nonlinearity is between 1.23 LSB and 1.19 LSB, whereas the differential nonlinearity is between 0.71 LSB and 0.92 LSB. The ADC signal-to-noise-and-distortion ratio and spurious-free dynamic range are 56.1 and 67 dB with a 39.5-kHz sinusoid input, respectively. The ADC figure-of-merit is of 20 fJ per conversion step, which is very competitive, as compared with state-of-the-art ADCs in similar 180-nm CMOS technologies.
Autors: Taherzadeh-Sani, M.;Lotfi, R.;Nabki, F.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2014, volume: 61, issue:8, pages: 584 - 588
Publisher: IEEE
 
» A 10-Gb/s CDR With an Adaptive Optimum Loop-Bandwidth Calibrator for Serial Communication Links
Abstract:
This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11  m CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than while consuming 82 mW at 10-Gb/s.
Autors: Lee, J.-Y.;Yoon, J.-H.;Bae, H.-M.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2014, volume: 61, issue:8, pages: 2466 - 2472
Publisher: IEEE
 
» A 1064- and 1074-nm Dual-Wavelength Nd:YAG Laser Using a Fabry–Perot Band-pass Filter as Output Mirror
Abstract:
We propose and demonstrate a 1064- and 1074-nm dual-wavelength Nd:YAG laser by exploiting a dielectric Fabry–Perot bandpass filter (FPF) as laser output mirror. A fiber-pigtailed 808-nm laser diode array is used to pump an -cut Nd:YAG crystal with a plano-plano resonator cavity. The dielectric FPF as output mirror is specially designed to balance the net gain of 1064 and 1074 nm to obtain a dual-wavelength laser. Simultaneous dual-wavelength lasing at 1064 and 1074 nm is successfully achieved. The maximum output power of the laser is 581 mW, and the slope conversion efficiency is 18.8% with the threshold pump power of 2.1 W. The design of the FPF used as output mirror, including the relationship between FWHM and spectral separation, peak wavelength location, and peak transmission, are discussed. Compared with the coupled-cavity, etalon, or specially coated mirror methods, the FPF method presented in this paper is both easy in the selection of oscillating wavelength and simple in design and fabrication.
Autors: Wang, X.Z.;Wang, Z.F.;Bu, Y.K.;Chen, L.J.;Cai, G.X.;Cai, Z.P.;
Appeared in: IEEE Photonics Journal
Publication date: Aug 2014, volume: 6, issue:4, pages: 1 - 6
Publisher: IEEE
 
» A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB
Abstract:
Pub DtlThis paper presents a 12.8 GS/s 32-way hierarchically time-interleaved SAR ADC with 4.6 ENOB in 65 nm CMOS. The prototype utilizes hierarchical sampling and cascode sampler circuits to enable greater than 25 GHz 3 dB effective resolution bandwidth (ERBW). We further employ a pseudo-differential SAR ADC to save power and area. The core circuit occupies only 0.23 mm 2 and consumes a total of 162 mW from dual 1.2 V/1.1 V supplies. The design achieves a SNDR of 29.4 dB at low frequencies and 26.4 dB at 25 GHz, resulting in a figure-of-merit of 0.79 pJ/conversion-step. As will be further described in the paper, the circuit architecture used in this prototype enables expansion to 25.6 GS/s or 51.2 GS/s via additional interleaving without significantly impacting ERBW.
Autors: Duan, Y.;Alon, E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1725 - 1738
Publisher: IEEE
 
» A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ
Abstract:
A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital- random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of .
Autors: Li, X.;Wei, Q.;Xu, Z.;Liu, J.;Wang, H.;Yang, H.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2014, volume: 61, issue:8, pages: 2337 - 2347
Publisher: IEEE
 
» A 15-V Bidirectional Ultrasound Interface Analog Front-End IC for Medical Imaging Using Standard CMOS Technology
Abstract:
A high-voltage (HV) interface analog front-end (AFE) integrated circuit (IC) for medical ultrasound imaging applications using 0.18- standard CMOS process is presented. The proposed AFE IC includes a HV pulser in the transmit path that safely generates up to 15-Vpp of unipolar pulses at 2.6 MHz, a HV switch for isolation between transmitter and receiver front-end parts, and a 95.1- low-power transimpedance preamplifier with 12-MHz bandwidth and 3.5- input referred noise in the receive path operating at a low 1.1-V supply voltage. Both the pulser and the switch utilize dynamically-gate-biased stacked 3.3-V transistors to enable HV operation without compromising device reliability. The implemented single-channel AFE IC prototype intended for interfacing capacitive micromachined ultrasound transducer consumes 0.15 of core die area, making it feasible to be applied for various multi-array medical ultrasound imaging systems.
Autors: Banuaji, A.;Cha, H.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2014, volume: 61, issue:8, pages: 604 - 608
Publisher: IEEE
 
» A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- CMOS
Abstract:
This brief describes a wide-range operating false-lock-free delay-locked loop (DLL) for a low-voltage differential signaling (LVDS) display interface. A false-lock detector circuit and a self-reset circuit internally prevent any possible false locks in a robust way. The proposed DLL immediately removes stuck false locks caused by an improper phase detector state. The DLL circuit does not require the duty ratio of the input clock to be 50%. The proposed circuit has been fabricated using the 0.15- 1P-6M mixed-mode CMOS technology. The proposed DLL is implemented for an LVDS display interface and supports operating from 20 to 135 MHz without any error. It consumes 2.2 mW under a 130-MHz operation.
Autors: Moon, Y.;Kong, I.;Ryu, Y.;Kang, J.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2014, volume: 61, issue:8, pages: 554 - 558
Publisher: IEEE
 
» A 2.4 GHz ULP Reconfigurable Asymmetric Transceiver for Single-Chip Wireless Neural Recording IC
Abstract:
This paper presents a 2.4 GHz ultra-low-power (ULP) reconfigurable asymmetric transceiver and demonstrates its application in wireless neural recording. Fabricated in CMOS technology, the transceiver is optimized for sensor-gateway communications within a star-shaped network, and supports both the sensor and gateway operation modes. Binary phase-shift keying (BPSK) modulation with high data rate (DR) of 1 to 8 Mbps is used in the uplink from sensor to gateway, while on-off keying (OOK) modulation with low DR of 100 kbps is adopted in the downlink. A fully integrated Class-E PA with moderate output power has also been proposed and achieves power efficiency of 53%. To minimize area usage, inductor reuse is adopted between PA and LNA, and eliminates the need of lossy T/R switch in the RF signal path. When used as sensor, the transceiver with frequency locked phase-locked loop (PLL) achieves TX (BPSK) power efficiency of 28% @ 0 dBm output power, and RX (OOK) sensitivity of @ 100 kbps while consuming only . When configured as gateway, the transceiver achieves sensitivity levels of , , and for 1, 5, and 8 Mbps BPSK, respectively. The transceiver is integrated with an 8-channel neural recording front-end, and neural signals from a rat are captured to verify the system functionality.
Autors: Tan, J.;Liew, W.-S.;Heng, C.-H.;Lian, Y.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Aug 2014, volume: 8, issue:4, pages: 497 - 509
Publisher: IEEE
 
» A 200 GHz Heterodyne Image Receiver With an Integrated VCO in a SiGe BiCMOS Technology
Abstract:
A 200 GHz heterodyne image receiver consisting of a mixer integrated with an on-chip voltage controlled oscillator (VCO) has been developed in a 0.18 SiGe BiCMOS technology. Incoming signals near 200 GHz are down-converted by the 3rd-order subharmonic mixer with V-band local oscillator (LO) pumping, which is provided by the Colpitts VCO with a stacked common-base buffer. The measured minimum conversion loss is 11.5 dB at 196 GHz with an input 1 db compression point ( ) of . The fabricated chip with an area of 600 400 including pads consumes total DC power of 25.5 mW. A two-dimensional 200 GHz image acquired with the receiver is presented to demonstrate its imaging application.
Autors: Yoon, D.;Rieh, J.-S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2014, volume: 24, issue:8, pages: 557 - 559
Publisher: IEEE
 
» A 21–48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Communications
Abstract:
This paper presents a mm-wave subharmonic injection-locked (SHIL) fractional-N frequency synthesizer for wireless multiband point-to-point backhaul communications. The SHIL synthesizer implements a low-phase-noise 4.5–6.1 GHz PLL and injects its output to a dual-modulus divider followed by an ultra-wideband injection-locked frequency-multiplier (ILFM) chain to achieve excellent phase noise over an ultra-wide frequency tuning range. The proposed ILFM chain employs higher-order LC tanks to generate a rippled phase response around 0 over a wide frequency range to significantly enhance the locking range and to eliminate expensive mm-wave frequency calibration loops. Fabricated in a 65 nm CMOS process, the synthesizer prototype measures a continuous output frequency range from 20.6 to 48.2 GHz with frequency resolution of 220 kHz and output phase noise between 107.0 and 113.9 dBc/Hz at 1 MHz offset while consuming 148 mW and occupying 1850 1130 m .
Autors: Li, A.;Zheng, S.;Yin, J.;Luo, X.;Luong, H.C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1785 - 1799
Publisher: IEEE
 
» A 248–262 GHz InP HBT VCO with Interesting Tuning Behavior
Abstract:
A fundamental-mode common-base voltage-controlled oscillator (VCO) based on 250-nm InP heterojunction bipolar transistor (HBT) technology is reported. The VCO, which employs varactors implemented by connecting the base and emitter of npn transistors as tuning components, shows a tuning range of 247.8–262.2 GHz. The output power is greater than 0 dBm over the entire tuning range, and dissipated dc power is around 85 mW. An unexpected tuning behavior was observed, which was shown to arise from the internal parasitic base inductance of the transistors used for varactors in this work.
Autors: Yun, J.;Kim, N.;Yoon, D.;Kim, H.;Jeon, S.;Rieh, J.-S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2014, volume: 24, issue:8, pages: 560 - 562
Publisher: IEEE
 
» A 2G/3G/4G SAW-Less Receiver Front-End Adopting Switchable Front-End Architecture
Abstract:
Pub DtlIn this paper, a surface acoustic wave (SAW)-less receiver (RX) front-end adopting switchable front-end architecture has been presented for second-generation/third-generation/fourth-generation cellular applications. Depending on the RX–transmitter (TX) frequency separation, a favorable down-mixing architecture is selected between a current-sampling mixer and a voltage-sampling mixer. The proposed switchable architecture meets the specification of an input-referred second-order intercept point (IIP2) for the SAW-less RX while minimizing the power consumption. The implemented RX front-end consists of a wideband capacitor cross-coupled common-gate low-noise amplifier, a 25% duty-cycle passive mixer with IIP2 calibration circuitry, a baseband transconductor, and a trans-impedance amplifier. Fabricated in a 65-nm CMOS process, the SAW-less RX front-end provides conversion gain of 42 dB, and achieves noise figure of below 3.3 dB, out-of-band input-referred third-order intercept point of dBm, and IIP2 of more than 56 dBm. It draws an average current of 14.8 mA from 1.2 V. The die area is 1.71 mm .
Autors: Kwon, K.;Han, J.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Aug 2014, volume: 62, issue:8, pages: 1716 - 1723
Publisher: IEEE
 
» A 3-D Dual-Polarized Near-Field Microwave Imaging System
Abstract:
Pub DtlA novel 3-D dual-polarized microwave imaging system based on the modulated scattering technique (MST) is presented. The system collects the magnitude and phase of the scattered field using 120 MST probes and 12 transmitter/collector antennas distributed around an object-of-interest in the near-field region. The 12 antennas form a middle circumferential layer while the printed MST probes are arranged on three circumferential layers including the middle layer. The antennas are linearly polarized double-layer Vivaldi antennas, each fixed inside its own cylindrical conducting cavity and slanted with respect to the vertical axis of the imaging chamber. The MST probes are etched on both sides of a thin substrate and loaded with five evenly distributed p-i-n diodes along their length. These are positioned vertically and horizontally so that the - and -components of the electric field is measured. Field data are collected using MST, calibrated, and then inverted using a multiplicatively regularized finite-element contrast source inversion algorithm. The system performance is evaluated by collecting and inverting data from different 3-D targets.
Autors: Asefi, M.;OstadRahimi, M.;Zakaria, A.;LoVetri, J.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Aug 2014, volume: 62, issue:8, pages: 1790 - 1797
Publisher: IEEE
 
» A 3-D Stacked High- PI-Based MEMS Inductor for Wireless Power Transmission System in Bio-Implanted Applications
Abstract:
This paper presents high- factor 3-D stacked MEMS inductors on polyimide substrate for wireless power transmission systems. The 3-D double layer stacked structure was designed, fabricated, and characterized, and self-planarization of polyimide was realized. The 3-D inductor achieves an inductance of 7.189 with a high- factor of 26.1 at 4.3 MHz. An inductively coupled wireless power transmission system was set up using the 3-D inductor in combination with a solenoid transmitting coil. At the resonant frequency of 1.6 MHz, the peak-to-peak output open circuit voltage could reach 5.2 V with a maximum power transmission efficiency of 11.74% and an output power of 35.5 mW. Effects of the load impedance and transmission distance on the output power were also investigated. Using this wireless transmission system, the driving of an implanted 3-D microelectrode array for neural prosthesis was demonstrated successfully, indicating that this 3-D stacked MEMS inductor design shows promise for applications in supplying power for implanted medical devices.
Autors: Sun, X.;Peng, X.;Zheng, Y.;Li, X.;Zhang, H.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Aug 2014, volume: 23, issue:4, pages: 888 - 898
Publisher: IEEE
 
» A 3.54 nJ/bit-RX, 0.671 nJ/bit-TX Burst Mode Super-Regenerative UWB Transceiver in 0.18- CMOS
Abstract:
Non-coherent ultra-wideband (UWB) transceiver employing energy detector suffers from degradation in output SNR due to the squarer. A burst mode super-regenerative UWB transceiver which can recover the received signal to rail-to-rail with relatively fewer post-amplification stages is proposed. Unlike other super-regenerative receiver architectures that use oscillator, the proposed architecture employs a positive feedback loop to achieve the super-regeneration of received signal and thus eliminates the need for external resonator or quench signal. The transceiver is suitable for low data rate sensor networks application covering spectrum of 3–5 GHz. Manufactured in CMOS 0.18- technology, the transceiver occupies an area of 2.2 mm 2 mm. By exploiting the duty cycle and the transceiver on-time through the burst mode operation for a given data rate of 1 Mbps, it can achieve transmitter energy efficiency of 0.671 nJ/bit and receiver energy efficiency of 3.54 nJ/bit.
Autors: Zheng, Y.;Zhu, Y.;Ang, C.-W.;Gao, Y.;Heng, C.-H.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2014, volume: 61, issue:8, pages: 2473 - 2481
Publisher: IEEE
 
» A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications
Abstract:
An 82 mW fully integrated stereo ground-referenced headphone module is designed in 40 nm CMOS. Lower platform cost is enabled by integrating the headphone module on the same SoC as the baseband functions. Maintaining device reliability with direct battery hook-up and providing large output swing are major challenges for this work, and several techniques were employed to guarantee safe operation for all of the devices under various conditions. Area reduction techniques were utilized to reduce the die cost and achieve lower platform cost. The module supports direct battery hookup with a battery range from 3.1 to 4.5 V and achieves a minimum low frequency, i.e., 217 Hz, PSRR of 110 dB at the lowest battery voltage. Audio quality is preserved by achieving a dynamic range of 100 dB, THD+N of 84 dB at 10 mW output power, and 160 V pop-and-click noise level during power-up and power-down. The module occupies an area of 0.675 mm on the SoC.
Autors: Abdelfattah, K.;Galal, S.;Mehr, I.;Chen, A.J.;Yu, C.;Tjie, M.;Tekin, A.;Jiang, X.;Brooks, T.L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1702 - 1714
Publisher: IEEE
 
» A 40 V 10 W 93%-Efficiency Current-Accuracy-Enhanced Dimmable LED Driver With Adaptive Timing Difference Compensation for Solid-State Lighting Applications
Abstract:
This paper presents a floating-buck dimmable LED driver for solid-state lighting applications. In the proposed driver, an adaptive timing difference compensation (ATDC) is developed to adaptively adjust the off-time of the low-side power switch to enable the driver to achieve high accuracy of the average LED current over a wide range of input voltages and number of output LED loads, fast settling time, and high operation frequency. The power efficiency benefits from the capabilities of using synchronous rectifier and having no sensing resistor in the power stage. The synchronous rectification under high input supply voltage is enabled by a proposed high-speed and low-power gate driver with pseudo-digital level shifters. Implemented in a 0.35 m 50 V CMOS process, experimental results show that the proposed LED driver can operate at 1 MHz and achieve peak power efficiency of 93% to support a wide range of series-connected output LEDs from 1 to 10 and a wide input range from 10 to 40 V. The proposed LED driver has only 2.8% current error from the average LED current of 345 mA and settles within 8.5 s after triggering the dimming condition, improving the settling time by 14 times compared with the state-of-the-art LED drivers.
Autors: Park, D.;Liu, Z.;Lee, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1848 - 1860
Publisher: IEEE
 
» A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis
Abstract:
Pub DtlIn this paper, we present a time-based equalization scheme to implement transmit de-emphasis in voltage-mode drivers. Using two-level pulse-width modulation, this work decouples the tradeoff between impedance matching, output swing, and de-emphasis resolution in conventional voltage-mode drivers using voltage-based de-emphasis. A prototype PWM-based 5 Gb/s voltage-mode transmitter was implemented in a 90 nm CMOS process and characterized across different channels and output swings. The horizontal/vertical eye opening at the end of 60 and 96 in stripline channels is 78 mv/0.6 UI and 8 mV/0.3 UI, respectively. Duty cycle distortion of the clock severely reduced the margins, so the overall performance can be improved by applying duty-cycle correction to clock signals. The transmitter consumes a total power 15.6 mW of which 2.5 mW is consumed in the digital PLL and 7.8 mW in the pre-/output drivers and regulators. This translates to a power efficiency of 3.1 mW/Gb/s, which compares favorably with the state of the art.
Autors: Saxena, S.;Nandwana, R.K.;Hanumolu, P.K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1827 - 1836
Publisher: IEEE
 
» A 60 GHz Drain-Source Neutralized Wideband Linear Power Amplifier in 28 nm CMOS
Abstract:
CMOS technology scaling has enabled the design of high speed and efficient digital circuits. However, the continued scaling is detrimental to the design of RF and mm-wave systems. Higher sensitivity to process variations and inaccuracies in modeling of active and passive devices pose another challenge to the design of these systems at deep submicron technology nodes. This paper describes the design of a 60 GHz power amplifier in 28 nm CMOS technology. A drain-source neutralization technique maintains the stability of the PA and the wideband nature is achieved by the application of low-k transformer networks. The PA comprises of three stages and achieves an overall bandwidth of 11 GHz with a peak gain of 24.4 dB. Using a two-way transmission line based power combiner, the PA delivers a saturated output power of 16.5 dBm with a peak power added efficiency (PAE) of 12.6%.
Autors: Thyagarajan, S.V.;Niknejad, A.M.;Hull, C.D.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2014, volume: 61, issue:8, pages: 2253 - 2262
Publisher: IEEE
 
» A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate
Abstract:
Pub DtlA two-stage pipelined ADC employs a double-sampling residue amplifier, two interleaved precharged DACs, and a new calibration scheme to correct for residue gain error, offset, and nonlinearity. The coarse and fine stages are implemented as flash ADCs incorporating several techniques to reduce their power, complexity, and kickback noise. Realized in 65 nm CMOS technology and sampling at 1 GHz, the prototype achieves an SNDR of 48 dB at the Nyquist rate and exhibits an FOM of 25 fJ/conversion-step while drawing 7.1 mW from a 1 V supply.
Autors: Hashemi, S.;Razavi, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1739 - 1750
Publisher: IEEE
 
» A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function
Abstract:
Pub DtlA 9.2 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast settling without exhibiting overshoots. While most previously reported peaking-free PLLs require additional circuit components which may adversely affect clock jitter or increase hardware complexity, the presented PLL requires only a new type of digital loop filter. The analysis on the loop dynamics and design of the optimal loop filter are presented. As for the implementation, a low-power linear time-to-digital converter (TDC) is realized with a set of three binary phase-frequency detectors whose triggering clocks are dithered using a delta-sigma modulator and phase interpolators. A digitally controlled oscillator (DCO) is implemented as a transformer-tuned LC oscillator whose frequency is set by a ratio between two digitally controlled currents. The digital PLL prototype, fabricated in a 65 nm CMOS, demonstrates 1.2 ps integrated jitter at 9.2 GHz and 1.58 s settling time with 700 kHz bandwidth while dissipating 63.9 mW at a 1.2 V nominal supply.
Autors: Ryu, S.;Yeo, H.;Lee, Y.;Son, S.;Kim, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1773 - 1784
Publisher: IEEE
 
» A Integrated Noise 4 MHz Bandwidth Second-Order Time-to-Digital Converter With Gated Switched-Ring Oscillator
Abstract:
This paper presents a second-order time-to-digital converter (TDC) by using a switched-ring oscillator (SRO) and a gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using SROs, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the oscillators. Furthermore, the performance of the proposed TDC is analyzed, including non-idealities such as phase noise, mismatch, and PVT variations. The prototype 1-1 MASH TDC achieves integrated noise in 4 MHz signal bandwidth at 400 MS/s while consuming 6.55 mW in a 65 nm CMOS process.
Autors: Yu, W.;Kim, K.;Cho, S.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2014, volume: 61, issue:8, pages: 2281 - 2289
Publisher: IEEE
 
» A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications
Abstract:
Pub DtlEmbedded nonvolatile memory (eNVM) is considered to be a critical building block in future system-on-chip and microprocessor systems. Various eNVM technologies have been explored for high-density applications including dual-poly embedded flash (eflash), FeRAM, STT-MRAM, and RRAM. On the other end of the spectrum, logic-compatible eNVM such as e-fuse, anti-fuse, and single-poly eflash memories have been considered for moderate-density low-cost applications. In particular, single-poly eflash memory has been gaining momentum as it can be implemented in a generic logic process while supporting multiple program-erase cycles. One key challenge for single-poly eflash is enabling bit-by-bit re-write operation without a boosted bitline voltage as this could cause disturbance issues in the unselected wordlines. In this work, we present details of a bit-by-bit re-writable eflash memory implemented in a generic 65 nm logic process which addresses this key challenge. The proposed 6 T eflash memory cell can improve the overall cell endurance by eliminating redundant program/erase cycles while preventing disturbance issues in the unselected wordlines. We also provide details of special high voltage circuits such as a voltage-doubler based charge pump circuit and a multistory high-voltage switch, for generating a reliable high-voltage output without causing damage to the standard logic transistors.
Autors: Song, S.-H.;Chun, K.C.;Kim, C.H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1861 - 1871
Publisher: IEEE
 
» A Brief History of Metal-Clad Switchgear [History]
Abstract:
Metal-clad switchgear has been a workhorse of medium-voltage distribution systems, both industrial and utility, for nearly 80 years. While changes in this equipment have not been nearly as frequent as in some other types of equipment, such as variable-frequency electronic drives, during that period, there were many developments in the design and application of metal-clad switchgear. However, since it has a normal service life of 40 years or so, rapid change in equipment design is not demanded by the users.
Autors: Bridger, B.;Brusso, B.;
Appeared in: IEEE Industry Applications Magazine
Publication date: Aug 2014, volume: 20, issue:4, pages: 7 - 81
Publisher: IEEE
 
» A Broadband Sensor Interface IC for Miniaturized Dielectric Spectroscopy From MHz to GHz
Abstract:
This paper describes a broadband sensor interface IC as part of a miniaturized measurement platform for MHz-to-GHz dielectric spectroscopy. Developed in 0.35 µm 2P/4M RF CMOS, the IC measures frequency-dependent S 21 magnitude and phase of a microfluidic dielectric sensor fabricated in a thick gold-on-glass microfabrication process and loaded with a material-under-test (MUT). The IC architecture implements a broadband frequency response analysis (bFRA) method by first down-converting the sensor response signal from the RF excitation frequency to an intermediate frequency (IF) of 1 MHz using a low-noise amplifier (LNA) and active mixer, followed by down-converting the IF signal to dc using a coherent detector employing IF amplification stages with programmable gain, a passive mixer driven by in-phase (I) and quadrature-phase (Q) signals and an active-RC low-pass filter (LPF). The sensor interfaced with the IC is fully capable of differentiating among deionized (DI) water, phosphate buffered saline (PBS), ethanol and methanol in tests conducted at four different excitation frequencies of 50 MHz, 500 MHz, 1 GHz and 3 GHz. Further, dielectric readings of ethanol from the sensor interfaced with the IC at five excitation frequencies in the range of 50 MHz to 2 GHz are in excellent agreement (error <1%) with those from using a vector network analyzer (VNA) as the sensor readout. A bulk-solution reference measurement by an Agilent 85070E dielectric probe kit interfaced with a VNA is also performed to verify proof-of-concept feasibility in conducting MHz-to-GHz dielectric spectroscopy with a miniaturized measurement platform using µL-sample volumes.
Autors: Bakhshiani, M.;Suster, M.A.;Mohseni, P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1669 - 1681
Publisher: IEEE
 
» A Cascaded Boost–Buck Converter for High-Efficiency Wireless Power Transfer Systems
Abstract:
Wireless power transfer (WPT) has attracted an ever increasing interest from both industry and academics over the past few years. Its applications vary from small power devices such as mobile phones and tablets to high power electric vehicles and from small transfer distance of centimeters to large distance of tens of centimeters. In order to achieve a high-efficiency WPT system, each circuit should function at a high efficiency along with the proper impedance matching techniques to minimize the power reflection due to the impedance mismatch. This paper proposes an analysis on the system efficiency to determine the optimal impedance requirement for coils, rectifier, and dc–dc converter. A novel cascaded boost–buck dc–dc converter is designed to provide the optimal impedance matching in WPT system for various loads including resistive load, ultracapacitors, and batteries. The proposed 13.56-MHz WPT system can achieve a total system efficiency over 70% in experiment.
Autors: Fu, M.;Ma, C.;Zhu, X.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Aug 2014, volume: 10, issue:3, pages: 1972 - 1980
Publisher: IEEE
 
» A case for assisted partial timing support using precision timing protocol packet synchronization for LTE-A
Abstract:
North American service providers are in the process of upgrading their radio access networks with next generation LTE equipment. They are finalizing a 4G rollout that involves highly stringent timing requirements, but in many cases they are relying on sole-source synchronization by using Global Navigation Satellite System (GNSS). Natural occurring disturbances, as well as unintentional radio frequency jamming, intentional jamming, and spoofing, make GNSS vulnerable to interference. This article presents a novel approach for addressing the issue of GNSS vulnerability by introducing a standard means of providing a redundant packet-based synchronization source for LTE base stations. It also describes how this new approach can mitigate noise caused by asymmetry and transit delay variation in packet networks.
Autors: Pearson, T.;Shenoi, K.;
Appeared in: IEEE Communications Magazine
Publication date: Aug 2014, volume: 52, issue:8, pages: 136 - 143
Publisher: IEEE
 
» A Characterization of the Orthogonal Grid Constructions of Copulas
Abstract:
A framework for constructing copulas that can be regarded as a patchwork-like assembly of arbitrary copulas, with nonoverlapping rectangles as patches, is studied in [B. De Baets and H. De Meyer, “Orthogonal grid constructions of copulas,” IEEE Trans. Fuzzy Syst., vol. 15, no. 6, pp. 1053–1062, Dec. 2007], where the authors provide sufficient conditions to derive a family of construction methods. Our aim in this paper is to provide a characterization of such constructions.
Autors: Sanchez, J.F.;Ubeda-Flores, M.;
Appeared in: IEEE Transactions on Fuzzy Systems
Publication date: Aug 2014, volume: 22, issue:4, pages: 1045 - 1047
Publisher: IEEE
 
» A CMOS Broadband Distributed -Path Tunable Bandpass Filter
Abstract:
A distributed CMOS -path tunable band-pass filter (BPF) technique is introduced to lower the in-band insertion loss and increase the out-of-band rejection of the traditional -path filter. Measurements from 0.3 to 1.6 GHz demonstrate a tunable BPF with 31 to 53 dB out-of-band rejection in a 65 nm process.
Autors: Thomas, C.M.;Larson, L.E.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2014, volume: 24, issue:8, pages: 542 - 544
Publisher: IEEE
 
» A Combination of Concentrator Photovoltaics and Water Cooling System to Improve Solar Energy Utilization
Abstract:
In this paper, concentrator photovoltaics (CPVs) were used to integrate the extraction of light energy and thermal energy. The water cooling system that is proposed in this paper provides effective cooling by circulating cold water to remove heat in the photovoltaics. The experimental results were subsequently analyzed and compared with the power generation efficiency of the examined photovoltaics. The use of a water-circulation cooling system improves the power capacity of the photovoltaics by 2%–15% and enhances the power generation efficiency of the photovoltaics by 2.29%–3.37%. Through the combined application of photovoltaic and thermal technologies, the total energy of the overall system can be improved by 37%–59% even after accounting for the energy consumption of the cooling system. As a result, environmental protection, energy savings, and an increase in the efficiency of sunlight utilization can be achieved. Finally, a neural network was used to optimize this increase in efficiency.
Autors: Kuo, M.;Lo, W.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Aug 2014, volume: 50, issue:4, pages: 2818 - 2827
Publisher: IEEE
 
» A Compact Dual-Polarized Printed Dipole Antenna With High Isolation for Wideband Base Station Applications
Abstract:
A compact dual-polarized printed dipole antenna for wideband base station applications is presented in this communication. The proposed dipole antenna is etched on three assembled substrates. Four horizontal triangular patches are introduced to form two dipoles in two orthogonal polarizations. Two integrated baluns connected with 50 SMA launchers are used to excite the dipole antenna. The proposed dipole antenna achieves a more compact size than many reported wideband printed dipole and magneto-electric dipole antennas. Both simulated and measured results show that the proposed antenna has a port isolation higher than 35 dB over 52% impendence bandwidth ( ). Moreover, stable radiation pattern with a peak gain of 7 dBi – 8.6 dBi is obtained within the operating band. The proposed dipole antenna is suitable as an array element and can be used for wideband base station antennas in the next generation IMT-advanced communications.
Autors: Gou, Y.;Yang, S.;Li, J.;Nie, Z.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2014, volume: 62, issue:8, pages: 4392 - 4395
Publisher: IEEE
 
» A Compact Hybrid Plasmonic Polarization Rotator for Silicon-Based Slot Waveguides
Abstract:
A compact polarization rotator (PR) for silicon-based slot waveguides is proposed, where a metal strip of aluminum (Al) is embedded in its upper-claddings. With the features of asymmetric hybrid plasmonic waveguide induced by the metal strip, an optimal optical axis rotation angle of 45° is realized, leading to high polarization conversion efficiency (PCE). The numerical results show that a PR of m in length at the wavelength of m is achieved with the PCE and insertion loss of 97.6% and 0.86 dB for TM-to-TE conversion, respectively. In addition, fabrication tolerances to the structural parameters are investigated and field evolution along the propagation distance through the PR is demonstrated.
Autors: Xu, Y.;Xiao, J.;Sun, X.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Aug 2014, volume: 26, issue:16, pages: 1609 - 1612
Publisher: IEEE
 
» A Compact Model of Program Window in HfOx RRAM Devices for Conductive Filament Characteristics Analysis
Abstract:
This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices.
Autors: Larcher, L.;Puglisi, F.M.;Pavan, P.;Padovani, A.;Vandelli, L.;Bersuker, G.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Aug 2014, volume: 61, issue:8, pages: 2668 - 2673
Publisher: IEEE
 
» A compact two-way high-power microwave combiner
Abstract:
A compact 2-way high-power microwave (HPM) waveguide combiner as an important equipment to realize the coherent microwave combination was theoretically designed, built, and proof-of-principle experimentally tested. The theoretical and experimental S-parameters are basically consistent with each other: return loss <−25 dB, and the isolation degree between 2-channels of the HPM combiner >25 dB to avoid the inter-modulating between the HPM sources. The C-band HPM experiment was carried out, and the power capacity of the HPM combiner was demonstrated to reach multi-gigawatts.
Autors: Chang, C.;Sun, J.;Xiong, Z.F.;Guo, L.T.;Liu, Y.S.;Zhang, Z.Q.;Wu, X.L.;
Appeared in: Review of Scientific Instruments
Publication date: Aug 2014, volume: 85, issue:8, pages: 084704 - 084704-5
Publisher: IEEE
 
» A Compact, Low-Profile Metasurface-Enabled Antenna for Wearable Medical Body-Area Network Devices
Abstract:
We propose a compact conformal wearable antenna that operates in the 2.36–2.4 GHz medical body-area network band. The antenna is enabled by placing a highly truncated metasurface, consisting of only a two by two array of I-shaped elements, underneath a planar monopole. In contrast to previously reported artificial magnetic conducting ground plane backed antenna designs, here the metasurface acts not only as a ground plane for isolation, but also as the main radiator. An antenna prototype was fabricated and tested, showing a strong agreement between simulation and measurement. Comparing to previously proposed wearable antennas, the demonstrated antenna has a compact form factor of , all while achieving a 5.5% impedance bandwidth, a gain of 6.2 dBi, and a front-to-back ratio higher than 23 dB. Further numerical and experimental investigations reveal that the performance of the antenna is extraordinarily robust to both structural deformation and human body loading, far superior to both planar monopoles and microstrip patch antennas. Additionally, the introduced metal backed metasurface enables a 95.3% reduction in the specific absorption rate, making such an antenna a prime candidate for incorporation into various wearable devices.
Autors: Jiang, Z.H.;Brocker, D.E.;Sieber, P.E.;Werner, D.H.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2014, volume: 62, issue:8, pages: 4021 - 4030
Publisher: IEEE
 
» A Comparative Study on the Effects of Annealing on the Characteristics of Zinc Oxide Thin-Film Transistors With Gate-Stacks of Different Gas-Permeability
Abstract:
The effects of different thermal processing on the characteristics of zinc oxide (ZnO) thin-film transistors (TFTs) with either gas-permeable or sealed gate-stack were studied and compared. The characteristics of a TFT heat-treated in a nonoxidizing ambience or under a sealed configuration degraded with increasing annealing temperature, though the former offered a comparatively wider process margin. On the other hand, the oxidization of the channel region of a TFT allowed by a gas-permeable gate-stack resulted in significant improvement in the transistor characteristics, e.g., eliminating the hysteresis and increasing the field-effect mobility to a relatively high value of 55 cm2/Vs. The difference in behavior is attributed to the annealing-dependent generation and annihilation of defects in ZnO under different coverage configurations, and suggests a general guideline on the thermal processing of ZnO TFTs.
Autors: Lu, L.;Li, J.;Wong, M.;
Appeared in: IEEE Electron Device Letters
Publication date: Aug 2014, volume: 35, issue:8, pages: 841 - 843
Publisher: IEEE
 
» A Comparison of Real-Time Thermal Rating Systems in the U.S. and the U.K.
Abstract:
Real-time thermal rating is a smart-grid technology that allows the rating of electrical conductors to be increased based on local weather conditions. Overhead lines are conventionally given a conservative, constant seasonal rating based on seasonal and regional worst case scenarios rather than actual, say, local hourly weather predictions. This paper provides a report of two pioneering schemes—one in the U.S. and one in the U.K.—where real-time thermal ratings have been applied. Thereby, we demonstrate that observing the local weather conditions in real time leads to additional capacity and safer operation. Second, we critically compare both approaches and discuss their limitations. In doing so, we arrive at novel insights which will inform and improve future real-time thermal rating projects.
Autors: Greenwood, D.M.;Gentle, J.P.;Myers, K.S.;Davison, P.J.;West, I.J.;Bush, J.W.;Ingram, G.L.;Troffaes, M.C.M.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Aug 2014, volume: 29, issue:4, pages: 1849 - 1858
Publisher: IEEE
 
» A Compensation Technique for Two-Stage Differential OTAs
Abstract:
In this brief, a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3-dB bandwidth, the unity gain frequency, and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole. The phase margin shows good robustness against process and temperature variations. The proposed technique poses no design constraints on the transconductance or capacitor values, which makes it attractive for low-power applications with low area overhead.
Autors: Abdulaziz, M.;Tormanen, M.;Sjoland, H.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2014, volume: 61, issue:8, pages: 594 - 598
Publisher: IEEE
 
» A Correlation Between Oxygen Vacancies and Reliability Characteristics in a Single Zirconium Oxide Metal-Insulator-Metal Capacitor
Abstract:
A correlation between reliability characteristics and failure mechanisms for time-dependent dielectric breakdown for a single ZrO2 metal–insulator–metal capacitor has been studied. Frenkel-Poole emission was the dominant mechanism in the high electric field region. The extracted dynamic constant and trap energy level were 4.013 and 0.963 eV, respectively. The variation of as a function of stress time under constant voltage stress (CVS) gradually decreased. Moreover, C /C under dynamic voltage stress was much greater than under CVS, which indicates that new defects and charge trapping could be generated in high- (HK) dielectric under dynamic voltage stress under negative voltage as well as positive voltage. The extracted average value of the Weibull slope ( ) at 125 °C was in the range 1.3–1.6. The average field acceleration parameter was cm/MV, and an effective dipole moment of bond breakage p was e Å. The thermochemical model (E model) suggested that the oxygen vacancies induced by the dipolar energy contribution (p (cdot ) E ) easily caused bond breakage in the HK dielectric. The energy required to form another V was weakened to the bond strength of polar molecules. The characteristic breakdown strength (E ) of ZrO2 was 6.31 MV/cm, and the extracted activation energy H was 1.874 eV when considering E model.
Autors: Kwon, H.;Kwon, S.;Jeong, K.;Oh, S.;Oh, S.;Choi, W.;Kim, T.;Kim, D.;Kang, C.;Lee, B.H.;Kirsch, P.;Lee, H.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Aug 2014, volume: 61, issue:8, pages: 2619 - 2627
Publisher: IEEE
 
» A coupling of martensitic and metamagnetic transitions with collective magneto-volume and table-like magnetocaloric effects
Abstract:
A coupling of the first-order paramagnetic-to-induced-ferromagnetic martensitic and the second-order antiferromagnetic-to-ferromagnetic metamagnetic transitions was found in MnNi0.8Fe0.2Ge alloy. Based on the coupling, a magneto-volume effect driven by the martensitic transition and a table-like magnetocaloric effect generated by the successive magnetic phase transitions arise collectively. By using the magneto-volume effect, the internal stress in the volume-expansion martensitic transition was determined at 350 MPa. The magnetocaloric effect, with a wide working temperature range of 26 K around room temperature, shows a small hysteresis loss (5 J kg−1) and a large net refrigerant capacity (157 J kg−1).
Autors: Liu, E.K.;Wei, Z.Y.;Li, Y.;Liu, G.D.;Luo, H.Z.;Wang, W.H.;Zhang, H.W.;Wu, G.H.;
Appeared in: Applied Physics Letters
Publication date: Aug 2014, volume: 105, issue:6, pages: 062401 - 062401-5
Publisher: IEEE
 
» A Cross-Correlation Method in Wavelet Domain for Demodulation of FBG-FP Static-Strain Sensors
Abstract:
Static-strain can be detected by measuring a cross-correlation of two FBG-based Fabry–Pérot interferometers (FBG-FPs). This letter addresses applying the wavelet transform to cross-correlation processing in noise-contaminated FBG-FP reflection spectrums for crust deformation measurement. Since the wavelet transform has a unique feature of varying time-frequency resolution, cross-correlation processing in the wavelet domain is more robust with correlated noise and window size and is less sensitive to nonstationary data. We discuss the experimental results in respect of the factors that could influence the sensor resolution. In addition, a staticstrain resolution of 1.3 n , higher than conventional cross-correlation method is obtained in the laboratory test by using this technique.
Autors: Huang, W.;Zhang, W.;Zhen, T.;Zhang, F.;Li, F.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Aug 2014, volume: 26, issue:16, pages: 1597 - 1600
Publisher: IEEE
 
» A dc–dc Converter for a Fully Integrated PID Compensator With a Single Capacitor
Abstract:
In this brief, proportional–integral–derivative (PID) compensation with a single capacitor for a fully integrated controller employed in a direct current–direct current converter operating in a voltage mode is presented. To make up a compact-area on-chip controller, a novel compensator is proposed, utilizing the ac ripple current of the inductor, which enables the PID controller to be implemented with only one capacitor and one resistor. The converter runs not only in a continuous conduction mode but also in a discontinuous conduction mode. The bandwidth of the overall loop is 120–200 kHz, which supports a fast transient response at a switching frequency of 1 MHz. The stability of the loop is guaranteed by theoretical analysis and experimental results to validate the proposed concept. The settling time is less than 85 at a load change of 1 A, and overshoot/undershoot voltages are within 50 mV. The buck converter with an input of 3.6 V and an output of 2.5 V for a maximum power of 3.125 W is fabricated in the 0.35- CMOS process, occupying a die area of 0.75 .
Autors: Park, H.;Cho, G.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2014, volume: 61, issue:8, pages: 629 - 633
Publisher: IEEE
 
» A Decision Procedure for Deadlock-Free Routing in Wormhole Networks
Abstract:
Deadlock freedom is a key challenge in the design of communication networks. Wormhole switching is a popular switching technique, which is also prone to deadlocks. Deadlock analysis of routing functions is a manual and complex task. We propose an algorithm that automatically proves routing functions deadlock-free or outputs a minimal counter-example explaining the source of the deadlock. Our algorithm is the first to automatically check a necessary and sufficient condition for deadlock-free routing. We illustrate its efficiency in a complex adaptive routing function for torus topologies. Results are encouraging. Deciding deadlock freedom is co-NP-Complete for wormhole networks. Nevertheless, our tool proves a 13 × 13 torus deadlock-free within seconds. Finding minimal deadlocks is more difficult. Our tool needs four minutes to find a minimal deadlock in a 11 × 11 torus while it needs nine hours for a 12 × 12 network.
Autors: Verbeek, F.;Schmaltz, J.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Aug 2014, volume: 25, issue:8, pages: 1935 - 1944
Publisher: IEEE
 
» A Decision-Directed Adaptive Gain Equalizer for Assistive Hearing Instruments
Abstract:
Assistive hearing instruments have a significant impact on speech enhancement when the signal-to-noise ratio is low. These instruments are usually developed using the conventional adaptive gain equalizer (AGE), which has low computational complexity and low distortion in real-time speech enhancement. The conventional AGEs are intended to boost the speech segments of speech signals but they are incapable of suppressing noise segments. The overall speech quality of the assistive hearing instruments may be reduced, as the noise segments still cannot be filtered out. In this paper, a decision-directed AGE is proposed for assistive hearing instruments. It aims to overcome the limitation of the conventional AGE, which is capable only of boosting speech segments in noisy speech but incapable of suppressing noise segments. The proposed approach simultaneously boosts the speech segments and suppresses noise segments in noisy speech. Experimental results with different types of real-world noise indicate that the proposed method achieves better speech quality than does the conventional AGE. The resulting method provides an improved functionality for assistive hearing instruments.
Autors: Kit Yan Chan;Siow Yong Low;Nordholm, S.;Yiu, K.F.C.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Aug 2014, volume: 63, issue:8, pages: 1886 - 1895
Publisher: IEEE
 
» A Decoupling Technique for Four-Element Symmetric Arrays With Reactively Loaded Dummy Elements
Abstract:
A decoupling technique for a symmetric four-element compact array is proposed. A dummy array terminated with optimum reactive loads is introduced to cancel the mutual couplings between the four radiating elements. A theory that leads to a general design procedure is developed. The technique is demonstrated by three practical design examples, including a compact and low-profile “cheese-cake” antenna array. Calculated channel capacities demonstrate that the performance of a 4-by-4 MIMO communication system that uses the cheese-cake array can be significantly improved as compared to the system using its coupled counterpart. This technique provides a promising approach to the design of a compact four-element array for a MIMO communication system.
Autors: Zhao, L.;Wu, K.-L.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2014, volume: 62, issue:8, pages: 4416 - 4421
Publisher: IEEE
 
» A Design Method for the Asymmetric Artificial Network With an Asymmetrical Transformer
Abstract:
Conducted asymmetric disturbances are measured at telecommunication ports of equipment under test using an asymmetric artificial network (AAN). Therefore, theoretical investigations are carried out to characterize an AAN with a mode-impedance matrix, introducing the common-mode and differential-mode impedances. By referring to this matrix, a theoretical design method is developed for the AAN with an asymmetrical transformer to satisfy the requirements for the mode impedances and the longitudinal conversion loss. By using this design method, two different prototype AANs are assembled: one meets the CISPR 22 specifications, and the other is used in power line telecommunication modem tests. A detailed experimental examination of the assembled AANs validates the proposed theoretical design method.
Autors: Hirasawa, N.;Akiyama, Y.;Amemiya, F.;Sugiura, A.;Kami, Y.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Aug 2014, volume: 56, issue:4, pages: 903 - 911
Publisher: IEEE
 
» A Development and Testing Instrumentation for GPS Software Defined Radio With Fast FPGA Prototyping Support
Abstract:
The modernization of global positioning systems (GPS) boosts the development of civil and military applications as accuracy and coverage of receivers continually improve. Recently, software defined radio (SDR) approach for GPS receivers (GPS-SDR) gained attention because of its flexibility for multimode operations in different environments. The SDR receiver developers continually advance algorithmic and/or hardware accelerator solutions. However, they need fast prototyping and testing instrumentation to refine and evaluate high performance multimode receivers. This paper presents a feasibility study of fast prototyping of the GPS receiver accelerators using graphical user interface environments. It also describes a testbed with integrated RF front-ends, GPS simulator, receiver, and assistance support. Particularly, a novel host-target codesign solution is demonstrated using a field programmable gate array (FPGA) peripheral and LabVIEW FPGA tool for a case study of a GPS acquisition module. Distributing tasks between the FPGA target and the personal computer host achieves a high performance solution. The fast prototyped solution is compared with a conventional FPGA and state-of-the-art implementations.
Autors: Soghoyan, A.;Suleiman, A.;Akopian, D.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Aug 2014, volume: 63, issue:8, pages: 2001 - 2012
Publisher: IEEE
 
» A Difference of Convex Functions Algorithm for Switched Linear Regression
Abstract:
This technical note deals with switched linear system identification and more particularly aims at solving switched linear regression problems in a large-scale setting with both numerous data and many parameters to learn. We consider the recent minimum-of-error framework with a quadratic loss function, in which an objective function based on a sum of minimum errors with respect to multiple submodels is to be minimized. The technical note proposes a new approach to the optimization of this nonsmooth and nonconvex objective function, which relies on Difference of Convex (DC) functions programming. In particular, we formulate a proper DC decomposition of the objective function, which allows us to derive a computationally efficient DC algorithm. Numerical experiments show that the method can efficiently and accurately learn switching models in large dimensions and from many data points.
Autors: Pham Dinh, T.;Le, H.M.;Le Thi, H.A.;Lauer, F.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Aug 2014, volume: 59, issue:8, pages: 2277 - 2282
Publisher: IEEE
 
» A Digitally Assisted, Signal Folding Neural Recording Amplifier
Abstract:
A novel signal folding and reconstruction scheme for neural recording applications that exploits the characteristics of neural signals is described in this paper. The amplified output is ‘folded’ into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 and power dissipation of 2.52 leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of t- is amplifier to simultaneously record spike and LFP signals.
Autors: Chen, Y.;Basu, A.;Liu, L.;Zou, X.;Rajkumar, R.;Dawe, G.S.;Je, M.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Aug 2014, volume: 8, issue:4, pages: 528 - 542
Publisher: IEEE
 
» A Discontinuous Galerkin Time Domain Framework for Periodic Structures Subject to Oblique Excitation
Abstract:
A nodal discontinuous Galerkin (DG) method is derived for the analysis of time-domain (TD) scattering from doubly periodic PEC/dielectric structures under oblique interrogation. Field transformations are employed to elaborate a formalism that is free from any issues with causality that are common when applying spatial periodic boundary conditions simultaneously with incident fields at arbitrary angles of incidence. An upwind numerical flux is derived for the transformed variables, which retains the same form as it does in the original Maxwell problem for domains without explicitly imposed periodicity. This, in conjunction with the amenability of the DG framework to non-conformal meshes, provides a natural means of accurately solving the first order TD Maxwell equations for a number of periodic systems of engineering interest. Results are presented that substantiate the accuracy and utility of our method.
Autors: Miller, N.C.;Baczewski, A.D.;Albrecht, J.D.;Shanker, B.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2014, volume: 62, issue:8, pages: 4386 - 4391
Publisher: IEEE
 
» A Distributed Multi-Agent Command Governor Strategy for the Coordination of Networked Interconnected Systems
Abstract:
A novel distributed coordination strategy is presented for networked, locally regulated and possibly dynamically coupled, interconnected systems. Such systems are assumed to be connected via data links and subject to pointwise-in-time global constraints on some relevant variables of them, to be enforced as a coordination goal along the overall system evolutions. Such a coordination-by-constraint paradigm is accomplished by resorting to a novel distributed multi-agent Command Governor (CG) approach where each agent is in charge to locally modify, whenever necessary and on the basis of a reduced amount of data exchanged with the other agents, the prescribed set-points to the regulated subsystems so that the coordination constraints are always satisfied. The strategy is described and its main properties analyzed, especially for what it concerns the stability, feasibility and Pareto optimality of the solution. A liveness analysis concerning the possible presence of undesirable Nash equilibria and/or deadlock situations is presented and a discussion on the scalability of the solution with the problem dimension is reported as well. The constrained coordination of a network of interconnected water tanks is presented as a final example in order to show the effectiveness of the proposed strategy.
Autors: Casavola, A.;Garone, E.;Tedesco, F.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Aug 2014, volume: 59, issue:8, pages: 2099 - 2112
Publisher: IEEE
 
» A Domain Decomposition Method for Boundary Integral Equations Using a Transmission Condition Based on the Near-Zone Couplings
Abstract:
A domain decomposition method (DDM) for the solution of boundary integral equations for impenetrable objects is presented. The approach uses a transmission condition which is based on the near-range couplings. In order to obtain close approximations of the global solution on the subdomains, the comparatively strong near-zone interactions are taken into account to avoid unphysical reflections from the domain interfaces. The algorithm can be accelerated by fast integral solvers such as the multilevel fast multipole method (MLFMM) by creating local subtrees, which coincide with the different computing domains. This concept is embedded in an inner-outer iterative solution algorithm in which the DDM acts as a preconditioner in the inner iterations. By introducing small overlap regions, the convergence of the iterative solver is further improved. This results in a very robust DDM which can be integrated into existing codes with reasonable effort and which is suited for parallelization. Numerical results for various open and closed objects demonstrate the effectiveness and the excellent performance of the proposed DDM for the solution of electromagnetic radiation and scattering problems.
Autors: Wiedenmann, O.;Eibert, T.F.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2014, volume: 62, issue:8, pages: 4105 - 4114
Publisher: IEEE
 
» A DSP for Sensing the Bladder Volume Through Afferent Neural Pathways
Abstract:
In this paper, we present a digital signal processor (DSP) capable of monitoring the urinary bladder volume through afferent neural pathways. The DSP carries out real-time detection and can discriminate extracellular action potentials, also known as on-the-fly spike sorting. Next, the DSP performs a decoding method to estimate either three qualitative levels of fullness or the bladder volume value, depending on the selected output mode. The proposed DSP was tested using both realistic synthetic signals with a known ground-truth, and real signals from bladder afferent nerves recorded during acute experiments with animal models. The spike sorting processing circuit yielded an average accuracy of 92% using signals with highly correlated spike waveforms and low signal-to-noise ratios. The volume estimation circuits, tested with real signals, reproduced accuracies achieved by offline simulations in Matlab, i.e., 94% and 97% for quantitative and qualitative estimations, respectively. To assess feasibility, the DSP was deployed in the Actel FPGA Igloo AGL1000V2, which showed a power consumption of 0.5 mW and a latency of 2.1 ms at a 333 kHz core frequency. These performance results demonstrate that an implantable bladder sensor that perform the detection, discrimination and decoding of afferent neural activity is feasible.
Autors: Mendez, A.;Belghith, A.;Sawan, M.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Aug 2014, volume: 8, issue:4, pages: 552 - 564
Publisher: IEEE
 
» A Family of Optimal Locally Recoverable Codes
Abstract:
A code over a finite alphabet is called locally recoverable (LRC) if every symbol in the encoding is a function of a small number (at most r ) other symbols. We present a family of LRC codes that attain the maximum possible value of the distance for a given locality parameter and code cardinality. The codewords are obtained as evaluations of specially constructed polynomials over a finite field, and reduce to a Reed-Solomon code if the locality parameter r is set to be equal to the code dimension. The size of the code alphabet for most parameters is only slightly greater than the code length. The recovery procedure is performed by polynomial interpolation over r points. We also construct codes with several disjoint recovering sets for every symbol. This construction enables the system to conduct several independent and simultaneous recovery processes of a specific symbol by accessing different parts of the codeword. This property enables high availability of frequently accessed data (“hot data”).
Autors: Tamo, I.;Barg, A.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Aug 2014, volume: 60, issue:8, pages: 4661 - 4676
Publisher: IEEE
 
» A Flexible Pinhole Camera Model for Coherent Nonuniform Sampling
Abstract:
The flexible pinhole camera (FPC) allows flexible modulation of the sampling rate over the field of view. The FPC is defined by a viewpoint and a map specifying the sampling locations on the image plane. The map is constructed from known regions of interest with interactive and automatic approaches. The FPC provides inexpensive 3D projection that allows rendering complex datasets quickly, in feed-forward fashion, by projection followed by rasterization. The FPC supports many types of data, including image, height field, geometry, and volume data. The resulting image is a coherent nonuniform sampling (CoNUS) of the dataset that matches the local variation of the dataset's importance. CoNUS images have been successfully implemented for remote visualization, focus-plus-context visualization, and acceleration of expensive rendering effects such as surface geometric detail and specular reflection. A video explaining and demonstrating the FPC is at http://youtu.be/kvFe5XjOPNM.
Autors: Popescu, Voicu;Benes, Bedrich;Rosen, Paul;Cui, Jian;Wang, Lili;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Aug 2014, volume: 34, issue:4, pages: 30 - 41
Publisher: IEEE
 
» A Fluidic Loading Mechanism in a Polarization Reconfigurable Antenna With a Comparison to Solid State Approaches
Abstract:
This work proposes a polarization-reconfigurable antenna composed of two independent, co-located, and orthogonal (“crossed”) narrow microstrip patch antennas with a novel pressure-driven fluidic loading network. Repeating and alternating high-low dielectric constant fluids in the network excite the two patches independently through capacitive coupling. A second iteration of this design with RF PIN diodes allows for a comparison between the fluidic reconfiguration mechanism and current state-of-the-art approaches. Circuit models for the antenna with each reconfiguration mechanism are developed to better understand the impacts on antenna performance. Furthermore, these models show good agreement with full-wave simulations and measured results taken from the two fabricated prototype antennas. Pattern data shows good linear polarization switching with both designs. The two mechanisms are compared based on the impact to electrical size, radiation patterns, efficiency, and switching speed.
Autors: Barrera, J.D.;Huff, G.H.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2014, volume: 62, issue:8, pages: 4008 - 4014
Publisher: IEEE
 
» A Frequency Shaping Neural Recorder With 3 pF Input Capacitance and 11 Plus 4.5 Bits Dynamic Range
Abstract:
This paper presents a frequency-shaping (FS) neural recording architecture and its implementation in a 0.13 m CMOS process. Compared with its conventional counterpart, the proposed architecture inherently rejects electrode offset, increases input impedance 5–10 fold, compresses neural data dynamic range (DR) by 4.5-bit, simultaneously records local field potentials (LFPs) and extracellular spikes, and is more suitable for long-term recording experiments. Measured at a 40 kHz sampling clock and V supply, the recorder consumes 50 W/ch, of which 22 W per FS amplifier, 24 W per buffer, 4 W per 11-bit successive approximation register analog-to-digital converter (SAR ADC). The input-referred noise for LFPs and extracellular spikes are 13 Vrms and 7 Vrms, respectively, which are sufficient to achieve high-fidelity full-spectrum neural data. In addition, the designed recorder has a 3 pF input capacitance and allows “ ”-bit neural data DR without system saturation, where the extra 4.5-bit owes to the FS technique. Its figure-of-merit (FOM) based on data DR reaches 36.0 fJ/conversion-step.
Autors: Xu, J.;Wu, T.;Liu, W.;Yang, Z.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Aug 2014, volume: 8, issue:4, pages: 510 - 527
Publisher: IEEE
 
» A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes
Abstract:
Pub DtlWe propose a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. A conventional approach to generate these currents is to drop a temperature sensitive voltage across a resistor. Since a large resistance is required to achieve nWs of power consumption with typical voltage levels (100 s of mV to 1 V), we introduce a new sensing element that outputs only 75 mV to save both power and area. The sensor is implemented in 0.18 m CMOS and occupies 0.09 mm while consuming 71 nW. After 2-point calibration, an inaccuracy of is achieved across 0 C to 100 C. With a conversion time of 30 ms, 0.3 C (rms) resolution is achieved. The sensor does not require any external references and consumes 2.2 nJ per conversion. The sensor is integrated into a wireless sensor node to demonstrate its operation at a system level.
Autors: Jeong, S.;Foo, Z.;Lee, Y.;Sim, J.-Y.;Blaauw, D.;Sylvester, D.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Aug 2014, volume: 49, issue:8, pages: 1682 - 1693
Publisher: IEEE
 
» A Fully-Integrated 77-GHz UWB Pseudo-Random Noise Radar Transceiver With a Programmable Sequence Generator in SiGe Technology
Abstract:
This paper describes a fully-integrated 77-GHz ultra-wideband pseudo-random noise (PRN) radar transceiver in a Silicon-Germanium technology. The transceiver is equipped with a programmable pseudo-random binary sequence (PRBS) generator, which is realized in a current-mode logic topology and can be operated with a clock rate of up to 4.25 GHz to enable a range resolution of 3.5 cm. The signal generation unit is simplified by including a frequency multiplier to create a 76.5-GHz carrier signal from a single 4.25-GHz input, that is also used as a clock for the PRBS generator. The transceiver achieves a phase noise of 105.3 dBc/Hz at 1-MHz offset frequency, a transmit output power of 6.2 dBm, a receive gain of 24 dB and an input-referred 1-dB compression point of 14 dBm. Track&hold circuits included in the receive path allow the use of a sub-sampling technique to reduce the IF data rate down to 1 MHz. Radar measurements with two PRN transceivers with different primitive polynomials were done concurrently to show a fundamental function of the programmable PRBS generator. Radar measurements with the PRN and the frequency-modulated continuous-wave (FMCW) principles show comparable results and the PRN radar proves to be a real alternative to the FMCW radar.
Autors: Ng, H.J.;Feger, R.;Stelzer, A.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Aug 2014, volume: 61, issue:8, pages: 2444 - 2455
Publisher: IEEE
 
» A gold hybrid structure as optical coupler for quantum well infrared photodetector
Abstract:
A hybrid structure consisting of a square lattice of gold disk arrays and an overlaying gold film is proposed as an optical coupler for a backside-illuminated quantum well infrared photodetector (QWIP). Finite difference time-domain method is used to numerically simulate the reflection spectra and the field distributions of the hybrid structure combined with the QWIP device. The results show that the electric field component perpendicular to the quantum well is strongly enhanced when the plasmonic resonant wavelength of the hybrid structure coincides with the response one of the quantum well infrared photodetector regardless of the polarization of the incident light. The effect of the diameter and thickness of an individual gold disk on the resonant wavelength is also investigated, which indicates that the localized surface plasmon also plays a role in the light coupling with the hybrid structure. The coupling efficiency can exceed 50 if the structural parameters of the gold disk arrays are well optimized.
Autors: Ding, Jiayi;Chen, Xiaoshuang;Li, Qian;Jing, Youliang;Li, Zhifeng;Li, Ning;Lu, Wei;
Appeared in: Journal of Applied Physics
Publication date: Aug 2014, volume: 116, issue:8, pages: 083101 - 083101-6
Publisher: IEEE
 
» A GPS L2C Signal Programmable Correlator
Abstract:
The Global Position System (GPS) is currently modernizing its signals. The L2C signal was incorporated in 2005 for civil use as a complement of the L1 signal. Having several signals in different bands lets the receiver correct the errors caused by the ionosphere efficiently and provide not only a major protection against interferences but also a better exactitude in the position calculation. In this paper, the design and implementation of a correlation channel for the GPS-L2C signal using Field Programmable Gate Arrays (FPGA) are presented. The correlation channels give the receiver essential information about the synchronism state with the received signals. With this information the receiver is able to synchronize with the signals coming from the satellites, demodulate the data and calculate its position and speed. Both the outstanding aspects of the implemented architecture as well as the most relevant results obtained from the validation tests are shown.
Autors: Gabriel Diaz, Juan;Gonzalo Garcia, Javier;Augustin Roncagliolo, Pedro;
Appeared in: IEEE Latin America Transactions
Publication date: Aug 2014, volume: 12, issue:5, pages: 841 - 846
Publisher: IEEE
 
» A green data transmission mechanism for wireless multimedia sensor networks using information fusion
Abstract:
In recent years, the workmanship of manufacturing sensors has achieved great success. The wide application of inexpensive hardware, such as complementary metal oxide semiconductor cameras and tiny microphones, has contributed to the development of WMSNs. WMSNs are composed of wirelessly connected devices that are able to collect information from the environment at any time. Most often, the types of information collected by WMSNs are video and audio streams, still images, and scalar sensor data. As with wireless sensor networks, the sensor devices in WMSNs are also strictly constrained in terms of memory, processing capability, storage capability, and especially energy. Although batteries can provide wireless sensors with energy, the energy is extremely limited. In practical applications, it is impossible for WMSNs to upload all of the multimedia data to users in remote regions. Hence, it is significant to develop energy-efficient techniques for data communication in WMSNs by in-network processing. In this article, a mechanism based on information fusion is proposed for reducing the volume of data being transferred. The mechanism is a trade-off between uploading the results of in-network data processing and uploading all of the raw data. Based on users' requirements, proper data will be uploaded, and the accuracy of querying will be as good as, or better than, uploading all of the raw data. Finally, the shortcomings and challenges of the mechanism are also described.
Autors: Zhang, Z.-J.;Lai, C.-F.;Chao, H.-C.;
Appeared in: IEEE Wireless Communications
Publication date: Aug 2014, volume: 21, issue:4, pages: 14 - 19
Publisher: IEEE
 
» A Grid-Level High-Power BTB (Back-To-Back) System Using Modular Multilevel Cascade Converters WithoutCommon DC-Link Capacitor
Abstract:
This paper provides an intensive discussion on analysis, simulation, and experiment of a back-to-back (BTB) systemunifying two modular multilevel cascade converters based on double-star chopper cells (MMCCs-DSCCs). Each of the twoDSCCs connected back-to-back consists of multiple cascaded chopper cells and a center-tapped inductor per leg. Lowvoltage steps bring significant reductions in harmonic voltage and current to the BTB system. Neither dc-link capacitornor voltage sensor is required for regulating the dc-link voltage and controlling the dc-link current. A three-phase200-V, 10-kW, 50-Hz downscaled BTB system with phase-shifted PWM is designed, constructed, and tested to verify itsoperating principles and performance. Analytical, simulated, and experimental results agree well with each other insteady and transient states. Experimental waveforms confirm the effectiveness of a self-starting/restartingprocedure.
Autors: Sekiguchi, K.;Khamphakdi, P.;Hagiwara, M.;Akagi, H.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Aug 2014, volume: 50, issue:4, pages: 2648 - 2659
Publisher: IEEE
 
» A high-temperature, ambient-pressure ultra-dry operando reactor cell for Fourier-transform infrared spectroscopy
Abstract:
The construction of a newly designed high-temperature, high-pressure FT-IR reaction cell for ultra-dry in situ and operando operation is reported. The reaction cell itself as well as the sample holder is fully made of quartz glass, with no hot metal or ceramic parts in the vicinity of the high-temperature zone. Special emphasis was put on chemically absolute water-free and inert experimental conditions, which includes reaction cell and gas-feeding lines. Operation and spectroscopy up to 1273 K is possible, as well as pressures up to ambient conditions. The reaction cell exhibits a very easy and variable construction and can be adjusted to any available FT-IR spectrometer. Its particular strength lies in its possibility to access and study samples under very demanding experimental conditions. This includes studies at very high temperatures, e.g., for solid-oxide fuel cell research or studies where the water content of the reaction mixtures must be exactly adjusted. The latter includes all adsorption studies on oxide surfaces, where the hydroxylation degree is of paramount importance. The capability of the reaction cell will be demonstrated for two selected examples where information and in due course a correlation to other methods can only be achieved using the presented setup.
Autors: Kock, Eva-Maria;Kogler, Michaela;Pramsoler, Reinhold;Klotzer, Bernhard;Penner, Simon;
Appeared in: Review of Scientific Instruments
Publication date: Aug 2014, volume: 85, issue:8, pages: 084102 - 084102-8
Publisher: IEEE
 
» A High-Throughput Zebrafish ScreeningMethod for Visual Mutants by Light-Induced Locomotor Response
Abstract:
Normal and visually-impaired zebrafish larvae have differentiable light-induced locomotor response (LLR), which is composed of visual and non-visual components. It is recently demonstrated that differences in the acute phase of the LLR, also known as the visual motor response (VMR), can be utilized to evaluate new eye drugs. However, most of the previous studies focused on the average LLR activity of a particular genotype, which left information that could address differences in individual zebrafish development unattended. In this study, machine learning techniques were employed to distinguish not only zebrafish larvae of different genotypes, but also different batches, based on their response to light stimuli. This approach allows us to perform efficient high-throughput zebrafish screening with relatively simple preparations. Following the general machine learning framework, some discriminative features were first extracted from the behavioral data. Both unsupervised and supervised learning algorithms were implemented for the classification of zebrafish of different genotypes and batches. The accuracy of the classification in genotype was over 80 percent and could achieve up to 95 percent in some cases. The results obtained shed light on the potential of using machine learning techniques for analyzing behavioral data of zebrafish, which may enhance the reliability of high-throughput drug screening.
Autors: Gao, Y.;Chan, R;Chow, T;Zhang, L.;Bonilla, S.;Pang, C.-P.;Zhang, M.;Leung, Y.F.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Aug 2014, volume: 11, issue:4, pages: 693 - 701
Publisher: IEEE
 
» A Highly Linear Integrated Temperature Sensor on a GaN Smart Power IC Platform
Abstract:
On a GaN smart power integrated circuit (IC) platform, a highly linear (i.e., proportional to absolute temperature) temperature sensor IC is demonstrated for building voltage references as well as temperature compensation functional blocks. The circuit is designed based on the temperature-dependent characteristics of GaN-based peripheral devices (e.g., heterojunction Schottky barrier diode, enhancement-/depletion-mode high electron mobility transistors, and lateral field-effect rectifiers) that are monolithically integrated with high-voltage power devices. This monolithic integration scheme facilitates the design efforts in taking full advantages of GaN’s superior capability to operate at high temperatures. Proper circuit operation was demonstrated at 275 °C.
Autors: Kwan, A.M.H.;Guan, Y.;Liu, X.;Chen, K.J.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Aug 2014, volume: 61, issue:8, pages: 2970 - 2976
Publisher: IEEE
 
» A Hybrid E-pulse Method for Discrimination of Conducting Scatterers in Resonance Region
Abstract:
Target scattered time domain response in the resonance region can be modelled by natural poles using the singularity expansion method (SEM). A hybrid of the conventional Extinction pulse (E-Pulse) and auto-regressive (AR) method is proposed in this communication for robust discrimination of radar targets. A new target discrimination number (TDN) is suggested, which gives enhanced discrimination margin for the decision process. The limitation of the conventional E-pulse method is highlighted using time domain responses of metallic cylinders of different radii obtained through simulations. The hybrid E-pulse technique is applied to scatterers in free space as well as under the surface and demonstrated to produce comfortable discrimination margins.
Autors: Singh, D.K.;Mohan, N.;Pande, D.C.;Bhattacharya, A.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Aug 2014, volume: 62, issue:8, pages: 4421 - 4425
Publisher: IEEE
 
» A Hybrid Model for Improved Hysteresis Loss Prediction in Electrical Machines
Abstract:
This paper presents a model for calculating the hysteresis loss in electrical machines. The model can achieve accurate and computationally efficient hysteresis loss calculations by utilizing both analytical equations and the Energetic hysteresis model. The model results are experimentally verified by comparing to a series of minor hysteresis loop measurements. The hybrid model is then implemented to calculate the core losses in a switched reluctance machine using finite-element simulation. The results show that precise machine core loss prediction requires having a model that is capable of calculating the hysteresis losses under a variety of minor hysteresis loops.
Autors: Ibrahim, M.;Pillay, P.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Aug 2014, volume: 50, issue:4, pages: 2503 - 2511
Publisher: IEEE
 
» A Hybrid PEEC–SPICE Method for Time-Domain Simulation of Mixed Nonlinear Circuits and Electromagnetic Problems
Abstract:
The simulation of mixed circuit and electromagnetic (EM) structures is of major interest in most EM applications. Many of the developed methods involve modifying a SPICE-like solver to incorporate an EM numerical method, or to extend the EM numerical method to handle the circuit components (e.g., diodes, transistors, etc.) by reimplementing their model definitions. A novel technique has been developed to simulate combined linear/nonlinear circuit and EM problems in time domain. This technique utilizes the partial element equivalent circuit method as the EM solver and employs OrCAD as the circuit solver. The link between the two solvers is established by defining the circuits connected to the EM structure as ports and approximating each port’s current–voltage relations at each time point by a system of linear equations. To demonstrate the capability of the developed method, four structures are examined. Good agreement of the results shows the feasibility of the developed method to solve this type of mixed problems. Since OrCAD is used for the circuit simulations, the need to modify a SPICE-like solver or to reimplement the definitions of the circuit devices has been removed. On the other hand, by manipulating the system of equations and proper optimization techniques, an optimal solver can be achieved.
Autors: Safavi, S.;Ekman, J.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Aug 2014, volume: 56, issue:4, pages: 912 - 922
Publisher: IEEE
 
» A Hybrid SIW and GCPW Guided-Wave Structure Coupler
Abstract:
Since substrate integrated waveguide (SIW) is not directly compatible with active circuits, additional transitions to planar transmission lines are indispensable. In this letter, a novel hybrid SIW-CPW structure coupler applying an antenna feeding network is presented. SIW is used as the radiating portion while coplanar waveguide (CPW) is the input matching portion that is connected directly to the active circuits. Without any transition structure, the whole system can be more compact. In addition, this hybrid coupler has a relative bandwidth of over 30% with the broadband amplitude and phase balance characteristic of CPW.
Autors: Guan, D.-F.;Qian, Z.-P.;Zhang, Y.-S.;Cai, Y.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Aug 2014, volume: 24, issue:8, pages: 518 - 520
Publisher: IEEE
 
» A Low Complexity Energy Efficiency Maximization Method for Multiuser Amplify-and-Forward MIMO Relay Systems With a Holistic Power Model
Abstract:
In this letter, we investigate the energy efficiency (EE) maximization problem in multiuser amplify-and-forward (AF) MIMO relay systems with a holistic power model. A low complexity EE maximization method is proposed to jointly select the active antennas and the user, as well as optimize the transmission power of the user and relay. More specifically, the active antennas at the relay are selected by a norm-based scheme. We also propose a low complexity iteration scheme based on fractional programming, which can efficiently solve the pseudo-concave problem, in order to select the user and optimize the transmission power. Simulation results show that the proposed low complexity method enjoys a probability of 99% to hit the optimal EE obtained by exhaustive search. Moreover, it has an average gain of 42% in the EE over the conventional AF MIMO relay protocol.
Autors: Zhou, X.;Bai, B.;Chen, W.;
Appeared in: IEEE Communications Letters
Publication date: Aug 2014, volume: 18, issue:8, pages: 1371 - 1374
Publisher: IEEE
 
» A Low Power Sub- W Chemical Gilbert Cell for ISFET Differential Reaction Monitoring
Abstract:
This paper presents a low power current-mode method for monitoring differentially derived changes in pH from ion-sensitive field-effect transistor (ISFET) sensors, by adopting the Chemical Gilbert Cell. The fabricated system, with only a few transistors, achieves differential measurements and therefore drift minimisation of continuously recorded pH signals obtained from biochemical reactions such as DNA amplification in addition to combined gain tunability using only a single current. Experimental results are presented, demonstrating the capabilities of the front-end at a microscopic level through integration in a lab-on-chip (LoC) setup combining a microfluidic assembly, suitable for applications that require differential monitoring in small volumes, such as DNA detection where more than one gene needs to be studied. The system was designed and fabricated in a typical 0.35 m CMOS process with the resulting topology achieving good differential pH sensitivity with a measured low power consumption of only 165 nW due to weak inversion operation. A tunable gain is demonstrated with results confirming 15.56 dB gain at 20 nA of ISFET bias current and drift reduction of up to 100 times compared to a single-ended measurement is also reported due to the differential current output, making it ideal for robust, low-power chemical measurement.
Autors: Kalofonou, M.;Toumazou, C.;
Appeared in: IEEE Transactions on Biomedical Circuits and Systems
Publication date: Aug 2014, volume: 8, issue:4, pages: 565 - 574
Publisher: IEEE
 
» A low temperature nonlinear optical rotational anisotropy spectrometer for the determination of crystallographic and electronic symmetries
Abstract:
Nonlinear optical generation from a crystalline material can reveal the symmetries of both its lattice structure and underlying ordered electronic phases and can therefore be exploited as a complementary technique to diffraction based scattering probes. Although this technique has been successfully used to study the lattice and magnetic structures of systems such as semiconductor surfaces, multiferroic crystals, magnetic thin films, and multilayers, challenging technical requirements have prevented its application to the plethora of complex electronic phases found in strongly correlated electron systems. These requirements include an ability to probe small bulk single crystals at the μm length scale, a need for sensitivity to the entire nonlinear optical susceptibility tensor, oblique light incidence reflection geometry, and incident light frequency tunability among others. These measurements are further complicated by the need for extreme sample environments such as ultra low temperatures, high magnetic fields, or high pressures. In this review we present a novel experimental construction using a rotating light scattering plane that meets all the aforementioned requirements. We demonstrate the efficacy of our scheme by making symmetry measurements on a μm scale facet of a small bulk single crystal of Sr2IrO4 using optical second and third harmonic generation.
Autors: Torchinsky, Darius H.;Chu, Hao;Qi, Tongfei;Cao, Gang;Hsieh, David;
Appeared in: Review of Scientific Instruments
Publication date: Aug 2014, volume: 85, issue:8, pages: 083102 - 083102-8
Publisher: IEEE
 
» A Low-Complexity ML Detection Algorithm for Spatial Modulation Systems With PSK Constellation
Abstract:
Spatial modulation (SM), which is a novel transmission scheme, is employed for active transmit antenna indexes and modulated signals to convey the information. To recover the transmitted information bits, the maximum likelihood (ML) joint detector is often used. However, its complexity linearly grows with the number of transmit antennas and the size of the signal set. A reduced-complexity ML optimal algorithm for SM systems with -QAM has been proposed. However, for -PSK modulation, there are not similar low-complexity ML detection algorithms yet to our knowledge. In this paper, a low-complexity ML detection algorithm for SM systems with -PSK modulation is proposed. By exploiting the features of -PSK constellation, we give the ML-estimated values of the transmitted symbols. Therefore, the ML search complexity is independent of the constellation size. Simulation results show that the proposed algorithm has the same performance as the ML-optimum detector and significant reduction in computational complexity compared with existing detectors for SM systems with -PSK modulation.
Autors: Men, H.;Jin, M.;
Appeared in: IEEE Communications Letters
Publication date: Aug 2014, volume: 18, issue:8, pages: 1375 - 1378
Publisher: IEEE
 
» A Low-Power 2.4-GHz Receiver Front End With a Lateral Current-Reusing Technique
Abstract:
A 2.4-GHz current-reused receiver front end is presented in this brief. Instead of using the traditional stack-on current-reusing scheme that compresses the voltage headroom, the proposed front end employs a lateral current-shunt branch to share most of the dc bias current of the transconductance transistors in an LNA and a mixer. To prevent the signal interaction between the two modules, an tank is inserted into the current-reusing path to cut off the radio-frequency signal path between the LNA and the mixer. The IF signal blocking is realized by inserting a cascode transistor that provides large impedance for the IF signal from the mixer. Theory analysis and simulation results indicate that the current-reusing structure improves the noise performance and only a small impact on the voltage gain. A prototype of the proposed front end is designed and fabricated in the 130-nm CMOS process. Measurement results indicate that the front end achieved a conversion gain of 25 dB, a double-sideband noise figure of 3.5 dB, and a third-order input intercept point (IIP3) of 13 dBm at an input frequency of 2.4 GHz. The dc consumption of the front end is 3 mA under a supply voltage of 1.2 V.
Autors: Chen, C.;Wu, J.;Huang, D.;Shi, L.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Aug 2014, volume: 61, issue:8, pages: 564 - 568
Publisher: IEEE
 
» A Low-Power Analog Baseband Section for 60-GHz Receivers in 90-nm CMOS
Abstract:
A low-power analog baseband section suitable for 60-GHz receivers using orthogonal frequency-division multiplexing (OFDM) with 16 quadrature amplitude modulation (16-QAM) modulation is presented in this paper. Power efficiency is achieved by combining active-RC with source-follower-based topologies in order to synthesize a custom sixth-order transfer function. The complete chain consists of the cascade of a first-order transimpedance amplifier with finely programmable gain, a fourth-order source-follower-based filter, and a coarse gain first-order programmable gain amplifier. The prototype is implemented in 90-nm CMOS. It achieves a 1-GHz cutoff frequency and programmable gain from 0 to 20 dB with 1-dB step control, drawing 9.5 mA (0–9 dB gain range) or 10.8 mA (10–20 dB gain range) from a 1-V supply. An 8.2-dBm third-order input intercept point and a 145-dBm/Hz input-referred noise power density are measured at 0- and 20-dB gain, respectively. The entire circuit occupies an area of .
Autors: D'Amico, S.;Spagnolo, A.;Donno, A.;Chironi, V.;Wambacq, P.;Baschirotto, A.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Aug 2014, volume: 62, issue:8, pages: 1724 - 1735
Publisher: IEEE
 
» A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond
Abstract:
In this paper, a low-cost and low-leakage gate-first high- metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 A/ m can be obtained for an OFF-state current of A/ m, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.
Autors: Ritzenthaler, R.;Schram, T.;Spessot, A.;Caillat, C.;Aoulaiche, M.;Cho, M.J.;Noh, K.B.;Son, Y.;Na, H.J.;Kauerauf, T.;Douhard, B.;Nazir, A.;Chew, S.A.;Milenin, A.P.;Altamirano-Sanchez, E.;Schoofs, G.;Albert, J.;Sebai, F.;Vecchio, E.;Paraschiv, V.;Vande
Appeared in: IEEE Transactions on Electron Devices
Publication date: Aug 2014, volume: 61, issue:8, pages: 2935 - 2943
Publisher: IEEE
 
» A Lumped Parameter Model and Its Code for Capacitor-Based Railgun With Arbitrary Number of PFUs
Abstract:
A lumped parameter model of capacitor-based railgun (CBRG) with arbitrary number of pulse-forming units is created and design of its simulation code is introduced. To show simulation and optimization capabilities of the code, two applications of the code are given. In the first example, a CBRG with topologically created pulse-forming network is simulated and the results are analyzed to show the availability of the code. In the second example, genetic algorithm-based and iteration-based methods on optimizing timing sequence of pulsed-power supply system are introduced and compared, and influence of timing sequence on launching performance is discussed. Finally, it is concluded that the iteration-based method has preferable effects on calculating timing sequence under the constriction of flat-topped rail current.
Autors: Zhang, H.;Cheng, G.;Guo, W.;Su, Z.;Zhang, T.;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Aug 2014, volume: 42, issue:8, pages: 2098 - 2103
Publisher: IEEE
 

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