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Electrical and Electronics Engineering publications abstract of: 05-2013 sorted by title, page: 0
» "Y function" method applied to saturation regime: Apparent saturation mobility and saturation velocity extraction
Abstract:


Autors:
Appeared in: Solid-State Electronics
Publication date: May 2013
Publisher: Elsevier B.V.
 
» “Equi-Ripple” Synthesis of Multiband Prototype Filters Using a Remez-Like Algorithm
Abstract:
This letter illustrates a new procedure for evaluating the characteristic polynomials associated to the prototype of a multiband microwave filter. This procedure is based on the Remez algorithm and allows an equiripple response in the assigned filter passbands and stopbands, once the number of poles in each passband and the number of imaginary transmission zeros in each stopband are assigned. Some examples and comparisons are reported to show the effectiveness of the new algorithm which has proved to be significantly faster than a similar one recently published in the literature.
Autors: Macchiarella, G.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: May 2013, volume: 23, issue:5, pages: 231 - 233
Publisher: IEEE
 
» 1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor
Abstract:
Object recognition is computationally intensive and it is challenging to meet 30-f/s real-time processing demands under sub-watt low-power constraints of mobile platforms even for heterogeneous many-core architecture. In this paper, an intelligent inference engine (IIE) is proposed as a hardware controller for a many-core processor to satisfy the requirements of low-power real-time object recognition. The IIE exploits learning and inference capabilities of the neurofuzzy system by adopting the versatile adaptive neurofuzzy inference system (VANFIS) with the proposed hardware-oriented learning algorithm. Using the programmable VANFIS, the IIE can configure its hardware topology adaptively for different target classifications. Its architecture contains analog/digital mixed-mode neurofuzzy circuits for updating online parameters to increase attention efficiency of object recognition process. It is implemented in 0.13-μm CMOS process and achieves 1.2-mW power consumption with 94% average classification accuracy within 1-μs operation delay. The 0.765-mm2 IIE achieves 76% attention efficiency and reduces power and processing delay of the 50-mm2 image processor by up to 37% and 28%, respectively, when 96% recognition accuracy is achieved.
Autors: Jinwook Oh;Seungjin Lee;Hoi-Jun Yoo;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: May 2013, volume: 21, issue:5, pages: 921 - 933
Publisher: IEEE
 
» 13.8-kV Selective High-Resistance Grounding System for a Geothermal Generating Plant—A Case Study
Abstract:
The 13.8-kV selective high-resistance grounding (HRG) systems for bus-connected generators are nonexistent due to two reasons: One is that the stray capacitance current of the system can be high ( A), and the other is that the sensitivity and selectivity of the ground-fault devices to detect low levels of ground-fault currents are required. This paper describes the relay types, sensors, settings on protective relays, and flow of currents for various fault locations in a 13.8-kV system and demonstrates how a selective HRG has been implemented. To the authors' knowledge, there is no HRG selective system at 13.8 kV.
Autors: Das, J.C.;Perich, E.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: May 2013, volume: 49, issue:3, pages: 1234 - 1243
Publisher: IEEE
 
» 2-D Discontinuous Galerkin Method for Streamer Discharge Simulations in Nitrogen
Abstract:
This paper proposes a discontinuous Galerkin (DG) method combined with hierarchical reconstruction to simulate the fluid model of streamer discharges. To simulate the rapid transient streamer discharge process, a method with high resolution and high order accuracy is highly desired. Combining the advantages of finite volume and finite element method, DG is such a choice. A simulation of a double-headed streamer discharge in Nitrogen was performed using 2-dimensional fluid model. The preliminary results are quantitatively agreed with those obtained by finite volume method combined with moving mesh, indicating the potential of extending the method to general streamer simulations in complex geometries.
Autors: Zhuang, C.;Zeng, R.;Zhang, B.;He, J.;
Appeared in: IEEE Transactions on Magnetics
Publication date: May 2013, volume: 49, issue:5, pages: 1929 - 1932
Publisher: IEEE
 
» 2.7 μm InAs quantum well lasers on InP-based InAlAs metamorphic buffer layers
Abstract:
This work reports 2.7 μm InAs/In0.6Ga0.4As quantum well lasers on InP-based metamorphic InxAl1-xAs graded buffers. X-ray diffraction measurement shows favorable strain compensation effect in the quantum wells. Type-I photoluminescence emission is observed around 2.7 μm at 77 K and red-shifts to 3 μm at 300 K. The continuous-wave lasing wavelength of the laser reaches 2.7 μm at 77 K, which is the longest wavelength from the interband lasing of InP-based antimony-free structures. The threshold current density is as low as 145 A/cm2 and the continuous-wave output power at injection current of 400 mA is over 5 mW.
Autors: Cao, Y.Y.;Zhang, Y.G.;Gu, Y.;Chen, X.Y.;Zhou, L.;Li, Hsby;
Appeared in: Applied Physics Letters
Publication date: May 2013, volume: 102, issue:20, pages: 201111 - 201111-3
Publisher: IEEE
 
» 20Gb/s WDM-OFDM-PON over 20-km single fiber uplink transmission using optical millimeter-wave signal seeding with rate adaptive bit-power loading
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Autors:

Highlights

Appeared in: Optical Fiber Technology
Publication date: May 2013
Publisher: Elsevier B.V.
 
» 3-D FE Wire Modeling and Analysis of Electromagnetic Signatures From Electric Power Drive Components and Systems
Abstract:
A 3-D finite-element (FE) optimized equivalent source numerical model for the analysis of low frequency electromagnetic field signatures in electric drives is proposed. An example electric drive system including a synchronous generator, an induction motor and power cables connecting a load is used to implement the model. The arrangement of the system setup is developed using a fully detailed 3DFE model to verify and compare with the results of the proposed equivalent source model. The proposed technique provides the exact field solution without large computational even with the presence of superposition. The equivalent source model (wire model) is created based on numerical techniques and physical theory of wave propagation. The superposition of the various components in this study is considered. The results of the proposed wire models match the results of the original models. For further verification, experimental results of the setup are compared with the numerical results. The importance of the proposed equivalent source is that it can be used for the evaluation of electromagnetic signatures and radiation patterns at the design stage. This enables performing various designs iterations to achieve compliant designs to electromagnetic compatibility standards. The proposed model can also be used for dynamic monitoring and diagnosing failures in the system.
Autors: Barzegaran, M.R.;Mohammed, O.A.;
Appeared in: IEEE Transactions on Magnetics
Publication date: May 2013, volume: 49, issue:5, pages: 1937 - 1940
Publisher: IEEE
 
» 3-D Finite Element Analysis of Eddy Current in Laminated Cores of the Interior Permanent-Magnet Motor
Abstract:
In this paper, a large-scale numerical analysis for eddy currents in laminated cores of an interior permanent-magnet motor is achieved. The eddy currents in the laminated cores caused by the axial flux are simulated by using the Earth Simulator, which is a vector-type parallel supercomputer.
Autors: Nakano, T.;Kawase, Y.;Yamaguchi, T.;Nakamura, M.;Nishikawa, N.;
Appeared in: IEEE Transactions on Magnetics
Publication date: May 2013, volume: 49, issue:5, pages: 1945 - 1948
Publisher: IEEE
 
» 3-D measurement of structural vibration using digital close-range photogrammetry
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Autors:
Appeared in: Sensors and Actuators A: Physical
Publication date: May 2013
Publisher: Elsevier B.V.
 
» 3-D Modeling of Thermo Inductive Non Destructive Testing Method Applied to Multilayer Composite
Abstract:
In this paper, a 3-D modeling of a thermo inductive nondestructing testing (NDT) technique applied to carbon fiber reinforced polymer (CFRP) composite is presented. A multiscale approach is used to calculate the electromagnetic and thermal field distribution. The relevance of the technique is then discussed for different positions of flaws and the optimal frequency is estimated.
Autors: Bui, H.K.;Wasselynck, G.;Trichet, D.;Ramdane, B.;Berthiau, G.;Fouladgar, J.;
Appeared in: IEEE Transactions on Magnetics
Publication date: May 2013, volume: 49, issue:5, pages: 1949 - 1952
Publisher: IEEE
 
» 3-D Optimization of Ferrite Inductor Considering Hysteresis Loss
Abstract:
This paper presents three-dimensional shape optimization of inductors for the dc-dc converters, in which the nonconforming voxel-based finite element method (FEM) is employed to realize fast FE mesh generation during the optimization. The operating point of the inductor under the bias current condition, which is estimated from the circuit analysis, is obtained by nonlinear FE analysis. Then, the FE equation linearized around the operating point is solved being coupled with the circuit equation to obtain the magnetic fields in the inductor. The hysteresis loss is computed from the Steinmetz formula. Validity of the field computation is tested by comparing the numerical results with measured data. The multiobjective optimization of the inductor shapes is performed to minimize the winding resistance and hysteresis loss. It is shown that the present method can effectively find the Pareto solutions which can lead to improvement in the efficiency of the dc-dc converter.
Autors: Sato, T.;Watanabe, K.;Igarashi, H.;Matsuo, T.;Mifune, T.;Kawano, K.;Suzuki, M.;Uehara, Y.;Furuya, A.;
Appeared in: IEEE Transactions on Magnetics
Publication date: May 2013, volume: 49, issue:5, pages: 2129 - 2132
Publisher: IEEE
 
» 3-D Unitary ESPRIT: Accurate attitude estimation for unmanned aerial vehicles with a hexagon-shaped ESPAR array
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Autors:
Appeared in: Digital Signal Processing
Publication date: May 2013
Publisher: Elsevier B.V.
 
» 3.1-10.6GHz ultra-wideband LNA design using dual-resonant broadband matching technique
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Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: May 2013
Publisher: Elsevier B.V.
 
» 32 & 16 Years Ago
Abstract:
A summary of articles published in Computer 32 and 16 years ago.
Autors: Holmes, Neville;
Appeared in: Computer
Publication date: May 2013, volume: 46, issue:5, pages: 13 - 14
Publisher: IEEE
 
» 3D face recognition using local binary patterns
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Autors:

Highlights

Appeared in: Signal Processing
Publication date: May 2013
Publisher: Elsevier B.V.
 
» 4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation
Abstract:
Two 4-Gb/s parallel receivers with adaptive far-end crosstalk (FEXT) cancellation are presented. By using the highpass filter, the crosstalk cancellation (XTC) signal is generated to compensate the FEXT signal. A power detection loop is adopted to achieve automatic tuning of the XTC coefficient for different channel spacing. The receivers with adaptive XTC are fabricated in 40-nm CMOS technology, and the core area occupies . The maximum power consumption from a 1.2-V supply is 15.6 mW. For two 4-Gb/s pseudorandom binary sequences of passing through FR4 printed circuit board traces with 5-in length and 8-mil spacing, the measured peak-topeak jitter of the data is reduced by 32.22 ps by using the adaptive XTC. The measured adaptation time of the power detection loop is 63.44 .
Autors: Lin, Y.-Y.;Liu, S.-I.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: May 2013, volume: 60, issue:5, pages: 252 - 256
Publisher: IEEE
 
» 50 years in the development of polymer suspension-type insulators
Abstract:
The article reviews 50 years in the development of polymer suspension-type insulators for overhead lines and outlines the remaining issues that limit their greater use.
Autors: Cherney, E.A.;
Appeared in: IEEE Electrical Insulation Magazine
Publication date: May 2013, volume: 29, issue:3, pages: 18 - 26
Publisher: IEEE
 
» 850nm IR transmissive electro-absorption modulator using GaAs micromachining
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Autors:
Appeared in: Sensors and Actuators A: Physical
Publication date: May 2013
Publisher: Elsevier B.V.
 
» 9-(Pyridin-3-yl)-9H-carbazole derivatives as host materials for green phosphorescent organic light-emitting diodes
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Autors:

Graphical abstract

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Highlights

Appeared in: Organic Electronics
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A 0.13 µm 8 Mb Logic-Based Cu Si O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction
Abstract:
A 0.13 µm 8 Mb resistive random access memory (ReRAM) test macro with cell size is developed based on logic process for embedded applications. Smart and adaptive write and read assist circuits are proposed to fix yield and power consumption issues arising from large variations in set/reset time and high-temperature cell resistance. Self-adaptive write mode (SAWM) helps increase the window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and the high power consumption is eliminated after the cell switches to during set. Self-adaptive read mode (SARM) increases read bit yield from 98% to 100% at 125 . The typical access time of the on-pitch voltage sense amplifier (SA) is 21 ns. High bandwidth throughput is supported.
Autors: Xue, X.;Jian, W.;Yang, J.;Xiao, F.;Chen, G.;Xu, S.;Xie, Y.;Lin, Y.;Huang, R.;Zou, Q.;Wu, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2013, volume: 48, issue:5, pages: 1315 - 1322
Publisher: IEEE
 
» A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O Transceiver in 65 nm CMOS
Abstract:
A low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100–200 using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. In the transmitter clocking circuitry, per-phase duty-cycle and phase-spacing adjustment is implemented to allow adequate timing margins at low operating voltages. Fabricated in a general purpose 65 nm CMOS process, the transceiver achieves 4.8–8 Gb/s at 0.47–0.66 pJ/b energy efficiency for –0.8 V.
Autors: Song, Y.-H.;Bai, R.;Hu, K.;Yang, H.-W.;Chiang, P.Y.;Palermo, S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2013, volume: 48, issue:5, pages: 1276 - 1289
Publisher: IEEE
 
» A 10-bit dual-plate sampling DAC with capacitor reuse on-chip reference voltage generator
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Autors:
Appeared in: Microelectronics Journal
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A 100 kV, 60 A solid state 4 kHz switching modulator for high power klystron driving
Abstract:
A solid state high power modulator capable of delivering 120 kV and 60 A developed in collaboration with the JEMA Corporation, ESS Bilbao, and the SNS (ORNL) for driving high power klystrons is presented. Pulses with less than 10 μs risetime and flatness under 0.1% are obtained with programmable frequency pulses between 2 and 50 Hz. Eight solid state switches combined with custom air-insulated high voltage transformers working at a switching frequency of 4 kHz produce high quality pulses by phase shifting the transformer drives. Each relative high frequency stage pumps a double stage high voltage Marx generator that supplies the output pulse shape and frequency. This merged topology between a Marx generator and direct modulator takes advantage of the strengths of both approaches. Low energy storage in the output stages assures safe operation in case of a load arc discharge. Real time voltage correction during the pulse is also provided to compensate for the droop inherent with the use of low energy storage in the output stages. Data at full power with a dummy resistive load are presented.
Autors: Cortazar, O.D.;Ganuza, D.;De La Fuente, J.M.;Zulaika, M.;Perez, A.;Anderson, D.E.;
Appeared in: Review of Scientific Instruments
Publication date: May 2013, volume: 84, issue:5, pages: 054706 - 054706-6
Publisher: IEEE
 
» A 130-nm CMOS 0.007- Ring-Oscillator-Based Self-Calibrating IR-UWB Transmitter Using an Asynchronous Logic Duty-Cycled PLL
Abstract:
We present a 0.007 impulse-radio ultrawideband transmitter (TX) based on a ring oscillator capable of synthesizing pulses with both controlled center frequency and bandwidth using a single duty-cycling/trigger reference input. The TX embeds a single-phase charge-pump phase-locked loop (PLL), implemented with asynchronous logic, with 55 logic elements overall. The system, including radio frequency output buffers, consumes measured 30–45 pJ/pulse with a measured efficiency of 47 at 285 MHz center frequency and in the range of 0.97–1.17 V. At 1.2V supply, the 130 nm CMOS TX tolerates 10 variation, maintaining robust lock and controlled power spectral density (PSD) at 300 MHz center frequency, 19 dBm radiated power at 1 MHz pulse-repetition frequency, and a fractional bandwidth of 0.23. At 300 MHz, the system achieves a measured 100 ps RMS jitter, and without output buffers, the sole PLL logic occupies an active silicon area of 0.0045 .
Autors: Crepaldi, M.;Demarchi, D.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: May 2013, volume: 60, issue:5, pages: 237 - 241
Publisher: IEEE
 
» A 130-nm CMOS 0.007- Ring-Oscillator-Based Self-Calibrating IR-UWB Transmitter Using an Asynchronous Logic Duty-Cycled PLL
Abstract:
We present a 0.007 impulse-radio ultrawideband transmitter (TX) based on a ring oscillator capable of synthesizing pulses with both controlled center frequency and bandwidth using a single duty-cycling/trigger reference input. The TX embeds a single-phase charge-pump phase-locked loop (PLL), implemented with asynchronous logic, with 55 logic elements overall. The system, including radio frequency output buffers, consumes measured 30–45 pJ/pulse with a measured efficiency of 47 at 285 MHz center frequency and in the range of 0.97–1.17 V. At 1.2V supply, the 130 nm CMOS TX tolerates 10 variation, maintaining robust lock and controlled power spectral density (PSD) at 300 MHz center frequency, 19 dBm radiated power at 1 MHz pulse-repetition frequency, and a fractional bandwidth of 0.23. At 300 MHz, the system achieves a measured 100 ps RMS jitter, and without output buffers, the sole PLL logic occupies an active silicon area of 0.0045 .
Autors: Crepaldi, M.;Demarchi, D.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: May 2013, volume: 60, issue:5, pages: 237 - 241
Publisher: IEEE
 
» A 182 mW 94.3 f/s in Full HD Pattern-Matching Based Image Recognition Accelerator for an Embedded Vision System in 0.13- CMOS Technology
Abstract:
A pattern-matching based image recognition accelerator (PRA) is presented for embedded vision applications. It is a hardware accelerator that performs interest point detection and matching for image-based recognition applications in real time in both mobile devices and vehicles. The proposed system is implemented as a small IP, and it has eight times higher throughput than state-of-the-art object recognition processors, which are implemented based on a heterogeneous many-core system. PRA has three key features: 1) joint algorithm–architecture optimizations for exploiting bit-level parallelism; 2) a low-power unified hardware platform for interest point detection and matching; and 3) scalable hardware architecture. PRA achieves performance improvement with only 30% of logic gates including static random-access memory (SRAM) compared to the state-of-the-art object recognition processors. It consists of 78.3 k logic gates and 128 kB SRAM, which are integrated in a test chip implemented for PRA verification. It achieves 94.3 frames per second (fps) in 1080 p full HD resolution at 200-MHz operating frequency while consuming 182 mW. Each complete operation for interest point detection and matching requires 2.09 cycles and 8 cycles on average, respectively, based on a unified bit-level matching accelerator, which is implemented only with 680 logic gates.
Autors: Park, J.-S.;Kim, H.-E.;Kim, L.-S.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: May 2013, volume: 23, issue:5, pages: 832 - 845
Publisher: IEEE
 
» A 19.2 mW, Gain and High-Selectivity 94 GHz LNA in 0.13 SiGe BiCMOS
Abstract:
In this letter, a high-gain and selectivity W-band LNA using 0.13 SiGe BiCMOS is proposed. A Q-enhanced cascode approach with a filter synthesis passband-forming technique was employed to achieve gain and selectivity improvement simultaneously. The amplifier achieved a gain of above 45 dB and a noise figure of 6–8.3 dB at 77–101 GHz with a power consumption of 19.2 mW. The LNA has high selectivity with a 3 dB-to-35 dB shape factor of 2.1, which is comparable with silicon-based passive millimeter-wave filters.
Autors: Bi, X.;Guo, Y.;Xiong, Y.Z.;Arasu, M.A.;Je, M.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: May 2013, volume: 23, issue:5, pages: 261 - 263
Publisher: IEEE
 
» A 19.2 mW, Gain and High-Selectivity 94 GHz LNA in 0.13 SiGe BiCMOS
Abstract:
In this letter, a high-gain and selectivity W-band LNA using 0.13 μm SiGe BiCMOS is proposed. A Q-enhanced cascode approach with a filter synthesis passband-forming technique was employed to achieve gain and selectivity improvement simultaneously. The amplifier achieved a gain of above 45 dB and a noise figure of 6-8.3 dB at 77-101 GHz with a power consumption of 19.2 mW. The LNA has high selectivity with a 3 dB-to-35 dB shape factor of 2.1, which is comparable with silicon-based passive millimeter-wave filters.
Autors: Xiaojun Bi;Yongxin Guo;Yong Zhong Xiong;Arasu, M.A.;Je, M.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: May 2013, volume: 23, issue:5, pages: 261 - 263
Publisher: IEEE
 
» A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters
Abstract:
A high-efficiency, large output-power, mm-wave digital transmitter architecture is proposed for high data rate m-ary QAM transmission. Because it operates entirely in digital mode, without any matching networks, it is scalable in frequency up to at least 50 GHz and portable to future generations of CMOS technologies. It consists of n broadband mm-wave IQ power-DAC pairs directly modulated in amplitude and phase by 4 x n independent digital data streams. The output signals combine in free space to form a programmable ASK, BPSK, QPSK, and m-ary QAM mm-wave transmitter. Several proof-of-concept circuits with one DAC cell, and with one and two IQ pairs of DAC cells were fabricated in 45-nm SOI CMOS. Using a series-stacked differential output stage with four cascoded n-MOSFETs driven in saturation by a CMOS-inverter chain, each power-DAC cell demonstrates a 24.3 dBm output power with 21.3% drain efficiency and 14.6% PAE, at 45 GHz directly into 50-Ω loads. The peak drain efficiency is 30% at 22.5 dBm output power and 19.4% PAE. Experiments show 5-Gb/s BPSK, and simultaneous 2-Gb/s BPSK and 2-Gb/s ASK modulation per DAC cell in the 44-48 GHz range. Eye diagrams at 28 Gb/s further demonstrate the broadband operation of the DAC cell and its suitability as a large-swing NRZ modulator driver in fiberoptic links.
Autors: Balteanu, A.;Sarkas, I.;Dacquay, E.;Tomkins, A.;Rebeiz, G.M.;Asbeck, P.M.;Voinigescu, S.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2013, volume: 48, issue:5, pages: 1126 - 1137
Publisher: IEEE
 
» A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks
Abstract:
A low power 2.4 GHz hybrid polyphase filter (PPF) based BFSK receiver with high frequency offset tolerance (FOT) at small modulation indexes (MIs) is presented for medium data rate wireless sensor network applications. A high FOT at low MI is achieved by a frequency-to-energy conversion architecture using PPFs without any frequency correction circuits. Channel selection and interference rejection are performed simultaneously by the PPFs without any extra hardware and power consumption. Furthermore, the proposed hybrid topology of the PPFs provides an improved adjacent channel rejection (ACR) at reduced power. The prototype receiver fabricated in a 0.13-µm CMOS process, including the RF and analog front-ends, consumes 1.97 mW from a 1 V supply. With a data rate of 1 Mb/s, a sensitivity of –84 dBm, a FOT of 450 kHz ( 180 ppm), and an ACR of 40 dB are achieved for a MI of 2.
Autors: Ni, R.;Mayaram, K.;Fiez, T.S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2013, volume: 48, issue:5, pages: 1250 - 1263
Publisher: IEEE
 
» A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer
Abstract:


Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A 256 Pixel Magnetoresistive Biosensor Microarray in 0.18 µm CMOS
Abstract:
Magnetic nanotechnologies have shown significant potential in several areas of nanomedicine such as imaging, therapeutics, and early disease detection. Giant magnetoresistive spin-valve (GMR SV) sensors coupled with magnetic nanotags (MNTs) possess great promise as ultra-sensitive biosensors for diagnostics. We report an integrated sensor interface for an array of 256 GMR SV biosensors designed in 0.18 µm CMOS. Arranged like an imager, each of the 16 column level readout channels contains an analog front-end and a compact ΣΔ modulator (0.054 mm ) with 84 dB of dynamic range and an input referred noise of 49 nT/ Hz. Performance is demonstrated through detection of an ovarian cancer biomarker, secretory leukocyte peptidase inhibitor (SLPI), spiked at concentrations as low as 10 fM. This system is designed as a replacement for optical protein microarrays while also providing real-time kinetics monitoring.
Autors: Hall, D.A.;Gaster, R.S.;Makinwa, K.A.A.;Wang, S.X.;Murmann, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2013, volume: 48, issue:5, pages: 1290 - 1301
Publisher: IEEE
 
» A 2×VDD output buffer with PVT detector for slew rate compensation
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Autors:
Appeared in: Microelectronics Journal
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A 30-V transmitter front-end IC for ultrasound medical imaging applications
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A 37.5 Body Channel Communication Wake-Up Receiver With Injection-Locking Ring Oscillator for Wireless Body Area Network
Abstract:
An ultra-low power wake-up receiver for body channel communication (BCC) is implemented in 130 nm CMOS process. The proposed wake-up receiver uses the injection-locking ring oscillator (ILRO) to replace the RF amplifier with low power consumption. Through the ILRO, the frequency modulated input signal is amplified to the full swing rectangular signal directly demodulated by the following low power PLL-based FSK demodulator. In addition, the energy-efficient BCC link mitigates the sensitivity and selectivity requirements for the receiver, which significantly reduces the power consumption. Furthermore, the auto frequency calibrator (AFC) is adopted to compensate the free running frequency of the ring oscillator which is caused by temperature variation and leakage current. The AFC reuses the PLL-based demodulator to periodically set the free running frequency to the desired frequency without any area overhead. As a result, the proposed wake-up receiver achieves a sensitivity of 62.7 dBm at a data rate of 200 kbps while consuming only 37.5 from the 0.7 V supply.
Autors: Cho, H.;Bae, J.;Yoo, H.-J.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: May 2013, volume: 60, issue:5, pages: 1200 - 1208
Publisher: IEEE
 
» A 453- 53–70-GHz Ultra-Low-Power Double-Balanced Source-Driven Mixer Using 90-nm CMOS Technology
Abstract:
Pub DtlAn ultra-low-power consumption and ultra-low local oscillator (LO) power double-balanced down-conversion mixer using standard 90-nm CMOS technology is presented in this paper. By employing a weak inversion biasing technique in a source-driven topology, the proposed -band mixer can operate at microwatt power consumption of 453 and has an ultra low LO power of . In addition, under 1.2-V standard supply voltage, the down-conversion mixer exhibits excellent conversion-gain flatness of and the measured LO-to-RF isolation is more than 37 dB from 53 to 70 GHz, and of at RF frequency of 60 GHz. Based on aforementioned results, the presented monolithic microwave integrated circuit can mitigate power-hungry issues while providing reasonable RF performance, which is important for a low-power communication system.
Autors: Li, W.-T.;Yang, H.-Y.;Chiang, Y.-C.;Tsai, J.-H.;Wu, M;Huang, T.-W.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: May 2013, volume: 61, issue:5, pages: 1903 - 1912
Publisher: IEEE
 
» A 453- 53–70-GHz Ultra-Low-Power Double-Balanced Source-Driven Mixer Using 90-nm CMOS Technology
Abstract:
An ultra-low-power consumption and ultra-low local oscillator (LO) power double-balanced down-conversion mixer using standard 90-nm CMOS technology is presented in this paper. By employing a weak inversion biasing technique in a source-driven topology, the proposed V-band mixer can operate at microwatt power consumption of 453 μW and has an ultra low LO power of -6 dBm. In addition, under 1.2-V standard supply voltage, the down-conversion mixer exhibits excellent conversion-gain flatness of 5.9±1.5 dB and the measured LO-to-RF isolation is more than 37 dB from 53 to 70 GHz, and OP1 dB of -9.2 dBm at RF frequency of 60 GHz. Based on aforementioned results, the presented monolithic microwave integrated circuit can mitigate power-hungry issues while providing reasonable RF performance, which is important for a low-power communication system.
Autors: Wei-Tsung Li;Hong-Yuan Yang;Yun-Chieh Chiang;Jeng-Han Tsai;Ming-Han Wu;Tian-Wei Huang;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: May 2013, volume: 61, issue:5, pages: 1903 - 1912
Publisher: IEEE
 
» A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator
Abstract:
A 6-GHz phase-locked loop based spread-spectrum clock generator employing a self-oscillating technique is proposed. The clock generator adopts the property of the inherent oscillation of a charge-pump PLL while introducing no extra quantization noise. With the amplitude and frequency control, modulation frequency and frequency deviation can be tuned at 31.5 kHz and 5000 ppm, respectively. The measured EMI reduction is 12.5 dB at the 100-kHz resolution bandwidth. The measured root mean square jitter is 2 ps and peak-to-peak is 15 ps. This work was fabricated in a 90-nm digital CMOS technology, occupies 0.54 and consumes 14.4 mW from a 1.2-V supply.
Autors: Wong, C.-H.;Lee, T.-C.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: May 2013, volume: 60, issue:5, pages: 1264 - 1273
Publisher: IEEE
 
» A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM
Abstract:
A quad-band GSM/GPRS/EDGE cellular system, implemented in 65-nm CMOS, is integrated in a multimedia SoC with BT and FM. A low-IF receiver with digital IRR tracking is selected for its smaller area and better noise figure. The receiver achieves a sensitivity of 110 dBm, an IIP3 of 9.5 dBm, and a calibrated image rejection ratio of 65 dBc, while consuming 61 mA. The polar transmitter architecture is chosen for its SAW-less TX capability, smaller area, and low current consumption. It achieves an ORFS (output radio frequency spectrum) of 68 dB and 64 dB at 400 kHz in GMSK and EDGE mode, respectively, while consuming 61 mA. The loop gain normalization, dc offset and AM/PM delay of the polar system are compensated to be better than 1% error, 1 mV, and 1.9 ns within 170 s, respectively. Several techniques are employed to minimize interference coupling within the SoC; these include frequency planning, circuit implementation, transceiver architecture optimization, and digital clock selection. The measured sensitivity and the output spectrum of the three wireless systems under full-feature phone operation are virtually unchanged.
Autors: Wu, T.-H.;Chang, H.-H.;Chen, S.-F.;Chiu, C.-S.;Lai, L.-S.;Wang, C.-H.;Yang, S.-Y.;Lin, T.-H.;Chen, J.-R.;Tsai, H.-C.;Yu, C.-Y.;Su, S.-Y.;Yu, T.-Y.;Chin, C.-C.;Dehng, G.-K.;Marques, A.;Wang, C.;Chien, G.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2013, volume: 48, issue:5, pages: 1161 - 1173
Publisher: IEEE
 
» A 70–100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link
Abstract:
A transmitter and receiver phased array chipset is demonstrated in the range between 70 and 100 GHz using a 0.18 µm SiGe BiCMOS process with of 240/270 GHz. Each chip comprises four phased array elements with distributed calibration memory and calibrated direct up- and down-conversion mixer chain. Each receive channel has a conversion gain of 33 dB and noise figure of < 7 dB from 75–95 GHz. Each transmit channel has a flat saturated output power of > 5 dBm between 70 and 100 GHz. Both transmitter and receiver arrays operate from 1.5 V and 2.5 V power supplies and consume 1 W each. Using a die-on-PCB prototype with integrated antennas, a wireless link operating at 10 Gb/s (using 16-QAM) or 8.75 Gb/s (using 32-QAM) is demonstrated at a distance of 1-meter with a carrier frequency of 88 GHz.
Autors: Shahramian, S.;Baeyens, Y.;Kaneda, N.;Chen, Y.-K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2013, volume: 48, issue:5, pages: 1113 - 1125
Publisher: IEEE
 
» A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation
Abstract:
Ring oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLLs. However, due to their supply noise sensitivity and high noise floor, their applications have been limited to low-performance applications. The proposed architecture introduces an analog feed-forward adaptive phase-noise cancellation architecture that extracts and suppresses phase noise of ROs outside the PLL bandwidth. The proposed technique can improve the phase noise at an arbitrary offset frequency and bandwidth, and, after initial calibration for gain, it is insensitive to process, voltage, and temperature variations. An experimental fractional PLL, with a loop bandwidth of 200 kHz, is utilized to demonstrate the active phase-noise cancellation approach. The cancellation loop is designed to suppress the phase noise at 1-MHz offset by 12.5 dB and reference spur by 13 dB with less than 17% increase in the overall power consumption at 5.1-GHz frequency. The measured phase noise at 1-MHz offset after cancellation is -105 dBc/Hz. The proposed RO-PLL is fabricated in 90-nm CMOS process. With noise cancellation loop enabled, the PLL consumes 24.7 mA at 1.2-V supply.
Autors: Seungkee Min;Copani, T.;Kiaei, S.;Bakkaloglu, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2013, volume: 48, issue:5, pages: 1151 - 1160
Publisher: IEEE
 
» A Bayesian approach to SAR imaging
Abstract:


Autors:
Appeared in: Digital Signal Processing
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A blind scene-based watermarking for video copyright protection
Abstract:


Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A Blind Time-Reversal Detector in the Presence of Channel Correlation
Abstract:
A blind target detector using the time reversal transmission is proposed in the presence of channel correlation. We calculate the exact moments of the test statistics involved. The derived moments are used to construct an accurate approximative Likelihood Ratio Test (LRT) based on multivariate Edgeworth expansion. Performance gain over an existing detector is observed in scenarios with channel correlation and relatively strong target signal.
Autors: Zheng, Z.;Wei, L.;Hamalainen, J.;Tirkkonen, O.;
Appeared in: IEEE Signal Processing Letters
Publication date: May 2013, volume: 20, issue:5, pages: 459 - 462
Publisher: IEEE
 
» A bottleneck Steiner tree based multi-objective location model and intelligent optimization of emergency logistics systems
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Autors:

Highlights

Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A brief survey of radio access network backhaul evolution: part II
Abstract:
In part I of this article we presented the design alternatives, issues, and challenges for designing backhaul for 2G (GSM, CDMA) and 3G (UMTS, CDMA2000) radio access networks (RANs). Part II extends the survey of backhaul technologies to address LTE-based RANs. We present various alternatives to deal with the specific requirements imposed by Evolved Packet System architecture on the backhaul design. In particular, we address handling of the X2 interface, network security through IPSec, distribution of frequency and phase synchronization, the impact of small cell design, self-organizing networks, and endend QoS management within backhaul. We also present a brief overview of active debates with respect to some of these design options as open issues, in particular the impact of LTE-Advanced requirements on LTE backhaul design.
Autors: Raza, H.;
Appeared in: IEEE Communications Magazine
Publication date: May 2013, volume: 51, issue:5
Publisher: IEEE
 
» A Broadband Omnidirectional Circularly Polarized Antenna
Abstract:
A broadband circularly polarized (CP) antenna is developed with an omnidirectional radiation pattern in the horizontal plane. Four broadband CP rectangular loop elements are employed for broadband omnidirectional CP radiation. The four rectangular loop elements are first printed on a flexible thin dielectric substrate and then rolled into a hollow cylinder. A conducting cylinder is introduced inside the hollow cylinder for achieving desired omnidirectional CP performance. A feeding network consisting of four broadband baluns and an impedance matching circuit is designed to feed the four rectangular loop elements. The omnidirectional CP antenna has a circular cross section with diameter of . Experimental results show that the omnidirectional CP antenna has bandwidths of 41% (1.65–2.5 GHz) for dB and 45% (1.58–2.5 GHz) for dB. The gain variation in the omnidirectional plane is less than 1 dB for the frequency range from 1.65 to 2.5 GHz. Good agreement is obtained between simulated and measured results.
Autors: Quan, X.;Li, R.;Tentzeris, M.M.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: May 2013, volume: 61, issue:5, pages: 2363 - 2370
Publisher: IEEE
 
» A Broadband Unidirectional Multi-Dipole Antenna With Very Stable Beamwidth
Abstract:
A broadband multi-dipole antenna with stable beamwidth is presented. Through a rational design of position of dipoles and a reflector, an antenna with a wide impedance bandwidth, stable radiation pattern and nearly identical E- and H-planes is achieved. A laboratory model has been characterized experimentally. Experimental results agree well with simulations. Results show that an impedance bandwidth of 59.7% for from 1.55 to 2.87 GHz was achieved. Stable radiation pattern with 3 dB beamwidth 63.3 2.9 degree at H-plane and 63.4 2 degree at E-plane and an antenna gain of 9 0.6 dBi was found over the operating frequencies.
Autors: Chu, Q.-X.;Luo, Y.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: May 2013, volume: 61, issue:5, pages: 2847 - 2852
Publisher: IEEE
 
» A carbon nanotube based ammonia sensor on cotton textile
Abstract:
A single-wall carbon nanotube (CNT) based ammonia (NH3) sensor was implemented on a cotton yarn. Two types of sensors were fabricated: Au/sensing CNT/Au and conducting/sensing/conducting all CNT structures. Two perpendicular Au wires were designed to contact CNT-cotton yarn for metal-CNT sensor, whereas nanotubes were used for the electrode as well as sensing material for the all CNT sensor. The resistance shift of the CNT network upon NH3 was monitored in a chemiresistor approach. The CNT-cotton yarn sensors exhibited uniformity and repeatability. Furthermore, the sensors displayed good mechanical robustness against bending. The present approach can be utilized for low-cost smart textile applications.
Autors: Han, Jin-Woo;Kim, Beomseok;Li, Jing;Meyyappan, M.;
Appeared in: Applied Physics Letters
Publication date: May 2013, volume: 102, issue:19, pages: 193104 - 193104-4
Publisher: IEEE
 
» A channel reuse strategy with adaptive channel allocation for all-optical WDM networks
Abstract:


Autors:
Appeared in: Optical Switching and Networking
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A charge-based capacitance model for AlGaAs/GaAs HEMTs
Abstract:


Autors:

Highlights

Appeared in: Solid-State Electronics
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A Class-G Switched-Capacitor RF Power Amplifier
Abstract:
A switched-capacitor power amplifier (SCPA) that realizes an envelope elimination and restoration/polar class-G topology is introduced. A novel voltage-tolerant switch enables the use of two power supply voltages which increases efficiency and output power simultaneously. Envelope digital-to-analog conversion in the polar transmitter is achieved using an SC RF DAC that exhibits high efficiency at typical output power backoff levels. In addition, high linearity is achieved and no digital predistortion is required. Implemented in 65 nm CMOS, the measured peak output power and power-added efficiency (PAE) are 24.3 dBm and 43.5%, respectively, whereas when amplifying 802.11g 64-QAM OFDM signals, the average output power and PAE are 16.8 dBm and 33%, respectively. The measured EVM is 2.9%.
Autors: Yoo, S.-M.;Walling, J.S.;Degani, O.;Jann, B.;Sadhwani, R.;Rudell, J.C.;Allstot, D.J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2013, volume: 48, issue:5, pages: 1212 - 1224
Publisher: IEEE
 
» A CMOS MEMS Capacitive Flow Sensor for Respiratory Monitoring
Abstract:
This letter presents a novel complementary metal-oxide-semiconductor (CMOS) micromachined capacitive flow sensor for respiratory monitoring. Airflow induces a pressure change on the suspended sensing plate and causes a capacitance change with respect to the bottom electrode. The microstructure fabricated by post-CMOS metal etch occupies an area of 190 190 and possesses a sensing capacitance of 180 fF. Output waveform of consecutive breaths is successfully measured with an output noise of 14 for a measuring bandwidth of 0.5 Hz, which is equivalent to a minimum detectable capacitance change and airflow velocity of 0.13 aF and 0.2 mm/sec, respectively.
Autors: Liao, S.-H.;Chen, W.-J.;Lu, M.S.-C.;
Appeared in: IEEE Sensors Journal
Publication date: May 2013, volume: 13, issue:5, pages: 1401 - 1402
Publisher: IEEE
 
» A Compact Multipath Mitigating Ground Plane for Multiband GNSS Antennas
Abstract:
This paper presents the design of a novel multipath mitigating ground plane for global navigation satellite system (GNSS) antennas. First, the concept of a compact low multipath cross-plate reflector ground plane (CPRGP) is presented. In comparison with the choke ring and electromagnetic band gap (EBG) ground planes, the proposed CPRGP has compact size, low mass, wide operational bandwidth, and simple configuration. The proposed CPRGP is then integrated with a circularly polarized dual-band GNSS antenna in order to assess the multipath mitigating performance over two frequency bands. Measurement results of the proposed CPRGP with GNSS antenna achieves a front-to-back ratio (FBR) over 25 dB at L1 (1.575 GHz) and L2 (1.227 GHz) bands and maximum backward cross-polarization levels below 23 dB at both bands. Antenna phase center variation remains less than 2 mm across both L1 and L2 bands. Furthermore, the performance comparison of the proposed CPRGP with the commercially available pinwheel antenna and the shallow corrugated ground plane is presented, showing the advantages of CPRGP for high precision GNSS applications.
Autors: Maqsood, M.;Gao, S.;Brown, T.W.C.;Unwin, M.;de vos Van Steenwijk, R.;Xu, J.D.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: May 2013, volume: 61, issue:5, pages: 2775 - 2782
Publisher: IEEE
 
» A comparative study of spacecraft attitude determination and estimation algorithms (a cost-benefit approach)
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Autors:
Appeared in: Aerospace Science and Technology
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A Comparison of Carrier-Based and Space Vector PWM Techniques for Three-Level Five-Phase Voltage Source Inverters
Abstract:
Multilevel inverter supplied multiphase variable-speed drive systems have in recent times started attracting more attention, due to various advantages that they offer when compared to the standard three-phase two-level drives. For proper functioning of such systems good pulsewidth modulation (PWM) strategy is of crucial importance. Control complexity of multiphase multilevel inverters increases rapidly with an increase in the number of phases and the number of levels. This paper deals with a three-level neutral point clamped (NPC) inverter supplied five-phase induction motor drive and analyses five PWM strategies: three are carrier-based (CBPWM) and two are space vector based (SVPWM). The aim is to provide a detailed comparison and thus conclude on pros and cons of each solution, providing a guideline for the selection of the most appropriate PWM technique. Experimental results are provided for all analysed PWM methods. The comparison of the PWM techniques is given in terms of the voltage and current waveforms and spectra, as well as the total harmonic distortion (THD) in a whole linear modulation index range, which is used as the global figure of merit. Properties of the common mode voltage (CMV) are also investigated. Complexity of the algorithms, in terms of the computational time requirements and memory consumption, is addressed as well. It is shown that the performance of the PWM techniques is very similar and that one CBPWM and one SVPWM technique are characterised with identical performance. However, using the algorithm complexity as the main criterion, space vector techniques are more involved.
Autors: Dordevic, O.;Jones, M.;Levi, E.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: May 2013, volume: 9, issue:2, pages: 609 - 619
Publisher: IEEE
 
» A Comparison of Model Predictive Control Schemes for MV Induction Motor Drives
Abstract:
In medium-voltage (MV) drives, the switching frequency is limited to a few hundred Hz, for which high-performance control and modulation schemes are necessary to maintain acceptable current and torque distortion. Forced machine current control (FMCC) is a predictive control strategy for MV drives which was proposed in the early 1980s, which can be formulated for either torque or current control. Recently, model predictive direct torque control (MPDTC) and model predictive direct current control (MPDCC) have been developed, sharing with FMCC the use of hysteresis bounds, switching and prediction horizons. However, the relative performances of these schemes are yet to be compared. Through simulation, this paper compares the schemes across a range of operating points. It is shown that the steady-state performance of MPDxC and FMCC is similar when the switching horizon of MPDxC is limited. However, when the switching horizon is extended, the performance of MPDxC is shown to be superior to FMCC, the horizon of which is inherently restricted.
Autors: Scoltock, J.;Geyer, T.;Madawala, U.K.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: May 2013, volume: 9, issue:2, pages: 909 - 919
Publisher: IEEE
 
» A comparison of two chromosome representation schemes used in solving a family-based scheduling problem
Abstract:


Autors:

Highlights

Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A comprehensive electric field analysis of a multifunctional electrospinning platform
Abstract:


Autors:
Appeared in: Journal of Electrostatics
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A Compressed Sensing Analog-to-Information Converter With Edge-Triggered SAR ADC Core
Abstract:
This paper presents the design and implementation of an analog-to-information converter (AIC) capable of Nyquist and compressed sensing modes of operation. The core of the AIC is a 10-bit edge-triggered charge-sharing SAR ADC with a figure of merit (FOM) of 55 fJ/conversion-step and Nyquist-sampling rate of 9.5 Msample/s. The integration of a pseudorandom clock generator enables compressed sensing operation via random sampling and subsequent asynchronous successive approximation conversion by the core ADC. The AIC allows complete reconstruction of a spectrum consisting of sparse single tones or sparse frequency bands using compressed sensing algorithms based on -minimization as well as regularization, which exploits group sparsity. Implemented in 90 nm CMOS, the prototype SAR ADC core achieves a maximum sample rate of 9.5 MS/s, an ENOB of 9.3 bits, and consumes 550 W from a 1.2 V supply. Measurement results of the AIC demonstrate an effective bandwidth of 25 MHz, which is greater than Nyquist-sampling rate with an improved effective FOM of 12.2 fJ/conversion-step for signals with sparse frequency support.
Autors: Trakimas, M.;D'Angelo, R.;Aeron, S.;Hancock, T.;Sonkusale, S.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: May 2013, volume: 60, issue:5, pages: 1135 - 1148
Publisher: IEEE
 
» A computational analysis of a fully-stocked dual-mode ventilated livestock vehicle during ferry transportation
Abstract:


Autors:

Highlights

Appeared in: Computers and Electronics in Agriculture
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A Computational Strategy to Solve Preventive Risk-Based Security-Constrained OPF
Abstract:
The benefit of risk-based (RB) security-constrained optimal power flow (SCOPF) model lies in its ability to improve the economic performance of a power system while enhancing the system's overall security level. However, the RB-SCOPF model is difficult to solve due to the following two characteristics: 1) the overload severity of a circuit changes with the loading condition on it, thus is hard to express with a deterministic function, and 2) the risk index is a function of the state variables in both normal and contingency states, which greatly increases the scale of optimization. To handle the first issue, a new expression of severity function is proposed so that it is possible to decompose the model into a SCOPF subproblem and a risk subproblem. To deal with the second issue, a nested Benders decomposition with multi-layer linear programming method is proposed. Illustrations use the ISO New England bulk system is provided to demonstrate the feasibility of the proposed method. Analysis is presented to demonstrate the merits of the RB-SCOPF over the traditional SCOPF model.
Autors: Wang, Q.;McCalley, J.D.;Zheng, T.;Litvinov, E.;
Appeared in: IEEE Transactions on Power Systems
Publication date: May 2013, volume: 28, issue:2, pages: 1666 - 1675
Publisher: IEEE
 
» A computer vision-based system for the automatic detection of lying behaviour of dairy cows in free-stall barns
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Autors:

Highlights

Appeared in: Biosystems Engineering
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A continuous-time cascaded delta-sigma modulator with PMW-based automatic RC time constant tuning and correlated double sampling
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A Contraction Approach to the Hierarchical Analysis and Design of Networked Systems
Abstract:
This brief is concerned with the stability of continuous-time networked systems. Using contraction theory, a result is established on the network structure and the properties of the individual component subsystems and their couplings to ensure the overall contractivity of the entire network. Specifically, it is shown that a contraction property on a reduced-order matrix that quantifies the interconnection structure, coupled with contractivity/expansion estimates on the individual component subsystems, suffices to ensure that trajectories of the overall system converge towards each other.
Autors: Russo, G.;di Bernardo, M.;Sontag, E.D.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: May 2013, volume: 58, issue:5, pages: 1328 - 1331
Publisher: IEEE
 
» A Convex Formulation for Learning a Shared Predictive Structure from Multiple Tasks
Abstract:
In this paper, we consider the problem of learning from multiple related tasks for improved generalization performance by extracting their shared structures. The alternating structure optimization (ASO) algorithm, which couples all tasks using a shared feature representation, has been successfully applied in various multitask learning problems. However, ASO is nonconvex and the alternating algorithm only finds a local solution. We first present an improved ASO formulation ($(i{rm ASO})$) for multitask learning based on a new regularizer. We then convert $(i{rm ASO})$, a nonconvex formulation, into a relaxed convex one ($(r{rm ASO})$). Interestingly, our theoretical analysis reveals that $(r{rm ASO})$ finds a globally optimal solution to its nonconvex counterpart $(i{rm ASO})$ under certain conditions. $(r{rm ASO})$ can be equivalently reformulated as a semidefinite program (SDP), which is, however, not scalable to large datasets. We propose to employ the block coordinate descent (BCD) method and the accelerated projected gradient (APG) algorithm separately to find the globally optimal solution to $(r{rm ASO})$; we also develop efficient algorithms for solving the key subproblems involved in BCD and APG. The experiments on the Yahoo webpages datasets and the Drosophila gene expression pattern images datasets demonstrate the effectiveness and efficiency of the proposed algorithms and confirm our theoretical analysis.
Autors: Chen, Jianhui;Tang, Lei;Liu, Jun;Ye, Jieping;
Appeared in: IEEE Transactions on Pattern Analysis and Machine Intelligence
Publication date: May 2013, volume: 35, issue:5, pages: 1025 - 1038
Publisher: IEEE
 
» A correlation based method for discrimination between inrush and short circuit currents in differential protection of power transformer using Discrete Wavelet Transform: Theory, simulation and experimental validation
Abstract:


Autors:
Appeared in: International Journal of Electrical Power & Energy Systems
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A Current Based Model for Load Flow Studies With UPFC
Abstract:
This paper deals with an alternative proposition for the steady state modeling of unified power flow controller (UPFC). Since current limitations are determinant to FACTS apparatus design, the proposed current based model (CBM) assumes the current as variable, allowing easy manipulation of current restrictions in optimal power flow evaluations. The performance of the proposed model and of the power injection model (PIM) are compared through a Quasi-Newton optimization approach. Two operating situations of a medium size network with 39 busbars were studied from the point of view of optimization and current limits, observing the performance of the UPFC modeling.
Autors: Pereira, M.;Zanetta, L.C.;
Appeared in: IEEE Transactions on Power Systems
Publication date: May 2013, volume: 28, issue:2, pages: 677 - 682
Publisher: IEEE
 
» A Decentralized Control of Partitioned Power Networks for Voltage Regulation and Prevention Against Disturbance Propagation
Abstract:
This paper investigates a secondary voltage control based on a graph partitioning method. The method divides the power system into regions to eventually prevent the propagation of disturbances and to minimize the interaction between these regions. The optimized number of regions is found based on the bus voltage sensitivity to disturbances being applied to loads in each region. Then, a number of representative buses are labelled as pilot buses displaying the critical point for voltage control in each region. The control uses decentralized controllers to eliminate voltage violations resulting from load variations and disturbances in the system. The decentralized controllers are implemented by fuzzy logic which is trained via offline simulations; they inject required reactive power into the regions to correct voltage violations. The methodology is applied to the IEEE 118-bus network. The results show the performance and ability of graph partitioning and fuzzy secondary voltage control to regulate the voltage and to avoid propagation of disturbances between regions.
Autors: Mehrjerdi, H.;Lefebvre, S.;Saad, M.;Asber, D.;
Appeared in: IEEE Transactions on Power Systems
Publication date: May 2013, volume: 28, issue:2, pages: 1461 - 1469
Publisher: IEEE
 
» A Decentralized Controller-Observer Scheme for Multi-Agent Weighted Centroid Tracking
Abstract:
In this technical note a decentralized controller-observer scheme for a multi-agent system is presented. The key idea is to develop, for each agent, an observer of the collective system's state and a motion controller. The observer is updated using only information from the agent itself and from its neighbors; the motion controller is designed in order to allow the team's weighted centroid to track an assigned time-varying reference. Convergence of the overall scheme is proven for directed and undirected communication graphs; moreover the extensions to the case of switching communication topologies and to the presence of saturation in the control input are discussed. Finally, numerical simulations are illustrated to validate the approach.
Autors: Antonelli, G.;Arrichiello, F.;Caccavale, F.;Marino, A.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: May 2013, volume: 58, issue:5, pages: 1310 - 1316
Publisher: IEEE
 
» A Decentralized Self-Adaptation Mechanism for Service-Based Applications in the Cloud
Abstract:
Cloud computing, with its promise of (almost) unlimited computation, storage, and bandwidth, is increasingly becoming the infrastructure of choice for many organizations. As cloud offerings mature, service-based applications need to dynamically recompose themselves to self-adapt to changing QoS requirements. In this paper, we present a decentralized mechanism for such self-adaptation, using market-based heuristics. We use a continuous double-auction to allow applications to decide which services to choose, among the many on offer. We view an application as a multi-agent system and the cloud as a marketplace where many such applications self-adapt. We show through a simulation study that our mechanism is effective for the individual application as well as from the collective perspective of all applications adapting at the same time.
Autors: Nallur, Vivek;Bahsoon, Rami;
Appeared in: IEEE Transactions on Software Engineering
Publication date: May 2013, volume: 39, issue:5, pages: 591 - 612
Publisher: IEEE
 
» A deeper insight into the operation regime of all-polymeric electrochemical transistors
Abstract:
All-Organic Electrochemical Transistors (OECTs) realized by employing Poly(3,4-EthyleneDiOxyThiophene) doped with Poly(Styrene Sulfonate) as conductive polymer show a dependence of their behavior on the gate to channel area ratio. This peculiarity has been investigated and the working mechanism has been explained in view of the behavior of the ionic component of the device. In particular, taking into account the current theory of OECT behavior, we have focused our attention on the role of the gate, trying to clarify if these devices may be considered as working in Faradaic or capacitive regime.
Autors: Demelas, M.;Scavetta, E.;Basirico, L.;Rogani, R.;Bonfiglio, A.;
Appeared in: Applied Physics Letters
Publication date: May 2013, volume: 102, issue:19, pages: 193301 - 193301-4
Publisher: IEEE
 
» A Delay-Aware Network Structure for Wireless Sensor Networks With In-Network Data Fusion
Abstract:
A wireless sensor network (WSN) comprises a large number of wireless sensor nodes. Wireless sensor nodes are battery-powered devices with limited processing and transmission power. Therefore, energy consumption is a critical issue in system designs of WSNs. In-network data fusion and clustering have been shown to be effective techniques in reducing energy consumption in WSNs. However, clustering can introduce bottlenecks to a network, which causes extra delays in a data aggregation process. The problem will be more severe when in-network data fusion does not yield any size reduction in outgoing data. Such problems can be greatly alleviated by modifying the network structure. In this paper, a delay-aware network structure for WSNs with in-network data fusion is proposed. The proposed structure organizes sensor nodes into clusters of different sizes so that each cluster can communicate with the fusion center in an interleaved manner. An optimization process is proposed to optimize intra-cluster communication distance. Simulation results show that, when compared with other existing aggregation structures, the proposed network structure can reduce delays in data aggregation processes and keep the total energy consumption at low levels provided that data are only partially fusible.
Autors: Cheng, C.-T.;Leung, H.;Maupin, P.;
Appeared in: IEEE Sensors Journal
Publication date: May 2013, volume: 13, issue:5, pages: 1622 - 1631
Publisher: IEEE
 
» A design methodology for optimally folded, pipelined architectures in VLSI applications using projective space lattices
Abstract:


Autors:
Appeared in: Microprocessors and Microsystems
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A Digital Current Control of Quasi-Z-Source Inverter With Battery
Abstract:
This paper presents a fixed frequency operating sliding mode (SM) current control method with fast response and improved stability. Different from the conventional SM control with variable switching frequency, the fixed-frequency SM controller is proposed to control the modulation index and shoot-through duty ratio of the voltage-fed quasi-Z-source inverter (qZSI), which will not increase the passive components and filter design difficulty. A large-signal dynamic model of the system has been established, which can be used for the system stability control in a wide operating range. By using linear approximation, the system small-signal model is also obtained to analyze the control system stability and transient response. Compared with the conventional current mode controller, the proposed SM controller can achieve faster response, lower current ripple and better stability for qZSI when the supply and load variation is large. Experimental results are presented to demonstrate the validity of the theoretical design and the effectiveness of the proposed controller.
Autors: Jianfeng Liu;Shuai Jiang;Dong Cao;Fang Zheng Peng;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: May 2013, volume: 9, issue:2, pages: 928 - 937
Publisher: IEEE
 
» A digital magnetic resonance imaging spectrometer using digital signal processor and field programmable gate array
Abstract:
A digital spectrometer for low-field magnetic resonance imaging is described. A digital signal processor (DSP) is utilized as the pulse programmer on which a pulse sequence is executed as a subroutine. Field programmable gate array (FPGA) devices that are logically mapped into the external addressing space of the DSP work as auxiliary controllers of gradient control, radio frequency (rf) generation, and rf receiving separately. The pulse programmer triggers an event by setting the 32-bit control register of the corresponding FPGA, and then the FPGA automatically carries out the event function according to preset configurations in cooperation with other devices; accordingly, event control of the spectrometer is flexible and efficient. Digital techniques are in widespread use: gradient control is implemented in real-time by a FPGA; rf source is constructed using direct digital synthesis technique, and rf receiver is constructed using digital quadrature detection technique. Well-designed performance is achieved, including 1 μs time resolution of the gradient waveform, 1 μs time resolution of the soft pulse, and 2 MHz signal receiving bandwidth. Both rf synthesis and rf digitalization operate at the same 60 MHz clock, therefore, the frequency range of transmitting and receiving is from DC to ∼27 MHz. A majority of pulse sequences have been developed, and the imaging performance of the spectrometer has been validated through a large number of experiments. Furthermore, the spectrometer is also suitable for relaxation measurement in nuclear magnetic resonance field.
Autors: Liang, Xiao;Binghe, Sun;Yueping, Ma;Ruyan, Zhao;
Appeared in: Review of Scientific Instruments
Publication date: May 2013, volume: 84, issue:5, pages: 054702 - 054702-8
Publisher: IEEE
 
» A distributed protocol for motion coordination in free-range vehicular systems
Abstract:


Autors:
Appeared in: Automatica
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A domain decomposition method for the simulation of fracture in polysilicon MEMS
Abstract:


Autors:
Appeared in: Microelectronics Reliability
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A DSP-Based Implementation of the Theory in Active Power Filtering Under Nonideal Voltage Conditions
Abstract:
This paper presents a three-phase three-wire shunt active power filtering system based on two level voltage source inverter which is intended to compensate both current harmonic distortion and reactive power under nonideal voltage conditions. The concepts of the p-q theory are used to calculate the reference compensating current according to the compensation strategy. An improvement in an existing phase-locked loop circuit is proposed to handle the shape of the small amount of additional current needed to cover the power system losses. In the dc-voltage loop, an optimal set point value which minimizes the harmonic distortion of the supply current and depends on power to be compensated is also proposed. Digital signal processor based implementation of the whole control system is described with details on the developed experimental platform dSPACE DS1103 for rapid prototyping. Experimental results obtained from a 15 kVA laboratory setup verify the effectiveness of the active filtering system.
Autors: Popescu, M.;Bitoleanu, A.;Suru, V.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: May 2013, volume: 9, issue:2, pages: 880 - 889
Publisher: IEEE
 
» A Dual Inverter Fed Four-Level Open-End Winding Induction Motor Drive With a Nested Rectifier-Inverter
Abstract:
A four-level inverter drive could be obtained by feeding an open-end winding induction motor by two two-level inverters from either side with unequal dc-link voltages, which are in the ratio of 2:1. This inverter modulation scheme is capable of producing 64 space-vector combinations. Some of the space vector combinations could result in the overcharging of the dc-link capacitor corresponding to the inverter operating with the lower voltage. In this paper, a new power circuit topology is proposed, in which, a rectifier-inverter combination is nested within a conventional two-level inverter configuration. The output of the conventional two-level inverter feeds one end of the open-end winding induction motor, while the output of the nested rectifier-inverter combination feeds the other end. The total dc-link voltage needed in the proposed topology is only 77% of the one needed in the conventional multilevel inverters. Also, the problem of zero-sequence current, commonly encountered in open-end winding induction motor drives, is avoided by resorting to a decoupled space vector modulation PWM scheme, which eliminates the zero-sequence voltage of the dual-inverter system by forcing the sampled average of the zero sequence voltage of individual inverters to zero.
Autors: Reddy, B.V.;Somasekhar, V.T.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: May 2013, volume: 9, issue:2, pages: 938 - 946
Publisher: IEEE
 
» A Dual Inverter-Based Supercapacitor Direct Integration Scheme for Wind Energy Conversion Systems
Abstract:
Interfacing converters used in connecting energy storage systems like supercapacitors and battery banks to wind power systems introduce additional cost and power losses. This paper therefore presents a direct integration scheme for supercapacitors used in mitigating short-term power fluctuations in wind power systems. This scheme uses a dual inverter topology for both grid connection and interfacing a supercapacitor bank. The main inverter of the dual inverter system is powered by the rectified output of a wind turbine-coupled permanent-magnet synchronous generator. The auxiliary inverter is directly connected to the supercapacitor bank. With this approach, an interfacing converter is not required, and there are no associated costs and power losses incurred. The operation of the proposed system is discussed in detail. Simulation and experimental results are presented to verify the efficacy of the proposed system in suppressing short-term wind power fluctuations.
Autors: Jayasinghe, S.D.G.;Vilathgamuwa, D.M.;Madawala, U.K.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: May 2013, volume: 49, issue:3, pages: 1023 - 1030
Publisher: IEEE
 
» A Dual-Gate Graphene FET Model for Circuit Simulation—SPICE Implementation
Abstract:
This paper presents a SPICE compatible model of a dual-gate bilayer graphene field-effect transistor. The model describes the functionality of the transistor in all the regions of operation for both hole and electron conduction. We present closed-form analytical equations that define the boundary points between the regions to ensure Jacobian continuity for efficient circuit simulator implementation. A saturation displacement current is proposed to model the drain current when the channel becomes ambipolar. The model proposes a quantum capacitance that varies with the surface potential. The model has been implemented in Berkeley SPICE-3, and it shows a good agreement against experimental data with the normalized root-mean-square error less than .
Autors: Umoh, I.J.;Kazmierski, T.J.;Al-Hashimi, B.M.;
Appeared in: IEEE Transactions on Nanotechnology
Publication date: May 2013, volume: 12, issue:3, pages: 427 - 435
Publisher: IEEE
 
» A dynamic local method for bandwidth adaptation in bundle links to conserve energy in core networks
Abstract:


Autors:
Appeared in: Optical Switching and Networking
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A fast algorithm for color space conversion and rounding error analysis based on fixed-point digital signal processors
Abstract:


Autors:

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Highlights

Appeared in: Computers & Electrical Engineering
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A fast algorithm for nonconvex approaches to sparse recovery problems
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Autors:

Highlights

Appeared in: Signal Processing
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A fast LDPC encoder/decoder for small/medium codes
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Autors:
Appeared in: Microelectronics Journal
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A fault diagnosis method for three-phase rectifiers
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Autors:
Appeared in: International Journal of Electrical Power & Energy Systems
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A fault tolerant control allocation scheme with output integral sliding modes
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Autors:
Appeared in: Automatica
Publication date: May 2013
Publisher: Elsevier B.V.
 
» A feature-based method for NC machining time estimation
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Highlights

Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: May 2013
Publisher: Elsevier B.V.
 

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