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Electrical and Electronics Engineering publications abstract of: 05-2012 sorted by title, page: 0
» "It's the Net, Stupid"
Abstract:
Devices on the Internet of all kinds benefit both from their connectivity and their ability to interact with large-scale computational resources that form part of the Internet ecosystem. Internet-based systems can manage networked devices, record and analyze their activities, and improve our ability to visualize the operation of large-scale aggregations of Internet-enabled systems
Autors: Cerf, Vinton G.;
Appeared in: IEEE Internet Computing
Publication date: May 2012, volume: 16, issue:3, pages: 96 - 96
Publisher: IEEE
 
» “Erratum: “Polarization engineered 1-dimensional electron gas arrays” [J. Appl. Phys. 111, 043715 (2012)]”
Abstract:
Autors: Nath, Digbijoy N.;Park, Pil Sung;Esposto, Michele;Brown, David;Keller, Stacia;Mishra, Umesh K.;Rajan, Siddharth;
Appeared in: Journal of Applied Physics
Publication date: May 2012, volume: 111, issue:9, pages: 099901 - 099901-1
Publisher: IEEE
 
» “The Whole Is More Than the Sum of Its Parts”—Aristotle [President's Column]
Abstract:
Autors: Kolias, N.;
Appeared in: IEEE Microwave Magazine
Publication date: May 2012, volume: 13, issue:4, pages: 22 - 60
Publisher: IEEE
 
» 'Fingerprinting for food stamps' row triggers North American privacy debate
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Autors:
Appeared in: Biometric Technology Today
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 0.07 mm2, 2 mW, 75 MHz-IF, fourth-order BPF using source-follower-based resonator in 90 nm CMOS
Abstract:
A highly-transistorised bandpass filter (BPF) using a source-followerbased (SFB) resonator is proposed. It benefits from the advantageous properties of the source follower (e.g. no parasitic pole, linear VGS I/O relationship, high-input and low-output impedances), while combining it with a compact and low-power grounded differential active inductor to synthesise the complex poles. Fabricated in 90 nm CMOS, a fourth-order 75 MHz-IF BPF prototype merging two such SFB resonators measures a 10 MHz bandwidth at 2 mW of power. The die size is merely 0.07 mm2.
Autors: Chen, Y.;Mak, P.-I.;Zhang, L.;Wang, Y.;
Appeared in: Electronics Letters
Publication date: May 2012, volume: 48, issue:10, pages: 552 - 554
Publisher: IEEE
 
» 0.5V bulk-driven analog building blocks
Abstract:


Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 1-50-MHz VHF electromagnetic sensor-interface power-attenuation detector circuit
Abstract:


Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 1-Bit Reconfigurable Unit Cell Based on PIN Diodes for Transmit-Array Applications in -Band
Abstract:
An electronically reconfigurable unit cell with 1-bit phase quantization (0 /180 ) is proposed for -band linear polarization transmit arrays. It consists of two rectangular patch antennas loaded by U- and O-slots and connected by a metallized via-hole. The transmission phase is controlled using two p-i-n diode switches integrated in the O-slot. An equivalent lumped-element circuit model is implemented and compared successfully to full-wave simulations. The numerical results are validated experimentally using an ad-hoc waveguide simulator. The prototype exhibits low insertion loss (1.8 dB) with the same level for both phase states, a broad 3-dB transmission bandwidth (14.7%), a 1-dB compression point of 13–15 dBm, and a gain of 5 dBi at 9.75 GHz. The performance and simplicity of the proposed unit cell make it attractive to build electronically steerable transmit arrays in -band.
Autors: Clemente, A.;Dussopt, L.;Sauleau, R.;Potier, P.;Pouliguen, P.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: May 2012, volume: 60, issue:5, pages: 2260 - 2269
Publisher: IEEE
 
» 100G and Beyond Transmission Technologies for Evolving Optical Networks and Relevant Physical-Layer Issues
Abstract:
As 100-Gb/s digital coherent systems enter commercial deployment, an effort is underway to uncover the technologies that will enable the next-generation optical fiber communication systems. We envisage that future optical transport will be software-defined, enabling flexible allocation of bandwidth resources, with dynamically adjustable per-channel data rates based on instantaneous traffic demand and quality-of-service requirements, leading to unprecedented network agility. Software-defined transponders will have the programmability to adopt various modulation formats, coding rates, and the signal bandwidth based on the transmission distance and type of fiber. Digital signal processing will become increasingly ubiquitous and sophisticated, capable of compensating all types of channel impairments, enabling advanced forward error correction coding, and performing functions previously handled poorly by optical analog hardware such as spectrum shaping and demultiplexing of optical channels.
Autors: Ip, E.;Ji, P.;Mateo, E.;Huang, Y.-K.;Xu, L.;Qian, D.;Bai, N.;Wang, T.;
Appeared in: Proceedings of the IEEE
Publication date: May 2012, volume: 100, issue:5, pages: 1065 - 1078
Publisher: IEEE
 
» 19-Gb/s adaptively modulated optical OFDM transmission by separated I/Q baseband delivery using 1GHz RSOAs
Abstract:


Autors:
Appeared in: Optical Fiber Technology
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 2-D sizing of sodium oxalate crystals by automated optical image analysis
Abstract:


Autors:

Graphical abstract

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Appeared in: Advanced Powder Technology
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 2011 RFIC Symposium Mini-Special Issue Editorial
Abstract:
Autors: Ponchak, G. E.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: May 2012, volume: 60, issue:5, pages: 1185 - 1185
Publisher: IEEE
 
» 20nm Gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2 source/drain
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Autors:
Appeared in: Solid-State Electronics
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 24-GHz Bandwidth-Enhanced Microstrip Array Printed on a Single-Layer Electrically-Thin Substrate for Automotive Applications
Abstract:
A 24-GHz microstrip array antenna is developed on a single-layer electrically-thin substrate to provide a cost-effective solution for automotive applications. By etching two straight slots close to and parallel with the non-radiating edges, the impedance bandwidth of a conventional rectangular microstrip patch is enhanced without affecting its radiation characteristics. To demonstrate the effectiveness of the proposed technique, an 8 8 planar array with a specified sidelobe level of 25 dB in both the -plane and -plane is studied and prototyped on the commercial substrate RT/duroid 5880 with a thickness of 0.25 mm. The measured impedance bandwidth for VSWR less than 2 is about 1.8 GHz, which corresponds to a relative bandwidth of 7.5%. In addition, the measured gain is 22.5 dBi at the center frequency while it is higher than 21 dBi over a frequency band of 1 GHz. Finally, the measured sidelobe level is 20 dB in the -plane and 18 dB in the -plane.
Autors: Han, L.;Wu, K.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: May 2012, volume: 60, issue:5, pages: 2555 - 2558
Publisher: IEEE
 
» 32.9 nV/rt Hz 60.6 dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC
Abstract:
The dual-band recording of the local-field potential (LFP, 0.1–200 Hz) and the spike potential (SP, 200 Hz–10 kHz) is important for physiological studies at the cellular level. Recent study shows that the LFP signal plays important roles in modulating many profound cellular mechanisms. Although various bio-signal acquisition circuits have been reported over the years, few designs are applicable to capture both LFP and SP signals. To record both signals accurately, acquisition circuits need low noise and good linearity in both bands. In this paper, we report the design of a dual-band acquisition IC for microelectrode array (MEA) recording. The novel design uses a continuous-time (CT) front-end with chopping to suppress the noise in the LFP band, and a discrete-time (DT) back-end to achieve good linearity. The acquisition channel is fully differential, which leads to a high common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) without the 50 Hz injection. The design interfaces the microelectrode with a transistor gate, which has high input impedance. A prototype monolithic acquisition IC is fabricated in a 0.35 m CMOS process. It includes 16 channels and an 11 bit successive-approximation (SAR) analog-to-digital converter (ADC). Every channel acquires cellular signals up to 20 mV with 32.9 nV/Hz and nonlinearity. The good linearity effectively prevents the aliasing and mixing between the two bands. For LFP signal, the recording noise is 0.9 V$_{rm rms}$. For SP signal, the recording noise is 3.3 V . The new design has high input impedance (320 M @1 kHz), high CMRR ( 110 dB) and PSRR ( 110 dB). The noise-efficiency factor (NEF) of the acquisition channel is 7.6. The IC is experimented to record the field potential from cultured rat cardiomyocytes in-vitro. Overall, the new MEA acquisition channel achieves the state-of-art performance.
Autors: Guo, J.;Yuan, J.;Huang, J.;Law, J. K.-Y.;Yeung, C.-K.;Chan, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2012, volume: 47, issue:5, pages: 1209 - 1220
Publisher: IEEE
 
» 32.9 nV/rt Hz 60.6 dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC
Abstract:
The dual-band recording of the local-field potential (LFP, 0.1-200 Hz) and the spike potential (SP, 200 Hz-10 kHz) is important for physiological studies at the cellular level. Recent study shows that the LFP signal plays important roles in modulating many profound cellular mechanisms. Although various bio-signal acquisition circuits have been reported over the years, few designs are applicable to capture both LFP and SP signals. To record both signals accurately, acquisition circuits need low noise and good linearity in both bands. In this paper, we report the design of a dual-band acquisition IC for microelectrode array (MEA) recording. The novel design uses a continuous-time (CT) front-end with chopping to suppress the noise in the LFP band, and a discrete-time (DT) back-end to achieve good linearity. The acquisition channel is fully differential, which leads to a high common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) without the 50 Hz injection. The design interfaces the microelectrode with a transistor gate, which has high input impedance. A prototype monolithic acquisition IC is fabricated in a 0.35 μm CMOS process. It includes 16 channels and an 11 bit successive-approximation (SAR) analog-to-digital converter (ADC). Every channel acquires cellular signals up to 20 mVpp with 32.9 nV/Hz0.5 and <; 0.1% nonlinearity. The good linearity effectively prevents the aliasing and mixing between the two bands. For LFP signal, the recording noise is 0.9 μVrms. For SP signal, the recording noise is 3.3 μVrms. The new design has high input impedance (320 M Ω@1 kHz), high CMRR ( >; 110 dB) and PSRR ( >; 110 dB). The noise-efficiency factor (NEF) of the acquisition channel is 7.6. The IC is experimented to record the field potential from cultured rat cardiomyocytes in-vitro. Overall, the new MEA acquisition channel achieves the state-of-art performance.
Autors: Jing Guo;Jie Yuan;Jiageng Huang;Law, J.K.-Y.;Chi-Kong Yeung;Mansun Chan;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2012, volume: 47, issue:5, pages: 1209 - 1220
Publisher: IEEE
 
» 3D Force sensor for Biomechanical applications
Abstract:


Autors:
Appeared in: Sensors and Actuators A: Physical
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 3D model based tracking for omnidirectional vision: A new spherical approach
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Autors:

Highlights

Appeared in: Robotics and Autonomous Systems
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 3D thermal-aware floorplanner using a MILP approximation
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Autors:
Appeared in: Microprocessors and Microsystems
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 5-11GHz CMOS PA with 158.941ps group delay and low power using current-reused technique
Abstract:


Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: May 2012
Publisher: Elsevier B.V.
 
» 60-GHz AMC-Based Circularly Polarized On-Chip Antenna Using Standard 0.18- m CMOS Technology
Abstract:
A 60-GHz artificial magnetic conductor (AMC)-based circularly polarized (CP) on-chip antenna has been designed and fabricated using standard 0.18- m six metal-layer CMOS technology. The design consists of a wideband circularly polarized loop antenna at the top layer M6 and a novel AMC structure at the bottom layer M1. The size of the antenna including the modified AMC structure is 1.8 1.8 0.3 mm . The circular open-loop structure is employed for antenna design because the gap within the loop can excite traveling wave current and then achieve circular polarized radiation. In addition, it is found that the bandwidth of circular polarization can be significantly increased by introducing one more inner parasitic loop. With the modified AMC structure integrated into the bottom layer, the antenna performance can be optimized and improved as more design freedom is introduced. The proposed antenna can offer a simulated peak gain of 3.7 dBi and a measured gain of 4.4 dBi, respectively, as well as simulated and measured axial ratio bandwidth to cover from 57 to 67 GHz.
Autors: Bao, X.-Y.;Guo, Y.-X.;Xiong, Y.-Z.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: May 2012, volume: 60, issue:5, pages: 2234 - 2241
Publisher: IEEE
 
» -Norm-Based Reconstruction Algorithm for Particle Sizing
Abstract:
An l1-norm-based reconstruction algorithm for particle sizing by using l1-regularization is introduced in this paper. Both simulation and experiment were conducted by using a photodiode array detector to evaluate the performance of the algorithm. Particle size distributions retrieved by using Chahine, truncated singular value decomposition (TSVD), and Tikhonov algorithms were also obtained to compare with that obtained by the l1-norm-based algorithm. In computer simulation, Rosin-Rammler, normal, and lognormal distributions of spherical particles from 7.6 to 98 in diameter were created. The measurement data of the photodiode array detector were generated based on Fraunhofer diffraction theory. Simulation results show that the l1-norm-based algorithm not only performs better than Chahine algorithm but also performs similar to the TSVD and Tikhonov algorithms for noise-free data and is less sensitive to the noise than the TSVD and Tikhonov algorithms for noise-contaminated data. In experiment, a standard particle plate covered by particles with known size distribution, i.e., Rosin-Rammler distribution, was used. The experimental results validated the effectiveness of the l1-norm-based algorithm.
Autors: Lijun Xu;Lei Xin;Zhang Cao;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: May 2012, volume: 61, issue:5, pages: 1395 - 1404
Publisher: IEEE
 
» Sampled Signal Reconstruction With Causality Constraints—Part II: Theory
Abstract:
This paper provides the theoretic foundation for the design of optimal reconstructors (also known as interpolators/holds) with a prescribed degree of causality. A compact frequency-domain solution is derived that mimics known interpolation techniques for ordinary transfer functions. In parallel, an extensive state space solution is documented. It complements the frequency-domain solution in that it constructively proves the various claims, and it also makes the solution concrete. The state space solution requires the solution of one Riccati and one Lyapunov matrix equation.
Autors: Meinsma, G.;Mirkin, L.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: May 2012, volume: 60, issue:5, pages: 2273 - 2285
Publisher: IEEE
 
» -Person Card Game Approach for Solving SET -COVER Problem in Wireless Sensor Networks
Abstract:
Solutions to SET K-COVER problem can prolong the lifetime of wireless sensor networks (WSNs) by partitioning the sensors into sets. In this paper, a novel purely distributed method for solving SET K-COVER problem is introduced based on the game theory, in which we consider the SET K-COVER problem as a noncooperative N-person card game. The sensors in WSN are considered as the players, the cover sets chosen by N sensors are considered as the strategies, and the sensing area covered alone is considered as the payoff function for each sensor. After the gaming process, the best strategies that all of the players have chosen constitute the Nash equilibrium. In addition, we analyze the effects of the initial strategies on the gaming result and propose a solution to avoid this effect in order to obtain a better coverage performance. We also extend the optimality of Nash equilibrium in the coverage game to a more general case. Besides that, the analysis of the convergence performance and the message complexity of the proposed algorithm are also presented. Extensive simulations have been conducted to show the superiority of the proposed algorithm in convergence, robustness, and coverage, comparing with the random, K-COVER, and synchronous Nash equilibria convergence algorithms. Finally, based on the results from real experiments on both small- and large-scale WSNs, we conclude that the proposed algorithm can be applied in real application environment and is also of good performance in both convergence and coverage. Furthermore, we also provide the comparisons between results from simulations and real experiments when some practical issues are considered.
Autors: Qiang Wang;Wenjie Yan;Yi Shen;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: May 2012, volume: 61, issue:5, pages: 1522 - 1535
Publisher: IEEE
 
» Out of Region Incrementing Scheme in Visual Cryptography
Abstract:
Recently, Wang introduced a novel (2, ) region incrementing visual cryptographic scheme (RIVCS), which can gradually reconstruct secrets in a single image with multiple security levels. In RIVCS, the secret image is subdivided into multiple regions in such a way that any shadow images, where , can be used to reveal the th region. However, Wang's scheme suffers from the incorrect-color problem, which the colors of reconstructed images may be reversed (i.e., the black and white are reversed). If the color of text is also the secret information, the incorrect-color problem will compromise the secret. Additionally, Wang's scheme is only suitable for the 2-out-of- case, i.e., -RIVCS where . In this paper, we propose a general -RIVCS, where and are any integers, that is able to reveal correct colors of all regions. This paper has made three main contributions: 1) our scheme is a general -RIVCS, where and can be any integers; 2) the incorrect-color problem is solved; and 3) our - RIVCS is theoretically proven to satisfy the security and contrast conditions.
Autors: Yang, C.-N.;Shih, H.-W.;Wu, C.-C.;Harn, L.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: May 2012, volume: 22, issue:5, pages: 799 - 810
Publisher: IEEE
 
» Control of Switched Nonlinear Systems in -Normal Form Using Multiple Lyapunov Functions
Abstract:
The problem of control of switched nonlinear systems in -normal form is investigated in this technical note where the solvability of the control problem for individual subsystems is unnecessary. Using the generalized multiple Lyapunov functions method and the adding a power integrator technique, we design a switching law and construct continuous state feedback controllers of subsystems explicitly by a recursive design algorithm to produce global asymptotical stability and a prescribed performance level. Multiple Lyapunov functions are exploited to reduce the conservativeness caused by adoption of a common Lyapunov function for all subsystems, which is usually required when applying the backstepping-like recursive design scheme. An example is provided to demonstrate the effectiveness of the proposed design method.
Autors: Long, L.;Zhao, J.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: May 2012, volume: 57, issue:5, pages: 1285 - 1291
Publisher: IEEE
 
» Retention Distribution Tail in a Multitime-Program MLC SONOS Memory Due to a Random-Program-Charge-Induced Current-Path Percolation Effect
Abstract:
A retention distribution tail in a multitime-program (MTP) silicon–oxide–nitride–oxide–silicon (SONOS) memory is investigated. We characterize a single-program-charge-loss-induced in nor-type SONOS multilevel cells (MLCs). Our measurement shows the following: 1) A single-charge-loss-induced exhibits an exponential distribution in magnitudes, which is attributed to a random-program-charge-induced current-path percolation effect, and 2) the standard deviation of the exponential distribution depends on the program-charge density and increases with a program level in an MLC SONOS. In addition, we measure a retention distribution in a 512-Mb MTP SONOS memory and observe a significant retention tail. A numerical retention distribution model including the percolation effect and a Poisson-distribution-based multiple-charge-loss model is developed. Our model agrees with the measured retention distribution in a 512-Mb SONOS well. The observed tail is realized mainly due to the percolation effect.
Autors: Chung, Y.-T.;Huang, T.-I.;Li, C.-W.;Chou, Y.-L.;Chiu, J.-P.;Wang, T.;Lee, M. Y.;Chen, K.-C.;Lu, C.-Y.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: May 2012, volume: 59, issue:5, pages: 1371 - 1376
Publisher: IEEE
 
» Control of Switched Nonlinear Systems in -Normal Form Using Multiple Lyapunov Functions
Abstract:
The problem of H control of switched nonlinear systems in p-normal form is investigated in this technical note where the solvability of the H control problem for individual subsystems is unnecessary. Using the generalized multiple Lyapunov functions method and the adding a power integrator technique, we design a switching law and construct continuous state feedback controllers of subsystems explicitly by a recursive design algorithm to produce global asymptotical stability and a prescribed H performance level. Multiple Lyapunov functions are exploited to reduce the conservativeness caused by adoption of a common Lyapunov function for all subsystems, which is usually required when applying the backstepping-like recursive design scheme. An example is provided to demonstrate the effectiveness of the proposed design method.
Autors: Lijun Long;Jun Zhao;
Appeared in: IEEE Transactions on Automatic Control
Publication date: May 2012, volume: 57, issue:5, pages: 1285 - 1291
Publisher: IEEE
 
» Out of Region Incrementing Scheme in Visual Cryptography
Abstract:
Recently, Wang introduced a novel (2, n ) region incrementing visual cryptographic scheme (RIVCS), which can gradually reconstruct secrets in a single image with multiple security levels. In RIVCS, the secret image is subdivided into multiple regions in such a way that any t shadow images, where 2 ≤ tn, can be used to reveal the (t-1) th region. However, Wang's scheme suffers from the incorrect-color problem, which the colors of reconstructed images may be reversed (i.e., the black and white are reversed). If the color of text is also the secret information, the incorrect-color problem will compromise the secret. Additionally, Wang's scheme is only suitable for the 2-out-of-n case, i.e., (k,n)-RIVCS where k=2. In this paper, we propose a general (k,n)-RIVCS, where k and n are any integers, that is able to reveal correct colors of all regions. This paper has made three main contributions: 1) our scheme is a general (k,n)-RIVCS, where k and n can be any integers; 2) the incorrect-color problem is solved; and 3) our (k,n)-RIVCS is theoretically proven to satisfy the security and contrast conditions.
Autors: Ching-Nung Yang;Hsiang-Wen Shih;Chih-Cheng Wu;Lein Harn;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: May 2012, volume: 22, issue:5, pages: 799 - 810
Publisher: IEEE
 
» Retention Distribution Tail in a Multitime-Program MLC SONOS Memory Due to a Random-Program-Charge-Induced Current-Path Percolation Effect
Abstract:
A Vt retention distribution tail in a multitime-program (MTP) silicon-oxide-nitride-oxide-silicon (SONOS) memory is investigated. We characterize a single-program-charge-loss-induced ΔVt in NOR-type SONOS multilevel cells (MLCs). Our measurement shows the following: 1) A single-charge-loss-induced ΔVt exhibits an exponential distribution in magnitudes, which is attributed to a random-program-charge-induced current-path percolation effect, and 2) the standard deviation of the exponential distribution depends on the program-charge density and increases with a program Vt level in an MLC SONOS. In addition, we measure a Vt retention distribution in a 512-Mb MTP SONOS memory and observe a significant Vt retention tail. A numerical Vt retention distribution model including the percolation effect and a Poisson-distribution-based multiple-charge-loss model is developed. Our model agrees with the measured Vt retention distribution in a 512-Mb SONOS well. The observed Vt tail is realized mainly due to the percolation effect.
Autors: Yueh-Ting Chung;Tzu-I Huang;Chi-Wei Li;You-Liang Chou;Jung-Piao Chiu;Tahui Wang;Lee, M.Y.;Kuang-Chao Chen;Chih-Yuan Lu;
Appeared in: IEEE Transactions on Electron Devices
Publication date: May 2012, volume: 59, issue:5, pages: 1371 - 1376
Publisher: IEEE
 
» A 0.1–0.3 V 40–123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters
Abstract:
This paper presents a 40–130 fJ/bit/ch on-chip data link design under a 0.1–0.3 V power supply. A bootstrapped CMOS repeater is proposed to drive a 10 mm on-chip bus. It features a to swing to enhance the driving capability and reduces the sub-threshold leakage current. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. A test chip is fabricated in a 55 nm SPRVT Low-K CMOS process. The measured results demonstrate that for a 10 mm on-chip bus, the achievable data rate is 0.8–100 Mbps, and the energy consumption is 40–123 fJ per bit under 0.1–0.3 V .
Autors: Ho, Y.;Su, C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2012, volume: 47, issue:5, pages: 1242 - 1251
Publisher: IEEE
 
» A 0.2–2.6 GHz Wideband Noise-Reduction Gm-Boosted LNA
Abstract:
This letter presents a wideband low-noise amplifier (LNA) which utilizes -boosted and noise-reduction techniques. The proposed DC-coupled 2-stage LNA employs an error amplifier to cancel the DC-offset voltage between the differential DC-coupled paths. The LNA is implemented in 90-nm digital CMOS technology. Within 0.2–2.6 GHz wideband applications, the LNA achieves 24 dB voltage gain, 1.9–2.9 dB NF, 3 dBm IIP3. The core power of the LNA draws 9 mA from 1 V supply voltage and occupies 0.046 .
Autors: Lee, H.-C.;Wang, C.-S.;Wang, C.-K.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: May 2012, volume: 22, issue:5, pages: 269 - 271
Publisher: IEEE
 
» A 0.8–2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass ADC in 0.13 m CMOS
Abstract:
A reconfigurable bandpass continuous-time RF ADC tunable over the 0.8–2 GHz frequency range is presented. System- and circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in both the first- and second-Nyquist zones to enable a wide tuning range from a fixed sampling frequency of 3.2 GHz. A fully-integrated on-chip quadrature phase-locked loop (QPLL) allows quadrature phase synchronization between a raised-cosine DAC and a quantizer. Implemented in 0.13 m CMOS the fully-integrated prototype achieves SNDR values of 50 dB, 46 dB, and 40 dB over a 1 MHz bandwidth at 796.5 MHz, 1.001 GHz and 1.924 GHz carrier frequencies, respectively, with a total power consumption of 41 mW. The measured phase noise of the QPLL is 113 dBc/Hz at an offset frequency of 1 MHz and the reference spur is 74.5 dBc. The RMS period jitter is 1.38 ps at 3.2 GHz.
Autors: Gupta, S.;Gangopadhyay, D.;Lakdawala, H.;Rudell, J. C.;Allstot, D. J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2012, volume: 47, issue:5, pages: 1141 - 1153
Publisher: IEEE
 
» A 1-V 15-Bit Audio -ADC in 0.18 m CMOS
Abstract:
In this paper a 1-V supply, 15-bit ADC design for audio applications is presented. The second order CIFB modulator with a 3-bit internal quantizer is adopted. The design of noise transfer function (NTF) is discussed from the viewpoint of mitigating the quantization noise mixture effect. A single-capacitor summing circuit is proposed which eliminates additional amplification or deliberate reference scaling. Nonideal effect due to parasitic capacitance is discussed. With proper modulator architecture, the design of building blocks is relaxed. Low gain amplifier with high power efficiency can be adopted which saves power. The decimator is implemented with cascade subfilters. Time multiplexing of arithmetic resources is employed for low hardware cost. Fabricated in 0.18 m CMOS, the prototype ADC achieves 91.3 dB peak SNDR with 16 kHz. The modulator dissipates 190 W and the decimator consumes 170 W. The core area of the ADC is 0.5 mm . The modulator occupies 0.3 mm and the decimator occupies 0.2 mm .
Autors: Liu, L.;Li, D.;Chen, L.;Ye, Y.;Wang, Z.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: May 2012, volume: 59, issue:5, pages: 915 - 925
Publisher: IEEE
 
» A 1-V 15-Bit Audio -ADC in 0.18 m CMOS
Abstract:
In this paper a 1-V supply, 15-bit ADC design for audio applications is presented. The second order CIFB modulator with a 3-bit internal quantizer is adopted. The design of noise transfer function (NTF) is discussed from the viewpoint of mitigating the quantization noise mixture effect. A single-capacitor summing circuit is proposed which eliminates additional amplification or deliberate reference scaling. Nonideal effect due to parasitic capacitance is discussed. With proper modulator architecture, the design of building blocks is relaxed. Low gain amplifier with high power efficiency can be adopted which saves power. The decimator is implemented with cascade subfilters. Time multiplexing of arithmetic resources is employed for low hardware cost. Fabricated in 0.18 m CMOS, the prototype ADC achieves 91.3 dB peak SNDR with 16 kHz. The modulator dissipates 190 W and the decimator consumes 170 W. The core area of the ADC is 0.5 mm . The modulator occupies 0.3 mm and the decimator occupies 0.2 mm .
Autors: Liu, L.;Li, D.;Chen, L.;Ye, Y.;Wang, Z.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: May 2012, volume: 59, issue:5, pages: 915 - 925
Publisher: IEEE
 
» A 1.2V, 130nm CMOS parallel continuous-time ?? ADC for OFDM UWB receivers
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Graphical Abstract

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Appeared in: Microelectronics Journal
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS
Abstract:
This paper presents a 10-bit 80-MS/s successive approximation time-to-digital converter (TDC) with a decision-select structure for on-chip timing measurement applications. Time-domain successive approximation is realized utilizing a relative timing difference between input and reference timings. While the successive approximation scheme allows high bit resolutions and low power consumptions, the decision-select structure enables fast bit conversions that lead to high sampling rates. The decision-select structure unrolls the successive approximation iteration loop and removes time-consuming timing estimation and adjustment procedures to minimize bit conversion times. As the successive approximation scheme relies on a binary search, exponential delay lines are adopted to achieve good power and noise performances by reducing the total number of delay stages. The proposed TDC uses only 0.048 delay stages per bit conversion. A test-chip prototype fabricated in a 65-nm CMOS technology consumes 9.6 mW at 80-MS/s and demonstrates 0.23-pJ/conversion-step figure-of merit (FOM) and 0.5-LSB single-shot precision.
Autors: Chung, H.;Ishikuro, H.;Kuroda, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2012, volume: 47, issue:5, pages: 1232 - 1241
Publisher: IEEE
 
» A 130-nm CMOS 100-Hz–6-GHz Reconfigurable Vector Signal Analyzer and Software-Defined Receiver
Abstract:
A monolithic 100-Hz–6-GHz reconfigurable vector signal analyzer (VSA) and software-defined receiver (SDR), following a two-step up–down conversion heterodyne scheme with robustness to various wideband interference scenarios and local oscillator (LO) harmonic mixing, is presented. The 130-nm CMOS chip does not require external filters or baseband processing to reduce the effect of interferences or LO harmonics. The receiver has tunable gain from 67 to 68 dB in steps of 0.5 dB, and tunable bandwidth from 0.4 to 11 MHz in steps of 0.5 MHz. The receiver sensitivity at the maximum gain is 82 dBm. A monolithic VSA/SDR enables various commercial and military wireless solutions.
Autors: Goel, A.;Analui, B.;Hashemi, H.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: May 2012, volume: 60, issue:5, pages: 1375 - 1389
Publisher: IEEE
 
» A 14 Gbps On-/Off- Keying Modulator in GaAs HBT Technology
Abstract:
A proof of concept on-/off- keying (OOK) modulator is designed and implemented in a commercial heterojunction bipolar transistors IC process. The modulator circuit consists of an amplifier/latch structure, which is used as an OOK modulator for the first time. One of its advantages is that the topology may be implemented in both field effect transistor and bipolar technology. The measurement results correspond well with simulation and show that the modulator is capable of handling carrier frequencies up to 28 GHz, and data rates up to 14 Gbps. The isolation of the modulator in the off-state is better than 27 dB over the whole frequency range.
Autors: He, Z.;Swahn, T.;Li, Y.;Zirath, H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: May 2012, volume: 22, issue:5, pages: 272 - 274
Publisher: IEEE
 
» A 1V, 69-73GHz CMOS power amplifier based on improved Wilkinson power combiner
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A 2-D Electronically Steered Phased-Array Antenna With 2 2 Elements in LC Display Technology
Abstract:
For the first time, a 2-D electronically steered phased-array antenna with a liquid-crystal (LC)-based variable delay line is presented. The structure, which is designed at 17.5 GHz, consists of a 2 2 microstrip patch antenna array, continuously variable delay lines with a novel geometry, RF feeding, and biasing networks. The expected insertion loss of the variable delay line is less than 4 dB with a maximum differential phase shift of 300 . During the measurements, the antenna is steered by applying an appropriate dc biasing in the range of 0–15 V to the variable delay lines. It is also shown that the return loss is always better than 15 dB at the operating frequency when the antenna is steered.
Autors: Karabey, O. H.;Gaebler, A.;Strunck, S.;Jakoby, R.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: May 2012, volume: 60, issue:5, pages: 1297 - 1306
Publisher: IEEE
 
» A 209–233 GHz Frequency Source in 90 nm CMOS Technology
Abstract:
This letter presents a J-band signal source based on a third harmonic generation of a differential Colpitts voltage controlled oscillator (VCO). The source covers a frequency range from 209.3 to 233.3 GHz, which corresponds to a 10.8% total tuning range. This is the widest tuning range in a J-band source signal reported to date. The VCO was fabricated using a 90 nm Mixed-Mode/RF CMOS process; it provides output power at 228 GHz, while consuming 48 mA from a 1.8 V supply, and an estimated phase noise of at 1 MHz offset from the carrier.
Autors: Khamaisi, B.;Socher, E.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: May 2012, volume: 22, issue:5, pages: 260 - 262
Publisher: IEEE
 
» A 24W Ku band GaN based power amplifier with 9.1dB linear gain
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A 3–10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System
Abstract:
This paper presents the design of a 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system. Based on a single phase-locked loop and two-stage frequency mixing architecture, it alleviates harmonics mixing and frequency pulling to diminish spurs generation. Also, only divide-by-2 dividers are needed in the feedback path of the PLL. Thus more precise I/Q sub-harmonics can be derived for the SSB mixer in the 14 bands carrier generation. The image spurs are suppressed below -45 dBc and improved by more than 22 dB incorporating with I/Q calibration. Implemented in a 0.18-μm CMOS technology, this chip drains 65 mA from a single 1.8 V supply. The chip size is 2.5 by 2.2 mm2 providing 14 bands I/Q phases.
Autors: Tai-You Lu;Wei-Zen Chen;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: May 2012, volume: 20, issue:5, pages: 948 - 958
Publisher: IEEE
 
» A 3-DOF parallel manufacturing module and its kinematic optimization
Abstract:


Autors:
Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A 3.1–4.8-GHz IR-UWB All-Digital Pulse Generator With Variable Channel Selection in 0.13- CMOS Technology
Abstract:
An all-digital pulse generator in a standard 0.13- CMOS technology for communication systems using an impulse radio ultrawideband signal is presented. A delay-line-based architecture utilizing only static logic gates for pulse generation with low-power characteristic is proposed in this brief. The center frequency and the fixed bandwidth of 500 MHz of the output signal can be digitally controlled to cover three channels in the low band of UWB spectrum. Delay-based binary phase shift keying and pulse position modulation schemes are exploited at the same time to modulate transmitted signals with further improvement in spectrum characteristics. The total energy consumption is 48 pJ/pulse at 1.2-V supply voltage without static bias currents.
Autors: Choi, Y.;Kim, Y.;Hoang, H.;Bien, F.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: May 2012, volume: 59, issue:5, pages: 282 - 286
Publisher: IEEE
 
» A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile
Abstract:
A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of to 3.5% in steps of 0.5% and three modulation frequencies of , and . It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 in a 0.13- CMOS process and consuming 23.72 mW at 3.5 GHz.
Autors: Sewook Hwang;Song, M.;Kwak, Y.-H.;Jung, I.;Kim, C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2012, volume: 47, issue:5, pages: 1199 - 1208
Publisher: IEEE
 
» A 30-MHz–2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems
Abstract:
A 30-MHz–2.4-GHz complementary metal oxide semiconductor (CMOS) receiver with an integrated tunable RF filter and a dynamic-range-scalable energy detector for both white-space and interference-level sensing in cognitive radio systems is reported. The second-order RF filter has only two stacked transistors, and its use, in combination with a subsequent harmonic rejection mixer, results in wideband interference rejection. The energy detector with programmable rectifiers provides dynamic-range (DR) scalability, enabling shared use for white-space/interference-level detection and automatic gain control. A prototype chip, fabricated using 90-nm CMOS technology, achieved over 42-dB harmonic rejection including 7th-order component without any external device, a 67-dB gain, a 5–8-dB noise figure, a 11-dBm in-band third-order intercept point, and a 38-dBm second-order intercept point while drawing only 25–37 mA from a 1.2-V power supply. Multi-resolution DR-scalable spectrum sensing with a 0.2–30-MHz detection bandwidth, 83-dBm minimum sensitivity, and a 29–48-dB DR was demonstrated.
Autors: Kitsunezuka, M.;Kodama, H.;Oshima, N.;Kunihiro, K.;Maeda, T.;Fukaishi, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2012, volume: 47, issue:5, pages: 1084 - 1093
Publisher: IEEE
 
» A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs
Abstract:
A DCO is realized in 0.13 m CMOS using 4 cores for a 5.6 to 11.5 GHz octave tuning bandwidth to provide the clock for an all digital D/PLL CDR circuit. The DCO is novel in that it can track more than a 130 degree C temperature variation while the CDR maintains an error free lock to data. Each core is directly coupled to a div/2 to produce I/Q signals that a 4:1 MUX combines into a single set of 2.8 to 5.8 GHz quadrature outputs to drive the sine interpolator of the CDR. Locked to maximum data rms jitter, integrated from 1 kHz to 1 GHz is 299 fs @ 9.953 Gb/s (Sonet OC-192) from a DCO phase noise of 116 dBc/Hz at 1 MHz offset. The gain is 190 ppm/bit with less than 2:1 variation over the full bandwidth. The combined DCO, divide by 2 and MUX current is 14 mA to 37 mA on a 1.2 V regulated supply at 25 C.
Autors: Titus, W. S.;Kenney, J. G.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2012, volume: 47, issue:5, pages: 1123 - 1130
Publisher: IEEE
 
» A 55-kW Three-Phase Inverter Based on Hybrid-Switch Soft-Switching Modules for High-Temperature Hybrid Electric Vehicle Drive Application
Abstract:
This paper presents a 55-kW three-phase inverter based on soft-switching modules for hybrid electric vehicle drives at high-temperature conditions. The main switch of the module is composed of the hybrid switch, which is composed of parallel IGBT and MOSFET. Highly integrated soft-switching modules have been employed to achieve switching loss as well as conduction loss reduction. The operation principle of the proposed inverter is analyzed in detail. Experimental evaluations of the inverter have been conducted through both inductive load and motor-dynamometer load at coolant temperatures ranging from 25 to 90 . Efficiency measurement using power meter showed that the peak efficiency is around 99%, and it drops slightly at lower speed and higher temperature conditions. To ensure measurement fidelity, a double-chamber differential calorimeter system was designed and calibrated for the inverter testing. Through long-hour testing, the measured efficiencies consistently showed 99% and higher. The soft-switching inverter has been operated reliably and demonstrated high efficiency at different temperature and test conditions.
Autors: Sun, P.;Lai, J.-S.;Liu, C.;Yu, W.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: May 2012, volume: 48, issue:3, pages: 962 - 969
Publisher: IEEE
 
» A 5MSps 13.25?W 8-bit SAR ADC with single-ended or differential input
Abstract:


Autors:

Graphical Abstract

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Appeared in: Microelectronics Journal
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A 6-GHz All-Digital Fractional- Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique
Abstract:
A 6-GHz all-digital fractional- frequency synthesizer using an FIR-embedded noise filtering technique is presented. This noise filtering technique is realized in the digital domain without multiple matched analog components. This fractional- frequency synthesizer is fabricated in a 90-nm CMOS process, and it occupies 0.18 . Its power is 28.8 mW with a supply of 1.2 V. The measured out-of-band phase noise at an offset of half the reference frequency is improved by more than 13 dB around 6 GHz considering cancellation variations for different output frequencies.
Autors: Lee, I-T.;Lu, H.-Y.;Liu, S.-I.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: May 2012, volume: 59, issue:5, pages: 267 - 271
Publisher: IEEE
 
» A -Band CMOS UWB Radar Transmitter With a Bi-Phase Modulating Pulsed Oscillator
Abstract:
This paper presents a -band CMOS UWB radar transmitter with highly accurate variable delay circuits and a bi-phase modulating pulsed oscillator. The UWB radar transmitter is composed of three blocks: variable delay circuits that consist of a digital synchronized counter and a Vernier delay line (VDL), a baseband control signal generator, and a pulsed oscillator. The VDL allows a high range accuracy level of several millimeters. Asymmetric signals generated by the baseband control signal generator can control the phase of each output pulse. Because the pulsed oscillator operates only for the duration of a pulse, it has an extremely low level of DC power consumption and no LO leakage. It is fabricated with 0.13- m CMOS technology and a chip with dimensions of 0.98 mm 0.69 mm. The output spectrum is centered at 26.0 GHz, and the pulse width is controllable from 280 to 680 ps. The peak output power is about 2 dBm.
Autors: Lee, S.;Kim, C.-Y.;Hong, S.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: May 2012, volume: 60, issue:5, pages: 1405 - 1412
Publisher: IEEE
 
» A -Band CMOS UWB Radar Transmitter With a Bi-Phase Modulating Pulsed Oscillator
Abstract:
This paper presents a K-band CMOS UWB radar transmitter with highly accurate variable delay circuits and a bi-phase modulating pulsed oscillator. The UWB radar transmitter is composed of three blocks: variable delay circuits that consist of a digital synchronized counter and a Vernier delay line (VDL), a baseband control signal generator, and a pulsed oscillator. The VDL allows a high range accuracy level of several millimeters. Asymmetric signals generated by the baseband control signal generator can control the phase of each output pulse. Because the pulsed oscillator operates only for the duration of a pulse, it has an extremely low level of DC power consumption and no LO leakage. It is fabricated with 0.13-μm CMOS technology and a chip with dimensions of 0.98 mm × 0.69 mm. The output spectrum is centered at 26.0 GHz, and the pulse width is controllable from 280 to 680 ps. The peak output power is about 2 dBm.
Autors: Sungeun Lee;Choul-Young Kim;Songcheol Hong;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: May 2012, volume: 60, issue:5, pages: 1405 - 1412
Publisher: IEEE
 
» A Batch-Authenticated and Key Agreement Framework for P2P-Based Online Social Networks
Abstract:
Online social networks (OSNs) such as Facebook and MySpace are flourishing because more and more people are using OSNs to share their interests with friends. Because security and privacy issues on OSNs are major concerns, we propose a security framework for simultaneously authenticating multiple users to improve the efficiency and security of peer-to-peer (P2P)-based OSNs. In the proposed framework, three batch authentication protocols are proposed, adopting the one-way hash function, ElGamal proxy encryption, and certificates as the underlying cryptosystems. The hash-based authentication protocol requires lower computational cost and is suitable for resource-limited devices. The proxy-based protocol is based on asymmetric encryption and can be used to exchange more information among users. The certificate-based protocol guarantees nonrepudiation of transactions by signatures. Without a centralized authentication server, the proposed framework can therefore facilitate the extension of an OSN with batched verifications. In this paper, we formally prove that the proposed batch authentication protocols are secure against both passive adversaries and impersonator attacks, can offer implicit key authentication, and require fewer messages to authenticate multiple users. We also show that our protocols can meet important security requirements, including mutual authentication, reputation, community authenticity, nonrepudiation, and flexibility. With these effective security features, our framework is appropriate for use in P2P-based OSNs.
Autors: Yeh, L.-Y.;Huang, Y.-L.;Joseph, A. D.;Shieh, S. W.;Tsaur, W.-J.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: May 2012, volume: 61, issue:4, pages: 1907 - 1924
Publisher: IEEE
 
» A Batch-Mode Active Learning Technique Based on Multiple Uncertainty for SVM Classifier
Abstract:
In this letter, we present a novel batch-mode active learning technique for solving multiclass classification problems by using the support vector machine classifier with the one-against-all architecture. The uncertainty of each unlabeled sample is measured by defining a criterion which not only considers the smallest distance to the decision hyperplanes but also takes into account the distances to other hyperplanes if the sample is within the margin of their decision boundaries. To select batch of most uncertain samples from all over the decision region, the uncertain regions of the classifiers are partitioned into multiple parts depending on the number of geometrical margins of binary classifiers passing on them. Then, a balanced number of most uncertain samples are selected from each part. To minimize the redundancy and keep the diversity among these samples, the kernel k-means clustering algorithm is applied to the set of uncertain samples, and the representative sample (medoid) from each cluster is selected for labeling. The effectiveness of the proposed method is evaluated by comparing it with other batch-mode active learning techniques existing in the literature. Experimental results on two different remote sensing data sets confirmed the effectiveness of the proposed technique.
Autors: Patra, S.;Bruzzone, L.;
Appeared in: IEEE Geoscience and Remote Sensing Letters
Publication date: May 2012, volume: 9, issue:3, pages: 497 - 501
Publisher: IEEE
 
» A Bayesian approach for place recognition
Abstract:


Autors:
Appeared in: Robotics and Autonomous Systems
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A Beamlet-Based Graph Structure for Path Planning Using Multiscale Information
Abstract:
Path-planning problems are fundamental in many applications, such as transportation, artificial intelligence, control of autonomous vehicles, and many more. In this paper, we consider the deterministic path-planning problem, equivalently, the single-pair shortest path problem on a given grid-like graph structure. Current commonly used algorithms in this area include the algorithm, Dijkstra's algorithm, and their numerous variants. We propose an innovative beamlet-based graph structure for path planning that utilizes multiscale information of the environment. This information is collected via a bottom-up fusion algorithm. This new graph structure goes beyond “nearest-neighbor” connectivity, incorporating “long-distance” interactions between the nodes of the graph. Based on this new graph structure, we obtain a multiscale version of , which is advantageous when preprocessing is allowable and feasible. Compared to the benchmark algorithm, the use of multiscale information leads to an improvement in terms of computational complexity. Numerical experiments indicate an even more favorable behavior than the one predicted by the theoretical complexity analysis.
Autors: Lu, Y.;Huo, X.;Tsiotras, P.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: May 2012, volume: 57, issue:5, pages: 1166 - 1178
Publisher: IEEE
 
» A Behavioral Circuit Model of Active-Matrix Liquid Crystal Displays for Optical Response Simulation
Abstract:
We propose a behavioral circuit model to precisely predict optical responses of an active-matrix liquid crystal (LC) display (LCD) using a patterned vertical alignment (PVA) mode. To get more accurate simulation results, we propose two LC groups with different time constants for a pixel after observing the LCD pixels by using a high-speed camera. In addition, we include a time-delay concept into our behavioral model for brightening or rising transitions. We describe the behavior of the PVA-LCD by using the analog hardware description language Verilog-A. We simulate the PVA-LCD panel by importing the behavioral circuit model in the circuit simulator SmartSPICE. The simulation results of the transient optical responses show excellent matches with the measurement ones.
Autors: Cho, Y.;Park, C.;Kim, J.-M.;Lee, S.-H.;Lee, S.-W.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: May 2012, volume: 59, issue:5, pages: 1430 - 1438
Publisher: IEEE
 
» A Biologically Inspired Validity Measure for Comparison of Clustering Methods over Metabolic Data Sets
Abstract:
In the biological domain, clustering is based on the assumption that genes or metabolites involved in a common biological process are coexpressed/coaccumulated under the control of the same regulatory network. Thus, a detailed inspection of the grouped patterns to verify their memberships to well-known metabolic pathways could be very useful for the evaluation of clusters from a biological perspective. The aim of this work is to propose a novel approach for the comparison of clustering methods over metabolic data sets, including prior biological knowledge about the relation among elements that constitute the clusters. A way of measuring the biological significance of clustering solutions is proposed. This is addressed from the perspective of the usefulness of the clusters to identify those patterns that change in coordination and belong to common pathways of metabolic regulation. The measure summarizes in a compact way the objective analysis of clustering methods, which respects coherence and clusters distribution. It also evaluates the biological internal connections of such clusters considering common pathways. The proposed measure was tested in two biological databases using three clustering methods.
Autors: Stegmayer, G.;Milone, D.H.;Kamenetzky, L.;Lopez, M.G.;Carrari, F.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: May 2012, volume: 9, issue:3, pages: 706 - 716
Publisher: IEEE
 
» A Boosted Bayesian Multiresolution Classifier for Prostate Cancer Detection From Digitized Needle Biopsies
Abstract:
Diagnosis of prostate cancer (CaP) currently involves examining tissue samples for CaP presence and extent via a microscope, a time-consuming and subjective process. With the advent of digital pathology, computer-aided algorithms can now be applied to disease detection on digitized glass slides. The size of these digitized histology images (hundreds of millions of pixels) presents a formidable challenge for any computerized image analysis program. In this paper, we present a boosted Bayesian multiresolution (BBMR) system to identify regions of CaP on digital biopsy slides. Such a system would serve as an important preceding step to a Gleason grading algorithm, where the objective would be to score the invasiveness and severity of the disease. In the first step, our algorithm decomposes the whole-slide image into an image pyramid comprising multiple resolution levels. Regions identified as cancer via a Bayesian classifier at lower resolution levels are subsequently examined in greater detail at higher resolution levels, thereby allowing for rapid and efficient analysis of large images. At each resolution level, ten image features are chosen from a pool of over 900 first-order statistical, second-order co-occurrence, and Gabor filter features using an AdaBoost ensemble method. The BBMR scheme, operating on 100 images obtained from 58 patients, yielded: 1) areas under the receiver operating characteristic curve (AUC) of 0.84, 0.83, and 0.76, respectively, at the lowest, intermediate, and highest resolution levels and 2) an eightfold savings in terms of computational time compared to running the algorithm directly at full (highest) resolution. The BBMR model outperformed (in terms of AUC): 1) individual features (no ensemble) and 2) a random forest classifier ensemble obtained by bagging multiple decision tree classifiers. The apparent drop-off in AUC at higher image resolutions is due to lack of fine detail in the expert annotation of CaP and is not an artifact of the- classifier. The implicit feature selection done via the AdaBoost component of the BBMR classifier reveals that different classes and types of image features become more relevant for discriminating between CaP and benign areas at different image resolutions.
Autors: Doyle, S.;Feldman, M.;Tomaszewski, J.;Madabhushi, A.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: May 2012, volume: 59, issue:5, pages: 1205 - 1218
Publisher: IEEE
 
» A bottleneck Steiner tree based multi-objective location model and intelligent optimization of emergency logistics systems
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Autors:

Highlights

Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A broadband and compact asymmetrical backward coupled-line coupler with high coupling level
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Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A Broadband U-Slot Coupled Microstrip-to-Waveguide Transition
Abstract:
A novel planar broadband microstrip-to-waveguide transition is proposed in this paper. The referred waveguide can be either rectangular waveguide or ridged waveguide. The transition consists of an open-circuited microstrip quarter-wavelength resonator and a resonant U-shaped slot on the upper broadside wall of a short-circuited waveguide. A physics-based equivalent-circuit model is also developed for interpreting the working mechanism and providing a coarse model for engineering design. The broadband transition can be regarded as a stacked two-pole resonator filter. Each coupling circuit can be approximately designed separately using the group-delay information at the center frequency. In addition to its broadband attribute, the transition is compact in size, vialess, and is highly compatible with planar circuits. These good features make the new transition very attractive for the system architecture where waveguide devices need to be surface mounted on a multilayered planer circuit. Two design examples are given to demonstrate the usefulness of the transition: one is a broadband ridged-waveguide bandpass filter and the other is a surface-mountable broadband low-temperature co-fired ceramic laminated waveguide cavity filter. Both filters are with the proposed transition for interfacing with microstrip lines, showing promising potentials in practical applications.
Autors: Huang, X.;Wu, K.-L.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: May 2012, volume: 60, issue:5, pages: 1210 - 1217
Publisher: IEEE
 
» A CFD greenhouse night-time condensation model
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Autors:
Appeared in: Biosystems Engineering
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A chaotic path planning generator for autonomous mobile robots
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Autors:
Appeared in: Robotics and Autonomous Systems
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A charge-pump and comparator based power-efficient pipelined ADC technique
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A clustering algorithm based on energy information and cluster heads expectation for wireless sensor networks
Abstract:


Autors:

Graphical Abstract

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Appeared in: Computers & Electrical Engineering
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A CMOS Distributed Amplifier With Distributed Active Input Balun Using GBW and Linearity Enhancing Techniques
Abstract:
A CMOS distributed amplifier (DA) with distributed active input balun is presented that achieves a gain-bandwidth product of 818 GHz, while improving linearity. Each cell within the DA employs dual-output two-stage topology that improves gain and linearity without adversely affecting bandwidth (BW) and power. Comprehensive analysis and simulations are carried out to investigate gain, BW, linearity, noise, and stability of the proposed cell, and compare them with conventional cells. Fabricated in a 65-nm low-power CMOS process, the 0.9- DA achieves 22 dB of gain and a of 10 dBm, while consuming dc power of 97 mW from a 1.3-V supply. A distributed balun, designed and fabricated in the same process, using the same topology achieves a BW larger than 70 GHz and a gain of 4 dB with 19.5-mW power consumption from 1.3-V supply.
Autors: Jahanian, A.;Heydari, P.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: May 2012, volume: 60, issue:5, pages: 1331 - 1341
Publisher: IEEE
 
» A Coclustering Approach for Mining Large Protein-Protein Interaction Networks
Abstract:
Several approaches have been presented in the literature to cluster Protein-Protein Interaction (PPI) networks. They can be grouped in two main categories: those allowing a protein to participate in different clusters and those generating only nonoverlapping clusters. In both cases, a challenging task is to find a suitable compromise between the biological relevance of the results and a comprehensive coverage of the analyzed networks. Indeed, methods returning high accurate results are often able to cover only small parts of the input PPI network, especially when low-characterized networks are considered. We present a coclustering-based technique able to generate both overlapping and nonoverlapping clusters. The density of the clusters to search for can also be set by the user. We tested our method on the two networks of yeast and human, and compared it to other five well-known techniques on the same interaction data sets. The results showed that, for all the examples considered, our approach always reaches a good compromise between accuracy and network coverage. Furthermore, the behavior of our algorithm is not influenced by the structure of the input network, different from all the techniques considered in the comparison, which returned very good results on the yeast network, while on the human network their outcomes are rather poor.
Autors: Pizzuti, C.;Rombo, S.E.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: May 2012, volume: 9, issue:3, pages: 717 - 730
Publisher: IEEE
 
» A Colon Video Analysis Framework for Polyp Detection
Abstract:
This paper presents an automated video analysis framework for the detection of colonic polyps in optical colonoscopy. Our proposed framework departs from previous methods in that we include spatial frame-based analysis and temporal video analysis using time-course image sequences. We also provide a video quality assessment scheme including two measures of frame quality. We extract colon-specific anatomical features from different image regions using a windowing approach for intraframe spatial analysis. Anatomical features are described using an eigentissue model. We apply a conditional random field to model interframe dependences in tissue types and handle variations in imaging conditions and modalities. We validate our method by comparing our polyp detection results to colonoscopy reports from physicians. Our method displays promising preliminary results and shows strong invariance when applied to both white light and narrow-band video. Our proposed video analysis system can provide objective diagnostic support to physicians by locating polyps during colon cancer screening exams. Furthermore, our system can be used as a cost-effective video annotation solution for the large backlog of existing colonoscopy videos.
Autors: Park, S. Y.;Sargent, D.;Spofford, I.;Vosburgh, K. G.;A-Rahim, Y.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: May 2012, volume: 59, issue:5, pages: 1408 - 1418
Publisher: IEEE
 
» A combined reactive and reinforcement learning controller for an autonomous tracked vehicle
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Autors:
Appeared in: Robotics and Autonomous Systems
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A Combined Series-Parallel Hybrid Envelope Amplifier for Envelope Tracking Mobile Terminal RF Power Amplifier Applications
Abstract:
An improved envelope amplifier architecture for envelope tracking RF power amplifiers is presented, consisting of two switching amplifiers and one linear amplifier. The first switching amplifier and the linear amplifier provide wideband and high-efficiency operation, while the second switching amplifier provides a reduced bandwidth variable supply to the linear amplifier to further reduce power loss. The first switching amplifier and the linear amplifier are fabricated together in a 150 nm CMOS process, while the second switching amplifier is external. Measurements show a maximum average efficiency of 82% for a 10 MHz LTE signal with a 6 dB PAPR at 29.7 dBm output power and an SFDR of 63 dBc for a single tone of 5 MHz driving an 8 load.
Autors: Hassan, M.;Larson, L. E.;Leung, V. W.;Asbeck, P. M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2012, volume: 47, issue:5, pages: 1185 - 1198
Publisher: IEEE
 
» A Communication Theoretical Modeling of Single-Layer Graphene Photodetectors and Efficient Multireceiver Diversity Combining
Abstract:
Graphene with groundbreaking properties has tremendous impact on physical sciences as 2-D atomic layer carbon sheet. Its unique electronic and photonic properties lead to applications such as transistors, graphene photodetectors (GPDs), and electronic circuit components. Metal–graphene–metal (MGM) GPDs with single- or multilayer graphene sheets are promising for future nanoscale optical communication architectures because of wide range absorption from far infrared to visible spectrum, fast carrier velocity, and advanced production techniques due to planar geometry. In this paper, signal-to-noise ratio (SNR), bit-error rate (BER), and data rate performances of nanoscale single-layer symmetric MGM photodetectors are analyzed for intensity modulation and direct detection (IM/DD) modulation. Shot and thermal noise limited (NL) performances are analyzed emphasizing graphene layer width dependence and domination of thermal NL characteristics for practical power levels. Tens of Gbit/s data rates are shown to be achievable with very low BERs for single-receiver (SR) GPDs. Furthermore, multireceiver (MR) GPDs and parallel line-scan (PLS) network topology are defined improving the efficiency of symmetric GPDs. SNR performance of SR PLS channels are both improved and homogenized with MR devices having the same total graphene area by optimizing their positions with max–min solutions and using maximal ratio and equal gain diversity combining techniques.
Autors: Gulbahar, B.;Akan, O. B.;
Appeared in: IEEE Transactions on Nanotechnology
Publication date: May 2012, volume: 11, issue:3, pages: 601 - 610
Publisher: IEEE
 
» A Compact and Low Power 5–10 GHz Quadrature Local Oscillator for Cognitive Radio Applications
Abstract:
This paper presents the design and implementation of a compact and low power quadrature local oscillator (LO) for creating 13.3–20 GHz signal initially from a differentially tuned LC-VCO and then converting it to the desired 5–10 GHz with continuous frequency coverage. To accomplish such purpose, a 4-stage differential injection-locked ring oscillator (ILRO) is used subsequently to the latch-based divider to generate quadrature output phases without restricting 50% duty cycle from input signals as those of conventional divide-by-2 approaches. When implemented in a 65 nm general purpose CMOS IC technology, the integrated quadrature-phased LO consumes 22 mA of current at a 1 V supply and is able to exhibit the worst-case phase noise of dBc/Hz at 1 MHz offset across the entire 5–10 GHz band for intended cognitive radio applications.
Autors: Lu, J.;Wang, N.-Y.;Chang, M.-C. F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: May 2012, volume: 47, issue:5, pages: 1131 - 1140
Publisher: IEEE
 
» A compact dielectric elastomer tubular actuator for refreshable Braille displays
Abstract:


Autors:
Appeared in: Sensors and Actuators A: Physical
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A compact low-profile dual-band antenna for WLAN and WAVE applications
Abstract:


Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A Compact Wideband Microstrip Crossover
Abstract:
In this letter, a planar microstrip crossover junction is presented. The conductor-backed coplanar waveguide (CB-CPW) structure with vias is employed as the core part of the crossover design. The dimensions of the CB-CPW crossover itself are 11.3 11.3 mm . Two kinds of the transitions between the microstrip line (MSL) and the CB-CPW structure are merged into a double side print circuit board. This presented crossover junction has a bandwidth from 10 up to 6000 MHz for 20 dB return loss, 1 dB insertion loss and dB isolation. Compared with the other designs, this planar crossover features wide bandwidth and compact configuration.
Autors: Liu, W.;Zhang, Z.;Feng, Z.;Iskander, M. F.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: May 2012, volume: 22, issue:5, pages: 254 - 256
Publisher: IEEE
 
» A comparative study of spacecraft attitude determination and estimation algorithms (A cost-benefit approach)
Abstract:


Autors:

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Appeared in: Aerospace Science and Technology
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A Comparative Study on Filtering Protein Secondary Structure Prediction
Abstract:
Filtering of Protein Secondary Structure Prediction (PSSP) aims to provide physicochemically realistic results, while it usually improves the predictive performance. We performed a comparative study on this challenging problem, utilizing both machine learning techniques and empirical rules and we found that combinations of the two lead to the highest improvement.
Autors: Kountouris, P.;Agathocleous, M.;Promponas, V.J.;Christodoulou, G.;Hadjicostas, S.;Vassiliades, V.;Christodoulou, C.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: May 2012, volume: 9, issue:3, pages: 731 - 739
Publisher: IEEE
 
» A comparison of two chromosome representation schemes used in solving a family-based scheduling problem
Abstract:


Autors:

Highlights

Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A complete SPICE subcircuit-based model library for organic photodiodes
Abstract:


Autors:

Graphical abstract

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Appeared in: Solid-State Electronics
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A comprehensive integration infrastructure for embedded system design
Abstract:


Autors:
Appeared in: Microprocessors and Microsystems
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A computational study of high-frequency behavior of graphene field-effect transistors
Abstract:
High Frequency potential of graphene field-effect transistors (FETs) is explored by quasi-static self-consistent ballistic and dissipative quantum transport simulations. The unity power gain frequency fMAX and the cut-off frequency fT are modeled at the ballistic limit and in the presence of inelastic phonon scattering for a gate length down to 5 nm. Our major results are (1) with a thin high-κ gate insulator, the intrinsic ballistic fT is above 5 THz at a gate length of 10 nm. (2) Inelastic phonon scattering in graphene FETs lowers both fT and fMAX, mostly due to decrease of the transconductance. (3) fMAX and fT are severely degraded in presence of source and drain contact resistance. (4) To achieve optimum extrinsic fMAX performance, careful choice of DC bias point and gate width is needed.
Autors: Chauhan, Jyotsna;Liu, Leitao;Lu, Yang;Guo, Jing;
Appeared in: Journal of Applied Physics
Publication date: May 2012, volume: 111, issue:9, pages: 094313 - 094313-7
Publisher: IEEE
 
» A computationally efficient numerical model of the offset of CMOS-integrated vertical Hall devices
Abstract:


Autors:
Appeared in: Sensors and Actuators A: Physical
Publication date: May 2012
Publisher: Elsevier B.V.
 
» A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers
Abstract:
We propose a new continuous-time (CT) delta-sigma modulator (DSM) to be utilized in radio-frequency (RF) subsampling receivers for analog-to-digital conversion. Subsampling DSMs employ sub-Nyquist sampling with respect to the input signal frequency and oversampling with respect to the signal bandwidth. The proposed CT-DSM mitigates the effects of subsampling by modifying the feedback path of the modulator to accommodate the RF replica of the feedback signal and by enhancing the quality factor of the loop filter. The novel modulator has significant improvements over previously published subsampling modulators as it provides jitter and image suppression and excess loop delay compensation to improve the dynamic range, thus enabling the modulator to be utilized in subsampling receivers when a relatively low sampling rate is desired.
Autors: Ucar, A.;Cetin, E.;Kale, I.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: May 2012, volume: 59, issue:5, pages: 272 - 276
Publisher: IEEE
 

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