Electrical and Electronics Engineering publications abstract of: 04-2015 sorted by title, page: 0

» 0.8/2.2-GHz Programmable Active Bandpass Filters in InP/Si BiCMOS Technology
Abstract:
Programmable active bandpass filters (BPFs) have been designed in a chip-scale heterogeneous integration technology, which intimately integrates InP HBTs on a deep scaled CMOS technology. Therefore, the active BPF can leverage both high performance of InP HBT and high density and programmability of CMOS. Two BPF prototypes, consisting of a programmable gain amplifier (PGA), a fifth- or third-order BPF core, and a buffer, have been designed and fabricated. The BPF center frequency can be switched from 0.8 to 2.2 GHz with 150-MHz passband and delivers -dB out-of-band (OOB) rejection for the fifth-order one. Four gain steps: 0, 6, 12, and 16 dB, are enabled by the front PGA to trade off noise and linearity performances. Due to the -GHz of InP HBTs, the BPF cores can leverage active-RC architecture for high linearity owing to the close-loop implementation. The fifth-order BPF prototype occupies a 1.5 1.02 mm area together with pads and draws 106/121 mA from a 3.3-V power supply for 0.8/2.2-GHz bands, respectively, which demonstrates OOB output third-order intercept points (OIP3s) of 22.69/21.25 dBm for 0.8/2.2-GHz bands at the high gain mode. The measurement results suggest the fifth-order BPF core achieves 36.69/35.25-dBm OOB OIP3s. In addition, the designed third-order programmable BPF has been successfully used as a technology yield vehicle to assist the BiCMOS technology development.
Autors: Xu, Z.;Winklea, D.;Oh, T.C.;Kim, S.;Chen, S.T.W.;Royter, Y.;Lau, M.;Valles, I.;Hitko, D.A.;Li, J.C.;Gu, Q.J.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Apr 2015, volume: 63, issue:4, pages: 1219 - 1227
Publisher: IEEE
 
» 1.9-kV AlGaN/GaN Lateral Schottky Barrier Diodes on Silicon
Abstract:
In this letter, we present AlGaN/GaN lateral Schottky barrier diodes on silicon with recessed anodes and dual field plates. A low specific ON-resistance (5.12 ), a low turn-ON voltage (<0.7 V), and a high reverse breakdown voltage (BV) (>1.9 kV) were simultaneously achieved in devices with a 25- anode/cathode distance, resulting in a power figure-of-merit BV / of 727 . The record high BV of 1.9 kV is attributed to the dual field-plate structure.
Autors: Zhu, M.;Song, B.;Qi, M.;Hu, Z.;Nomoto, K.;Yan, X.;Cao, Y.;Johnson, W.;Kohn, E.;Jena, D.;Xing, H.G.;
Appeared in: IEEE Electron Device Letters
Publication date: Apr 2015, volume: 36, issue:4, pages: 375 - 377
Publisher: IEEE
 
» 3-D SEEA charge analyses on surface of insulators in vacuum
Abstract:
In the bridged vacuum gaps, the secondary electron emission avalanche (SEEA) occurring along the surface of solid insulator and the resultant surface charging play a crucial role in the progress of surface discharge. In order to sophisticate the insulation design of high voltage vacuum devices, analysis and control of SEEA charging are of importance. Boersh et al. have proposed a boundary condition on the surface of an insulator to solve the charge distribution at an equilibrium state of SEEA charging. The boundary condition can be easily adopted for analyzing two dimensional SEEA charge distributions. However, the above condition by Boersh et al. cannot be applied in the case of three dimensional distributions. In this paper, the authors newly developed the boundary condition for three dimensional applications and created a numerical simulation code for analyzing three dimensional SEEA charge distributions. Two types of insulator were examined in this study; one was a solid cylinder and the other a hollow cylinder. In the case of the solid cylinder, electric field strength on the cathode was calculated and compared with the measurement. On the other hand, in the case of the hollow cylinder, the calculated result was compared with the charge distribution experimentally obtained by a movable electrostatic probe system. These calculation and measurement results have shown reasonable agreement and we have validated the newly developed numerical simulation method for three dimensional SEEA charge distributions.
Autors: Umemoto, T.;Shimizu, Y.;Naruse, H.;Yamamoto, O.;
Appeared in: IEEE Transactions on Dielectrics and Electrical Insulation
Publication date: Apr 2015, volume: 22, issue:2, pages: 1298 - 1305
Publisher: IEEE
 
» 340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS
Abstract:
This paper describes an on-die lightweight nanoAES hardware accelerator, fabricated in 22 nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption and decryption on mobile SOCs. Compared to conventional 128 bit AES implementations, this design uses a single 8 bit Sbox circuit along with ShiftRows byte-order data processing to compute all AES rounds in native composite-field. This approach along with a serial-accumulating MixColumns circuit, area-optimized encrypt and decrypt Galois-field polynomials and integrated on-the-fly key generation circuit results in a compact encrypt/decrypt layout occupying 2200/2736 m and lowest-reported gate count of 1947/2090 respectively, while achieving: (i) maximum operating frequency of 1.133 GHz and total power consumption of 13 mW with leakage component of 500 W, measured at 0.9 V, 25 C, (ii) nominal AES-128 encrypt/decrypt throughput of 432/671 Mbps respectively, with peak energy-efficiency of 289 Gbps/W measured at near-threshold operation of 430 mV (11 higher than previously reported implementations), (iii) encrypt/decrypt latencies of 336/216 cycles and total energy consumption of 3.9/2.5 nJ respectively, (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 45 Mbps, 170 W, measured at 340 mV, 25 C and (v) first-reported Galois-field polynomial-based micro-architectural- co-optimization, resulting in distinct area-optimized encrypt and decrypt polynomials with up to 9% area reduction at iso-performance.
Autors: Mathew, S.;Satpathy, S.;Suresh, V.;Anders, M.;Kaul, H.;Agarwal, A.;Hsu, S.;Chen, G.;Krishnamurthy, R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 1048 - 1058
Publisher: IEEE
 
» 3D Perception Based Quality Pooling: Stereopsis, Binocular Rivalry, and Binocular Suppression
Abstract:
One of the most challenging ongoing issues in the field of 3D visual research is how to interpret human 3D perception over virtual 3D space between the human eye and a 3D display. When a human being perceives a 3D structure, the brain classifies the scene into the binocular or monocular vision region depending on the availability of binocular depth perception in the unit of a certain region (coarse 3D perception). The details of the scene are then perceived by applying visual sensitivity to the classified 3D structure (fine 3D perception) with reference to the fixation. Furthermore, we include the coarse and fine 3D perception in the quality assessment, and propose a human 3D Perception-based Stereo image quality pooling (3DPS) model. In 3DPS we divide the stereo image into segment units, and classify each segment as either the binocular or monocular vision region. We assess the stereo image according to the classification by applying different visual weights to the pooling method to achieve more accurate quality assessment. In particular, it is demonstrated that 3DPS performs remarkably for quality assessment of stereo images distorted by coding and transmission errors.
Autors: Lee, K.;Lee, S.;
Appeared in: IEEE Journal of Selected Topics in Signal Processing
Publication date: Apr 2015, volume: 9, issue:3, pages: 533 - 545
Publisher: IEEE
 
» 3D-Mesa “Bridge” Silicon Microdosimeter: Charge Collection Study and Application to RBE Studies in Radiation Therapy
Abstract:
Microdosimetry is an extremely useful technique, used for dosimetry in unknown mixed radiation fields typical of space and aviation, as well as in hadron therapy. A new silicon microdosimeter with 3D sensitive volumes has been proposed to overcome the shortcomings of the conventional Tissue Equivalent Proportional Counter. In this article, the charge collection characteristics of a new 3D mesa microdosimeter were investigated using the ANSTO heavy ion microprobe utilizing 5.5 MeV and 2 MeV ions. Measurement of the microdosimetric characteristics allowed for the determination of the Relative Biological Effectiveness of the heavy ion therapy beam at the Heavy Ion Medical Accelerator in Chiba (HIMAC), Japan. Well-defined sensitive volumes of the 3D mesa microdosimeter have been observed and the microdosimetric RBE obtained showed good agreement with the TEPC. The new 3D mesa “bridge” microdosimeter is a step forward towards a microdosimeter with fully free-standing 3D sensitive volumes.
Autors: Tran, L.T.;Chartier, L.;Prokopovich, D.A.;Reinhard, M.I.;Petasecca, M.;Guatelli, S.;Lerch, M.L.F.;Perevertaylo, V.L.;Zaider, M.;Matsufuji, N.;Jackson, M.;Nancarrow, M.;Rosenfeld, A.B.;
Appeared in: IEEE Transactions on Nuclear Science
Publication date: Apr 2015, volume: 62, issue:2, pages: 504 - 511
Publisher: IEEE
 
» 40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface
Abstract:
This paper explores the use of transformer-coupled (TC) technique for the 2:1 MUX and the 1:2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely used current-mode logic (CML) designs of latch and multiplexer/demultiplexer (MUX/DEMUX) are replaced by the proposed TC approach to allow the more headroom and to lower the power consumption. Through the stacked transformer, the input clock pulls down the differential source voltage of the TC latch and the TC multiplexer core while alternating between the two-phase operations. With the enhanced drain-source voltage, the TC design attracts more drain current with less width-to-length ratio of NMOS than that of the CML counterpart. The source-offset voltage is decreased so that the supply voltage can be reduced. The lower supply voltage improves the power consumption and facilitates the integration with low voltage supply SerDes interface. The MUX and the DEMUX chips are fabricated in 65-nm standard CMOS process and operate at 0.7-V supply voltage. The chips are measured up to 40-Gb/s with sub-hundred milliwatts power consumption.
Autors: Chen, F.-T.;Wu, J.-M.;Chang, M.-C.F.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2015, volume: 62, issue:4, pages: 1042 - 1051
Publisher: IEEE
 
» 6.5 V High Threshold Voltage AlGaN/GaN Power Metal-Insulator-Semiconductor High Electron Mobility Transistor Using Multilayer Fluorinated Gate Stack
Abstract:
In this letter, the approach of partial AlGaN recess and multiple layers of fluorinated Al2O3 gate dielectric is utilized to achieve highest reported positive gate threshold voltage ( ) without severe reduction on 2-D electron gas carrier mobility in AlGaN/GaN HEMTs. Guided by the design and verification through analytical model, proper fluorine ions incorporation is made through fabrication. The approach resulted in a high of +6.5 V and competitive drain saturation current ( ) of 340 mA/mm. Furthermore, low gate leakage current and high breakdown voltage of 1140 V were also demonstrated.
Autors: Wang, Y.;Liang, Y.C.;Samudra, G.S.;Huang, H.;Huang, B.;Huang, S.;Chang, T.;Huang, C.;Kuo, W.;Lo, G.;
Appeared in: IEEE Electron Device Letters
Publication date: Apr 2015, volume: 36, issue:4, pages: 381 - 383
Publisher: IEEE
 
» 76–81-GHz CMOS Transmitter With a Phase-Locked-Loop-Based Multichirp Modulator for Automotive Radar
Abstract:
This paper presents the design of a linear frequency-modulated continuous-wave (FMCW) radar transmitter (TX) for automotive radar applications. The TX has a wide operating range from 76 to 81 GHz by employing a frequency-doubling architecture using an LC voltage-controlled oscillator operating at 38–40.5 GHz and a differential frequency doubler using a single transformer. A chirp generator is integrated into the TX, which provides various frequency chirp profiles with programmable chirp slope and sweep duration. The proposed CMOS FMCW TX can be applied to various modulation algorithms for multiple target detection and the avoidance of ghost targets. The TX is implemented using 65-nm CMOS technology. The chip size is 1.48 1.85 mm . The measurement results shows a 76–81-GHz frequency range and 3-dBm output power while dissipating 320 mW. The phase-noise density of the TX is dBm/Hz at an offset frequency of 1 MHz when the output frequency is 77 GHz.
Autors: Park, J.;Ryu, H.;Ha, K.-W.;Kim, J.-G.;Baek, D.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Apr 2015, volume: 63, issue:4, pages: 1399 - 1408
Publisher: IEEE
 
» -Model Dual-Band Impedance Transformer for Unequal Complex Impedance Loads
Abstract:
This letter presents a -model dual-band impedance transformer which can match two unequal arbitrary complex loads at two frequencies. The required nonlinear simultaneous equations are derived to obtain the physical parameters of transmission lines and stubs. Return loss for the proposed matching circuit is measured to validate the results of the presented structure simulations. Excellent agreement between analytical and measured results confirms the proposed structure.
Autors: Manoochehri, O.;Asoodeh, A.;Forooraghi, K.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2015, volume: 25, issue:4, pages: 238 - 240
Publisher: IEEE
 
» -Model Dual-Band Impedance Transformer for Unequal Complex Impedance Loads
Abstract:
This letter presents a -model dual-band impedance transformer which can match two unequal arbitrary complex loads at two frequencies. The required nonlinear simultaneous equations are derived to obtain the physical parameters of transmission lines and stubs. Return loss for the proposed matching circuit is measured to validate the results of the presented structure simulations. Excellent agreement between analytical and measured results confirms the proposed structure.
Autors: Manoochehri, O.;Asoodeh, A.;Forooraghi, K.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2015, volume: 25, issue:4, pages: 238 - 240
Publisher: IEEE
 
» Recognition of 2014 Transactions and Magazine Papers Reviewer
Abstract:
Lists the reviewers who contributed to IEEE Industry Applications Magazine and the IEEE Transactions on Industry Applications in 2014.
Autors: Speck, C.E.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Apr 2015, volume: 51, issue:2, pages: 1117 - 1131
Publisher: IEEE
 
» A 0.1–1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA
Abstract:
A 0.1–1.5 GHz harmonic rejection (HR) receiver front-end is presented. A flexible HR mixer is proposed to correct phase ambiguity and a vector gain calibration is used to eliminate the gain/phase mismatch and improve the HR ratio. With the proposed hybrid 8-phase LO generator, the highest oscillation frequency of the frequency synthesizer is reduced from four times to twice of the highest operation frequency. The power-scalable Class-AB fully-differential opamp with Miller feed-forward compensation and quasi-floating gate (QFG) technique is proposed to implement the low power blocker-resilient TIA. The HR receiver has been implemented in 65 nm CMOS. With 1.8 core chip area and 5.4–24.5 mA current consumption from a 1.2 V power supply, the receiver achieves 85 dB conversion gain, 4.3 dB NF, 13 dBm/ 14 dBm IB/OB-IIP3, 54/56 dB HR3/HR5 (30–40 dB improvement with the vector gain calibration), and 2.3% EVM for 32QAM modulation.
Autors: Zhang, X.;Chi, B.;Wang, Z.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2015, volume: 62, issue:4, pages: 1005 - 1014
Publisher: IEEE
 
» A 10- to 30-kHz Adjustable Frequency Resonant Full-Bridge Multicell Power Converter
Abstract:
The design and construction of a full-bridge flying capacitor multicell inverter (FCMI) composed of two legs is disclosed. Each leg consists of three switching cells. In order to control the power converter, a square wave signal switching technique has been used; the converter output frequency has increased at three times the switching frequency. Moreover, the system can be tuned by a variable inductor coupled with a high-voltage transformer allowing the FCMI to work under a resonance condition from 10- to 30-kHz frequency range. The goal of this converter is to generate a dielectric barrier discharge (DBD) at atmospheric pressure applied in environmental remediation and biological interaction studies. The proposed inverter has been tested with two different DBD reactors, one of them intended for the degradation of organic compound metacresol dissolved in water.
Autors: Lopez-Fernandez, J.A.;Pena-Eguiluz, R.;Lopez-Callejas, R.;Mercado-Cabrera, A.;Jaramillo-Sierra, B.;Rodriguez-Mendez, B.;Valencia-Alvarado, R.;Munoz-Castro, A.E.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Apr 2015, volume: 62, issue:4, pages: 2215 - 2223
Publisher: IEEE
 
» A 10-mm MR-Conditional Unidirectional Pneumatic Stepper Motor
Abstract:
Magnetic resonance (MR) conditional robotic devices facilitate accurate interventional procedures under MR imaging (MRI) guidance. For this purpose, a compact (10-mm diameter) MR-conditional stepper motor is presented. The device features seven key components, which contribute to a dense and easy to fabricate design. Alternating bursts of pressurized air and vacuum can drive the motor in 60° per step to achieve a maximum torque of 2.4 mNm. The relationship between torque and angular speed was investigated to demonstrate motor performance under different loading conditions. The stepper motor was tested in a GE 3T MRI scanner to verify its MR-compatibility. A maximum artifact width of 3 mm was measured in MRI images and a maximum signal-to-noise ratio reduction of 2.49% was recorded.
Autors: Yue Chen;Mershon, C.D.;Tse, Z.T.H.;
Appeared in: IEEE/ASME Transactions on Mechatronics
Publication date: Apr 2015, volume: 20, issue:2, pages: 782 - 788
Publisher: IEEE
 
» A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter
Abstract:
This brief presents an energy-efficient 10-bit accuracy with 20-kS/s successive approximation register analog-to-digital converter for portable pulse oximeter. A data-dependent capacitor reset (DDCR) switching scheme for the capacitive digital-to-analog converter (CDAC) to reduce the average switching energy and the number of unit capacitors is proposed and implemented. Compared with the conventional capacitor switching scheme for CDACs, the proposed DDCR switching scheme reduces the average switching energy and the total number of unit capacitors by 97% and 75%, respectively. We achieved a signal-to-noise-and-distortion ratio of 56.5 dB and a spurious-free dynamic range of 64.7 dBc at the Nyquist input frequency. The measured peak differential and integral nonlinearities are 0.44 and 0.58 least significant bit, respectively. The figure of merit is 9.1 fJ/conversion-step. The prototype, fabricated in the 0.11- CMOS process, occupies 0.033 mm2.
Autors: Lee, H.;Park, S.;Lim, C.;Kim, C.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2015, volume: 62, issue:4, pages: 357 - 361
Publisher: IEEE
 
» A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band
Abstract:
A 12 bit Dual-Rate Hybrid digital-to-analog converter (DAC) architecture with a split Nyquist (1 GS/s) and delta-sigma modulator path (8 GS/s) is proposed and implemented in 65 nm CMOS. Based on the hybrid architecture, the delta-sigma-assisted pre-distortion scheme compensates for the current steering cell mismatch, which further reduces the analog circuit complexity and area. The proposed 8X unrolled pipeline delta-sigma modulator allows for high-speed third-order noise shaping with a digital standard cell design flow. The measured spurious-free dynamic range achieves 91–76 dB over the 500 MHz Nyquist band. The proposed DAC architecture is mostly digital and hence favors future technology scaling.
Autors: Su, S.;Tsai, T.-I;Sharma, P.K.;Chen, M.S.-W.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 896 - 907
Publisher: IEEE
 
» A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector
Abstract:
A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-leakage digital process. A background bit-weight calibration exploiting the comparator resolving time information and the employment of a sub-binary DAC in the first SAR stage are two key techniques in this work to attain high conversion throughput and power savings at the same time using a simple, low-gain ( 30 dB) residue amplifier. The overall architecture and the digital calibration also enable the downsizing of the first SAR stage to that of the kT/C limit, yielding a wideband input network delivering an over 80 dB spurious-free dynamic range (SFDR) while digitizing a 300 MHz input at 160 MS/s. The core ADC consumes 4.96 mW and occupies an area of 0.042 mm ; the calibration circuits dissipate 0.1 mW (estimated). An 86.9 dB SFDR and a 66.7 dB signal-to-noise plus distortion ratio (SNDR) were measured with a 2 V , 5 MHz sine-wave input at full speed. The ADC achieves a Walden figure-of-merit (FoM) of 20.7 fJ/conversion-step with a Nyquist input.
Autors: Zhou, Y.;Xu, B.;Chiu, Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 920 - 931
Publisher: IEEE
 
» A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices
Abstract:
A 13.56 MHz wireless power transfer system with a 1X/2X reconfigurable resonant regulating (R ) rectifier and wireless power control for biomedical implants is presented. Output voltage regulation is achieved through two mechanisms: 1) a local PWM loop at the secondary side controls the duty cycle of mode-switching of the rectifier between the 1X and 2X modes; and 2) a global control loop obtains the mode-switching information from the secondary side and send it back to the primary side through the wireless channel and adjusts the transmitter power of the primary coil to adapt to load and coupling variations. Two novel backscattering uplink techniques are proposed for fast and energy-efficient data feedback. The first is for general data transmission using Manchester code; and the second is for fast duty cycle feedback to cater for fast load-transient responses. Stability analysis of the entire system with the two control loops is also presented. The primary transmitter and the secondary R rectifier are fabricated in 0.35 µm CMOS process with the digital control circuits implemented using FPGA. The measured maximum received power and receiver efficiency are 102 mW and 92.6%, respectively. For load transients, the overshoot and the undershoot are approximately 110 mV and the settling times are less than 130 µs.
Autors: Li, X.;Tsui, C.-Y.;Ki, W.-H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 978 - 989
Publisher: IEEE
 
» A 2 GHz 2 Mb/s Semi-Digital -Point Modulator With Separate FIR-Embedded 1-Bit DCO Modulation in 0.18 m CMOS
Abstract:
A 2 GHz two-point modulator which has a separate high-pass control for DCO modulation is implemented in 0.18 m CMOS. The proposed modulator with the two-path DCO modulation enables a flexible gain partition for the high-pass and low-pass modulation paths within the DCO and relaxes the DCO nonlinearity with 1-b modulation and embedded finite-impulse response (FIR) filtering. A semi-digital PLL with another FIR filtering in the low-pass modulation enhances PLL linearity with a hybrid loop control. The proposed semi-digital modulator achieves 2.03% RMS EVM with 2 Mb/s GFSK modulation, dBc/Hz phase noise at 3 MHz offset, and dBc reference spur.
Autors: Xu, N.;Rhee, W.;Wang, Z.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2015, volume: 25, issue:4, pages: 253 - 255
Publisher: IEEE
 
» A 2.4 GHz Power Amplifier With 40% Global Efficiency at 5 dBm Output for Autonomous Wireless Sensor Nodes
Abstract:
Energy scavenged Wireless Sensor Nodes (WSNs) usually require a small output power ( 0 dBm) due to their short-range application and limited power budget. This makes the RF Power Amplifier (PA) design differ from conventional PAs as the output power becomes comparable to the PA driver's power consumption. In this letter, a 2.4 GHz tuned switching PA and driver is proposed with an on-chip duty cycle calibration loop to enhance efficiency. A prototype is fabricated in 40 nm CMOS technology and supports On-Off keying (OOK). Measurements show a global efficiency of 40% when delivering 5 dBm to a 50 load.
Autors: Stoopman, M.;Philips, K.;Serdijn, W.A.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2015, volume: 25, issue:4, pages: 256 - 258
Publisher: IEEE
 
» A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With Oversampling
Abstract:
In this brief, a delay-locked loop (DLL)-based burst-mode clock and data recovery (BMCDR) circuit using a oversampling technique is realized for passive optical network. With the help of DLL to track the input phase, the proposed circuit can recover the burst-mode data in a short acquisition time and achieve large jitter tolerance. In addition, a 2.5-GHz four-phase clock generator is embedded in the chip. Implemented with a 0.18- CMOS technology, experiment shows that the acquisition time can be accomplished in the time of 31 bits. Incoming 2.5-Gb/s input data of pseudorandom binary sequence, the retimed data has a root-mean-square jitter of 8.557 ps and a peak-to-peak jitter of 32.0 ps, and the measured bit error rate is less than . The area of the whole chip is 1.4 1.4 , where the BMCDR circuit core occupies 0.81 0.325 . The total power consumption is 130 mW from a 1.8 V supply voltage.
Autors: Lin, J.;Yang, C.;Wu, H.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Apr 2015, volume: 23, issue:4, pages: 791 - 795
Publisher: IEEE
 
» A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS
Abstract:
A fractional-N LC-PLL in 28 nm CMOS that uses vertical layout integration techniques to achieve area reduction without performance penalties is proposed. The design utilizes multi-metal layers to vertically integrate dual interposed inductors on top of the active PLL circuit elements, resulting in an area of 0.07 mm 2 . The PLL covers a wide-frequency range from 2.7 GHz to 7 GHz, consuming a total power of 14 mW. At 7 GHz, the RMS jitter is 0.56 ps in integer mode and 1.1 ps in fractional mode.
Autors: Lee, C.-H.;Kabalican, L.;Ge, Y.;Kwantono, H.;Unruh, G.;Chambers, M.;Fujimori, I.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 856 - 866
Publisher: IEEE
 
» A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS
Abstract:
This paper presents a continuous-time ΔΣ modulator targeted at optimizing power efficiency for input bandwidth exceeding 50 MHz. Delay in the feedback path is carefully minimized and traditional techniques for DAC mismatch correction and excess loop delay compensation are both replaced with digital schemes. Power is also minimized by relaxing loop filter BW requirements and using a power efficient opamp topology. The modulator achieves 73 dB dynamic range (DR) in 80 MHz BW while consuming 23 mW. The peak SNR is 70 dB and the peak SNDR is 67.5 dB, resulting in FOMs of 168 dB and 163 dB based on DR and SNDR, respectively.
Autors: Ho, S.;Lo, C.-L.;Ru, J.;Zhao, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 908 - 919
Publisher: IEEE
 
» A 270-to-300 GHz Sub-Harmonic Injection Locked Oscillator for Frequency Synthesis in Sub-mmW Systems
Abstract:
This letter describes a sub-mmW oscillator with more than 10% tuning range oscillation frequency. In particular, the circuit includes a high sensitivity sub-harmonic injection technique that forces the 270-to-300 GHz output signal to multiply by 6 a 45-to-50 GHz injection signal. Thus, the output spectral and phase noise properties depend only on the injected lower frequency signal. The circuit is fabricated in a BiCMOS 55 nm technology and it is measured using probes. It achieves a 30 GHz tuning range and locks all over it. The measured phase noise is-105 dBc/Hz at 1 MHz offset at 297 GHz and the power consumption is 52 mW.
Autors: Siligaris, A.;Andee, Y.;Jany, C.;Puyal, V.;Guerra, J.M.;Jimenez, J.L.G.;Vincent, P.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2015, volume: 25, issue:4, pages: 259 - 261
Publisher: IEEE
 
» A 3.2 V –15 dBm Adaptive Threshold-Voltage Compensated RF Energy Harvester in 130 nm CMOS
Abstract:
This paper presents an adaptive RF-DC power converter designed to efficiently convert RF signals to DC voltages utilizing auxiliary transistors to control the threshold voltage of the transistors in the main rectifier chain dynamically. The proposed circuit passively reduces the threshold voltage of the forward-biased transistors to increase the harvested power and the output voltage and increases the threshold voltage of the reverse-biased transistors to reduce the leakage current to prevent the loss of previously stored energy. A 12-stage adaptive threshold-compensated rectifier is designed and implemented in IBM's 0.13 CMOS technology. The proposed rectifier exhibits measured maximum power conversion efficiency (PCE) of 32% at 15 dBm (32 ) of input power while delivering 3.2 V to a 1 M load. At a remarkably low input power of 20.5 dBm (8.9 ) for a 1 M load, the rectifier produces an output voltage of 1 V.
Autors: Hameed, Z.;Moez, K.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2015, volume: 62, issue:4, pages: 948 - 956
Publisher: IEEE
 
» A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit
Abstract:
A 5.0 G-pixel/s readout circuit for 15.3 mm 8.6 mm optical size, 3.7 M-pixel, 1300 fps, and digital output image sensor for industrial applications is presented. With the column parallel ADC, the speed bottleneck is the vertical analog readout. To achieve a 5.0 G-pixel/s readout rate, a high speed column readout circuit is introduced. The novel pixel readout with the slew-enhancement and the time-interleaved correlated double sampling circuit is introduced to increase the readout rate. Besides, the A/D converter with the delay-and-gray code counter and the distributed digital data transfer schemes are innovated in order to reduce the noise interference to the foreground analog signal settling. The 1 horizontal (1H) readout time is 1.0 s.
Autors: Okura, S.;Nishikido, O.;Sadanaga, Y.;Kosaka, Y.;Araki, N.;Ueda, K.;Morishita, F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 1016 - 1024
Publisher: IEEE
 
» A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
Abstract:
A digital fractional-N PLL that employs a high resolution TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than 106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fs integrated jitter. This translates to a FoM of 240.5 dB, which is the best among the reported fractional-N PLLs.
Autors: Elkholy, A.;Anand, T.;Choi, W.-S.;Elshazly, A.;Hanumolu, P.K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 867 - 881
Publisher: IEEE
 
» A 4.78 mm 2 Fully-Integrated Neuromodulation SoC Combining 64 Acquisition Channels With Digital Compression and Simultaneous Dual Stimulation
Abstract:
A 65 nm CMOS 4.78 mm 2 integrated neuromodulation SoC consumes 348 µA from an unregulated 1.2 V to 1.8 V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50 Hz and engaging two stimulators with a pulse width of 250 µs/phase, differential current of 150 µA, and a pulse frequency of 100 Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.
Autors: Biederman, W.;Yeager, D.J.;Narevsky, N.;Leverett, J.;Neely, R.;Carmena, J.M.;Alon, E.;Rabaey, J.M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 1038 - 1047
Publisher: IEEE
 
» A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology
Abstract:
A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10 -9 . The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.
Autors: Navid, R.;Chen, E.-H.;Hossain, M.;Leibowitz, B.;Ren, J.;Chou, C.-H.A.;Daly, B.;Aleksic, M.;Su, B.;Li, S.;Shirasgaonkar, M.;Heaton, F.;Zerbe, J.;Eble, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 814 - 827
Publisher: IEEE
 
» A 44 GHz CMOS RFIC Dual-Function Attenuator with Band-Pass-Filter Response
Abstract:
A dual-function attenuator possessing both attenuation and band-pass filtering functions is proposed. The new dual-function band-pass attenuator architecture is derived by replacing the quarter-wavelength transmission line of a conventional attenuator with a 2nd-order admittance-inverter band-pass filter. Design formulas for the dual-function band-pass attenuator are derived. A 3-b CMOS dual-function band-pass step attenuator designed using a 0.18 BiCMOS technology shows measured insertion loss of 4.4–5.9 dB, RMS amplitude error of 0.8–1.4 dB, RMS phase error of 1.9–6.7 over 36–52 GHz, input P1dB higher than 20 dBm at 44 GHz, and band-pass-filtering response with stop-band rejections greater than 18 dB at 24 and 64 GHz.
Autors: Bae, J.;Nguyen, C.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2015, volume: 25, issue:4, pages: 241 - 243
Publisher: IEEE
 
» A 5.9-GHz Fully Integrated GaN Frontend Design With Physics-Based RF Compact Model
Abstract:
This paper presents the design of a fully integrated high-efficiency and high-power RF frontend for the IEEE 802.11p standard in GaN HEMT technology. An embedded transmitter/receiver (Tx/Rx) switching scheme and a dual-bias power amplifier linearization technique are used to improve Tx efficiency and linearity. An accurate physics-based nonlinear large-signal device model is developed and used for the design, providing insight into the impact of the behavioral nuances of the GaN HEMTs on RF circuit performance. The fully integrated RF frontend is fabricated in 0.25- GaN-on-SiC technology and occupies only 2 mm 1.2 mm. The Tx branch achieves 48.5% drain efficiency at 33.9 dBm, with 28-V supply. With orthogonal frequency-division multiplexing modulated signals, it achieves 30% average efficiency at 27.8-dBm output power while meeting the 25-dB error vector magnitude limit without predistortion. The Rx branch achieves 22-dBm output third-order intercept point with 3.7-dB noise figure at 12-V supply. The fully integrated high-efficiency and linear RF frontend designed with physics-based RF GaN compact models is demonstrated for the first time for future device-to-device applications.
Autors: Choi, P.;Goswami, S.;Radhakrishna, U.;Khanna, D.;Boon, C.-C.;Lee, H.-S.;Antoniadis, D.;Peh, L.-S.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Apr 2015, volume: 63, issue:4, pages: 1163 - 1173
Publisher: IEEE
 
» A 60 GHz 2.5 Gbps OOK Modulator with Data-Dependent Impedance Cell for Enhanced ON/OFF Isolation in 0.18 m BiCMOS Process
Abstract:
A 60 GHz on/off-keying (OOK) modulator with data-dependent impedance cell for enhanced ON/OFF isolation supporting up to 2.5 Gbps data rate is presented. Based on a single-stage cascode amplifier, the OOK modulator achieves 36.5 dB isolation and 11.5 dB forward gain, resulting in very high ON/OFF isolation of 48 dB by incorporating the data-dependent impedance cell. The OOK modulator is realized in a 0.18 m BiCMOS process, occupies 0.95 mm 0.95 mm with pads and 0.4 mm 0.28 mm without pads, and only consumes 4.5 mA at 1.8 V supply voltage ( 8.1 mW).
Autors: Jang, S.;Nguyen, C.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2015, volume: 25, issue:4, pages: 244 - 246
Publisher: IEEE
 
» A 60-GHz CMOS Dual-Mode Power Amplifier With Efficiency Enhancement at Low Output Power
Abstract:
A 60-GHz dual-mode power amplifier (PA) with efficiency enhancement at low output power in 65-nm bulk CMOS is presented. The PA consists of two cascaded common-source driver stages and one transformer-based output stage. The dual-mode output stage is reconfigured into a stacked-transistor amplifier with a 2.5-V power supply in high-power (HP) mode for high-power-handling capability and a cascode amplifier with a 1.2-V power supply in low-power (LP) mode for efficiency enhancement at low output power. The measured results show that the presented PA achieves a small-signal gain of 23.5/21.3 dB, a saturated output power value of 17.6/11.4 dBm, a 1-dB output power value of 12.5/4.7 dBm, and a peak power-added-efficiency (PAE) value of 20.4%/13.3% in the HP/LP mode at 60 GHz, respectively. The PAE at 10-dBm output power is improved by 2.8x (10.6% versus 3.8%) by utilizing the LP mode compared with the HP-mode-only PA. The total chip area is 0.68 mm × 0.35 mm, including pads.
Autors: Kuang, L.;Chi, B.;Jia, H.;Jia, W.;Wang, Z.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2015, volume: 62, issue:4, pages: 352 - 356
Publisher: IEEE
 
» A 65 nm Cryptographic Processor for High Speed Pairing Computation
Abstract:
Pairings are attractive and competitive cryptographic primitives for establishing various novel and powerful information security schemes. This paper presents a flexible and high-performance processor for cryptographic pairings over pairing-friendly curves at high security levels. In this design, hardware for Fp2 arithmetic is optimized to accelerate the pairing computation, and especially a combined modular multiplier, which implements (AB + CD) based on Montgomery method, is proposed. This combined multiplier has the data path delay close to that of a single multiplier implementing (AB) but saves 20% area cost compared with two single multipliers. The Design I of the proposed processor is the first fabricated chip for pairing cryptography. An improved version, Design II, is implemented using TSMC 65-nm CMOS technology and achieves the working frequency of 633 MHz after placing and routing. As demonstrated, the optimal ate pairings of 126- and 128-bit security can be computed by Design II in 0.521 and 0.554 ms, respectively. These results outperform the hardware implementations reported by previous works.
Autors: Han, J.;Li, Y.;Yu, Z.;Zeng, X.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Apr 2015, volume: 23, issue:4, pages: 692 - 701
Publisher: IEEE
 
» A Bias-Free Quantum Random Number Generation Using Photon Arrival Time Selectively
Abstract:
We present a high-quality bias-free quantum random number generator (QRNG) using photon arrival time selectively, in accordance with the number of photon detection events within a sampling time interval in attenuated light. It is well shown in both theoretical analysis and experimental verification that this random number production method eliminates both bias and correlation perfectly without more postprocessing and that the random number can clearly pass the standard randomness tests. We fulfill theoretical analysis and experimental verification of the method whose rate can reach up to 45 Mb/s.
Autors: Jian-min Wang;Tian-yu Xie;Hong-fei Zhang;Dong-xu Yang;Chao Xie;Jian Wang;
Appeared in: IEEE Photonics Journal
Publication date: Apr 2015, volume: 7, issue:2, pages: 1 - 8
Publisher: IEEE
 
» A Blind Zone Alert System Based on Intra-Vehicular Wireless Sensor Networks
Abstract:
Due to the increasing number of sensors deployed in modern vehicles, intra-vehicular wireless sensor networks (IVWSNs) have recently received a lot of attention in the automotive industry, as they can reduce the amount of wiring harness inside a vehicle. By removing the wires, car manufacturers can reduce the weight of a vehicle and improve engine performance, fuel economy, and reliability. In addition to these direct benefits, an IVWSN is a versatile platform that can support other vehicular applications as well. An example application, known as a side blind zone alert (SBZA) system, which monitors the blind zone of the vehicle and alerts the driver in a timely manner to prevent collisions, is discussed in this paper. The performance of the IVWSN-based SBZA system is evaluated via real experiments conducted on two test vehicles. Our results show that the proposed system can achieve approximately 95%–99% detection rate with less than 15% false alarm rate. Compared with commercial systems using radars or cameras, the main benefit of the IVWSN-based SBZA is substantially lower cost.
Autors: Lin, J.;Talty, T.;Tonguz, O.K.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Apr 2015, volume: 11, issue:2, pages: 476 - 484
Publisher: IEEE
 
» A Broadband Tunable Multilayer Substrate Integrated Waveguide Phase Shifter
Abstract:
A novel low loss, electronically controllable two-layer substrate integrated waveguide (SIW) phase shifter is presented in this letter. Wideband coupling between two layers ensures the wide bandwidth. PIN diodes are used to achieve electronic control of phase shifter. An equivalent circuit model for this device is developed and explained. A compact and low loss five-level digital phase shifter using the proposed structure is designed, fabricated and measured. The simulated results excellently agree with measured results. Including the microstrip-to-SIW transitions, the measured insertion loss is dB over desired frequency band, with an amplitude and phase imbalance of dB , respectively. Return loss performance of better than 15 dB is observed from 10 to 14 GHz, providing a wide relative bandwidth of around 33%. Measured results validate better performance compared to its SIW counterparts.
Autors: Muneer, B.;Qi, Z.;Shanjia, X.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2015, volume: 25, issue:4, pages: 220 - 222
Publisher: IEEE
 
» A BST-Integrated Capacitively Loaded Patch for - and -band Beamsteerable Reflectarray Antennas in Satellite Communications
Abstract:
Tunable reflectarray unit cells operating at - and -bands are presented in this paper using barium strontium titanate (BST) technology. A patch antenna is capacitively loaded with a narrow gap in the middle and a thin-film BST layer is deposited under the patch. By tuning the dc-bias voltage across the gap, the dielectric properties of the BST layer are changed and then an integrated tunable capacitor is realized. The proposed design is evaluated using both full-wave simulations and measurements. Due to the monolithic integration of the tuning mechanism with the unit cell, the antenna element can be applied at millimeter-wave frequencies without suffering from packaging and bonding problems. The effects of substrate thickness, system pressure, and operating frequency on the performance of the BST-integrated unit cell are presented. An overall phase range of 298° and 263° with maximum reflection losses of and at - and -bands, respectively, are measured when the unit cells are operated for maximum phase range. By judiciously selecting the frequency of operation, a phase range of 250° with maximum reflection losses of 5.6 and 5.8 dB at 30.7 and 10.27 GHz are achieved. The presented analysis provides guidelines for optimizing the unit cell’s performance required for efficient beam-scanning reflectarray antennas.
Autors: Karnati, K.K.;Shen, Y.;Trampler, M.E.;Ebadi, S.;Wahid, P.F.;Gong, X.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Apr 2015, volume: 63, issue:4, pages: 1324 - 1333
Publisher: IEEE
 
» A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method
Abstract:
A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of 104 dBc/Hz and 1.5 ps integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of 225.8 dB.
Autors: Nandwana, R.K.;Anand, T.;Saxena, S.;Kim, S.-J.;Talegaonkar, M.;Elkholy, A.;Choi, W.-S.;Elshazly, A.;Hanumolu, P.K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2015, volume: 50, issue:4, pages: 882 - 895
Publisher: IEEE
 
» A cloud-based approach to spectrum monitoring
Abstract:
Thousands of wireless communication systems have been fielded, with hundreds more under development. The RF spectrum has growing economic value to consumers, businesses, and governments worldwide. This has generated such a demand for wireless bandwidth that spectrum allocation, the existing primary method of spectrum management, is becoming increasingly inadequate. In this paper, we briefly summarize the response to the U.S. National Telecommunications and Information Agency???s Notice of Inquiry concerning a Spectrum Monitoring Pilot Program and present a cloud-based system-of-systems for spectrum monitoring based on the response to the Inquiry. We describe the interface to the cloud as an important enabler and propose a solution that allows ontology descriptions to be used for both spectrum management and monitoring. These ontology descriptions support the use of semantic techniques such as queries, responses, and reasoning.
Autors: Cooklev, T.;Darabi, J.;Mcintosh, C.;Mosaheb, M.;
Appeared in: IEEE Instrumentation & Measurement Magazine
Publication date: Apr 2015, volume: 18, issue:2, pages: 33 - 37
Publisher: IEEE
 
» A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth
Abstract:
A new combinatorial impairment-compensation digital predistorter (DPD) for a sub-GHz IEEE 802.11af-WLAN CMOS transmitter (TX) is proposed. For the TX to cover a 10x-wide bandwidth, the DPD implements a modified dynamic deviation reduction (DDR)-based Volterra series to jointly nullify the frequency-dependent I/Q imbalance, counter-intermodulation (CIM) of mixers, and nonlinearities of power amplifier (PA) with memory effect. The interactions of those impairments are firstly analyzed using two Volterra series. After applying the tandem properties of Volterra series, interactions of all impairments can be described in one Volterra series by bonding those impairments in parallel. Coefficients of the DPD are extracted with the Least- Square (LS) estimator, achieving lower running complexity than the existing DPDs, which were developed to handle the PA nonlinearities only. Verifications are based on both system-level simulations and silicon measurements of a 65-nm CMOS TX prototype. When the TX delivers a 6-MHz bandwidth, 2048-point, 64-QAM OFDM signal at 10 dBm output power, the measured EVM is 3.7% and adjacent channel leakage ratio (ACLR) is 40.2 dBc under individual DPD applied at each RF. A novel one-shot calibration for reuse in the entire TV-band is demonstrated also, showing EVM 4.2% and ACLR 39.8 dBc.
Autors: Cheang, C.-F.;Un, K.-F.;Yu, W.-H.;Mak, P.-I.;Martins, R.P.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2015, volume: 62, issue:4, pages: 1025 - 1032
Publisher: IEEE
 
» A Combined Process of Liftoff and Printing for the Fabrication of Scalable Inkjet Printed Microstructures on a Flexible Substrate
Abstract:
In this paper, a combined process of liftoff and printing (CPLoP) techniques is introduced to realize size-scalable printed silver microstructures with line widths ranging from 5 to 70 and resistivities of on a flexible polyimide substrate via thermal sintering at 300 °C for 30 min. In addition, a printed interdigitated capacitor with an electrode line width and spacing of and a printed spiral square inductor with a 10- line width and 5- spacing in an area of 1 mm have been successfully demonstrated with an area capacitance and inductance of 0.43 pF/mm at 10 KHz and 1.054 /mm up to 100 KHz, respectively, which are the orders of magnitude performance improvement in comparison with the contemporary inkjet-printed capacitors and inductors. Owing to the significant reduction of energy demand in processing tools and waste generation in processing materials, the results have revealed that the CPLoP process can facilitate the advancement of printing manufacture technology for microelectronics applications.
Autors: Fu, Y.;Liang, Y.R.;Cheng, Y.;Wu, P.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Apr 2015, volume: 62, issue:4, pages: 1248 - 1254
Publisher: IEEE
 
» A Compact Dual-Band Orthogonal Circularly Polarized Antenna Array With Disparate Elements
Abstract:
A dual-band orthogonally and circularly polarized antenna array with disparate elements is presented. By using corner-truncated stacked patches as elements, both left hand circular polarization (LHCP) in 12 GHz band and right hand circular polarization (RHCP) in 14 GHz band are realized in a shared antenna aperture. Furthermore, by employing disparate elements, the coupling between the two bands is suppressed effectively inside the feed network, hence improving isolation. The measured results of a four-element array agreed well with the simulated ones, achieving isolation better than 20 dB in the dual bands, and a maximum gain of 13.2 dBic for the LHCP and 13.9 dBic for the RHCP. The proposed array can find applications in satellite communications.
Autors: Ye, S.;Geng, J.;Liang, X.;Jay Guo, Y.;Jin, R.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Apr 2015, volume: 63, issue:4, pages: 1359 - 1364
Publisher: IEEE
 
» A Compact Implementation of Parasitic Inductance Cancellation for Shunt Capacitor Filters on Multilayer PCBs
Abstract:
Parasitic inductance limits the high-frequency performance of surface mount capacitors in a shunt filtering configuration. This paper introduces a new compact design for cancelling this parasitic inductance that makes use of magnetic coupling between vias, as well as between coplanar traces. This design is intended for use on PCBs with more than two layers, and is an extension of the designs presented in the recent paper by the authors, “Parasitic Inductance Cancellation for Surface Mount Shunt Capacitor Filters.” Implementations of the new design are shown to exhibit similar filtering performance to comparable implementations of previously published designs, while requiring nearly 40% less board area. Additionally, implementations of the design are demonstrated to be effective in the practical situation of filtering the noise due to crosstalk on a four-layer board.
Autors: McDowell, A.J.;Hubing, T.H.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Apr 2015, volume: 57, issue:2, pages: 257 - 263
Publisher: IEEE
 
» A Comparative Assessment of Predictive Accuracies of Conventional and Machine Learning Scoring Functions for Protein-Ligand Binding Affinity Prediction
Abstract:
Accurately predicting the binding affinities of large diverse sets of protein-ligand complexes efficiently is a key challenge in computational biomolecular science, with applications in drug discovery, chemical biology, and structural biology. Since a scoring function (SF) is used to score, rank, and identify potential drug leads, the fidelity with which it predicts the affinity of a ligand candidate for a protein’s binding site has a significant bearing on the accuracy of virtual screening. Despite intense efforts in developing conventional SFs, which are either force-field based, knowledge-based, or empirical, their limited predictive accuracy has been a major roadblock toward cost-effective drug discovery. Therefore, in this work, we explore a range of novel SFs employing different machine-learning (ML) approaches in conjunction with a variety of physicochemical and geometrical features characterizing protein-ligand complexes. We assess the scoring accuracies of these new ML SFs as well as those of conventional SFs in the context of the 2007 and 2010 PDBbind benchmark datasets on both diverse and protein-family-specific test sets. We also investigate the influence of the size of the training dataset and the type and number of features used on scoring accuracy. We find that the best performing ML SF has a Pearson correlation coefficient of 0.806 between predicted and measured binding affinities compared to 0.644 achieved by a state-of-the-art conventional SF. We also find that ML SFs benefit more than their conventional counterparts from increases in the number of features and the size of training dataset. In addition, they perform better on novel proteins that they were never trained on before.
Autors: Ashtawy, H.M.;Mahapatra, N.R.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Apr 2015, volume: 12, issue:2, pages: 335 - 347
Publisher: IEEE
 
» A comparison of thermoset and thermoplastic arc chutes in molded-case circuit breakers under fault clearing
Abstract:
Molded-case circuit breakers (MCCB) are vital devices that are used in many distribution systems for protection from faults in the network. During a fault, a large increase in current passes through the terminals of the MCCB and the contacts open by electromagnetic actuation. On opening, a low-voltage arc is struck between the contacts, forming a high-temperature plasma of thousands of degrees Celsius. The plasma causes thermal degradation of the insulating materials and erosion of the contacts and is a source of intense UV, which may further cause degradation of the insulating materials. In the case of a polyester based MCCB, electrically conductive soot is produced, which is detrimental to the long-term performance of the device.
Autors: Beema Thangarajan, R.;Chetwani, S.;Shrinet, V.;Oak, M.;Jain, S.;
Appeared in: IEEE Electrical Insulation Magazine
Publication date: Apr 2015, volume: 31, issue:2, pages: 30 - 35
Publisher: IEEE
 
» A Comprehensive Approach for Transient Performance of Grounding System in the Time Domain
Abstract:
It is important to identify the impulse performance of the grounding system for lightning protection. However, the performance is nonlinear and dynamic under impulse condition. The electrical parameters of the grounding system are not only frequency dependent, but are also time dependent. Moreover, the mutual couplings between the grounding conductors cannot be ignored. Based on the hybrid electromagnetic method and vector fitting, a time-domain approach for the transient performance of the grounding system is developed. All the aforementioned phenomena can be covered in this method. Meanwhile, the sudden change of the parameters resulting from the soil ionization is also successfully dealt with in this paper. Compared with previous study results and field tests, the method proves to be reliable and effective.
Autors: Wu, J.;Zhang, B.;He, J.;Zeng, R.;
Appeared in: IEEE Transactions on Electromagnetic Compatibility
Publication date: Apr 2015, volume: 57, issue:2, pages: 250 - 256
Publisher: IEEE
 
» A Cooperative Train Control Model for Energy Saving
Abstract:
Increasing attention is being paid to energy efficiency in subway systems to reduce operational cost and carbon emissions. Optimization of the driving strategy and efficient utilization of regenerative energy are two effective methods to reduce the energy consumption for electric subway systems. Based on a common scenario that an accelerating train can reuse the regenerative energy from a braking train on the opposite track, this paper proposes a cooperative train control model to minimize the practical energy consumption, i.e., the difference between traction energy and the reused regenerative energy. First, we design a numerical algorithm to calculate the optimal driving strategy with the given trip time, in which the variable traction force, braking force, speed limits, and gradients are considered. Then, a cooperative train control model is formulated to adjust the departure time of the accelerating train for reducing the practical energy consumption during the trip by efficiently using the regenerative energy of the braking train. Furthermore, a bisection method is presented to solve the optimal departure time for an accelerating train. Finally, the optimal driving strategy is obtained for the accelerating train with the optimal departure time. Case studies based on the Yizhuang Line, Beijing Subway, China, are presented to illustrate the effectiveness of the proposed approach on energy saving.
Autors: Su, S.;Tang, T.;Roberts, C.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Apr 2015, volume: 16, issue:2, pages: 622 - 631
Publisher: IEEE
 
» A Coordinated Voltage Control Approach for Coordination of OLTC, Voltage Regulator, and DG to Regulate Voltage in a Distribution Feeder
Abstract:
Integration of small-scale electricity generators, known as distributed generation (DG), into the distribution networks has become increasingly popular at the present. This tendency together with the falling price of the synchronous-type generator has potential to give DG a better chance at participating in the voltage regulation process together with other devices already available in the system. The voltage control issue turns out to be a very challenging problem for the distribution engineers since existing control coordination schemes would need to be reconsidered to take into account the DG operation. In this paper, we propose a control coordination technique, which is able to utilize the ability of DG as a voltage regulator and, at the same time, minimize interaction with other active devices, such as an on-load tap changing transformer and a voltage regulator. The technique has been developed based on the concept of control zone, line drop compensation, dead band, as well as the choice of controllers' parameters. Simulations carried out on an Australian system show that the technique is suitable and flexible for any system with multiple regulating devices including DG.
Autors: Muttaqi, K.M.;Le, A.D.T.;Negnevitsky, M.;Ledwich, G.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Apr 2015, volume: 51, issue:2, pages: 1239 - 1248
Publisher: IEEE
 
» A Cross-Layer Perspective on Energy-Harvesting-Aided Green Communications Over Fading Channels
Abstract:
In this paper, we consider the power allocation of the physical layer and the buffer delay of the upper application layer in energy harvesting green networks. The total power required for reliable transmission includes the transmission power and the circuit power. The harvested power (which is stored in a battery) and the grid power constitute the power resource. The uncertainty of data generated from the upper layer, the intermittence of the harvested energy, and the variation of the fading channel are taken into account and described as independent Markov processes. In each transmission, the transmitter decides the transmission rate and the allocated power from the battery, and the rest of the required power will be supplied by the power grid. The objective is to find an allocation sequence of transmission rate and battery power to minimize the long-term average buffer delay under the average grid power constraint. A stochastic optimization problem is formulated accordingly to find such transmission rate and battery power sequence. Furthermore, the optimization problem is reformulated as a constrained Markov decision process (MDP) problem whose policy is a 2-D vector with the transmission rate and the power allocation of the battery as its elements. We prove that the optimal policy of the constrained MDP can be obtained by solving the unconstrained MDP. Then, we focus on the analysis of the unconstrained average-cost MDP. The structural properties of the average optimal policy are derived. Moreover, we discuss the relations between elements of the 2-D policy. Next, based on the theoretical analysis, the algorithm to find the constrained optimal policy is presented for the finite-state-space scenario. In addition, heuristic policies (two deterministic policies and a mixed policy) with low complexity are given for the general state space. Finally, simulations are performed under these policies to demonstrate their effectiveness.
Autors: Zhang, T.;Chen, W.;Han, Z.;Cao, Z.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Apr 2015, volume: 64, issue:4, pages: 1519 - 1534
Publisher: IEEE
 
» A Decentralized Multiagent-Based Voltage Control for Catastrophic Disturbances in a Power System
Abstract:
In this paper, a multiagent-based voltage and reactive power control in the case of a multiple contingency is presented. Incorporating the agent-based autonomous feature to the intelligence of the remote terminal units, the present power system control structure can be used to help in preventing system voltage collapse during catastrophic disturbances. The control algorithm is based on a decentralized architecture of intelligent agents and the determination of a local zone that can carry out quick countermeasures in a decentralized manner as a multiagent system (MAS) during an emergency situation. An adaptive determination of the local zones undergoing voltage collapse has been developed based on the electrical distances among the generators and loads. Once assigned, the elements of the Jacobian matrix can be used to determine the optimum actions that need to be carried out at each power system element (such as increasing the voltages of generators and load shedding) within the assigned local zone. The contract net protocol is used for agent interactions. Simulation results using the IEEE-57 bus system show that the proposed method can act quickly to respond to emergency conditions to ensure that voltage collapse can be avoided.
Autors: Islam, S.R.;Muttaqi, K.M.;Sutanto, D.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Apr 2015, volume: 51, issue:2, pages: 1201 - 1214
Publisher: IEEE
 
» A Digital Frequency Multiplication Technique for Energy Efficient Transmitters
Abstract:
A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13- CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.
Autors: Manikandan, R.R.;Kumar, A.;Amrutur, B.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Apr 2015, volume: 23, issue:4, pages: 781 - 785
Publisher: IEEE
 
» A Direct Digital Readout Circuit for Impedance Sensors
Abstract:
A new, simple and high-accuracy impedance-to-digital converter (IDC) is proposed in this paper. Conventionally, the parameters of sensors that can be modeled using a parallel combination of a capacitor (C) and a resistor (R) are measured using ac bridges, excited from a sinusoidal source. Recently, with the widespread use of digital systems in instrumentation, capacitance-to-digital converters and resistance-to-digital converters gained a lot of importance. An IDC that accepts sensors having C and R in parallel and provides digital outputs directly proportional to the C and R values is presented in this paper. This can be used not only for sensors whose C and R values vary with the measurand but also when C or R of a sensor needs to be measured keeping the output not affected by parasitic R or C present in parallel with the sensing element. Another application of the IDC is in the measurement of the dissipation factor of dielectric materials. The proposed IDC is based on a dual-slope technique, and hence provides high accuracy and immunity to noise and interference. A prototype of the proposed IDC has been developed and tested in the laboratory. Accuracy of the prototype IDC developed was 0.15% for the measurement of C and 0.04% for the measurement of R. The total conversion time of the prototype converter developed is 3 s, and its total power dissipation is 175.8 mW. The IDC was also interfaced with a polymer-based impedance humidity sensor, measured its C and R values for a range of humidity, computed the humidity, and compared its performance with another instrument, showing the practicality of the proposed IDC.
Autors: Vooka, P.;George, B.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Apr 2015, volume: 64, issue:4, pages: 902 - 912
Publisher: IEEE
 
» A Direct PCA-Based Approach for Real-Time Description of Physiological Organ Deformations
Abstract:
Dynamic magnetic resonance (MR)-imaging can provide functional and positional information in real-time, which can be conveniently used online to control a cancer therapy, e.g., using high intensity focused ultrasound or radio therapy. However, a precise real-time correction for motion is fundamental in abdominal organs to ensure an optimal treatment dose associated with a limited toxicity in nearby organs at risk. This paper proposes a real-time direct principal component analysis (PCA)-based technique which offers a robust approach for motion estimation of abdominal organs and allows correcting motion related artifacts. The PCA was used to detect spatio-temporal coherences of the periodic organ motion in a learning step. During the interventional procedure, physiological contributions were characterized quantitatively using a small set of parameters. A coarse-to-fine resolution scheme is proposed to improve the stability of the algorithm and afford a predictable constant latency of 80 ms. The technique was evaluated on 12 free-breathing volunteers and provided an improved real-time description of motion related to both breathing and cardiac cycles. A reduced learning step of 10 s was sufficient without any need for patient-specific control parameters, rendering the method suitable for clinical use.
Autors: Denis de Senneville, B.;El Hamidi, A.;Moonen, C.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Apr 2015, volume: 34, issue:4, pages: 974 - 982
Publisher: IEEE
 
» A Directional Inline-Type Millimeter-Wave MEMS Power Sensor for GaAs MMIC Applications
Abstract:
This letter presents a directional inline millimeter-wave microelectromechanical systems (MEMS) power sensor with both thermoelectric and capacitive detection elements, in order to show the power transfer direction and improve the high-power detection range. In the design, a certain percentage of the incident power is extracted by a coplanar-waveguide directional coupler, and sensed in a MEMS fixed–fixed beam for the capacitive detection and in a thermopile-based sensor for the thermoelectric detection. This power sensor offers the compatible capability with the GaAs monolithic microwave integrated circuits technology. Measured reflection and insertion losses are less than −14 and 1.3 dB at 30−36 GHz, respectively. Experiments demonstrate that the thermoelectric sensor confirms the directionality of this inline sensor for the known power level with average sensitivities of and 1.02 V thermoelectrically at 34 GHz for two different input ports. [2014-0149]
Autors: Zhang, Z.;Liao, X.;Wang, K.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Apr 2015, volume: 24, issue:2, pages: 253 - 255
Publisher: IEEE
 
» A Disassembly-Free Offline Detection and Condition Monitoring Technique for Eccentricity Faults in Salient-Pole Synchronous Machines
Abstract:
A novel scheme to reliably monitor the condition of static and dynamic eccentricity (DE) faults in salient-pole synchronous machines (SPSMs) through the standard short-circuit test is proposed in this paper. The detection technique is based on offline current signature analysis that does not require machine disassembly. The procedure is unaffected by machine saturation or supply voltage harmonics. In this scheme, DE fault is monitored by exploiting the presence of inherent static eccentricity (SE), whereas SE fault monitoring is achieved using residual estimation technique. The proposed method is found to work for both star and delta-connected machines. Results obtained from an experimental three-phase 2-kW SPSM have been used to validate the proposed eccentricity condition monitoring method.
Autors: Ilamparithi, T.;Nandi, S.;Subramanian, J.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Apr 2015, volume: 51, issue:2, pages: 1505 - 1515
Publisher: IEEE
 
» A Distortion-Resistant Routing Framework for Video Traffic in Wireless Multihop Networks
Abstract:
Traditional routing metrics designed for wireless networks are application-agnostic. In this paper, we consider a wireless network where the application flows consist of video traffic. From a user perspective, reducing the level of video distortion is critical. We ask the question “Should the routing policies change if the end-to-end video distortion is to be minimized?” Popular link-quality-based routing metrics (such as ETX) do not account for dependence (in terms of congestion) across the links of a path; as a result, they can cause video flows to converge onto a few paths and, thus, cause high video distortion. To account for the evolution of the video frame loss process, we construct an analytical framework to, first, understand and, second, assess the impact of the wireless network on video distortion. The framework allows us to formulate a routing policy for minimizing distortion, based on which we design a protocol for routing video traffic. We find via simulations and testbed experiments that our protocol is efficient in reducing video distortion and minimizing the user experience degradation.
Autors: Papageorgiou, G.;Singh, S.;Krishnamurthy, S.V.;Govindan, R.;La Porta, T.;
Appeared in: IEEE/ACM Transactions on Networking
Publication date: Apr 2015, volume: 23, issue:2, pages: 412 - 425
Publisher: IEEE
 
» A Distributed Fault-Tolerant Topology Control Algorithm for Heterogeneous Wireless Sensor Networks
Abstract:
This paper introduces a distributed fault-tolerant topology control algorithm, called the Disjoint Path Vector (DPV), for heterogeneous wireless sensor networks composed of a large number of sensor nodes with limited energy and computing capability and several supernodes with unlimited energy resources. The DPV algorithm addresses the k-degree Anycast Topology Control problem where the main objective is to assign each sensor's transmission range such that each has at least k-vertex-disjoint paths to supernodes and the total power consumption is minimum. The resulting topologies are tolerant to k-1 node failures in the worst case. We prove the correctness of our approach by showing that topologies generated by DPV are guaranteed to satisfy k-vertex supernode connectivity. Our simulations show that the DPV algorithm achieves up to 4-fold reduction in total transmission power required in the network and 2-fold reduction in maximum transmission power required in a node compared to existing solutions.
Autors: Bagci, H.;Korpeoglu, I.;Yazıcı, A.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Apr 2015, volume: 26, issue:4, pages: 914 - 923
Publisher: IEEE
 
» A Distributed LT Code Design for Multiple-Access Relay Networks Subject to Erasures
Abstract:
This letter proposes a new distributed Luby transform (LT) code which is particularly suitable for the multiple-access relay network with erasure channels. We analyze the asymptotic performance of our distributed coding scheme by virtue of AND-OR tree analysis and present the simulation results of finite length comparing with existing methodologies. The proposed coding scheme is shown to be superior to conventional strategies in presence of both source-relay and relay-sink erasures.
Autors: Yang, H.;Jiang, M.;Shen, H.;Zhao, C.;
Appeared in: IEEE Communications Letters
Publication date: Apr 2015, volume: 19, issue:4, pages: 509 - 512
Publisher: IEEE
 
» A Double-Layer VLC System With Low-Complexity ML Detection and Binary Constellation Designs
Abstract:
We consider a double-layer visible light communication system where transmitted data is split into two layers with different priorities and variant transmission rates. High-priority data is assigned to the upper layer with low transmission rate, while low-priority data is assigned to the lower layer with higher transmission rate. For this scenario, we develop a low-complexity maximum likelihood detection algorithm. In addition, several binary constellation designs corresponding to different priority orders are presented. Computer simulations show that maximum likelihood detection detection significantly improves the error-rate performance, compared to sum detection, without compromising the computational complexity of the receiver.
Autors: Zhu, H.;Zhu, Y.;Zhang, J.;Zhang, Y.;
Appeared in: IEEE Communications Letters
Publication date: Apr 2015, volume: 19, issue:4, pages: 561 - 564
Publisher: IEEE
 
» A Dual-Band 180-Degree Hybrid Coupler Based on Coupled-Line Sections
Abstract:
This letter presents a novel 180 degree hybrid coupler structure based on coupled-line sections which offers a compact circuit and a dual-band operation. The structure is based on 90 degree and 180 degree coupled lines suitable to offer a 180 degree hybrid coupler behavior at two frequency bands when the even and odd impedances of the coupled-line sections are properly determined. The circuit presents a symmetry plane that enables an even/odd analysis. The dual-band operation of the structure has been verified by means of a prototype implemented in microstrip technology operating at 2.4 and 5 GHz.
Autors: Corrales, E.;Baldomero, A.;de Paco, P.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2015, volume: 25, issue:4, pages: 211 - 213
Publisher: IEEE
 
» A Dual-Wavelength Rational Harmonic Mode-Locked Fiber Ring Laser With Different Repetition Frequencies
Abstract:
A dual-wavelength rational harmonic mode-locked fiber ring laser with different repetition frequencies is theoretically analyzed and experimentally demonstrated. In this scheme, two wavelength channels are inserted into the laser loop to form two resonant cavities. By tuning the length of each channel, required rational harmonic mode-locking conditions can be achieved, and dual-frequency mode-locked signals are simultaneously generated at different wavelengths. In addition, the supermode suppression ratio is further improved due to the mode competition caused by this dual-cavity configuration. In the experimental demonstration, when the fourth-order (or fifth-order) harmonic mode-locked signal is generated in Cavity 1, the first-, second-, and third-order (or fourth-order) harmonic mode-locked signals, respectively, can be generated in Cavity 2 by tuning its length. The measured radio frequency spectra and waveforms show that the signals have high quality. Compared with a conventional rational harmonic mode-locked laser (RHMLL), more than 10 dB supermode suppression ratio improvement is obtained. Since this system can flexibly implement multiwavelength and multifrequency signal generation without adding much cost, it may have wide applications in optical communication system, photonic microwave signal generation, and optical waveform synthesizers.
Autors: Zi, Y.;Jiang, Y.;Ma, C.;Bai, G.;Jia, Z.;Wu, T.;Huang, F.;
Appeared in: IEEE Photonics Journal
Publication date: Apr 2015, volume: 7, issue:2, pages: 1 - 9
Publisher: IEEE
 
» A Dynamic Algorithm for Distributed Feedback Control for Manufacturing Production, Capacity, and Maintenance
Abstract:
We propose a dynamic algorithm for distributed feedback control which unifies the functions of production and maintenance scheduling at the shop floor level, and machinery capacity control at the CNC level, which are usually considered in isolation in practice. A continuous-time control theoretic approach is used to model dynamics of these three functions in a unified manner, considering stochastic machine failures and a corresponding maintenance interval. Theories of nonlinear control and discontinuous differential equations are used to analytically predict the system dynamics including the resulting discontinuous dynamics.
Autors: Lee, S.;Prabhu, V.V.;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Apr 2015, volume: 12, issue:2, pages: 628 - 641
Publisher: IEEE
 
» A Fast Hadamard Transform for Signals With Sublinear Sparsity in the Transform Domain
Abstract:
In this paper, we design a new iterative low-complexity algorithm for computing the Walsh-Hadamard transform (WHT) of an N dimensional signal with a K-sparse WHT. We suppose that N is a power of two and K = O(Nα), scales sublinearly in N for some α ∈ (0, 1). Assuming a random support model for the nonzero transform-domain components, our algorithm reconstructs the WHT of the signal with a sample complexity O(K log2(N/K)) and a computational complexity O(K log2(K) log2(N/K)). Moreover, the algorithm succeeds with a high probability approaching 1 for large dimension N. Our approach is mainly based on the subsampling (aliasing) property of the WHT, where by a carefully designed subsampling of the time-domain signal, a suitable aliasing pattern is induced in the transform domain. We treat the resulting aliasing patterns as parity-check constraints and represent them by a bipartite graph. We analyze the properties of the resulting bipartite graphs and borrow ideas from codes defined over sparse bipartite graphs to formulate the recovery of the nonzero spectral values as a peeling decoding algorithm for a specific sparse-graph code transmitted over a binary erasure channel. This enables us to use tools from coding theory (belief-propagation analysis) to characterize the asymptotic performance of our algorithm in the very sparse (α ∈ (0, 1/3]) and the less sparse (α ∈ (1/3, 1)) regime. Comprehensive simulation results are provided to assess the empirical performance of the proposed algorithm.
Autors: Scheibler, R.;Haghighatshoar, S.;Vetterli, M.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Apr 2015, volume: 61, issue:4, pages: 2115 - 2132
Publisher: IEEE
 
» A Five-Parameter Model of the AlGaN/GaN HFET
Abstract:
We introduce an analytic expression for the drain current of an AlGaN/GaN heterojunction field-effect transistor (HFET) as a function of its gate and drain voltages. We derive the function from a compact physical model of conduction current in the HFET. The proposed expression for the current is configured by five parameters, which can be expressed in terms of the geometry and materials of a device. We extend the model to small-signal RF operation by embedding it in a 12-parameter network that represents terminal feed impedances and device parasitics. We adjust the parameters of the extended model to simultaneously fit dc and RF measurements of an industrial transistor.
Autors: Bilbro, G.L.;Trew, R.J.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Apr 2015, volume: 62, issue:4, pages: 1157 - 1162
Publisher: IEEE
 
» A Flexible Charge-Balanced Ratiometric Open-Loop Readout System for Capacitive Inertial Sensors
Abstract:
This brief presents an open-loop readout circuit for capacitive accelerometers. It combines a ratiometric approach with charge balancing for high linearity. The charge balance is implemented with a delta–sigma loop that acts as an analog-to-digital converter for a readout signal. The system avoids the low-signal-tone power levels present in current charge-balanced implementations, making it a flexible readout technique for accelerometers with varying sensitivities and dynamic ranges.
Autors: Amini, S.;Johns, D.A.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2015, volume: 62, issue:4, pages: 317 - 321
Publisher: IEEE
 
» A Four-Leg Matrix Converter Ground Power Unit With Repetitive Voltage Control
Abstract:
In this paper, a four-leg matrix converter is proposed as the power conversion core for aircraft ground power unit (GPU) applications. This structure allows easy management of unbalanced and nonlinear loads with minimal disruption of the power supply operation. A hybrid repetitive-traditional control system is proposed to regulate the output voltage of the GPU. This solution reduces the steady-state tracking error, maintaining fast dynamic characteristics, and increases the stability of the converter compared to conventional approaches. Simulations and experimental results from a 7.5-KW converter prototype are presented to verify the operation of the proposed configuration and to prove the effectiveness of the solution.
Autors: Rohouma, W.;Zanchetta, P.;Wheeler, P.W.;Empringham, L.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Apr 2015, volume: 62, issue:4, pages: 2032 - 2040
Publisher: IEEE
 
» A Fractal Dimension and Wavelet Transform Based Method for Protein Sequence Similarity Analysis
Abstract:
One of the key tasks related to proteins is the similarity comparison of protein sequences in the area of bioinformatics and molecular biology, which helps the prediction and classification of protein structure and function. It is a significant and open issue to find similar proteins from a large scale of protein database efficiently. This paper presents a new distance based protein similarity analysis using a new encoding method of protein sequence which is based on fractal dimension. The protein sequences are first represented into the 1-dimensional feature vectors by their biochemical quantities. A series of Hybrid method involving discrete Wavelet transform, Fractal dimension calculation (HWF) with sliding window are then applied to form the feature vector. At last, through the similarity calculation, we can obtain the distance matrix, by which, the phylogenic tree can be constructed. We apply this approach by analyzing the ND5 (NADH dehydrogenase subunit 5) protein cluster data set. The experimental results show that the proposed model is more accurate than the existing ones such as Su’s model, Zhang’s model, Yao’s model and MEGA software, and it is consistent with some known biological facts.
Autors: Yang, L.;Tang, Y.Y.;Lu, Y.;Luo, H.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Apr 2015, volume: 12, issue:2, pages: 348 - 359
Publisher: IEEE
 
» A Framework for Composing SOAP, Non-SOAP and Non-Web Services
Abstract:
Recently, there is a trend on developing mobile applications based on service-oriented architecture in numerous application domains, such as telematics and smart home. Although efforts have been made on developing composite SOAP services, little emphasis has been put on invoking and composing a combination of SOAP, non-SOAP, and non-web services into a composite process to execute complex tasks on various mobile devices. Main challenges are two-fold: one is how to invoke and compose heterogeneous web services with various protocols and content types, including SOAP, RESTful, and OSGi services; and the other is how to integrate non-web services, like web contents and mobile applications, into a composite service process. In this work, we propose an approach to invoking and composing SOAP, non-SOAP, and non-web services with two key features: an extended BPEL engine bundled with adapters to enable direct invocation and composition of SOAP, RESTful and OSGi services based on Adapter pattern; and two transformation mechanisms devised to enable conversion of web contents and Android activities into OSGi services. In the experimental evaluations, we demonstrate network traffic and turnaround time of our approach are better than those of the traditional ones.
Autors: Lee, J.;Lee, S.-J.;Wang, P.-F.;
Appeared in: IEEE Transactions on Services Computing
Publication date: Apr 2015, volume: 8, issue:2, pages: 240 - 250
Publisher: IEEE
 
» A Framework for the Event-Triggered Stabilization of Nonlinear Systems
Abstract:
Event-triggered control consists of closing the feedback loop whenever a predefined state-dependent criterion is satisfied. This paradigm is especially well suited for embedded systems and networked control systems since it is able to reduce the amount of communication and computation resources needed for control, compared to the traditional periodic implementation. In this paper, we propose a framework for the event-triggered stabilization of nonlinear systems using hybrid systems tools, that is general enough to encompass most of the existing event-triggered control techniques, which we revisit and generalize. We also derive two new event-triggering conditions which may further enlarge the inter-event times compared to the available policies in the literature as illustrated by two physical examples. These novel techniques exemplify the relevance of introducing additional variables for the design of the triggering law. The proposed approach as well as the new event-triggering strategies are flexible and we believe that they can be used to address other event-based control problems.
Autors: Postoyan, R.;Tabuada, P.;Nesic, D.;Anta, A.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Apr 2015, volume: 60, issue:4, pages: 982 - 996
Publisher: IEEE
 
» A Framework of Constructions of Minimal Storage Regenerating Codes With the Optimal Access/Update Property
Abstract:
In this paper, we present a generic framework for constructing systematic minimum storage regenerating codes with two parity nodes based on the invariant subspace technique. Codes constructed in our framework not only contain some best known codes as special cases, but also include some new codes with key properties, such as the optimal access property and the optimal update property. In particular, for a given storage capacity of an individual node, one of the new codes has the largest number of systematic nodes and two of the new codes have the largest number of systematic nodes with the optimal update property.
Autors: Jie Li;Xiaohu Tang;Parampalli, U.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Apr 2015, volume: 61, issue:4, pages: 1920 - 1932
Publisher: IEEE
 
» A Fringe Field Switching Liquid Crystal Display With Fast Grayscale Response Time
Abstract:
A fast-response fringe-field switching (FFS) liquid crystal display using patterned common electrodes is proposed. By applying a restoring pulse voltage on common electrodes, the relaxation process of liquid crystals is expedited by the electric field. The average gray-to-gray decay time is over sevenfold faster compared with the conventional FFS mode.
Autors: Xu, D.;Chen, H.;Wu, S.-T;Li, M.-C.;Lee, S.-L.;Tsai, W.-C.;
Appeared in: Journal of Display Technology
Publication date: Apr 2015, volume: 11, issue:4, pages: 353 - 359
Publisher: IEEE
 
» A Fully Analog High Performances Automatic System for Phase Measurement of Electrical and Optical Signals
Abstract:
In this paper, we present a high performance, automatic fully analog phase-to-voltage converter (PVC) circuit for phase shift measurements of periodic waveforms and repeated pulsed signals with zero and nonzero mean values. The PVC operation is fully automatic because an internal closed feedback loop guarantees the self-phase alignment (self-locking) between the reference and input signals. The system has been tested by measuring the phase shifts between the electrical signals generated by digital waveform generators and by photodiodes. The PVC output voltage dynamic range is ±10 V, independently from the phase-shift full-scales equal to ±10°, ±1°, and ±0.1°. The increase of the PVC sensitivity, expressed in volts/degree, which can be easily set to about 1, 10, and 100 V/°, is achieved without any amplification of the signal so avoiding the increasing and/or introduction of additional electronic noise to the measurements. As a consequence, for the smallest phase-shift full-scale equal to ±0.1°, the proposed PVC circuit is capable to achieve phase resolutions in the order of 0.0001°, a value one order of magnitude better than that one of commercial lock-in amplifiers. In the case of optical applications, the PVC is able to detect laser power variations with sensitivity values settable to about 6, 60, and 600 V/μW so achieving the best resolution of 16 pW.
Autors: De Marcellis, A.;Ferri, G.;Palange, E.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Apr 2015, volume: 64, issue:4, pages: 1043 - 1054
Publisher: IEEE
 
» A Game Theoretic Optimization Framework for Home Demand Management Incorporating Local Energy Resources
Abstract:
Facilitated by advanced information and communication technologies (ICT) infrastructure and optimization techniques, smart grid has the potential to bring significant benefits to the energy consumption management. This paper presents a game theoretic consumption scheduling framework based on the use of mixed integer programming (MIP) to schedule consumption plan for residential consumers. In particular, the optimization framework incorporates integration of locally generated renewable energy in order to minimize dependency on conventional energy and the consumption cost. The game theoretic model is designed to coordinatively manage the scheduling of appliances of consumers. The Nash equilibrium of the game exists and the scheduling optimization converges to an equilibrium where all consumers can benefit from participating in. Simulation results are presented to demonstrate the proposed approach and the benefits of home demand management.
Autors: Zhu, Z.;Lambotharan, S.;Chin, W.H.;Fan, Z.;
Appeared in: IEEE Transactions on Industrial Informatics
Publication date: Apr 2015, volume: 11, issue:2, pages: 353 - 362
Publisher: IEEE
 
» A GaN Pulse Width Modulation Integrated Circuit for GaN Power Converters
Abstract:
We report the first gallium nitride (GaN)-based pulse width modulation (PWM) integrated circuit (IC) featuring monolithically integrated enhancement- and depletion-mode high electron mobility transistors and lateral field-effect rectifiers on the GaN smart power technology platform. The PWM IC is able to generate 1-MHz PWM signal with its duty cycle modulated effectively by a reference voltage ( over a wide range with good linearity. It features a 5 V supply voltage and is composed of a sawtooth generator and a comparator, both of which can be operated at 1 MHz and exhibit proper functionality over a wide temperature range (from 25 °C to 250 °C). This circuit demonstration further proves the feasibility of an all-GaN solution that features monolithically integrated peripheral gate control circuits and power switches for GaN power converters. An all-GaN solution would lead to a compact system with improved efficiency and enhanced reliability.
Autors: Wang, H.;Kwan, A.M.H.;Jiang, Q.;Chen, K.J.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Apr 2015, volume: 62, issue:4, pages: 1143 - 1149
Publisher: IEEE
 
» A Gecko-Inspired Electroadhesive Wall-Climbing Robot
Abstract:
Geckos can climb fast on vertical wall surfaces, whether dry or wet, smooth or rough. The principles of a gecko?s attachment abilities have been studied in detail, and wall-climbing robots based on the biomimetic adhesion of geckos have been proposed. However, the synthetic dry fibrillar adhesive that mimics the gecko?s adhesive footpad is still under development and does not yet achieve as high performances as a gecko. This adhesion method has some disadvantages, such as low payload and sensitivity to surface contaminants involving dust. Many studies have been conducted on the bionic design of robots to simulate a gecko?s motion but using other adhesive mechanisms instead. By combining the gecko?s motion modes and the specific adhesive mechanisms, various novel wall-climbing robots can be envisioned.
Autors: Rui Chen;
Appeared in: IEEE Potentials
Publication date: Apr 2015, volume: 34, issue:2, pages: 15 - 19
Publisher: IEEE
 
» A General Framework for FPGA-Based Real-Time Emulation of Electrical Machines for HIL Applications
Abstract:
Hardware-in-the-loop (HIL) technology is increasingly becoming the preferred, reliable, and cost-effective alternative in a virtual scenario for tedious, time-consuming, and expensive tests on real devices. This paper presents a digital hardware emulation of commonly used electrical machines for HIL simulation on the field-programmable gate arrays (FPGAs) in a general framework. This paper provides a useful and comprehensive comparison between floating- and fixed-point arithmetic for hardware implementation, and addresses the differences of deeply pipelined and highly paralleled realization schemes, and the contribution of schematic and textual programming language methods for design configuration of electrical machine models. The hardware implementation by these approaches is evaluated in terms of real-time step size, accuracy, and hardware resource consumption. Finally, an experimentally measured electrical machine behavior is employed to demonstrate the effectiveness of the emulated electrical machine.
Autors: Roshandel Tavana, N.;Dinavahi, V.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Apr 2015, volume: 62, issue:4, pages: 2041 - 2053
Publisher: IEEE
 
» A general utility optimization framework for energy-harvesting-based wireless communications
Abstract:
In the near future, wireless communication systems are expected to achieve more cost-efficient and sustainable operations by replacing conventional fixed power supplies such as batteries with energy harvesting devices, which could provide electric energy from renewable energy sources (e.g., solar and wind). Such EH power supplies, however, are random and unstable in nature, and as a result impose new challenges on reliable communication design and have triggered substantial research interest in EH-based wireless communications. Building on existing works, in this article, we develop a general optimization framework to maximize the utility of EH wireless communication systems. Our framework encapsulates a variety of design problems, such as throughput maximization and outage probability minimization in single-user and multiuser setups, and provides useful guidelines to the practical design of general EH-based communication systems with different assumptions regarding the knowledge of time-varying wireless channels and EH rates at the transmitters.
Autors: Li, H.;Xu, J.;Zhang, R.;Cui, S.;
Appeared in: IEEE Communications Magazine
Publication date: Apr 2015, volume: 53, issue:4, pages: 79 - 85
Publisher: IEEE
 
» A Generalized Channel Coding Theory for Distributed Communication
Abstract:
This paper presents generalized channel coding theorems for a time-slotted distributed communication system where a transmitter-receiver pair is communicating in parallel with other transmitters. Assume that the channel code of each transmitter is chosen arbitrarily in each time slot. The coding choice of a transmitter is denoted by a code index parameter, which is known neither to other transmitters nor to the receiver. Fundamental performance limitation of the system is characterized using an achievable region defined in the space of the code index vectors. As the codeword length is taken to infinity, for all code index vectors inside the region, the receiver will decode the message reliably, while for all code index vectors outside the region, the receiver will report a collision reliably. A generalized system error performance measure is defined as the weighted sum of probabilities of different types of communication error events. Assume that the receiver chooses an “operation region” and intends to decode the message if the code index vector is inside the operation region. Achievable bounds on the tradeoff between the operation region and the generalized error performance measure are obtained under the assumption of a finite codeword length.
Autors: Luo, J.;
Appeared in: IEEE Transactions on Communications
Publication date: Apr 2015, volume: 63, issue:4, pages: 1043 - 1056
Publisher: IEEE
 
» A Goal-Oriented Error Estimator for Reduced Basis Method Modeling of Microwave Devices
Abstract:
This letter proposes a novel a-posteriori error estimator suitable for the reduced order modeling of microwave circuits. Unlike the existing error estimators based on impedance function residuals, the new one exploits the residual error associated with the computation of the scattering matrix. The estimator can be effectively used in the Reduced Basis Method (RBM) to automatically generate reduced-order models. The results of numerical experiments show that the new error estimator predicts the errors in the computed S-parameters more accurately than the other existing approaches, and that it can be used to automate the generation of wideband reduced models.
Autors: Rewienski, M.;Lamecki, A.;Mrozowski, M.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2015, volume: 25, issue:4, pages: 208 - 210
Publisher: IEEE
 
» A google for DNA
Abstract:
In 2005, next-generation sequencing began to change the field of genetics research. Obtaining a person???s entire genome became fast and relatively cheap. Databases of genetic information were growing by the terabyte, and doctors and researchers were in desperate need of a way to efficiently sift through the information for the cause of a particular disorder or for clues to how patients might respond to treatment.
Autors: Ossola, A.;
Appeared in: IEEE Spectrum
Publication date: Apr 2015, volume: 52, issue:4, pages: 16 - 16
Publisher: IEEE
 
» A GPU Approach to Subtrajectory Clustering Using the Fréchet Distance
Abstract:
Given a trajectory T we study the problem of reporting all subtrajectory clusters of T. To measure similarity between trajectory we choose the Frechet distance. We adapt an existing serial algorithm into a GPU parallel algorithm, resulting in substantial speed-ups, in some cases up to 11× faster, and increasing the size of the data that can be handled in reasonable amount of time, tests were performed on trajectories three times the size as previously managed. This is to the best of our knowledge not only the first GPU implementation of a subtrajectory clustering algorithm but also the first implementation using the continuous Frechet distance, instead of the discrete Frechet distance.
Autors: Gudmundsson, J.;Valladares, N.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Apr 2015, volume: 26, issue:4, pages: 924 - 937
Publisher: IEEE
 
» A Gradient Index Liquid Crystal Microlens Array for Light-Field Camera Applications
Abstract:
We have developed a microlens array (MLA) that utilizes liquid crystal (LC) for switching between light field and normal picturing modes in the camera application. The gradient index (GRIN) profile in an LC layer was obtained by applying the electric field distribution between a pair of molded-and-buried concave and planar electrodes. The concave array was formed by the imprinting method with ultraviolet curing resin. An indium tin oxide layer was deposited on the concave array to make the transparent electrode, which was then buried and flattened with the same resin. The transparency and flatness of the electrodes and resin keep the image quality high without applied voltage in the normal mode, and the electrode in the concave shape causes the LC layer to have a GRIN profile that acts as a MLA when voltage is applied in the light-field mode. The fabricated MLA showed suitable mode-switching operations by applying (for light-field mode) or not applying (for normal mode) a voltage of ±4 V.
Autors: Kwon, H.;Kizu, Y.;Kizaki, Y.;Ito, M.;Kobayashi, M.;Ueno, R.;Suzuki, K.;Funaki, H.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Apr 2015, volume: 27, issue:8, pages: 836 - 839
Publisher: IEEE
 
» A Gridded High-Compression-Ratio Carbon Nanotube Cold Cathode Electron Gun
Abstract:
In order to develop field emission cold cathode radiation source devices, a gridded carbon nanotube (CNT) cold cathode electron gun is theoretically and experimentally investigated in this letter. The planar grid and annular CNT cold cathode are used and optimal parameters of a high-compression-ratio electron gun are obtained by particle in cell simulation software. A 4-mA/10-kV annular electron beam with an average radius of 1.75 mm is achieved based on a permanent magnet in the experiment. The area compression ratio of electron beam is
Autors: Yuan, X.;Zhang, Y.;Yang, H.;Li, X.;Xu, N.;Deng, S.;Yan, Y.;
Appeared in: IEEE Electron Device Letters
Publication date: Apr 2015, volume: 36, issue:4, pages: 399 - 401
Publisher: IEEE
 
» A Heuristic Operation Strategy for Commercial Building Microgrids Containing EVs and PV System
Abstract:
Commercial building microgrids will play an important role in the smart energy city. Stochastic and uncoordinated electric vehicle (EV) charging activities, which may cause performance degradations and overloads, have put great stress on the distribution system. In order to improve the self-consumption of PV energy and reduce the impact on the power grid, a heuristic operation strategy for commercial building microgrids is proposed. The strategy is composed of three parts: the model of EV feasible charging region, the mechanism of dynamical event triggering, and the algorithm of real-time power allocation for EVs. Furthermore, in order to lower the cost of computation resource, the strategy is designed to operate without forecasting on photovoltaic output or EV charging demand. A comprehensive result obtained from simulation tests has shown that the proposed strategy has both satisfactory results and high efficiency, which can be utilized in embedded systems for real-time allocation of EV charging rate.
Autors: Nian Liu;Qifang Chen;Jie Liu;Xinyi Lu;Peng Li;Jinyong Lei;Jianhua Zhang;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Apr 2015, volume: 62, issue:4, pages: 2560 - 2570
Publisher: IEEE
 
» A High Performance Single-Domain LCD With Wide Luminance Distribution
Abstract:
In this paper, we review the device structures and present the simulation results of four single-domain LCDs with a quasi-collimated backlight and a free-form optics-engineered diffuser. Such a non-emissive LCD exhibits similar luminance distribution to an emissive OLED, while keeping high transmittance, high contrast ratio over a large (80 ) viewing cone, with low ambient reflection, indistinguishable color shift, and negligible off-axis grayscale distortion.
Autors: Gao, Y.;Luo, Z.;Zhu, R.;Hong, Q.;Wu, S.-T.;Li, M.-C.;Lee, S.-L.;Tsai, W.-C.;
Appeared in: Journal of Display Technology
Publication date: Apr 2015, volume: 11, issue:4, pages: 315 - 324
Publisher: IEEE
 
» A High-Speed Protection Circuit for IGBTs Subjected to Hard-Switching Faults
Abstract:
This paper describes a high-speed protection circuit for insulated-gate bipolar transistors (IGBTs) subjected to hard-switching faults (HSFs). The reverse transfer capacitance depends on the collector–emitter voltage, and it produces a significant effect on the switching behavior not only under normal conditions but also under HSF conditions. A gate charge characteristic under HSF conditions differs from that under normal turn-on conditions. Hence, an HSF can be detected by monitoring both the gate–emitter voltage and the amount of gate charge during the turn-on transient period. IGBTs can be rapidly protected from destruction by using this method because a blanking time is unnecessary. Simulation and experiment verify the validity of the proposed high-speed protection circuit.
Autors: Horiguchi, T.;Kinouchi, S.;Nakayama, Y.;Oi, T.;Urushibata, H.;Okamoto, S.;Tominaga, S.;Akagi, H.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Apr 2015, volume: 51, issue:2, pages: 1774 - 1781
Publisher: IEEE
 
» A Highly Scalable Single Poly-Silicon Embedded Electrically Erasable Programmable Read Only Memory With Tungsten Control Gate by Full CMOS Process
Abstract:
A highly scalable single poly-silicon multiple time programmable erasable programmable read only memory (EEPROM) with tungsten metallic control gate (W-CG) manufactured by full -CMOS process is successfully demonstrated in this letter. Since the coupling ratio of conventional EEPROM cell is reduced with decreasing cell size, a smaller size in W-CG cell with a reduced spacing of CG to floating gate (FG) can obtain a higher coupling ratio and increase programming/erasing window owing to its novel lateral metal-insulator-poly coupling structure.
Autors: Chung, C.;Chang-Liao, K.;
Appeared in: IEEE Electron Device Letters
Publication date: Apr 2015, volume: 36, issue:4, pages: 336 - 338
Publisher: IEEE
 
» A Hopf Resonator for 2-D Artificial Cochlea: Piecewise Linear Model and Digital Implementation
Abstract:
The mammalian auditory system is able to process sounds over an extraordinarily large dynamic range, which makes it possible to extract information from very small changes both in sound amplitude and frequency. Evidently, response of the cochlea is essentially nonlinear, where it operates within Hopf bifurcation boundaries to maximize tuning and amplification. This paper presents a set of piecewise linear (PWL) and multiplierless piecewise linear (MLPWL1 and MLPWL2) active cochlear models, which mimic a range of behaviors, similar to the biological cochlea. These proposed models show similar dynamical characteristics of the Hopf equation for the active nonlinear artificial cochlea. Accordingly, a compact model structure is proposed upon which a 2-D cochlea is developed. The proposed models are investigated, in terms of their digital realization and hardware cost, targeting large scale implementation. Hardware synthesis and physical implementation on a FPGA show that the proposed models can reproduce precise active cochlea behaviors with higher performance and considerably lower computational costs in comparison with the original model. Results indicate that the MLPWL1 model has a lower computational overhead, precision, and hardware cost, while the PWL model has a higher precision and dynamically tracks the original model. On the other hand, the MLPWL2 model outperforms the others in terms of accuracy, dynamical tracking of the original model and implementation cost. The gain variations of the original, PWL, MLPWL1, and MLPWL2 models are 230, 100, 105, and 230 dB, respectively. The mean normalized root mean square errors (NRMSEs) of the PWL, MLPWL1, and MLPWL2 models are 0.11%, 11.97%, and 0.34%, respectively, as compared to the original cochlear model.
Autors: Nouri, M.;Ahmadi, A.;Alirezaee, S.;Karimi, G.;Ahmadi, M.;Abbott, D.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2015, volume: 62, issue:4, pages: 1117 - 1125
Publisher: IEEE
 
» A hybrid algorithm based on s transform and affinity propagation clustering for separation of two simultaneously artificial partial discharge sources
Abstract:
This paper presents a hybrid algorithm for separation of two simultaneous partial discharge (PD) sources of oil-paper insulation based on S transform (ST) and affinity propagation clustering (APC). Similarities between PD pulses are acquired by comparisons of the corresponding ST-amplitude (STA) matrices, which are input of APC to realize the PD pulses separation and obtain two sub-groups of PD pulses having similar time-frequency characteristics. A classification-based model for separation results validation are developed using a support vector machine with particle swarm optimization (PSO-SVM) classifier and 27 phase-resolved partial discharge (PRPD) statistical features. Artificial defect models are made to simulate two PD sources simultaneously active. Several PD data of different two simultaneous PD sources are acquired in laboratory and adopted for algorithm testing. It is shown that ST computes very fast and is suitable for online PD applications. The separation results of PD data produced in laboratory are verified by the developed validation model, which demonstrate that ST combined with APC can effectively eliminate pulse-shaped noises (PSN) and separate pulses of two simultaneous PD sources. Comparisons with typical separation methods from the state of the art provide better separation performance of the proposed ST combined with APC algorithm for two simultaneous PD sources. The obtained results in this work provide a solid basis for the data mining technique that can be used to facilitate PD diagnosis of transformers.
Autors: Wang, K.;Li, J.;Zhang, S.;Liao, R.;Wu, F.;Yang, L.;Li, J.;Grzybowski, S.;Yan, J.;
Appeared in: IEEE Transactions on Dielectrics and Electrical Insulation
Publication date: Apr 2015, volume: 22, issue:2, pages: 1042 - 1060
Publisher: IEEE
 
» A K-Band Reconfigurable Pulse-Compression Automotive Radar Transmitter in 90-nm CMOS
Abstract:
A K-band ultra-wideband (UWB) pulse-compression (PC) automotive radar transmitter in 90-nm CMOS is presented, which is composed of the fully integrated pulse generator, mixer, driver amplifier, phase-locked loop, and timing circuitry. The PC technique with coding gain can effectively enhance the detection resolution and also improve the signal-to-noise ratio (SNR). We propose a PC transmitter allowing fast and precise code generation with small power consumption and chip area, and also offering reconfigurable capability. Compared with previously reported UWB pulse radars with relatively simple coding schemes, the proposed transmitter features a much more challenging 15-bit pseudonoise code design using high-speed shift registers, which can improve SNR up to 23.5 dB. The measured results demonstrate correct output waveforms corresponding to different modulation codes with the spectrum well confined under the regulation mask. With a modulation rate over 3 Gb/s (pulse repeat frequency of 6.125 MHz), a resolution of can be achieved.
Autors: Tan, K.-W.;Lo, A.-H.;Chu, T.-S.;Hsu, S.S.H.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Apr 2015, volume: 63, issue:4, pages: 1380 - 1387
Publisher: IEEE
 
» A Little Ingenuity Solves an Elephant-Sized Problem
Abstract:
A student team from NC State has designed a collar to help control wild elephants that threaten human property and life in Africa and Asia. The Web extra at https://youtu.be/aQV_BkOL4vA is a video showing how students from North Carolina State University designed a collar to keep elephants away from farms and villages. In this field test in South Africa, a buzzing sound from the collar causes an elephant to turn away from the protected area. Video by Emma Besaw. The second Web extra at http://youtu.be/ap1dSwCc6fY is a video in which editor Greg Byrd introduces the new Student Design Showcase column, dedicated to innovative, interesting student projects from computer science and engineering.
Autors: Byrd, Greg;
Appeared in: Computer
Publication date: Apr 2015, volume: 48, issue:4, pages: 74 - 77
Publisher: IEEE
 
» A Low Phase-Noise Wide Tuning-Range Quadrature Oscillator Using a Transformer-Based Dual-Resonance LC Ring
Abstract:
This paper presents a dual-band quadrature voltage-controlled oscillator (QVCO) using a transformer-based high-order LC-ring resonator, which inherently provides quadrature signals without requiring noisy coupling transistors as in traditional approaches, thereby achieving low phase-noise performance. Moreover, the proposed resonator shows two possible oscillation frequencies, which are exploited to realize a wide-tuning range QVCO employing a mode-switching transistor network. Due to the use of transformers, the oscillator has a minimal area penalty compared to the conventional designs. The implemented prototype in a 65-nm CMOS process achieves a continuous tuning range of 77.8% from 2.75 to 6.25 GHz while consuming from 9.7 to 15.6 mA current from a 0.6-V supply. The measured phase-noise figure-of-merit at 1-MHz offset ranges from 184 to 188.2 dB throughout the entire tuning range. The QVCO also exhibits good quadrature accuracy with 1.5 maximum phase error and occupies a relatively small silicon area of 0.35 .
Autors: Bajestan, M.M.;Rezaei, V.D.;Entesari, K.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Apr 2015, volume: 63, issue:4, pages: 1142 - 1153
Publisher: IEEE
 
» A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory
Abstract:
The continuing miniaturization of complementary metal oxide semiconductor (CMOS) technology has brought in two critical issues—the high power and long global interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents a new design of the key component in processors—multi-bit full adder, whose input and output data are stored in perpendicular magnetic anisotropy (PMA) domain wall (DW) racetrack memory (RTM). The MTJ sharing technique with demultiplexing approach is used in the proposed non-volatile full adder (NVFA) to greatly reduce the area and power, and improve the speed and sensing margin as well. The proposed NVFA scheme can also apply to the other types of non-volatile memory (NVM). Compared to the state-of-art magnetic full adder (MFA), our proposed NVFA has reduced the power and area by 5.9 times and 50%, respectively. It also accelerates the speed by 10% and increases the sensing margin by more than 66%.
Autors: Huang, K.;Zhao, R.;Lian, Y.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2015, volume: 62, issue:4, pages: 1109 - 1116
Publisher: IEEE
 
» A Low-Complexity Embedded Compression Codec Design With Rate Control for High-Definition Video
Abstract:
A hardwired design of embedded compression engine targeting the reduction of full high-definition (HD) video transmission bandwidth over the wireless network is developed. It adopts an intra-coding framework and supports both lossless and rate-controlled near lossless compression options. The lossless compression algorithm is based on a simplified Context-Based, Adaptive, Lossless Image Coding (CALIC) scheme featuring pixelwise gradient-adjusted prediction and error-feedback mechanism. To reduce the implementation complexity, an adaptive Golomb-Rice coding scheme in conjunction with a context modeling technique is used in lieu of an adaptive arithmetic coder. With the measures of prediction adjustment, the near lossless compression option can be implemented on top of the lossless compression engine with minimized overhead. An efficient bit-rate control scheme is also developed and can support rate or distortion-constrained controls. For full HD (previously encoded) and nonfull HD test sequences, the lossless compression ratio of the proposed scheme, on average, is 21% and 46%, respectively, better than the Joint Photographic Experts Group-Lossless Standard and the Fast, Efficient Lossless Image Compression System (FELICS) schemes. The near lossless compression option can offer additional 6%–20% bit-rate reduction while keeping the Peak Signal-to-Noise Ratio value 50 dB or higher. The codec is further optimized complexity-wise to facilitate a high-throughput chip implementation. It features a five-stage pipelined architecture and two parallel computing kernels to enhance the throughput. Fabricated using the Taiwan semiconductor manufacturing company 90-nm complementary metal-oxide–semiconductor technology, the design can operate at 200 MHz and supports a 64 frames/s processing rate for full HD videos.
Autors: Hwang, Y.;Lyu, M.;Lin, C.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Apr 2015, volume: 25, issue:4, pages: 674 - 687
Publisher: IEEE
 
» A Low-Cost and Noninvasive System for the Measurement and Detection of Faulty Streetlights
Abstract:
Badly lit roads lead to vehicle accidents and encourage crime. Therefore, it is important to rapidly detect and report faulty streetlights (FSLs) to the relevant authorities to keep roads safe. Currently, communities primarily depend on electrical inspectors to check streetlights regularly, which may result in long and unnecessary delays prior to repair. Recent studies have focused on adding a networking capability (i.e., a wireless sensor network) into street light poles to enable real-time status reports. However, a smart system that would incorporate sensors and network modules into every streetlight would be expensive; therefore, it would be nearly impossible to realize this system quickly. In this paper, we propose a noninvasive method for detecting faulty lights that involves designing special equipment, called the Hitchhiker, which could be installed on vehicles and would collect information about streetlights' intensity. This system would not require the modification of conventional streetlights. The collected data would be used to create illumination maps (IMaps), the analysis of which could help identify changes in lighting intensity in specific regions. As far as we know, this is an unprecedented approach; no other approaches use IMaps to find FSLs and consider cost and invasiveness. The proposed system could be extended to a citywide scale with minimal cost, and could be used as a complementary system for electrical inspectors possibly identifying FSLs sooner and shortening the duration of poor lighting on streets.
Autors: Huang-Chen Lee;Huang-Bin Huang;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Apr 2015, volume: 64, issue:4, pages: 1019 - 1031
Publisher: IEEE
 

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