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Electrical and Electronics Engineering publications abstract of: 04-2014 sorted by title, page: 0
» "Beer Batter?" [Microwave Bytes Back]
Abstract:
Autors: Jampton, H.;
Appeared in: IEEE Microwave Magazine
Publication date: Apr 2014, volume: 15, issue:2, pages: 128 - 128
Publisher: IEEE
 
» Åsgard Subsea Gas Compression—Technology Qualification Testing With High-Speed VSD and Very Long Step-Out Cable
Abstract:
The power system, including variable-speed drives (VSDs), transformers, and long subsea power cables, is one of the main building blocks in the development of subsea gas compression. This paper presents results from full-scale technology qualification testing of a power system onshore where the VSD is controlling a 188-Hz 7.8-MW gas compressor motor over a simulated distance of 47 km. The extensive testing shows that it is possible to control the compressor/motor speed from start-up throughout the whole load envelope without the need for motor voltage and current feedback. By the use of estimator-based control, it is also possible to provide motor overcurrent protection. This paper shows how resonances in the long cable system can be handled by the use of optimization of the generated voltage waveform instead of using a VSD sine filter. The successful technology qualification shows applicability for subsea compressors with a rated frequency of up to 200 Hz, at least 8-MW shaft power, and a step-out distance of at least 50 km.
Autors: Monsen, B.;Rongve, K.S.;Laegreid, T.;Gutscher, C.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Apr 2014, volume: 50, issue:2, pages: 1552 - 1561
Publisher: IEEE
 
» “No Free Lunch” Theorems Applied to the Calibration of Traffic Simulation Models
Abstract:
In 1997, Wolpert and Macready derived “No free lunch theorems for optimization.” They basically state that “the expected performance of any pair of optimization algorithms across all possible problems is identical.” This is to say that there is no algorithm that outperforms the others over the entire domain of problems. In other words, the choice of the most appropriate algorithm depends upon the specific problem under investigation, and a certain algorithm, while providing good performance (both in terms of solution quality and convergence speed) on certain problems, may reveal weak on certain others. This apparently straightforward concept is not always acknowledged by optimization practitioners. A typical example, in the field of traffic simulation, concerns the calibration of traffic models. In this paper, a general method for verifying the robustness of a calibration procedure (suitable, in general, for any simulation optimization) is proposed based on a test with synthetic data. The main obstacle to this methodology is the significant computation time required by all the necessary simulations. For this reason, a Kriging approximation of the simulation model is proposed instead. The methodology is tested on a specific case study, where the effect on the optimization problem of different combinations of parameters, optimization algorithms, measures of goodness of fit, and levels of noise in the data is also investigated. Results show the clear dependence between the performance of a calibration procedure and the case study under analysis and ascertain the need for global solutions in simulation optimization with traffic models.
Autors: Ciuffo, B.;Punzo, V.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Apr 2014, volume: 15, issue:2, pages: 553 - 562
Publisher: IEEE
 
» 1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing
Abstract:
This work demonstrates the first fabricated 1 Mb nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90 nm CMOS technology and mushroom phase-change memory (PCM) technology. The primary challenge for enabling reliable array operation with such aggressive cell is presented, namely, severely degraded sensing margin due to significantly lower ON/OFF ratio of resistive memories (~10² for PCM) than that of traditional MOSFETs (>10 5 ). To address this challenge, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding and 2) a clocked self-referenced sensing scheme (CSRSS). In addition, the two-bit encoding can also improve algorithmic mapping by effectively compressing TCAM entries. The 1 Mb chip demonstrates reliable low voltage search operation (VDDmin ~750 mV) and a match delay of 1.9 ns under nominal operating conditions.
Autors: Li, J.;Montoye, R.K.;Ishii, M.;Chang, L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 896 - 907
Publisher: IEEE
 
» 1 to 220 GHz Complex Permittivity Behavior of Flexible Polydimethylsiloxane Substrate
Abstract:
Coplanar transmission lines (CPW) are realized on polydimethylsiloxane (PDMS) substrate in order to characterize its complex permittivity, from 1 to 220 GHz. By varying the complex permittivity, the propagation constant of the PDMS-CPW calculated with full wave software is matched to those extracted by de-embedding techniques using S-parameters measurements. The real permittivity evolves from 2.9 to 2.55 while the loss tangent increases slowly to reach 0.048 at 210 GHz.
Autors: Cresson, P.-Y.;Orlic, Y.;Legier, J.-F.;Paleczny, E.;Dubois, L.;Tiercelin, N.;Coquet, P.;Pernod, P.;Lasri, T.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 278 - 280
Publisher: IEEE
 
» 1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS
Abstract:
This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for , . The 0.07–0.39 mV INL, 2–70 DNL, and 66–74 dB of SFDR, enable us to target various formats for 9–12 bit Low-voltage digitizers.
Autors: Aamir, S.A.;Angelov, P.;Wikner, J.J.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Apr 2014, volume: 22, issue:4, pages: 888 - 898
Publisher: IEEE
 
» 1/f noise in semiconductor and metal nanocrystal solids
Abstract:
Electrical 1/f noise is measured in thin films of CdSe, CdSe/CdS, ZnO, HgTe quantum dots and Au nanocrystals. The 1/f noise, normalized per nanoparticle, shows no systematic dependence on the nanoparticle material and the coupling material. However, over 10 orders of magnitude, it correlates well with the nearest neighbor conductance suggesting some universal magnitude of the 1/f noise in these granular conductors. In the hopping regime, the main mechanism of 1/f noise is determined to be mobility fluctuated. In the metallic regime obtained with gold nanoparticle films, the noise drops to a similar level as bulk gold films and with a similar temperature dependence.
Autors: Liu, Heng;Lhuillier, Emmanuel;Guyot-Sionnest, Philippe;
Appeared in: Journal of Applied Physics
Publication date: Apr 2014, volume: 115, issue:15, pages: 154309 - 154309-7
Publisher: IEEE
 
» 14%-efficient flexible CdTe solar cells on ultra-thin glass substrates
Abstract:
Flexible glass enables high-temperature, roll-to-roll processing of superstrate devices with higher photocurrents than flexible polymer foils because of its higher optical transmission. Using flexible glass in our high-temperature CdTe process, we achieved a certified record conversion efficiency of 14.05% for a flexible CdTe solar cell. Little has been reported on the flexibility of CdTe devices, so we investigated the effects of three different static bending conditions on device performance. We observed a consistent trend of increased short-circuit current and fill factor, whereas the open-circuit voltage consistently dropped. The quantum efficiency under the same static bend condition showed no change in the response. After storage in a flexed state for 24 h, there was very little change in device efficiency relative to its unflexed state. This indicates that flexible glass is a suitable replacement for rigid glass substrates, and that CdTe solar cells can tolerate bending without a decrease in device performance.
Autors: Rance, W.L.;Burst, J.M.;Meysing, D.M.;Wolden, C.A.;Reese, M.O.;Gessert, T.A.;Metzger, W.K.;Garner, S.;Cimo, P.;Barnes, T.M.;
Appeared in: Applied Physics Letters
Publication date: Apr 2014, volume: 104, issue:14, pages: 143903 - 143903-4
Publisher: IEEE
 
» 20-Year Tradition of TELSIKS Conferences - TELSIKS 2013 [Chapter News]
Abstract:
Autors: Milovanovic, B.;Marinkovic, Z.;
Appeared in: IEEE Microwave Magazine
Publication date: Apr 2014, volume: 15, issue:2, pages: 104 - 108
Publisher: IEEE
 
» 200 MeV Proton Radiography Studies With a Hand Phantom Using a Prototype Proton CT Scanner
Abstract:
Proton radiography has applications in patient alignment and verification procedures for proton beam radiation therapy. In this paper, we report an experiment which used 200 MeV protons to generate proton energy-loss and scattering radiographs of a hand phantom. The experiment used the first-generation proton computed tomography (CT) scanner prototype, which was installed on the research beam line of the clinical proton synchrotron at Loma Linda University Medical Center. It was found that while both radiographs displayed anatomical details of the hand phantom, the energy-loss radiograph had a noticeably higher resolution. Nonetheless, scattering radiography may yield more contrast between soft and bone tissue than energy-loss radiography, however, this requires further study. This study contributes to the optimization of the performance of the next-generation of clinical proton CT scanners. Furthermore, it demonstrates the potential of proton imaging (proton radiography and CT), which is now within reach of becoming available as a new, potentially low-dose medical imaging modality.
Autors: Plautz, T.;Bashkirov, V.;Feng, V.;Hurley, F.;Johnson, R.P.;Leary, C.;Macafee, S.;Plumb, A.;Rykalin, V.;Sadrozinski, H.F.-W.;Schubert, K.;Schulte, R.;Schultze, B.;Steinberg, D.;Witt, M.;Zatserklyaniy, A.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Apr 2014, volume: 33, issue:4, pages: 875 - 881
Publisher: IEEE
 
» 28-GBd 32QAM FMF Transmission With Low Complexity Phase Estimators and Single DPLL
Abstract:
As spatial division multiplexed transmission systems employing few mode fibers (FMFs) rely heavily on digital signal processing (DSP), the impact of computational complexity should be considered. A key DSP process block is the carrier phase estimation (CPE), which consists of a phase estimator and digital phase locked loop (DPLL) per output. In this letter, a low complexity phase estimator is proposed, and the common-mode laser frequency offset is exploited to reduce the number of DPLLs. The combination of a low complexity CPE and single DPLL is experimentally demonstrated for a 28 GBd six-channel transmission over a 41.7-km FMF, carrying up to 32 quadrature amplitude modulation. Thereby, the nonlinear tolerances for the proposed CPE scheme are shown to perform similarly as the more computationally complex conventional CPE scheme.
Autors: van Uden, R.G.H.;Okonkwo, C.M.;Chen, H.;de Waardt, H.;Koonen, A.M.J.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Apr 2014, volume: 26, issue:8, pages: 765 - 768
Publisher: IEEE
 
» 3 dB 90 Hybrid Quasi-Optical Coupler With Air Field Slab in SIW Technology
Abstract:
This letter presents a new class of small-size and high performance directional coupler based on substrate integrated waveguide (SIW) technology. This type of coupler is composed of a waveguide section of four arms connected by a central junction. Quasi-optical coupler technique is realized on standard waveguide by simply inserting a slab with different permittivity in central section to act as a mirror. To make this coupler realizable in the SIW format, the air slab is simply implemented by rectangular through-hole. Characteristics of the proposed coupler with respect to various parameters are presented and discussed. A prototype at 10 GHz is designed, fabricated and measured. Experimental results show that the proposed SIW cruciform coupler has a bandwidth of more than 15% over the operating frequency range.
Autors: Djerafi, T.;Wu, K.;Tatu, S.O.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 221 - 223
Publisher: IEEE
 
» 3 dB 90 Hybrid Quasi-Optical Coupler With Air Field Slab in SIW Technology
Abstract:
This letter presents a new class of small-size and high performance directional coupler based on substrate integrated waveguide (SIW) technology. This type of coupler is composed of a waveguide section of four arms connected by a central junction. Quasi-optical coupler technique is realized on standard waveguide by simply inserting a slab with different permittivity in central section to act as a mirror. To make this coupler realizable in the SIW format, the air slab is simply implemented by rectangular through-hole. Characteristics of the proposed coupler with respect to various parameters are presented and discussed. A prototype at 10 GHz is designed, fabricated and measured. Experimental results show that the proposed SIW cruciform coupler has a bandwidth of more than 15% over the operating frequency range.
Autors: Djerafi, T.;Wu, K.;Tatu, S.O.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 221 - 223
Publisher: IEEE
 
» 32 Bit 32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler
Abstract:
In this paper, we present a multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. Given the user's requirements (e.g., throughput), a dynamic voltage/frequency scaling management unit configures the multiplier to operate at the proper precision and frequency. Adapting to the run-time workload of the targeted application, razor flip-flops together with a dithering voltage unit then configure the multiplier to achieve the lowest power consumption. The single-switch dithering voltage unit and razor flip-flops help to reduce the voltage safety margins and overhead typically associated to DVS to the lowest level. The large silicon area and power overhead typically associated to reconfigurability features are removed. Finally, the proposed novel MP multiplier can further benefit from an operands scheduler that rearranges the input data, hence to determine the optimum voltage and frequency operating conditions for minimum power consumption. This low-power MP multiplier is fabricated in AMIS 0.35- technology. Experimental results show that the proposed MP design features a 28.2% and 15.8% reduction in circuit area and power consumption compared with conventional fixed-width multiplier. When combining this MP design with error-tolerant razor-based DVS, PP, and the proposed novel operands scheduler, 77.7%–86.3% total power reduction is achieved with a total silicon area overhead as low as 11.1%. This paper successfully demonstrates that a MP architecture can allow more aggressive frequency/suppl- voltage scaling for improved power efficiency.
Autors: Zhang, X.;Boussaid, F.;Bermak, A.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Apr 2014, volume: 22, issue:4, pages: 759 - 770
Publisher: IEEE
 
» 32 Bit 32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler
Abstract:
In this paper, we present a multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. Given the user's requirements (e.g., throughput), a dynamic voltage/frequency scaling management unit configures the multiplier to operate at the proper precision and frequency. Adapting to the run-time workload of the targeted application, razor flip-flops together with a dithering voltage unit then configure the multiplier to achieve the lowest power consumption. The single-switch dithering voltage unit and razor flip-flops help to reduce the voltage safety margins and overhead typically associated to DVS to the lowest level. The large silicon area and power overhead typically associated to reconfigurability features are removed. Finally, the proposed novel MP multiplier can further benefit from an operands scheduler that rearranges the input data, hence to determine the optimum voltage and frequency operating conditions for minimum power consumption. This low-power MP multiplier is fabricated in AMIS 0.35- μm technology. Experimental results show that the proposed MP design features a 28.2% and 15.8% reduction in circuit area and power consumption compared with conventional fixed-width multiplier. When combining this MP design with error-tolerant razor-based DVS, PP, and the proposed novel operands scheduler, 77.7%-86.3% total power reduction is achieved with a total silicon area overhead as low as 11.1%. This paper successfully demonstrates that a MP architecture can allow more aggressive frequency/supply voltage scaling for improved power efficiency.
Autors: Xiaoxiao Zhang;Boussaid, F.;Bermak, A.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Apr 2014, volume: 22, issue:4, pages: 759 - 770
Publisher: IEEE
 
» 3D Magnetic Field Sensor Concept for Use in Inertial Measurement Units (IMUs)
Abstract:
We report on the design, fabrication, and characterization of a microfabricated 3D magnetic field sensor that is suitable for co-integration with inertial sensors to form single-chip inertial measurement units. In contrast to classical resonant MEMS magnetometers, which are based on Lorentz force measurement, our sensor uses permanent magnetic materials and piezoresistive detection with silicon strain gauges of nanometric section, leading to low power consumption and high sensitivity for small sensor size. Thin multilayers of CoFe and PtMn as ferro- and antiferromagnetic materials are integrated within the MEMS fabrication process. Sensitivities of 1.09 V/T for - and - components of the magnetic field and 0.124 V/T for - component of the magnetic field were measured, respectively. To be sensitive to magnetic fields along all three spatial directions, two permanent magnetization directions on the same die are required. Implementation of the two magnetization directions was validated by a measured correlation of 99.7% between - and - sensitivity axes. Power consumption of the 3D sensor is for polarization with a 100 dc current. With resolutions of 100 for - and -component of the magnetic field and 350 - tex Notation="TeX">${rm nT}/surd{rm Hz}$ for - component, the sensor is suitable for precise measurement of earth magnetic field.
Autors: Ettelt, D.;Rey, P.;Jourdan, G.;Walther, A.;Robert, P.;Delamare, J.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Apr 2014, volume: 23, issue:2, pages: 324 - 333
Publisher: IEEE
 
» 5 Earth-imaging start-ups coming to a sky near you [News]
Abstract:
Words like "provocative" and "disruptive" are rarely applied to the staid world of satellite imaging. But that's exactly the kind of talk the industry is generating, with the launches of more than two dozen Earth-imaging satellites in the last few months and more planned by year's end.
Autors: Kumagai, J.;
Appeared in: IEEE Spectrum
Publication date: Apr 2014, volume: 51, issue:4, pages: 20 - 21
Publisher: IEEE
 
» 50 GHz mm-Wave CMOS Active Inductor
Abstract:
This letter presents a millimeter-wave active inductor circuit designed and fabricated in 65 nm bulk CMOS technology. The measurement results show an equivalent inductance of 133 pH with a quality factor exceeding 400 at 50 GHz, demonstrating experimentally for the first time the possibility to implement high- active inductors in CMOS technology operating at the mm-waves.
Autors: Pepe, D.;Zito, D.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 254 - 256
Publisher: IEEE
 
» 5G service on your 4G phone? [News]
Abstract:
"This is going to change everything," said Steve Perlman in a New York City hotel room in February, two days before revealing that his new start??up, Artemis Networks, plans to commercialize its pCell wireless technology. "We can deliver in 2014 all the goals of 5G on 4G phones," he said, including more network capacity and faster, more reliable connections.
Autors: Bleicher, A.;
Appeared in: IEEE Spectrum
Publication date: Apr 2014, volume: 51, issue:4, pages: 13 - 18
Publisher: IEEE
 
» 600 V-18 A GaN Power MOS-HEMTs on 150 mm Si Substrates With Au-Free Electrodes
Abstract:
We present the development of an Au-free ohmic contact metallization for high voltage GaN-based high electron mobility transistors (HEMTs). In this letter, low contact resistance (0.81 ) is obtained for Au-free electrodes on AlGaN/GaN HEMT structures. Using Au-free ohmic processes, large scale high power GaN metal–oxide–semiconductor HEMTs were successfully fabricated in a procedure fully compatible with standard Si CMOS manufacturing with the maximum drain current of more than 18 A and low OFF-state leakage current of at of 600 V. The practicality of the devices was further demonstrated by measurements of the current collapse effects under severe operating conditions and the temperature dependence of the electrical characteristics.
Autors: Seo, D.W.;Choi, H.G.;Twynam, J.;Kim, K.M.;Yim, J.S.;Moon, S.-W.;Jung, S.;Lee, J.;Roh, S.D.;
Appeared in: IEEE Electron Device Letters
Publication date: Apr 2014, volume: 35, issue:4, pages: 446 - 448
Publisher: IEEE
 
» 911 for the 21st Century
Abstract:
No matter how smart your phone may be, your Mayday call likely relies on an ancient 2400- baud modem to tell emergency responders what they most need to know??your location. And as phone technology advances, the problem is getting worse. · An elementary school in Illinois found this out the hard way when a school official called 911 to report that two kindergartners had wandered off. The call went to an emergency communications center in Canada, delaying the response by several minutes. The children were eventually found, but the delay could have made a deadly difference in other circumstances. · Engineers have installed a patchwork of updates to try to keep pace with calling technology, but they've reached their limit. It's time to rebuild the system from the ground up–and that's exactly what's happening in the United States and in many other places around the world.
Autors: Barnes, R.;Rosen, B.;
Appeared in: IEEE Spectrum
Publication date: Apr 2014, volume: 51, issue:4, pages: 58 - 64
Publisher: IEEE
 
» Consonant Approximations of Belief Functions
Abstract:
In this paper, we solve the problem of approximating a belief measure with a necessity measure or “consonant belief function” in a geometric framework. Consonant belief functions form a simplicial complex in both the space of all belief functions and the space of all mass vectors: Partial approximations are first sought in each component of the complex, while global solutions are selected among them. As a first step in this line of study, we seek here approximations that minimize Lp norms. Approximations in the mass space can be interpreted in terms of mass redistribution, while approximations in the belief space generalize the maximal outer consonant approximation. We compare them with each other and with other classical approximations and illustrate them with the help of a running example.
Autors: Cuzzolin, F.;
Appeared in: IEEE Transactions on Fuzzy Systems
Publication date: Apr 2014, volume: 22, issue:2, pages: 420 - 436
Publisher: IEEE
 
» : Ensemble Extreme Learning Machines for Hyperspectral Image Classification
Abstract:
Extreme learning machine (ELM) has attracted attentions in pattern recognition field due to its remarkable advantages such as fast operation, straightforward solution, and strong generalization. However, the performance of ELM for high-dimensional data, such as hyperspectral image, is still an open problem. Therefore, in this paper, we introduce ELM for hyperspectral image classification. Furthermore, in order to overcome the drawbacks of ELM caused by the randomness of input weights and bias, two new algorithms of ensemble extreme learning machines (Bagging-based and AdaBoost-based ELMs) are proposed for the classification task. In order to illustrate the performance of the proposed algorithms, support vector machines (SVMs) are used for evaluation and comparison. Experimental results with real hyperspectral images collected by reflective optics spectrographic image system (ROSIS) and airborne visible/infrared imaging spectrometer (AVIRIS) indicate that the proposed ensemble algorithms produce excellent classification performance in different scenarios with respect to spectral and spectral–spatial feature sets.
Autors: Samat, A.;Du, P.;Liu, S.;Li, J.;Cheng, L.;
Appeared in: IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing
Publication date: Apr 2014, volume: 7, issue:4, pages: 1060 - 1069
Publisher: IEEE
 
» Filter Design and Performance Analysis for Grid-Interconnected Systems
Abstract:
The use of power converters is very important in maximizing the power transfer from renewable energy sources such as wind, solar, or even a hydrogen-based fuel cell to the utility grid. An filter is often used to interconnect an inverter to the utility grid in order to filter the harmonics produced by the inverter. Although there is an extensive amount of literature available describing filters, there has been a gap in providing a systematic design methodology. Furthermore, there has been a lack of a state-space mathematical modeling approach that considers practical cases of delta- and wye-connected capacitors showing their effects on possible grounding alternatives. This paper describes a design methodology of an filter for grid-interconnected inverters along with a comprehensive study of how to mitigate harmonics. The procedures and techniques described in this paper may be used in small-scale renewable energy conversion systems and may be also retrofitted for medium- and large-scale grid-connected systems.
Autors: Reznik, A.;Simoes, M.G.;Al-Durra, A.;Muyeen, S.M.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Apr 2014, volume: 50, issue:2, pages: 1225 - 1232
Publisher: IEEE
 
» Filter Design and Performance Analysis for Grid-Interconnected Systems
Abstract:
The use of power converters is very important in maximizing the power transfer from renewable energy sources such as wind, solar, or even a hydrogen-based fuel cell to the utility grid. An LCL filter is often used to interconnect an inverter to the utility grid in order to filter the harmonics produced by the inverter. Although there is an extensive amount of literature available describing LCL filters, there has been a gap in providing a systematic design methodology. Furthermore, there has been a lack of a state-space mathematical modeling approach that considers practical cases of delta- and wye-connected capacitors showing their effects on possible grounding alternatives. This paper describes a design methodology of an LCL filter for grid-interconnected inverters along with a comprehensive study of how to mitigate harmonics. The procedures and techniques described in this paper may be used in small-scale renewable energy conversion systems and may be also retrofitted for medium- and large-scale grid-connected systems.
Autors: Reznik, A.;Simoes, M.G.;Al-Durra, A.;Muyeen, S.M.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Apr 2014, volume: 50, issue:2, pages: 1225 - 1232
Publisher: IEEE
 
» Consonant Approximations of Belief Functions
Abstract:
In this paper, we solve the problem of approximating a belief measure with a necessity measure or “consonant belief function” in a geometric framework. Consonant belief functions form a simplicial complex in both the space of all belief functions and the space of all mass vectors: Partial approximations are first sought in each component of the complex, while global solutions are selected among them. As a first step in this line of study, we seek here approximations that minimize norms. Approximations in the mass space can be interpreted in terms of mass redistribution, while approximations in the belief space generalize the maximal outer consonant approximation. We compare them with each other and with other classical approximations and illustrate them with the help of a running example.
Autors: Cuzzolin, F.;
Appeared in: IEEE Transactions on Fuzzy Systems
Publication date: Apr 2014, volume: 22, issue:2, pages: 420 - 436
Publisher: IEEE
 
» A –90 dBm Sensitivity Wireless Transceiver Using VCO-PA-LNA-Switch-Modulator Co-Design for Low Power Insect-Based Wireless Sensor Networks
Abstract:
This paper presents a wireless transceiver intended for insect-based wireless sensor networks (WSNs). The transceiver utilizes several design techniques developed to meet the challenging low power and low size requirements in insect-based WSNs. The techniques include current reuse in the voltage-controlled oscillator (VCO) and power amplifier (PA), fast PLL on/off switching for low-power on/off keying (OOK) modulation, and switching between transmit and receive (TX/RX) modes without an off-chip switch. Also, the VCO, PA, low noise amplifier (LNA), OOK modulator, and TX/RX switch are co-designed and integrated into a single block to reduce the system complexity significantly. The transceiver is designed and fabricated in a 0.13-µm CMOS process. The transmitter provides an output power in the range of –30 dBm to –4.4 dBm while consuming an average power of 1.2 mW to 4.5 mW. The phase locked-loop (PLL) does not use a high-Q external resonator, and its phase noise depends on the PA output power because of the current reuse in the VCO and PA. The PLL phase noise at 1 MHz offset at 2.4 GHz varies from –103.3 dBc/Hz to –116.7 dBc/Hz. The receiver achieves a sensitivity of –90 dBm at 1 Mbps data rate for a BER = 0.1%. An example wireless sensor node design utilizing the proposed wireless transceiver achieves a modest weight of 1 gram, and a small form factor of 12.5 mm × 12.5 mm.
Autors: Sayilir, S.;Loke, W.-F.;Lee, J.;Diamond, H.;Epstein, B.;Rhodes, D.L.;Jung, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 996 - 1006
Publisher: IEEE
 
» A – -dBm Dual-Channel UHF Passive CMOS RFID Tag Design
Abstract:
Previous research results showed that UHF passive CMOS RFID tags had difficulty to achieve sensitivity less than -20 dBm. This paper presents a dual-channel 15-bit UHF passive CMOS RFID tag prototype that can work at sensitivity lower than -20 dBm. The proposed tag chip harvests energy and backscatters uplink data at 866.4-MHz (for ETSI) or 925-MHz (for FCC) channel and receives downlink data at 433-MHz channel. Consequently, the downlink data transmission does not interrupt our tag from harvesting RF energy. To use the harvested energy efficiently, we design a tag chip that includes neither a regulator nor a VCO such that the harvested energy is completely used in receiving, processing, and backscattering data. Without a regulator, our tag uses as few active analog circuits as possible in the receiver front-end. Instead, our tag uses a novel digital circuit to decode the received data. Without a VCO, the design of our tag can extract the required clock signal from the downlink data. Measurement result shows that the sensitivity of the proposed passive tag chip can reach down to -21.2 dBm. Such result corresponds to a 19.6-m reader-to-tag distance under 36-dBm EIRP and 0.4-dBi tag antenna gain. The chip was fabricated in TSMC 0.18- μm CMOS process. The die area is 0.958 mm ×0.931mm.
Autors: Chia-Yu Yao;Wei-Chun Hsia;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2014, volume: 61, issue:4, pages: 1269 - 1279
Publisher: IEEE
 
» A – -dBm Dual-Channel UHF Passive CMOS RFID Tag Design
Abstract:
Pub DtlPrevious research results showed that UHF passive CMOS RFID tags had difficulty to achieve sensitivity less than . This paper presents a dual-channel 15-bit UHF passive CMOS RFID tag prototype that can work at sensitivity lower than . The proposed tag chip harvests energy and backscatters uplink data at 866.4-MHz (for ETSI) or 925-MHz (for FCC) channel and receives downlink data at 433-MHz channel. Consequently, the downlink data transmission does not interrupt our tag from harvesting RF energy. To use the harvested energy efficiently, we design a tag chip that includes neither a regulator nor a VCO such that the harvested energy is completely used in receiving, processing, and backscattering data. Without a regulator, our tag uses as few active analog circuits as possible in the receiver front-end. Instead, our tag uses a novel digital circuit to decode the received data. Without a VCO, the design of our tag can extract the required clock signal from the downlink data. Measurement result shows that the sensitivity of the proposed passive tag chip can reach down to . Such result corresponds to a 19.6-m reader-to-tag distance under 36-dBm EIRP and 0.4-dBi tag antenna gain. The chip was fabricated in TSMC 0.18- CMOS process. The die area is 0.958 mm .
Autors: Yao, C.-Y.;Hsia, W.-C.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2014, volume: 61, issue:4, pages: 1269 - 1279
Publisher: IEEE
 
» A 0.45–1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS
Abstract:
A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM capacitor, distributed across a 14 KB register file (RF) load is demonstrated in 22 nm tri-gate CMOS. The multi-conversion-ratio SCVR provides a wide output voltage range of 0.45–1 V from a fixed input voltage of 1.225 V. It achieves 63–84% conversion efficiency and supports a maximum load current density of 0.88 A/mm 2 . The area overhead of the dedicated SCVR on the load is 3.6%. Measured data is presented on various performance indices in detail. Subsequent learning on tradeoffs between various factors like capacitance characteristics, conversion efficiency and current density are delineated and, correlated with theoretical estimates. Performance of RF array shows comparable results when powered with the SCVR and the external rail. The all-digital, modular design allows efficient spatial distribution across the load and hence robust power delivery. The extremely fast response times in the order of few nanoseconds is targeted to benefit agile power management. This work evinces voltage regulator technology as a standard homogenous CMOS component, which can proliferate DVFS domains for maximum energy and area benefits.
Autors: Jain, R.;Geuskens, B.M.;Kim, S.;Khellah, M.;Kulkarni, J.;Tschanz, J.W.;De, V.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 917 - 927
Publisher: IEEE
 
» A 0.6–107 µW Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG
Abstract:
Pub DtlCompressive sensing has been used to overcome communication constraints (energy and bandwidth) in low-power sensors. In this work, we present a seizure-detection processor that directly uses compressively-sensed electroencephalograms (EEGs) for embedded signal analysis. In addition to addressing communication, this has two advantages for local computation. First, with compressive sensing, reconstruction costs are typically severe, precluding embedded analysis; directly analyzing the compressed signals circumvents reconstruction costs, enabling embedded analysis within applications. Second, compared to Nyquist-sampled signals, the use of compressed representations reduces the computational energy of signal analysis due to the reduced number of signal samples. We describe an algorithmic formulation as well as a hardware architecture that enables two strong power-management knobs, wherein application-level performance can scale with computational energy. The two knobs are parameterized as follows: 1) ξ, which quantifies the amount of data compression, and 2) ν, which determines the approximation error within the proposed compressed-domain processing algorithm. For ξ and ν in the range 2-24×, the energy to extract signal features (over 18 channels) is 70.8-1.3 nJ, and the detector's performance for sensitivity, latency, and specificity is 96-91%, 4.7-5.3 sec., and 0.17-0.30 false-alarms/hr., respectively (compared to a baseline performance of 96%, 4.6 sec., and 0.15 false-alarms/hr.).
Autors: Shoaib, M.;Lee, K.H.;Jha, N.K.;Verma, N.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2014, volume: 61, issue:4, pages: 1105 - 1118
Publisher: IEEE
 
» A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application
Abstract:
A 1 Tbit/s bandwidth PHY is demonstrated through CoWoS™ platform. Two chips: SOC and embedded DRAM (eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/s with VDDQ = 0.3 V are proven between SOC chip and eDRAM chip in experimental results with 1 mm signal trace length on the silicon interposer. A novel timing compensation mechanism is presented to achieve a low-power and small area eDRAM PHY that excludes PLL/DLL but retains good timing margin. Another data sampling alignment training approach is employed to enhance timing robustness. A compact low-swing IO also achieves power efficiency of 0.105 mW/Gbps.
Autors: Lin, M.-S.;Tsai, C.-C.;Chang, C.-H.;Huang, W.-H.;Hsu, Y.-Y.;Yang, S.-C.;Fu, C.-M.;Chou, M.-H.;Huang, T.-C.;Chen, C.-F.;Huang, T.-C.;Adham, S.;Wang, M.-J.;Shen, W.W.;Mehta, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 1063 - 1074
Publisher: IEEE
 
» A 1.59 Gpixel/s Motion Estimation Processor With 211 to +211 Search Range for UHDTV Video Encoder
Abstract:
3840 × 2160 and 7680 × 4320 UHDTV formats deliver remarkably enhanced visual experience relative to high definition but in the meanwhile involve huge complexity and memory bandwidth requirements in video encoding. Especially, enlarged motion distances of UHDTV lead to additional difficulties in the implementation of motion estimation, which is originally the most critical bottleneck of an encoder. This paper presents a motion estimation processor design for H.264/AVC. A test chip is implemented in 40 nm CMOS. With algorithm and architecture co-optimization, the processor delivers a maximum throughput of 1.59 Gpixel/s for 7680 × 4320 48 fps video, at least 7.5 times faster than previous designs. The corresponding core power dissipation is 622 mW at 210 MHz, with energy efficiency improved by at least 23%. The chip's DRAM bandwidth requirement is also 68% lower than previous chips. With a maximum search range of ±211 (horizontal) by ±106 (vertical) around a predictive search center, the proposed motion estimation processor well accommodates the high motion of UHDTV.
Autors: Dajiang Zhou;Jinjia Zhou;Gang He;Goto, S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 827 - 837
Publisher: IEEE
 
» A 10-Bit 800-MHz 19-mW CMOS ADC
Abstract:
A pipelined ADC employs charge-steering op amps to relax the trade-offs among speed, noise, and power consumption. Such op amps afford a fourfold increase in speed and a twofold reduction in noise for a given power consumption and voltage gain. Applying full-rate nonlinearity and gain error calibration, a prototype realized in 65-nm CMOS technology exhibits a Nyquist SNDR of 52.2 dB and draws 19 mW at 800 MHz. The ADC also demonstrates a new histogram-based background calibration technique.
Autors: Chiang, S.-H.W.;Sun, H.;Razavi, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 935 - 949
Publisher: IEEE
 
» A 10-Gb/s, 107-mW Double-Edge Pulsewidth Modulation Transceiver
Abstract:
Pub DtlA 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation to overcome frequency-dependent losses in electrical interconnects. Time domain modulation is discussed as a means to enhance the spectral efficiency in channels with sharp frequency roll-off similar to multilevel voltage-domain modulation such as 4-PAM. The transmitter and receiver are high-speed programmable digital-to-time and time-to-digital converters that adapt to channel bandwidth characteristics with a timing resolution of 40 ps. This paper presents a low-jitter, phase rotation architecture for cycle-to-cycle transmit pulsewidth control. The transceiver includes an elastic buffer to move data between synchronous and plesiochronous clock domains and is implemented in 45-nm CMOS SOI. Transmitter and receiver functionality is demonstrated to 10 Gb/s at a BER of under and is compared against NRZ schemes at the same rate. The inductor-less transmitter and receiver active circuitry respectively occupy an area of 93 94 and 218 160 m , and consume a total 107 mW from a 1.2 V supply.
Autors: Wang, W.;Buckwalter, J.F.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2014, volume: 61, issue:4, pages: 1068 - 1080
Publisher: IEEE
 
» A 100 fps, Time-Correlated Single-Photon-Counting-Based Fluorescence-Lifetime Imager in 130 nm CMOS
Abstract:
A fully-integrated single-photon avalanche diode (SPAD) and time-to-digital converter (TDC) array for high-speed fluorescence lifetime imaging microscopy (FLIM) in standard 130 nm CMOS is presented. This imager is comprised of an array of 64-by-64 SPADs each with an independent TDC for performing time-correlated single-photon counting (TCSPC) at each pixel. The TDCs use a delay-locked-loop-based architecture and achieve a 62.5 ps resolution with up to a 64 ns range. A data-compression datapath is designed to transfer TDC data to off-chip buffers, which can support a data rate of up to 42 Gbps. These features, combined with a system implementation that leverages a x4 PCIe-cabled interface, allow for demonstrated FLIM imaging rates at up to 100 frames per second.
Autors: Field, R.M.;Realov, S.;Shepard, K.L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 867 - 880
Publisher: IEEE
 
» A 16-Core Processor With Shared-Memory and Message-Passing Communications
Abstract:
A 16-core processor with both message-passing and shared-memory inter-core communication mechanisms is implemented in 65 nm CMOS. Message-passing communication is enabled in a 3 6 Mesh packet-switched network-on-chip, and shared-memory communication is supported using the shared memory within each cluster. The processor occupies 9.1 and operates fully functional at a clock rate of 750 MHz at 1.2 V and maximum 800 MHz at 1.3 V. Each core dissipates 34 mW under typical conditions at 750 MHz and 1.2 V while executing embedded applications such as an LDPC decoder, a 3780-point FFT module, an H.264 decoder and an LTE channel estimator.
Autors: Yu, Z.;Xiao, R.;You, K.;Quan, H.;Ou, P.;Yu, Z.;He, M.;Zhang, J.;Ying, Y.;Yang, H.;Han, J.;Cheng, X.;Zhang, Z.;Jing, M.;Zeng, X.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2014, volume: 61, issue:4, pages: 1081 - 1094
Publisher: IEEE
 
» A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS
Abstract:
This paper presents a 160 GHz center frequency pulsed 65 nm CMOS transceiver for short range radar applications. Four phased array transceivers were implemented in a single chip with antennas implemented in a BGA package. The implemented transmitter is capable of producing pulses of 100 ps widths ( 20 GHz RF bandwidth) at a 160 GHz carrier frequency. The measured effective isotropic radiated power (EIRP) is 18.8 dBm for continuous wave outputs. The analog beam forming receiver achieves an overall gain of 42.5 dB, 14 dBm , 7 GHz bandwidth, and a noise figure of 22.5 dB. The sliding window time-dilation baseband relaxes the output data rate and subsequent digital processing requirements. Fine grained duty cycling reduces power dissipation. The entire chip consumes 2.2 W from 1.2/1.4 V supplies in a 65 nm digital CMOS process.
Autors: Ginsburg, B.P.;Ramaswamy, S.M.;Rentala, V.;Seok, E.;Sankaran, S.;Haroun, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 984 - 995
Publisher: IEEE
 
» A 2 dB NF Receiver With 10 mA Battery Current Suitable for Coexistence Applications
Abstract:
A receiver architecture suitable for coexistence applications is presented. The receiver features an auxiliary path to deflect blockers away from the main receiver without disturbing the desired received signal. The sub-2-dB noise-figure (NF) receiver addresses the coexistence blocking issues without compromising the performance, achieving comparable NF and blocker tolerance to the state-of-the-art. Implemented in 40 nm CMOS, the entire receiver including the VCO and synthesizer drains 10 mA of battery current.
Autors: Mirzaei, A.;Mikhemar, M.;Murphy, D.;Darabi, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 972 - 983
Publisher: IEEE
 
» A 2.14-GHz GaN MMIC Doherty Power Amplifier for Small-Cell Base Stations
Abstract:
A novel 2.14-GHz Doherty power amplifier (PA) was designed and fabricated using a 0.25- m GaN on SiC monolithic microwave integrated circuit (MMIC), to build small-cell base stations. To reduce the size and loss, lumped passive elements were employed in a manner of minimizing the device count. The core components of the PA were integrated on the MMIC die to reduce the area, and low-loss chip inductors were mounted around the die to enhance the efficiency. An unconventional uneven power splitting was also used to enhance the performance. For a continuous wave, a 2-dB-gain-compression power of 40.5 dBm was obtained with a drain efficiency (DE) of 60.4%. At 7.3-dB backed-off power, a DE of 52.2% was obtained with a power gain of 15.7 dB. When a 10-MHz-bandwidth long-term evolution signal with 7.1-dB peak-to-average power ratio was applied, an adjacent channel leakage ratio (ACLR) of dBc with a DE of 51.8% was achieved at an average power of 33.2 dBm. After a digital pre-distortion process, the ACLR and DE were improved to dBc and 52.7%, respectively.
Autors: Kim, C.H.;Jee, S.;Jo, G.-D.;Lee, K.;Kim, B.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 263 - 265
Publisher: IEEE
 
» A 28 GHz Hybrid PLL in 32 nm SOI CMOS
Abstract:
A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. In addition to the analog proportional path, the PLL includes a set of digital proportional path controls, so that the two approaches can be experimentally compared. At 28 GHz the RMS jitter is 199 fs (1 MHz to 1 GHz), phase noise is –110 dBc/Hz at 10 MHz offset. The 14 × 160 µm 2 32 nm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31 mA from a 1 V supply.
Autors: Ferriss, M.;Rylyakov, A.;Tierno, J.A.;Ainspan, H.;Friedman, D.J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 1027 - 1035
Publisher: IEEE
 
» A 2D-3D Switchable Driving Method for Reducing Power Consumption of Thin-Film Transistor Liquid Crystal Display TV With Film-Type Patterned Retarder
Abstract:
This paper presents a new 2D–3D switchable driving method for a 3D thin-film transistor liquid crystal display (TFT-LCD) TV. The proposed driving method, which uses a film-type patterned retarder (FPR), can reduce unnecessary power consumption while displaying 2D images. The proposed driving method can change a part of a pixel according to the driving mode; the part is operated as a black matrix in a 3D display mode, whereas in a 2D display mode, the part is operated as a normal pixel. To realize the proposed driving method without increasing the data signal rates, the number of gate driver integrated circuits (ICs), and the bezel size of the panel, a novel pixel structure and an integrated a-Si:H gate driver, which can be implemented in a small size, are developed. The power consumption of the proposed driving method measured at the full white gray level is 67 W in a 47-in full-high-definition (FHD) TFT-LCD TV. This result shows that the power consumption of the proposed driving method decreases by 28% compared with that of the conventional driving method in the 2D display mode.
Autors: Kim, D.-S.;Chae, H.-Y.;Jo, S.-H.;Kwon, O.-K.;
Appeared in: Journal of Display Technology
Publication date: Apr 2014, volume: 10, issue:4, pages: 299 - 307
Publisher: IEEE
 
» A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization
Abstract:
This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The implementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility provided by the FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V, and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed explanations of the body-biasing techniques specific to this technology are largely presented, in the context of a multi- co-integration, which enable this energy efficient silicon implementation. The system integrates all the advanced IPs for energy efficiency as well as the body bias generator and a fast (µs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance, with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V, or +544% at 0.61 V with 1.3 V FBB.
Autors: Jacquet, D.;Hasbani, F.;Flatresse, P.;Wilson, R.;Arnaud, F.;Cesana, G.;Di Gilio, T.;Lecocq, C.;Roy, T.;Chhabra, A.;Grover, C.;Minez, O.;Uginet, J.;Durieu, G.;Adobati, C.;Casalotto, D.;Nyer, F.;Menut, P.;Cathelin, A.;Vongsavady, I.;Magarshack, P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 812 - 826
Publisher: IEEE
 
» A 3.6-to-1.8-V Cascode Buck Converter With a Stacked Filter in 65-nm CMOS
Abstract:
This brief presents the analysis, design, and measurements of an integrated synchronous cascode dc–dc buck converter in 65-nm CMOS. Guidelines for optimal design of each thick-oxide device in the switch bridge are derived in order to obtain enhanced power efficiency. The form factor is improved by stacking the high- inductor and other converter components. The circuit shows a measured efficiency of 67.9% when converting 3.6 to 1.8 V at a switching frequency of 120 MHz and a load current of 140 mA. The efficiency enhancement factor of 26.4% is among the highest for integrated buck converters.
Autors: Ostman, K.B.;Jarvenhaara, J.K.;Broussev, S.S.;Viitaniemi, I.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2014, volume: 61, issue:4, pages: 234 - 238
Publisher: IEEE
 
» A 30 mK, 13.5 T scanning tunneling microscope with two independent tips
Abstract:
We describe the design, construction, and performance of an ultra-low temperature, high-field scanning tunneling microscope (STM) with two independent tips. The STM is mounted on a dilution refrigerator and operates at a base temperature of 30 mK with magnetic fields of up to 13.5 T. We focus on the design of the two-tip STM head, as well as the sample transfer mechanism, which allows in situ transfer from an ultra high vacuum preparation chamber while the STM is at 1.5 K. Other design details such as the vibration isolation and rf-filtered wiring are also described. Their effectiveness is demonstrated via spectral current noise characteristics and the root mean square roughness of atomic resolution images. The high-field capability is shown by the magnetic field dependence of the superconducting gap of CuxBi2Se3. Finally, we present images and spectroscopy taken with superconducting Nb tips with the refrigerator at 35 mK that indicate that the effective temperature of our tips/sample is approximately 184 mK, corresponding to an energy resolution of 16 μeV.
Autors: Roychowdhury, Anita;Gubrud, M.A.;Dana, R.;Anderson, J.R.;Lobb, C.J.;Wellstood, F.C.;Dreyer, M.;
Appeared in: Review of Scientific Instruments
Publication date: Apr 2014, volume: 85, issue:4, pages: 043706 - 043706-9
Publisher: IEEE
 
» A 390 ps On-Wafer True-Time-Delay Line Developed by a Novel Micro-Coax Technology
Abstract:
A CMOS-compatible on-wafer true-time-delay (TTD) line for broadband microwave applications is demonstrated using a novel micro-coax technology. The insertion loss of the developed TTD line is less than 2.55 dB for a constant group delay of 390 ps from dc to 40 GHz, without control power or control voltage. To the best of our knowledge, the fabricated micro-coaxial TTD line provides the best figures-of-merit (FOM) value (0.00641 dB/ps at 40 GHz) among reported on-wafer TTD lines.
Autors: Tian, Y.;Lee, K.;Wang, H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 233 - 235
Publisher: IEEE
 
» A 4.8-mW/Gb/s 9.6-Gb/s 5 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS
Abstract:
A low-jitter and low-power source-synchronous serializer/deserializer transmitter (TX) with a data rate of 9.6 Gb/s is presented. The TX consists of five data channels plus one forwarded-clock channel and features a total jitter of 20.39 ps p-p at bit error rate. Low jitter is achieved through the use of a phase-locked loop with bandwidth linearization that has a random RMS jitter of 0.66 ps. A global clock distribution network is proposed to minimize the power-supply-induced jitter and the power consumption. The TX transmits preemphasized data through a current-mode logic driver with a four-tap feedforward equalizer. The on-chip output impedance and the signal amplitude can be accurately calibrated by a successive approximation register logic separately. The total power consumption for the 5 1-lane TX physical core fabricated in 65-nm bulk CMOS running at 9.6 Gb/s is 230 mW or 4.8 mW/Gb/s.
Autors: Yuan, S.;Wang, Z.;Zheng, X.;Huang, K.;Xu, N.;Rhee, W.;Wu, L.;Zhang, C.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2014, volume: 61, issue:4, pages: 209 - 213
Publisher: IEEE
 
» A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications
Abstract:
A machine-learning (ML) assisted cardiac sensor SoC (CS-SoC) is designed for mobile healthcare applications. The heterogeneous architecture realizes the cardiac signal acquisition, filtering with versatile feature extractions and classifications, and enables the higher order analysis over traditional DSPs. Besides, the asynchronous architecture with dynamic standby controller further suppresses the system active duty and the leakage power dissipation. The proposed chip is fabricated in a 90-nm standard CMOS technology and operates at 0.5 V–1.0 V (0.7 V–1.0 V for SRAM and I/O interface). Examined with healthcare monitoring applications, the CS-SoC dissipates 48.6/105.2 µW for real-time syndrome detections of ECG-based arrhythmia/VCG-based myocardial infarction with 95.8/99% detection accuracy, respectively.
Autors: Hsu, S.-Y.;Ho, Y.;Chang, P.-Y.;Su, C.;Lee, C.-Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 801 - 811
Publisher: IEEE
 
» A 5-Gb/s Noise Optimized Receiver Using a Switched TIA for Wireless Optical Communications
Abstract:
Pub DtlThis paper reports a systematic approach for designing a low noise and low power optical receiver targeting high sensitivity imaging architectures for optical wireless communications. For line of sight tracking in optical wireless communications, a switching matrix is employed between the pixel/photodetector array and the transimpedance (TIA) amplifier. An optimization procedure is introduced to balance various performance parameters in the optical receiver front end when including the effect of the switch. The presented optical receiver consists of a low noise, wideband TIA, where noise and stability are optimized using a series inductor at the input. The TIA is followed by a limiter with offset cancellation and 50 output buffer capable of 900 mV p-p differential output swing, over the 50 resistance of the BERTScope. The receiver implemented in the IBM 130 nm CMOS technology, achieves a bit error rate of at 5-Gb/s corresponding to 2.8 current at the input and at 4-Gb/s corresponding to 2.1 input current, in presence of 1 pF input capacitance representing the photodiode. The total power consumption including the on chip 50 differential output buffer is 68 mW from 1.5 V DC supply. The die area including bonding pads and output buffer is .
Autors: Nakhkoob, B.;Hella, M.M.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2014, volume: 61, issue:4, pages: 1255 - 1268
Publisher: IEEE
 
» A 5-Gb/s Serial-Link Redriver With Adaptive Equalizer and Transmitter Swing Enhancement
Abstract:
Pub DtlA single-lane, dual-channel, 5-Gb/s serial link redriver with no clock data recovery (CDR) or phase-locked loop (PLL) has been developed by using a standard 0.13- m CMOS technology. New features and techniques have been developed in both the architecture and the analog modules to meet the jitter and protocol requirements for a redriver for multi-Gb/s operation, which is made difficult by the lack of CDR and a PLL. These techniques include: 1) adaptive receiver equalization; 2) enhanced transmitter output swing and programmable de-emphasis/swing settings; 3) a robust state flow control combined with various signal detectors to provide automatic state and mode switching without affecting operations of upstream and downstream ports. The redriver chip consumes 165 mA in 5 Gb/s bidirectional full-duplex operation from a single 3.3 V power supply.
Autors: Liu, H.;Wang, Y.;Xu, C.;Chen, X.;Lin, L.;Yu, Y.;Wang, W.;Majumder, A.;Chui, G.;Brown, D.;Fang, A.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2014, volume: 61, issue:4, pages: 1001 - 1011
Publisher: IEEE
 
» A 5-V 290- Low-Noise Chopper-Stabilized Capacitive-Sensor Readout Circuit in 0.8- CMOS Using a Correlated-Level-Shifting Technique
Abstract:
In this brief, a low-power high-resolution readout front end intended for capacitive sensors is presented, in which the circuit uses correlated-level-shifting (CLS) and chopper-stabilization (CS) techniques. CLS is a relatively new switched-capacitor (SC) technique that is used to reduce errors from finite operational amplifier (op-amp) gain, whereas CS is a classic technique that is used to reduce the adverse effects of dc offset and low-frequency noise associated with the op-amp. In this brief, the capacitive sensor is physically emulated by a pair of on-chip differential variable capacitors that are in the femtofarad range. The proposed front end is designed in a 0.8- CMOS technology and consumes 290 from a single 5-V supply. The readout circuit achieves a capacitance noise floor of 0.018 aF/ at 400 Hz with a sensitivity of 50 mV/fF.
Autors: Shiah, J.;Mirabbasi, S.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2014, volume: 61, issue:4, pages: 254 - 258
Publisher: IEEE
 
» A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register
Abstract:
In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For pipelined operation, a novel time-register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse-train time-amplifier, a 9-bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/stage TDCs and a 3 b delay-line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/s while consuming 15.4 mW. Compared to other high-resolution state-of-the-art TDCs, the proposed pipelined TDC achieves the best figure-of-merit (FoM) without any calibration.
Autors: Kim, K.;Yu, W.;Cho, S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 1007 - 1016
Publisher: IEEE
 
» A Batch-Mode Active Learning Algorithm Using Region-Partitioning Diversity for SVM Classifier
Abstract:
In this paper, a region-partitioning active learning (AL) technique is proposed for classification of remote sensing (RS) images based on the support vector machines (SVM) classifier. In the batch-mode AL process, diversity information is required to select a batch of informative samples. A new AL technique that aims to introduce diversity information is proposed based on relative positions of candidate samples in the feature space. The proposed technique selects informative samples according to an uncertainty criterion at each iteration. These samples are selected with an extra constraint to guarantee that they are not located in the same region of the feature space. The proposed technique is compared with state-of-the-art methods adopted in the RS community. Experimental tests were performed on three data sets, including one very high spatial resolution multispectral data set and two hyperspectral data sets. The proposed algorithm displays a classification performance that is similar to or even better than the state-of-the-art methods. In addition, the proposed algorithm performs efficiently in terms of computational time.
Autors: Huo, L.-Z.;Tang, P.;
Appeared in: IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing
Publication date: Apr 2014, volume: 7, issue:4, pages: 1036 - 1046
Publisher: IEEE
 
» A Bibliometric Analysis of the Intelligent Transportation Systems Research Based on Science Mapping
Abstract:
In this paper, we highlight the conceptual structure of the intelligent transportation systems (ITS) research field in the period 1992–2011. To do that, an automatic approach for detecting and visualizing hidden themes and their evolution across a consecutive span of years is applied. This automatic approach, which is based on co-word analysis, combines performance analysis and science mapping. To show the conceptual evolution of ITS, three consecutive periods have been defined, i.e., 1992–2001, 2002–2006, and 2007–2011. We have identified that the ITS research has been focused on six main thematic areas, i.e., VEHICLE-AND-ROAD-TRACKING, DRIVER-BEHAVIOR-AND-SAFETY, SCENARIOS-SIMULATION, TRAFFIC-FLOW-AND-TRAFFIC-MANAGEMENT, VEHICLE-CONTROL, and VEHICLE-NAVIGATION.
Autors: Cobo, M.J.;Chiclana, F.;Collop, A.;de Ona, J.;Herrera-Viedma, E.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Apr 2014, volume: 15, issue:2, pages: 901 - 908
Publisher: IEEE
 
» A Broadband 3 dB Tandem Coupler Utilizing Right/Left Handed Transmission Line Sections
Abstract:
A new type of broadband 3 dB tandem coupler has been proposed featuring frequency characteristics of the resulting coupling similar to those of a classic 3 dB two-section asymmetric coupled-line directional coupler. The coupler is composed of two loosely coupled-line sections having electrical lengths close to quarter-wavelength connected by right-handed and left-handed transmission line sections. Theoretical analysis and design equations have been presented with an exemplary realization. Measurements of the manufactured tandem coupler operating at having wide operational bandwidth have been shown to validate the presented analysis.
Autors: Staszek, K.;Sorocki, J.;Kaminski, P.;Wincza, K.;Gruszczynski, S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 236 - 238
Publisher: IEEE
 
» A broadband transformation-optics metasurface lens
Abstract:
We present a transformational metasurface Luneburg lens based on the quasi-conformal mapping method, which has weakly anisotropic constitutive parameters. We design the metasurface lens using inhomogeneous artificial structures to realize the required surface refractive indexes. The transformational metasurface Luneburg lens is fabricated and the measurement results demonstrate very good performance in controlling the radiated surface waves.
Autors: Wan, Xiang;Xiang Jiang, Wei;Feng Ma, Hui;Jun Cui, Tie;
Appeared in: Applied Physics Letters
Publication date: Apr 2014, volume: 104, issue:15, pages: 151601 - 151601-4
Publisher: IEEE
 
» A center frequency adjustable narrow band filter for the detection of weak single frequency signal
Abstract:
We describe and implement a center frequency adjustable narrow band filter based on the crystal filter for the detection of weak single frequency signal. It is formed by a multiplier, a direct digital frequency synthesizer, a multi-stage crystal bandpass filter, and a micro control unit which is used to set the center frequency of the filter. A theoretical study is proposed and experimentally validated. The test results show that the 3 db and 20 db bandwidths are 0.84 Hz and 2.73 Hz, respectively, and the filter system can effectively detect the signal with amplitude below 1 μV and a frequency which ranges from 10 Hz to the frequency that is mainly limited by the components applied.
Autors: Xin, Yunhong;Xiang, ZhenMing;Dong, LeMing;Zhu, Bing;Cao, Hui;Fang, Yu;
Appeared in: Review of Scientific Instruments
Publication date: Apr 2014, volume: 85, issue:4, pages: 044708 - 044708-4
Publisher: IEEE
 
» A close correlation between nanostructure formations and the thickness dependence of the critical current density in pure and BaSnO3-added GdBa2Cu3O7-δ films
Abstract:
A close correlation between the nanostructure formations and the thickness dependence of the in-field critical current density (Jc) in GdBa2Cu3O7-δ (GdBCO) films is reported. Pure and 2 wt. % BaSnO3 (BSO)-added GdBCO films with film thicknesses (d) ranging from 0.2 μm to 1.5 μm were deposited on SrTiO3 single-crystalline substrates by using a pulsed laser deposition technique. Magnetization data measured at 77 K with the magnetic field applied parallel to the c-axis of the films showed the general trend of decreasing in-field Jc with increasing residual film thickness. The two special inversions, however, were observed at d ∼ 0.6 μm, for which the Jc’s of both the pure and BSO-added GdBCO films were larger than those of the films with d ∼ 0.4 μm. A sequential ion-milling process and scanning electron microscopy studies were employed to examine the microstructural evolution in the 1.5- μm-thick GdBCO films. For the pure GdBCO films, nanosized dislocations were observed to start growing at intersections of perpendicularly connected a-axis-oriented grains in a residual film thickness (t) of ∼ 0.6 μm and the growth persisted to the top surface of the 1.5-μm-thick GdBCO film. For the BSO-added GdBCO films, the density of BSO nanorods was estimated to be decreased versus t with an increase found at t of ∼ 0.6 μm A reason for this inversions of Jc might be the nanostructure formations at t ∼ 0.6 μm, which were proved to serve as effective pinning centers.
Autors: Tran, D.H.;Putri, W.B.K.;Kang, B.;Lee, N.H.;Kang, W.N.;
Appeared in: Journal of Applied Physics
Publication date: Apr 2014, volume: 115, issue:16, pages: 163901 - 163901-6
Publisher: IEEE
 
» A cohesive law for interfaces in graphene/hexagonal boron nitride heterostructure
Abstract:
Graphene/hexagonal boron nitride (h-BN) heterostructure has showed great potential to improve the performance of graphene device. We have established the cohesive law for interfaces between graphene and monolayer or multi-layer h-BN based on the van der Waals force. The cohesive energy and cohesive strength are given in terms of area density of atoms on corresponding layers, number of layers, and parameters in the van der Waals force. It is found that the cohesive law in the graphene/multi-layer h-BN is dominated by the three h-BN layers which are closest to the graphene. The approximate solution is also obtained to simplify the expression of cohesive law. These results are very useful to study the deformation of graphene/h-BN heterostructure, which may have significant impacts on the performance and reliability of the graphene devices especially in the areas of emerging applications such as stretchable electronics.
Autors: Zhang, Chenxi;Lou, Jun;Song, Jizhou;
Appeared in: Journal of Applied Physics
Publication date: Apr 2014, volume: 115, issue:14, pages: 144308 - 144308-6
Publisher: IEEE
 
» A Colorless Remote Antenna Unit for Bidirectional Photonic Antenna Remoting
Abstract:
A colorless (wavelength-independent) remote antenna unit (RAU) for bidirectional photonic antenna remoting is proposed and demonstrated, which is based on a reflective semiconductor optical amplifier electroabsorption modulator (SOA-EAM). Due to the gain saturation effect in the semiconductor optical amplifier (SOA) of the reflective SOA-EAM, the microwave signal carried by the downlink optical signal is received and effectively erased. Then, the electroabsorption modulator (EAM) converts the uplink RF signal to an optical signal, which is reflected back to the center office (CO) by the high-reflection coated facet of the device to provide the uplink service. No signal downconversion is needed since the modulation bandwidth of the EAM can reach tens of GHz. A proof-of-concept experiment is carried out. The RAU performs well in a bidirectional radio over fiber (ROF) system for providing 500 Mb/s wireless services centered at 2 GHz.
Autors: Zhu, B.;Chen, G.;Zhang, F.;Guo, R.;Zhu, D.;Pan, S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 275 - 277
Publisher: IEEE
 
» A Compact 3 dB -Plane Waveguide Directional Coupler With Full Bandwidth
Abstract:
A compact 3 dB -Plane waveguide directional coupler (patent pending) with full bandwidth is proposed in this letter. It consists of a pair of rectangular waveguides placed parallel to each other along their broad side. The tight coupling and wide bandwidth are achieved by using reduced height waveguide and large aperture in the common broad wall of the two parallel waveguides. For verification purpose, a prototype has been manufactured and measured. The measured results show that return loss and isolation of the coupler better than 25 and 26 dB, respectively, and the power-split unbalance within 0.6 dB are achieved over the full waveguide bandwidth.
Autors: Zhang, Y.;Wang, Q.;Xin, H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 227 - 229
Publisher: IEEE
 
» A Compact 3 dB -Plane Waveguide Directional Coupler With Full Bandwidth
Abstract:
A compact 3 dB -Plane waveguide directional coupler (patent pending) with full bandwidth is proposed in this letter. It consists of a pair of rectangular waveguides placed parallel to each other along their broad side. The tight coupling and wide bandwidth are achieved by using reduced height waveguide and large aperture in the common broad wall of the two parallel waveguides. For verification purpose, a prototype has been manufactured and measured. The measured results show that return loss and isolation of the coupler better than 25 and 26 dB, respectively, and the power-split unbalance within 0.6 dB are achieved over the full waveguide bandwidth.
Autors: Zhang, Y.;Wang, Q.;Xin, H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 227 - 229
Publisher: IEEE
 
» A Compact Architecture for Simulation of Spatio-Temporally Correlated MIMO Fading Channels
Abstract:
Radio channel impairments have a dramatic impact on the performance of wireless communication systems and hence, utilizing realistic radio channel models is crucial for the accurate performance validation of emerging wireless systems. However, faithful radio propagation channel models are computationally intensive for software-based simulations, especially for multiple antenna systems. This article presents the design and implementation of a multiple-input multiple-output (MIMO) baseband fading channel simulator on a field-programmable gate array (FPGA). In addition to the well-known independent and identically distributed channel model, the simulator supports three spatio-temporally correlated fading channel models which are commonly used for performance analysis. The implemented MIMO fading channel simulator is compact enough to be integrated with the baseband design under test on the same FPGA for accelerated performance validations.
Autors: Alimohammad, A.;Fard, S.F.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2014, volume: 61, issue:4, pages: 1280 - 1288
Publisher: IEEE
 
» A compact fast ionization gauge for in situ measurement of high-density neutral flow dynamics
Abstract:
A compact ionization gauge has been developed to carry out in situ measurements of high density (1020–1022 m−3) neutral gas flow dynamics with high temporal and spatial resolution. Key design aspects are discussed including gauge sensitivity and time response scaling with decreased probe dimensions, high-pressure operation, improved driver circuit bandwidth, and techniques for constructing a miniaturized probe head. Gas adsorption was discovered to significantly alter emission current and gauge sensitivity over timescales of several seconds. This effect must be taken into consideration when making time-resolved, high-density measurements. Over short timescales gauge response was predicted by scaling the sensitivity of a nominal Bayard-Alpert gauge to account for variations in probe dimensions and species-dependent ionization cross-section. Time-resolved neutral density profiles have been acquired in the Magnetized Shock Experiment at Los Alamos National Laboratory, providing data on the initial conditions of the ionization, plasmoid formation, and translation processes. It is shown that the desired density profiles can be achieved using a dynamic gas fill and that density can be scaled independently of the spatial profile.
Autors: Weber, T.E.;Intrator, T.P.;
Appeared in: Review of Scientific Instruments
Publication date: Apr 2014, volume: 85, issue:4, pages: 043501 - 043501-6
Publisher: IEEE
 
» A Compact Superconducting Filter at 6.5 MHz Using Capacitor-Loaded Spiral-in-Spiral-Out Resonators
Abstract:
Chip-capacitor-loaded spiral-in-spiral-out (SISO) resonators are proposed for superconducting filters at the HF band. Interdigital capacitors are used between resonators to provide large coupling values at the fundamental mode and small coupling values at harmonic modes. A compact four-pole high-temperature superconducting filter centered at 6.5 MHz is demonstrated, with a 8% fractional bandwidth, 0.13 dB insertion loss, and 14.3 dB return loss. The spurious response of the filter is below dB up to about 13 times of the fundamental mode.
Autors: Xu, Z.;Wei, B.;Cao, B.;Guo, X.;Zhang, X.;Wang, D.;Song, X.;Lu, X.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 242 - 244
Publisher: IEEE
 
» A Comparative Analysis of the Effects of Dynamic Optical Circuit Provisioning on IP Routing
Abstract:
We analyze the effects of dynamic optical circuit setup on IP routing in general and on two routing mechanisms in particular, i.e., explicit routing and shortest-path-first routing. We present analytical models for computing the size and placement of optical circuits and propose model adaptations driven by the IP router system design. The results show that without careful consideration of intrinsic capabilities of IP routing protocol and forwarding, the size and location of optical circuits used can be vastly underestimated, also leading to significant disruptions in real networks. We present the Optical Bypass mechanisms and show that these methods, unlike traditional IP routing-based solutions, affect a comparatively lower number of IP routes and can be computed near-optimally, even under unknown traffic matrix conditions, making them effective and feasible.
Autors: Chamania, M.;Jukan, A.;
Appeared in: IEEE/ACM Transactions on Networking
Publication date: Apr 2014, volume: 22, issue:2, pages: 429 - 442
Publisher: IEEE
 
» A comparison of four direct geometry time-of-flight spectrometers at the Spallation Neutron Source
Abstract:
The Spallation Neutron Source at Oak Ridge National Laboratory now hosts four direct geometry time-of-flight chopper spectrometers. These instruments cover a range of wave-vector and energy transfer space with varying degrees of neutron flux and resolution. The regions of reciprocal and energy space available to measure at these instruments are not exclusive and overlap significantly. We present a direct comparison of the capabilities of this instrumentation, conducted by data mining the instrument usage histories, and specific scanning regimes. In addition, one of the common science missions for these instruments is the study of magnetic excitations in condensed matter systems. We have measured the powder averaged spin wave spectra in one particular sample using each of these instruments, and use these data in our comparisons.
Autors: Stone, M.B.;Niedziela, J.L.;Abernathy, D.L.;DeBeer-Schmitt, L.;Ehlers, G.;Garlea, O.;Granroth, G.E.;Graves-Brook, M.;Kolesnikov, A.I.;Podlesnyak, A.;Winn, B.;
Appeared in: Review of Scientific Instruments
Publication date: Apr 2014, volume: 85, issue:4, pages: 045113 - 045113-13
Publisher: IEEE
 
» A Comparison of Uncertainty Evaluation Methods for On-Wafer -Parameter Measurements
Abstract:
An experimental analysis of on-wafer S-parameter uncertainties is presented. Recently, two different approaches, based either on differential numerical programming or on a fully analytical solution, have been introduced. In order to establish their suitability, a careful comparison is given for on-wafer measurements. Through this comparison, possible limitations and causes of errors are also highlighted. Finally, the uncertainty evaluation of the 16-term error model is presented for the first time.
Autors: Teppati, V.;Ferrero, A.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Apr 2014, volume: 63, issue:4, pages: 935 - 942
Publisher: IEEE
 
» A Comprehensive Graphene FET Model for Circuit Design
Abstract:
During the last years, graphene-based field-effect transistors (GFETs) have shown outstanding RF performance; therefore, they have attracted considerable attention from the electronic devices and circuits communities. At the same time, analytical models that predict the electrical characteristics of GFETs have evolved rapidly. These models, however, have a complexity level that can only be handled with the help of a circuit simulator. On the other hand, analog circuit designers require simple models that enable them to carry out fast hand calculations, i.e., to create circuits using small-signal hybrid - models, calculate figures of merit, estimate gains, pole-zero positions, and so on. This paper presents a comprehensive GFET model that is simple enough for being used in hand calculations during circuit design and at the same time, it is accurate enough to capture the electrical characteristics of the devices in the operating regions of interest. Closed analytical expressions are provided for the drain current , small-signal transconductance gain , output resistance , and parasitic capacitances and . In addition, figures of merit, such as intrinsic voltage gain , transconductance efficiency , and transit frequency are presented. The proposed model has been compared to a complete analytical model and al- o to measured data available in current literature. The results show that the proposed model follows closely to both the complete analytical model and the measured data; therefore, it can be successfully applied in the design of GFET analog circuits.
Autors: Rodriguez, S.;Vaziri, S.;Smith, A.;Fregonese, S.;Ostling, M.;Lemme, M.C.;Rusu, A.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Apr 2014, volume: 61, issue:4, pages: 1199 - 1206
Publisher: IEEE
 
» A Conjoined Electron and Thermal Transport Study of Thermal Degradation Induced During Normal Operation of Multigate Transistors
Abstract:
A 3-D full-band particle Monte Carlo (MC) simulator, with full electron and phonon dispersion and a 2-D quantum correction is self-consistently coupled to a phonon MC simulator. The coupling entails feeding the phonon data obtained from the 3-D electrical MC to the phonon MC. The phonon MC reciprocates by providing the resulting spatial temperature map, which is used in the electron MC, with temperature-dependent scattering table, in a self-consistent manner. A key feature of our model is its ability to delineate the influence of the various phonon modes on the electronic transport through the application of anharmonic phonon decay and full phonon dispersion. The electrothermal simulator developed is utilized to assess the performance of silicon-on-insulator (SoI) multigate (MG) MOSFET with nanoscale cross sections. This paper shows that the hotspot in inversion mode SoI MG MOSFET with 20-nm gate length permeates into the channel as the cross section is reduced (covering of the channel for the 5 nm 5 nm cross section). Furthermore, cross-sectional scaling, a key design rule to mitigate short-channel effects, degenerates device performance well beyond the ideal current gain limits of MG MOSFET architecture of double-gate, trigate, and gate-all-around MOSFET. Consequently, at the sub-20-nm scale adding more gate does not necessarily improve performance.
Autors: Mohamed, M.;Aksamija, Z.;Vitale, W.;Hassan, F.;Park, K.-H.;Ravaioli, U.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Apr 2014, volume: 61, issue:4, pages: 976 - 983
Publisher: IEEE
 
» A Constant Efficiency of Rectifying Circuit in an Extremely Wide Load Range
Abstract:
Wireless power transmission (WPT) is actively being researched and developed. WPT transfers power to electrical load without a wire. One of the problems is that the efficiency is easily affected by load resistance and input power. Therefore, an impedance matching circuit becomes crucial for realization of high-efficiency wireless power systems. In this study, we proposed a maximum power point tracking (MPPT) method for a low-power milliwatt-level RF-dc rectifying circuit using a dc–dc converter. We proposed an RF-dc–dc circuit that consists of an RF-dc rectifier circuit and a dc–dc converter. We measured the RF-to-dc conversion efficiency of the RF-dc–dc circuit using 2.45-GHz microwave power. When the buck–boost converter is connected to the rectifying circuit, the RF-to-dc efficiency of rectifier is approximately steady at 75%, despite the load resistance changing from 100 to 5000 . The overall efficiency of the RF-dc–dc circuit is still over 60%, even though the load resistance varied from 100 to 5000 and the input power changed from 40 to 100 mW.
Autors: Huang, Y.;Shinohara, N.;Mitani, T.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Apr 2014, volume: 62, issue:4, pages: 986 - 993
Publisher: IEEE
 
» A Control-Theoretic Approach to Rate Adaption for DASH Over Multiple Content Distribution Servers
Abstract:
Recently, dynamic adaptive streaming over HTTP (DASH) has been widely deployed on the Internet. However, the research about DASH over multiple content distribution servers (MCDS-DASH) is limited. Compared with traditional single-server DASH, MCDS-DASH is able to offer expanded bandwidth, link diversity, and reliability. It is, however, a challenging problem to smooth video bitrate switching over multiple servers due to their diverse bandwidths. In this paper, we propose a block-based rate adaptation method considering both the diverse bandwidths and feedback buffered video time. In our method, multiple fragments are grouped into a block and the fragments are downloaded in parallel from multiple servers. We propose to adapt video bitrate at the block level rather than at the fragment level. By dynamically adjusting the block length and scheduling fragment requests to multiple servers, the requested video bitrates from the multiple servers are synchronized, making the fragments download in an orderly way. Then, we propose a control-theoretic approach to select an appropriate bitrate for each block. By modeling and linearizing the rate adaption system, we propose a novel proportional-derivative controller to adapt video bitrate with high responsiveness and stability. Theoretical analysis and extensive experiments on our network testbed and the Internet demonstrate the good efficiency of the proposed method.
Autors: Zhou, C.;Lin, C.;Zhang, X.;Guo, Z.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Apr 2014, volume: 24, issue:4, pages: 681 - 694
Publisher: IEEE
 
» A Cross-Layer Backpressure Architecture for Wireless Multihop Networks
Abstract:
Contemporary wireless multihop networks operate much below their capacity due to the poor coordination among transmitting nodes. In this paper, we present XPRESS, a cross-layer backpressure architecture designed to reach the capacity of wireless multihop networks. Instead of a collection of poorly coordinated wireless routers, XPRESS turns a mesh network into a wireless switch. Transmissions over the network are scheduled using a throughput-optimal backpressure algorithm. Realizing this theoretical concept entails several challenges, which we identify and address with a cross-layer design and implementation on top of our wireless hardware platform. In contrast to previous work, we implement and evaluate backpressure scheduling over a TDMA MAC protocol, as it was originally proposed in theory. Our experiments in an indoor testbed show that XPRESS can yield up to 128% throughput gains over 802.11.
Autors: Laufer, R.;Salonidis, T.;Lundgren, H.;Le Guyadec, P.;
Appeared in: IEEE/ACM Transactions on Networking
Publication date: Apr 2014, volume: 22, issue:2, pages: 363 - 376
Publisher: IEEE
 
» A cryogenic infrared calibration target
Abstract:
A compact cryogenic calibration target is presented that has a peak diffuse reflectance, R ⩽ 0.003, from 800 to 4800 cm−1 (12 − 2 μm). Upon expanding the spectral range under consideration to 400–10 000 cm−1 (25 − 1 μm) the observed performance gracefully degrades to R ⩽ 0.02 at the band edges. In the implementation described, a high-thermal-conductivity metallic substrate is textured with a pyramidal tiling and subsequently coated with a thin lossy dielectric coating that enables high absorption and thermal uniformity across the target. The resulting target assembly is lightweight, has a low-geometric profile, and has survived repeated thermal cycling from room temperature to ∼4 K. Basic design considerations, governing equations, and test data for realizing the structure described are provided. The optical properties of selected absorptive materials—Acktar Fractal Black, Aeroglaze Z306, and Stycast 2850 FT epoxy loaded with stainless steel powder—are characterized and presented.
Autors: Wollack, E.J.;Kinzer, R.E.;Rinehart, S.A.;
Appeared in: Review of Scientific Instruments
Publication date: Apr 2014, volume: 85, issue:4, pages: 044707 - 044707-5
Publisher: IEEE
 
» A Current Regulator for Inverter-Based Massively Column-Parallel ADCs
Abstract:
The inverter-based switched-capacitor delta–sigma analog-to-digital conversion (ADC) has become popular due to its low-voltage low-power capabilities. This brief proposes a new current regulation technique for the inverter-based circuits. The proposed circuit controls both the power supply and the common-mode levels in response to the process–voltage–temperature variations by sensing the current in the replica inverter. The proposed sense and regulation circuit is implemented for the regulation of massively column-parallel ADCs, and the measurement results prove that the performance is well controlled regardless of the variations.
Autors: Yeo, J.;Choi, Y.;Roh, J.;Han, G.;Chae, Y.;Ham, S.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2014, volume: 61, issue:4, pages: 224 - 228
Publisher: IEEE
 
» A Delaunay-Based Coordinate-Free Mechanism for Full Coverage in Wireless Sensor Networks
Abstract:
Recently, many schemes have been proposed for detecting and healing coverage holes to achieve full coverage in wireless sensor networks (WSNs). However, none of these schemes aim to find the shortest node movement paths to heal the coverage holes, which could significantly reduce energy usage for node movement. Also, current hole healing schemes require accurate knowledge of sensor locations; obtaining this knowledge consumes high energy. In this paper, we propose a Delaunay-based coordinate-free mechanism (DECM) for full coverage. Based on rigorous mathematical analysis, DECM can detect coverage holes and find the locally shortest paths for healing holes in a distributed manner without requiring accurate node location information. Also, DECM incorporates a cooperative movement mechanism that can prevent generating new holes during node movements in healing holes. Simulation results and experimental results from the real-world GENI Orbit testbed show that DECM achieves superior performance in terms of the energy-efficiency, effectiveness of hole healing, energy consumption balance and lifetime compared to previous schemes.
Autors: Chenxi Qiu;Haiying Shen;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Apr 2014, volume: 25, issue:4, pages: 828 - 839
Publisher: IEEE
 
» A Deterministic Digital Background Calibration Technique for VCO-Based ADCs
Abstract:
This paper presents a digital background calibration technique to realize a linear voltage-controlled-oscillator (VCO) based ADC. The distortion caused due to the VCO's nonlinear tuning characteristics is eliminated by introducing an inverse voltage-to-frequency transfer function in the signal path. The proposed calibration unit runs in the background and detects the inverse transfer function using a highly digital frequency locked loop. Like many other VCO-based ADCs, the proposed technique does not require analog building blocks such as operational amplifiers, multi-bit feed-back DACs etc., and retains the scaling friendly properties. Implemented in a 90 nm CMOS process, the on-chip calibration improves SNDR of an open-loop VCO-based ADC from 46 dB to more than 73 dB in 5 MHz signal bandwidth while consuming 4.1 mW power. The ADC achieves a figure-of-merit of 91–112 fJ/conv-step for different input frequencies.
Autors: Rao, S.;Reddy, K.;Young, B.;Hanumolu, P.K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 950 - 960
Publisher: IEEE
 
» A Distributed Method for Compressive Data Gathering in Wireless Sensor Networks
Abstract:
Compressive data gathering (CDG) has recently emerged to provide energy efficient data aggregation in wireless sensor networks. CDG requires efficient routing (forwarding) trees to gather encoded data from sensor nodes to the sink. This paper presents a decentralized method for the compressive data gathering problem (DCDG). Our method allows each sensor node to locally make a decision in constructing and maintaining the forwarding trees and has minimal complexity and overhead with outstanding performance.
Autors: Ebrahimi, Dariush;Assi, Chadi;
Appeared in: IEEE Communications Letters
Publication date: Apr 2014, volume: 18, issue:4, pages: 624 - 627
Publisher: IEEE
 
» A Distributed Optimization Framework for Multi-Channel Multi-User Small Cell Networks
Abstract:
Small cell enchantment is emerging as the key technique for wireless network evolution. {One challenging problem for small cell enhancement is how to achieve high data rate with as-low-as-possible control and computation overheads. As a solution, we propose a low-complexity distributed optimization framework in this paper.} Our solution includes two parts. One is a novel implicit information exchange mechanism that enables channel-aware opportunistic scheduling and resource allocation among links. The other is the sub-gradient based algorithm with a polynomial-time complexity. What is more, for large scale systems, we design an improved distributed algorithm based on insights obtained from the problem structure. This algorithm achieves a close-to-optimal performance with a much lower complexity. Our numerical evaluations validate the analytical results and show the advantage of our algorithms.
Autors: Li, Shuqin;Cai, Liyu;
Appeared in: IEEE Communications Letters
Publication date: Apr 2014, volume: 18, issue:4, pages: 604 - 607
Publisher: IEEE
 
» A Divide-by-Four Transformer-Coupled Regenerative Frequency Divider With Quadrature Outputs
Abstract:
A divide-by-four transformer-coupled regenerative frequency divider implemented by a TSMC 90 nm CMOS process is presented. A transformer-coupling technique and a source-injected current-mode-logic divider were proposed to increase the injection signal level and widen the operation range of the loop divider. A subharmonic mixer with bottom-switching pairs was used to reduce dc power consumption and optimize the conversion gain. The divider core consumes 6.8 mW at 1.2 V supply voltage. Without using the tuning techniques, the measured locking range is 4.7 GHz (20.9%) from 20.1 to 24.8 GHz. The phase deviation of the quadrature output is less than 0.72 .
Autors: Lin, Y.-S.;Wu, C.-H.;Lu, C.-L.;Wang, Y.-H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2014, volume: 24, issue:4, pages: 260 - 262
Publisher: IEEE
 
» A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface
Abstract:
A 800 Mb/s to 3.2 Gb/s memory interface is designed that achieves 30% improved energy efficiency by eliminating idle mode power completely. The link is similar to a standard DDR architecture with the addition of a fast-lock DLL on the memory side that wakes up from 0 mW and locks within 3 clock cycles consuming 24 mW with residual timing error less than 33 mUI. Following initial lock, the DLL operates in a closed loop to compensate for V,T drift consuming 6 mW @ 1.6 GHz including a replica buffer. By incorporating an injection locked oscillator inside the loop, the DLL provides PLL like high frequency input jitter filtering, and corrects ±10% DCD without an additional duty cycle correction loop.
Autors: Hossain, M.;Aquil, F.;Chau, P.S.;Tsang, B.;Le, P.;Wei, J.;Stone, T.;Daly, B.;Tran, C.;Eble, J.C.;Knorpp, K.;Zerbe, J.L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2014, volume: 49, issue:4, pages: 1048 - 1062
Publisher: IEEE
 
» A Fast-Performing Error Simulation of Wideband Radiation Patterns for Large Planar Phased Arrays With Overlapped Subarray Architecture
Abstract:
We present an efficient solution for the fast computation of wideband radiation patterns of large planar arrays with overlapped subarray architecture, subject to beamforming errors. We obtain very good results fully hosting the simulation on a desktop platform, and even better results implementing a small portion of code on commercially-available graphical processing units (GPUs). Errors can be introduced throughout the beamforming chain and include random phase/magnitude errors, element failures, and surface deformation errors. At the core of the computational architecture are interchangeable primitives that quickly compute the entire far-field subarray pattern, subject to errors and user-defined tapers. The primitives are routines that address the general case of arrays with non-uniformly spaced elements (to model surface distortion) and the special case of arrays with uniformly-spaced elements. Both grid-type primitives are CPU hosted, while only the general non-uniform grid primitive type is GPU hosted due to its excellent run-time performance. The simulation quickly generates wideband patterns for the entire forward-looking hemisphere with sufficient resolution to accurately evaluate directivity and sidelobe metrics. Using only the non-uniform grid type hosted on the GPU, we show significant run-time improvement over both CPU-hosted implementations: 18.0 over the general non-uniform grid and 5.7 over the uniform grid.
Autors: Ricciardi, G.F.;Connelly, J.R.;Krichene, H.A.;Ho, M.T.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Apr 2014, volume: 62, issue:4, pages: 1779 - 1788
Publisher: IEEE
 
» A Feasible and Easy-to-Implement Anticollision Algorithm for the EPCglobal UHF Class-1 Generation-2 RFID Protocol
Abstract:
Dynamic frame slotted Aloha (DFSA) has been widely adopted to solve the anticollision problem in a radio frequency identification (RFID) system. In a DFSA procedure, the interrogator needs to continuously estimate tag backlog and select a new frame length for identifying the backlog. Intuitively, the accuracy of the tag estimator will affect the read performance. Hence, a considerable amount of research effort has been invested to improve the accuracy of backlog estimation. The improvement in general comes at the expense of large computation load and may lead to a serious challenge if one needs to implement such a kind of estimators in a real RFID system. This paper analyzes the influence of estimation error on read performance. Based on the analysis, we propose a feasible and easy-to-implement anticollision algorithm. Our proposed algorithm can achieve a normalized throughput of 35% that is very close to the theoretical maximum 36.1% for an EPCglobal UHF Class-1 Generation-2 system. The easy-to-implement advantage of our algorithm comes at the expense of only 1% reduction in normalized throughput as compared with the case where maximum throughput can be obtained. The results obtained are useful in designing fast and efficient interrogators.
Autors: Chen, W.-T.;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Apr 2014, volume: 11, issue:2, pages: 485 - 491
Publisher: IEEE
 
» A field theory of piezoelectric media containing dislocations
Abstract:
A field theory is proposed to extend the standard piezoelectric framework for linear elastic solids by accounting for the presence and motion of dislocation fields and assessing their impact on the piezoelectric properties. The proposed theory describes the incompatible lattice distortion and residual piezoelectric polarization fields induced by dislocation ensembles, as well as the dynamic evolution of these fields through dislocation motion driven by coupled electro-mechanical loading. It is suggested that (i) dislocation mobility may be enhanced or inhibited by the electric field, depending on the polarity of the latter, (ii) plasticity mediated by dislocation motion allows capturing long-term time-dependent properties of piezoelectric polarization. Due to the continuity of the proposed electro-mechanical framework, the stress/strain and polarization fields are smooth even in the dislocation core regions. The theory is applied to gallium nitride layers for validation. The piezoelectric polarization fields associated with bulk screw/edge dislocations are retrieved and surface potential modulations are predicted. The results are extended to dislocation loops.
Autors: Taupin, V.;Fressengeas, C.;Ventura, P.;Lebyodkin, M.;Gornakov, V.;
Appeared in: Journal of Applied Physics
Publication date: Apr 2014, volume: 115, issue:14, pages: 144902 - 144902-8
Publisher: IEEE
 
» A field-programmable-gate-array based time digitizer for the time-of-flight mass spectrometry
Abstract:
The time-of-flight (TOF) mass spectrometry is one of the most widely used techniques to get information about the composition and structure of compounds. The time digitizer, based on time-to-digital conversion, is one of the important parts in modern TOF mass spectrometry, which is often implemented with analog circuitry or application-specific-integrated-circuit (ASIC) devices. However, it is difficult to achieve a high density with the analog approach. Furthermore, ASIC requires a long design cycle and the function cannot be easily revised for different applications. In this work, we present a highly flexible, accurate, yet low-costing design of time digitizer which is based on a field-programmable-gate-array (FPGA) and time interpolation method. Test results indicate that the bin size of this time digitizer is 390 ps with an average standard deviation (about 150 ps). The differential nonlinearity is in the range of −0.10 to +0.05 LSB (least significant bit), and the measurement time range is larger than 107 s. Compared with other techniques, it reduces the system complexity while providing a good flexibility. In addition, this technique can also accommodate one or more STOP pulse measurements for each START pulse reference, enabling measurement of multiple times-of-flight with a common start trigger. Besides, a time stamp is recorded for each input pulse, rendering this time digitizer versatile in other applications. Moreover, because of the programmable characteristic of a FPGA, more functions can be integrated in the time digitizer, such as a trigger function, data transfer interface; the parameters such as the number of the channels. The measurement range can also be modified according to different requirements.
Autors: Ye, Chunfeng;Zhao, Lei;Zhou, Zhongyue;Liu, Shubin;An, Qi;
Appeared in: Review of Scientific Instruments
Publication date: Apr 2014, volume: 85, issue:4, pages: 045115 - 045115-7
Publisher: IEEE
 
» A Final Word about Stories
Abstract:
It was May 2010 when my "call for insights" first appeared in this magazine. For nearly four years, you, gentle readers, have responded to that call and have shared your experiences, challenges, and learnings. I appreciate all of you who submitted, who revised and responded to shepherding, but especially, all who stayed the course and produced a published article. This article is my farewell to the series, but it will continue on even though I'm no longer steering it. If you haven't yet submitted something for publication, I encourage you to do that. We need to hear your insights!
Autors: Rising, Linda;
Appeared in: IEEE Software
Publication date: Apr 2014, volume: 31, issue:2, pages: 14 - 17
Publisher: IEEE
 
» A Force and Displacement Self-Sensing Piezoelectric MRI-Compatible Tweezer End Effector With an On-Site Calibration Procedure
Abstract:
This paper describes a self-sensing technique for a piezoelectrically driven magnetic resonance imaging (MRI)-compatible tweezer style end effector, suitable for robot assisted MRI guided surgery. Nested strain amplification mechanisms are used to amplify the displacement of the piezo actuators to practical levels for robotics. By using a hysteretic piezoelectric model and a two port network model for the compliant nested strain amplifiers, it is shown that force and displacement at the tweezer tip can be estimated if the input voltage and charge are measured. One piezo unit is used simultaneously as a sensor and an actuator, preserving the full actuation capability of the device. An on-site calibration procedure is proposed that calibrates the combined electromechanical model without requiring specific loading conditions on the inner piezoelectric actuators. Experimental validation shows an average of 12% error between the self-sensed and true values.
Autors: McPherson, T.;Ueda, J.;
Appeared in: IEEE/ASME Transactions on Mechatronics
Publication date: Apr 2014, volume: 19, issue:2, pages: 755 - 764
Publisher: IEEE
 
» A Fragile Watermarking Algorithm for Hologram Authentication
Abstract:
A fragile watermarking algorithm for hologram authentication is presented in this paper. In the proposed algorithm, the watermark is embedded in the discrete cosine transform (DCT) domain of a hologram. The watermarked hologram is stored in spatial domain with finite precision level. By enhancing the precision for storing the watermarked hologram pixels, the distortion produced by the proposed watermarking scheme can be lowered. While providing high perceptual transparency, the proposed algorithm also attains high performance detection to delivery errors and malicious tampering. Experimental results reveal that the proposed algorithm can be used as an effective filter for blocking polluted or tampered holograms from 3D magnitude and/or phase reconstruction.
Autors: Chau-Jern Cheng;Wen-Jyi Hwang;Han-Yi Zeng;Yu-Chih Lin;
Appeared in: Journal of Display Technology
Publication date: Apr 2014, volume: 10, issue:4, pages: 263 - 271
Publisher: IEEE
 
» A Framework for Estimating Driver Decisions Near Intersections
Abstract:
We present a framework for the estimation of driver behavior at intersections, with applications to autonomous driving and vehicle safety. The framework is based on modeling the driver behavior and vehicle dynamics as a hybrid-state system (HSS), with driver decisions being modeled as a discrete-state system and the vehicle dynamics modeled as a continuous-state system. The proposed estimation method uses observable parameters to track the instantaneous continuous state and estimates the most likely behavior of a driver given these observations. This paper describes a framework that encompasses the hybrid structure of vehicle–driver coupling and uses hidden Markov models (HMMs) to estimate driver behavior from filtered continuous observations. Such a method is suitable for scenarios that involve unknown decisions of other vehicles, such as lane changes or intersection access. Such a framework requires extensive data collection, and the authors describe the procedure used in collecting and analyzing vehicle driving data. For illustration, the proposed hybrid architecture and driver behavior estimation techniques are trained and tested near intersections with exemplary results provided. Comparison is made between the proposed framework, simple classifiers, and naturalistic driver estimation. Obtained results show promise for using the HSS–HMM framework.
Autors: Gadepally, V.;Krishnamurthy, A.;Ozguner, U.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Apr 2014, volume: 15, issue:2, pages: 637 - 646
Publisher: IEEE
 
» A Framework for Wide-Area Monitoring and Control Systems Interoperability and Cybersecurity Analysis
Abstract:
Wide-area monitoring and control (WAMC) systems are the next-generation operational-management systems for electric power systems. The main purpose of such systems is to provide high resolution real-time situational awareness in order to improve the operation of the power system by detecting and responding to fast evolving phenomenon in power systems. From an information and communication technology (ICT) perspective, the nonfunctional qualities of these systems are increasingly becoming important and there is a need to evaluate and analyze the factors that impact these nonfunctional qualities. Enterprise architecture methods, which capture properties of ICT systems in architecture models and use these models as a basis for analysis and decision making, are a promising approach to meet these challenges. This paper presents a quantitative architecture analysis method for the study of WAMC ICT architectures focusing primarily on the interoperability and cybersecurity aspects.
Autors: Chenine, M.;Ullberg, J.;Nordstrom, L.;Wu, Y.;Ericsson, G.N.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Apr 2014, volume: 29, issue:2, pages: 633 - 641
Publisher: IEEE
 
» A Frequency Synchronization Method for a Self-Oscillating PWM Signal Generator
Abstract:
This brief proposes a frequency synchronization method for a full-digital self-oscillating pulsewidth modulation (PWM) signal generator. The self-oscillating PWM signal generator (PSG) generates a variable switching frequency, which results in poor drive performance for a three-phase power inverter or converter. The proposed frequency synchronization method utilizes an additional carrier signal, such as a triangular wave, to fix the switching frequency of a self-oscillating PSG. The switching frequency is synchronized by the triangular wave. As a test case, a switching frequency of 312.5 kHz is used for a performance evaluation of the proposed PSG with a sampling frequency of 12.5 MHz. A first-order noise-shaped output has been obtained. A high-precision PWM signal with low distortion and high resolution of the effective duty cycle has been achieved within the bandwidth. The proposed synchronized self-oscillating PSG is implemented in a three-phase brushless dc motor driver system to confirm the three-phase synchronization performance. Undesirable ripple current from asynchronous operation was not observed. The switching frequencies were synchronized among the three phases.
Autors: Li, W.;Niimi, Y.;Orino, Y.;Hirata, S.;Kurosawa, M.K.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2014, volume: 61, issue:4, pages: 244 - 248
Publisher: IEEE
 

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