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Electrical and Electronics Engineering publications abstract of: 04-2012 sorted by title, page: 0
» "Fair-Share" for Fair Bandwidth Allocation in Cloud Computing
Abstract:
Current mechanisms for controlling network resources cannot prevent users from interfering with each other in a shared cloud environment. Proposals made to rectify this, use mechanisms which require interrupts with high timing precision, and usually unevenly distribute bandwidth to TCP flows. We propose the use of an alternative mechanism to manage network resources and compare the performance of both.
Autors: Doyle, Joseph;Shorten, Robert;O'Mahony, Donal;
Appeared in: IEEE Communications Letters
Publication date: Apr 2012, volume: 16, issue:4, pages: 550 - 553
Publisher: IEEE
 
» "Please rush all possible assistance" [History]
Abstract:
When the RMS Titanic scraped an iceberg on the night of 14 April 1912, its wireless operators began sending distress calls on one of the world's most advanced radios: a 5-kilowatt rotary spark transmitter that on a clear night could send signals from the middle of the Atlantic to New York City or London. The equipment was owned by Marconi's Wireless Telegraph Co. and operated by two of its employees, Jack Phillips and Harold Bride.
Autors: Magoun, A.B.;
Appeared in: IEEE Spectrum
Publication date: Apr 2012, volume: 49, issue:4, pages: 22 - 23
Publisher: IEEE
 
» “Organic CantiFET”: A Nanomechanical Polymer Cantilever Sensor With Integrated OFET
Abstract:
Nanomechanical cantilever based biochemical sensors translate molecular interactions into nanomechanical motions that can be measured by different transduction techniques. Improved sensitivity, reliability, and also cost effectiveness of such sensor platforms have been achieved by the use of polymer materials, along with the employment of smart and compatible transduction techniques. This paper explores an ultrasensitive nanomechanical cantilever sensor platform with a novel transduction technique by integrating a strain-sensitive organic field-effect transistor within a polymer nanomechanical cantilever. This sensor, named as “organic CantiFET,” has a surface stress sensitivity of 401 with a low-noise floor. This categorizes the organic CantiFET as an efficient biochemical sensor having a minimum detectable surface stress in the range of 0.18 mN/m. [2011-0141]
Autors: Seena, V.;Nigam, A.;Pant, P.;Mukherji, S.;Rao, V. R.;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Apr 2012, volume: 21, issue:2, pages: 294 - 301
Publisher: IEEE
 
» 'Fingerprinting for food stamps' row triggers North American privacy debate
Abstract:


Autors:
Appeared in: Biometric Technology Today
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 'Tis Not! 'Tis So! [From the Editor's Desk]
Abstract:
Autors: Wood, J.;
Appeared in: IEEE Microwave Magazine
Publication date: Apr 2012, volume: 13, issue:2, pages: 6 - 6
Publisher: IEEE
 
» 0.5V bulk-driven analog building blocks
Abstract:


Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 1-50-MHz VHF electromagnetic sensor-interface power-attenuation detector circuit
Abstract:


Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor
Abstract:
We present a resonant adiabatic mixed-signal 128 × 256 array processor that achieves the energy efficiency of 1.1 TMACS (1012 multiply accumulates per second) per mW of power operating from a 1.6 V DC supply. The 1.9 μm × 9 μm 3T NMOS unit cell with a single-wire pitch multiplexed bit/compute line provides charge-conserving 1b-1b multiplication and single-node charge-domain analog accumulation. A stochastic data modulation scheme minimizes on-chip capacitance variability maintaining sinusoidal clock oscillations near resonance.
Autors: Karakiewicz, R.;Genov, R.;Cauwenberghs, G.;
Appeared in: IEEE Sensors Journal
Publication date: Apr 2012, volume: 12, issue:4, pages: 785 - 792
Publisher: IEEE
 
» 1/f noise of Josephson-junction-embedded microwave resonators at single photon energies and millikelvin temperatures
Abstract:
We present measurements of 1/f frequency noise in both linear and Josephson-junction-embedded superconducting aluminum resonators in the low power, low temperature regime—typical operating conditions for superconducting qubits. The addition of the Josephson junction does not result in additional frequency noise, thereby placing an upper limit for fractional critical current fluctuations of 1×10-8 (
1/
 Hz
) at 1 Hz for sub-micron, shadow evaporated junctions. These values imply a minimum dephasing time for a superconducting qubit due to critical current noise of 40–1400  μs depending on qubit architecture. Occasionally, at temperatures above 50 mK, we observe the activation of individual fluctuators which increase the level of noise significantly and exhibit Lorentzian spectra.
Autors: Murch, K. W.;Weber, S. J.;Levenson-Falk, E. M.;Vijay, R.;Siddiqi, I.;
Appeared in: Applied Physics Letters
Publication date: Apr 2012, volume: 100, issue:14, pages: 142601 - 142601-3
Publisher: IEEE
 
» 100GbE and beyond for warehouse scale computing interconnects
Abstract:


Autors:
Appeared in: Optical Fiber Technology
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 18/20 T high magnetic field scanning tunneling microscope with fully low voltage operability, high current resolution, and large scale searching ability
Abstract:
We present a home-built 18/20 T high magnetic field scanning tunneling microscope (STM) featuring fully low voltage (lower than ±15 V) operability in low temperatures, large scale searching ability, and 20 fA high current resolution (measured by using a 100 GOhm dummy resistor to replace the tip-sample junction) with a bandwidth of 3.03 kHz. To accomplish low voltage operation which is important in achieving high precision, low noise, and low interference with the strong magnetic field, the coarse approach is implemented with an inertial slider driven by the lateral bending of a piezoelectric scanner tube (PST) whose inner electrode is axially split into two for enhanced bending per volt. The PST can also drive the same sliding piece to inertial slide in the other bending direction (along the sample surface) of the PST, which realizes the large area searching ability. The STM head is housed in a three segment tubular chamber, which is detachable near the STM head for the convenience of sample and tip changes. Atomic resolution images of a graphite sample taken under 17.6 T and 18.0001 T are presented to show its performance.
Autors: Li, Quanfeng;Wang, Qi;Hou, Yubin;Lu, Qingyou;
Appeared in: Review of Scientific Instruments
Publication date: Apr 2012, volume: 83, issue:4, pages: 043706 - 043706-5
Publisher: IEEE
 
» 19% Efficient Thin-Film Crystalline Silicon Solar Cells From Layer Transfer Using Porous Silicon: A Loss Analysis by Means of Three-Dimensional Simulations
Abstract:
We present a study about loss analysis in both-sides-contacted silicon solar cells from a porous silicon (PSI) layer transfer process. Experimental results achieved by a variation of the rear-side contact geometry are characterized by different techniques such as electroluminescence and quantum efficiency measurements and reproduced by 3-D simulations using Sentaurus Device. Since such a device simulation does not include resistive losses in the metallization, we use a network simulation to account for losses caused by the grid. Considering the optimal contact geometry, the simulations indicate the power losses in the emitter, at the rear-side contacts, in the base, and in the metallization grid to be in the same order of magnitude.
Autors: Petermann, J. H.;Ohrdes, T.;Altermatt, P. P.;Eidelloth, S.;Brendel, R.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Apr 2012, volume: 59, issue:4, pages: 909 - 917
Publisher: IEEE
 
» 19-Gb/s adaptively modulated optical OFDM transmission by separated I/Q baseband delivery using 1GHz RSOAs
Abstract:


Autors:
Appeared in: Optical Fiber Technology
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 2011 EuroSimE international conference on thermal, mechanical and multi-physics simulation and experiments in micro-electronics and micro-systems
Abstract:


Autors:
Appeared in: Microelectronics Reliability
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 2012 top 10 tech cars
Abstract:
When people dream about the future of driving, they picture hundreds of millions of cars humming almost imperceptibly on batteries or fuel cells, their power plants emitting water vapor or nothing. Rarely does petroleum fuel-and foul-the green fantasy. But don't let that vision distract you from reality. Although the world's biggest automakers are determined to bring electrified cars to the masses, their real business-and the world's business-will continue to revolve around the internal combustion engine for decades to come. The signs are accumulating: Morgan Stanley now projects that just 4.5 percent of new cars sold in 2025 will be EVs, sharply down from its previous estimate of 8.6 percent.
Autors: Ulrich, L.;
Appeared in: IEEE Spectrum
Publication date: Apr 2012, volume: 49, issue:4, pages: 44 - 55
Publisher: IEEE
 
» 20nm Gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2 source/drain
Abstract:


Autors:
Appeared in: Solid-State Electronics
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 2D Phononic Crystal Sensor with Normal Incidence of Sound
Abstract:


Autors:
Appeared in: Sensors and Actuators A: Physical
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 3-D Face Recognition With Local Shape Descriptors
Abstract:
In this paper, we present a novel automatic approach based on local shape descriptors to discriminate 3-D facial scans of different individuals. Our approach begins with registration, smoothing and uniform resampling of 3-D face data. Then, uniformly resampled 3-D face data are used to generate shape index, curvedness, gaussian and mean curvature values on each point of the data. Hence we obtain 2-D matrices of shape index, curvedness, gaussian and mean curvature values representing 3-D geometry information. SIFT descriptors are applied to 2-D matrices and high dimensional feature vector having shape information is obtained. Finally, high dimensional feature vector is projected to the low dimensional subspace where projection matrix is calculated by linear discriminant analysis. Features in this low dimensional subspace are compared by using cosine distance similarity metric. Proposed method is shown to have 98.35% and 98.25% detection rates at 0.001 false alarm rate for All vs. All and ROC3 experiments respectively on FRGC v2.0 database. To the best of our knowledge, these are the best results among similar studies available in 3-D face recognition literature.
Autors: Inan, T.;Halici, U.;
Appeared in: IEEE Transactions on Information Forensics and Security
Publication date: Apr 2012, volume: 7, issue:2, pages: 577 - 587
Publisher: IEEE
 
» 3-D Generic Elastic Models for Fast and Texture Preserving 2-D Novel Pose Synthesis
Abstract:
This paper provides an in-depth analysis on face shape alignment for pose insensitive face recognition. The dissimilarity between two face images can be modeled as the difference in intensity between these two images, obtained by warping these faces onto the same shape. In order to achieve this, we must first align both face images independently to obtain a sparse 2-D shape representation. We achieve this by using a Combination of ASMs and AAMs (CASAAMs). We then exchange these two shapes and obtain new intensity (texture) faces based on these exchanged shapes. This allows us to align the two faces with increased pixel-level correspondence while simultaneously achieving a certain degree of pose correction. In order to account for large pose variation, it becomes necessary to model the underlying 3-D face structure for the synthesis of novel 2-D poses. However, in many real-world scenarios, only a single image of the subject is provided and acquisition of the 3-D model is not always feasible. To tackle this common real-world scenario, we propose a novel approach for modeling faces, called 3D Generic Elastic Model (3D-GEM), which can be deformed from a single 2-D image. Our analysis shows that 3-D depth information of human faces does not dramatically change across people, indicating that precise depth information of a person is not needed to generate useful novel 2-D poses. This is a significant discovery that makes our method feasible. We thus demonstrate that our 3-D face model can be efficiently produced by using a generic depth model which can be elastically deformed based on input facial features. This face model can then be rotated in 3-D in order to synthesize any arbitrary 2-D facial pose. Experimental results show that 3-D faces modeled by our proposed work effectively handle large 3-D pose changes in face alignment and they can be used for achieving pose tolerant face recognition. We also provide comparative results of face synthesis obtained by an actual - -D face scanner and our approach, showing our proposed modeling approach is both effective and efficient.
Autors: Heo, J.;Savvides, M.;
Appeared in: IEEE Transactions on Information Forensics and Security
Publication date: Apr 2012, volume: 7, issue:2, pages: 563 - 576
Publisher: IEEE
 
» 3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 3D MIMO-OFDM Channel Estimation
Abstract:
In this paper bandwidth efficient pilot design for a MIMO-OFDM downlink is addressed. By exploiting the spatial correlation of signals originating from neighboring transmit antennas, the principle of pilot aided channel estimation (PACE) by two-dimensional (2D) interpolation in time and frequency is extended to the spatial domain; giving rise to three-dimensional (3D) PACE. By invoking the multi-dimensional sampling theorem conditions for regular pilot patterns to attain minimum overhead are derived. Provided sufficient spatial correlation 3D-PACE reduces pilot overhead by 50% compared to conventional 2D-PACE. Unfortunately, spatial correlation may not be universally available: while for outdoor macro-cells, where transmit antennas are typically mounted above rooftop, the assumption of spatially correlated channels is justified, in indoor deployments where spatial correlation tends to be low, spatial interpolation may not be feasible. On the other hand, in indoor environments cell sizes together with mobile velocities are substantially smaller, giving rise to lower Doppler and channel delay spreads. We show that a sophisticated pilot design is able to retain the low pilot overhead of 3D-PACE by exploiting these heterogeneous correlation properties, in the way that high spatial correlation compensates for low correlation in time and/or frequency, and vice versa.
Autors: Auer, Gunther;
Appeared in: IEEE Transactions on Communications
Publication date: Apr 2012, volume: 60, issue:4, pages: 972 - 985
Publisher: IEEE
 
» 3D thermal-aware floorplanner using a MILP approximation
Abstract:


Autors:
Appeared in: Microprocessors and Microsystems
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 40 Gb/s and 100 Gb/s ethernet short-reach optical and copper host board channel design
Abstract:
Since its inception in the early ??70s, Ethernet has gradually displaced other popular standards, such as token-ring, while becoming the de facto standard for local area networks in the enterprise office and data center environments. During Ethernet??s lifetime, data rates have increased from the original 10 Mb/s to 10 Gb/s. Now, 40 Gb/s and 100 Gb/s standards have been defined, ushering in the next generation of equipment and components. This article presents the challenges of designing 40 Gb/s and 100 Gb/s Ethernet host board channels that are targeted for data center applications. The data center infrastructure comprises: a short-reach optical multimode fiber of length 100 m or less; and/or a copper twinax shielded cable of length 7 m or less, to interconnect collocated communication equipment racks. The recently published 40 Gb/s and 100 Gb/s Ethernet standard specifies the copper interfaces (CR4/CR10) and the short-reach optical nonretimed optical interfaces (SR4/SR10). This article reviews the Ethernet copper and fiber short-reach application compliance test techniques, and identifies common specifications and areas of divergence for both applications. Cable specifications and its insertion loss budget are also reviewed, providing conclusions that will aid the communications equipment and components manufacturer with a clear reference to address the design and implementation of a standards-compliant product.
Autors: Rabinovich, R.;
Appeared in: IEEE Communications Magazine
Publication date: Apr 2012, volume: 50, issue:4, pages: 129 - 133
Publisher: IEEE
 
» 40-Gb/s All-Optical Clock Recovery Based on an Mode-Locked Semiconductor Fiber Laser Using Nonlinear Polarization Rotation
Abstract:
We demonstrate all-optical clock recovery (AOCR) of 40-Gb/s return-to-zero on–off keying signals using nonlinear polarization rotation in a mode-locked semiconductor fiber laser (ML-SFL). First, we characterize the ML-SFL, which serves as the basis for AOCR. Next, we analyze the recovered clock properties (in particular, the root-mean-square timing jitter and power fluctuations) as a function of the input-signal characteristics. The results show that the approach can recover a good quality clock over a large range of input signal characteristics.
Autors: Huang, T.;Sun, J.;Li, J.;Chen, L. R.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Apr 2012, volume: 24, issue:8, pages: 682 - 684
Publisher: IEEE
 
» 42-GHz 0.5-MW ECRH System for Tokamaks SST-1 and Aditya
Abstract:
A 42-GHz electron cyclotron resonance heating (ECRH) system will be used to carry out preionization and start-up experiments on tokamaks SST-1 and Aditya. The system would give reliable start-up in the SST-1 tokamak at 1.5-T operating toroidal magnetic field. The fundamental O-mode will be launched from the low-field side of the tokamak. The same system will be used in tokamak Aditya to carry out second-harmonic ECRH-assisted breakdown experiments at 0.75-T operation. The gyrotron capable of delivering 500-kW power will be installed such that it will deliver power to both the tokamaks without dismantling any component. An approximately 50-m-long transmission line will be used to transmit power from the gyrotron to each tokamak. The total transmission loss in the line is less than 20%; in this case, we can launch 400-kW power to carry out reliable ECRH-assisted breakdown experiments at the fundamental and second harmonics. The launcher design is different for both the tokamaks. In Aditya, due to space restriction, a simple waveguide-type launcher is used to launch ECRH power in X-mode at the second harmonic. In the SST-1 tokamak, there are two options to launch ECRH power: 1) from the radial port and 2) from the top port. From the radial port, a conventional ECRH launcher consisting of two mirrors (one focusing and one plane) would be used; however, from the top port, one mirror would be used along with a corrugated waveguide. The VME-based data acquisition and control system will be used for the 42-GHz ECRH system. The slow interlocks would be activated through software while the fast interlocks would be hardwired to remove the high voltage within 10 . This paper discusses the physics and technical aspect of the 42-GHz ECRH system and preliminary design of launchers for SST-1 and Aditya.
Autors: Shukla, B. K.;Bora, D.;Goswami, R.;Babu, R.;Patel, J.;Chattopadhyay, P. K.;Srinivasan, R.;Patel, H.;Dhorajia, P.;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Apr 2012, volume: 40, issue:4, pages: 1234 - 1238
Publisher: IEEE
 
» 5-11GHz CMOS PA with 158.941ps group delay and low power using current-reused technique
Abstract:


Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» 60 GHz SiGe:C HBT Power Amplifier With 17.4 dBm Output Power and 16.3% PAE
Abstract:
Single stage cascode power amplifier for 60 GHz band is presented in this letter. Modeling methodology, together with effects of (im)proper local interconnect modeling on achievable output power is discussed. Design partitioning is proposed to reduce the complexity of EM models, while retaining the accuracy of simulation. Test chip was fabricated in a 0.25 m BiCMOS SiGe:C HBT technology with 200/200 GHz , and measured on-wafer. Measurement results are in close agreement with simulation, validating our modeling approach. Saturated output power of 17.4 dBm and peak PAE of 16.3% was measured at 61.5 GHz. Small signal measurements indicate that the PA covers the whole unlicensed 60 GHz band.
Autors: Grujic, D.;Savic, M.;Bingol, C.;Saranovac, L.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2012, volume: 22, issue:4, pages: 194 - 196
Publisher: IEEE
 
» 7 Billion Milestone [From the Editor's Desk]
Abstract:
Autors: Floyd, L.;
Appeared in: IEEE Industry Applications Magazine
Publication date: Apr 2012, volume: 18, issue:2, pages: 2 - 2
Publisher: IEEE
 
» 802.11a Compliant Spatial Diversity Receiver IC in BiCMOS
Abstract:
This paper presents an integrated 802.11a compliant receiver integrated circuit (IC), which is capable of processing four antenna signals using RF multiple-input multiple-output (RF-MIMO) schemes. Following four low-noise amplifiers, the weighting is performed using Cartesian vector modulators, whose output signals are combined and down-converted. The baseband filters, variable gain amplifiers (VGAs), a quadrature voltage-controlled oscillator, and digital interfaces are integrated. Experimental results demonstrate the performance of the individual components, as well as the RF-MIMO capabilities of the whole chip. The IC achieves a receiver noise figure of 3.6 dB, a phase noise of at 1-MHz offset, and an equivalent Cartesian weighting precision of 6 6 bit. An RF input signal of up to (1-dB compression) can be processed, while the maximum RF path gain amounts to 28.6 dB. The baseband VGA provides further 9–61-dB gain in 64 steps.
Autors: Wickert, M.;Mayer, U.;Ellinger, F.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Apr 2012, volume: 60, issue:4, pages: 1097 - 1104
Publisher: IEEE
 
» 9-GHz Wideband CMOS RX and TX Front-Ends for Universal Radio Applications
Abstract:
Wideband receiver (RX) and transmitter (TX) RF front-ends for wireless universal radio applications are presented. The RX is comprised of a two-stage low-noise amplifier (LNA) applying feedback and shunt peaking, a combiner buffer for performance boosting, and an inverter-based in-phase/quadrature (IQ) down-conversion mixer. The wideband LNA provides input matching of better than from dc to beyond 10 GHz. The conversion gain (CG) of the RX front-end has a peak value of 31 dB with a 3-dB bandwidth up to 9 GHz. The minimal noise figure is 6 dB and kept below 9 dB within the entire operational bandwidth. The RX has a linearity in terms of intermodulation distortion of better than . The direct conversion TX involving inverter-based IQ modulator and Darlington-type pre-power amplifier features operation up to 9 GHz with 10-dB mean CG and an average output power of 4 dBm at 1-dB compression level. Excluding buffers and local oscillator generation, the RX and TX dissipate 54 and 84 mW, respectively, from a 1.2-V voltage supply. The circuit prototypes have been fabricated in a standard 65-nm CMOS low-power process without any additional RF options and occupy an area of only 0.77 and 0.53 , respectively.
Autors: Hampel, S. K.;Schmitz, O.;Tiebout, M.;Mertens, K.;Rolfes, I.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Apr 2012, volume: 60, issue:4, pages: 1105 - 1116
Publisher: IEEE
 
» Pattern Run-Length for Test Data Compression
Abstract:
This paper presents a new pattern run-length compression method whose decompressor is simple and easy to implement. It encodes runs of compatible or inversely compatible patterns, either inside a single test data segment or across multiple test data segments. Experimental results show that it can achieve an average compression ratio of 67.64% and considerable test application time savings.
Autors: Lee, L.-J.;Tseng, W.-D.;Lin, R.-B.;Chang, C.-H.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Apr 2012, volume: 31, issue:4, pages: 644 - 648
Publisher: IEEE
 
» Laser Power Converter With Undercut Mesa for Simultaneous High-Speed Data Detection and DC Electrical Power Generation
Abstract:
We demonstrate novel high-speed laser power converters (LPCs), which not only can detect the envelope of incoming high-speed optical data but also can efficiently convert its optical dc component to dc electrical power. By utilizing the graded p-type GaAs and n-type layers as photoabsorption (P) and collector (C) layers, respectively, the problem of slow-motion holes under 830-nm-optical-wavelength excitation and the conduction-band-offset-induced electron blocking effect between the P/C layers, which seriously limit the high-speed performance of LPC, can both be eliminated. Furthermore, by using the undercut mesa structure of the C layer to further reduce the large junction capacitance under forward operation, we can achieve invariable high-speed performance ( 9 GHz) from zero to near turn-on voltage ( 0.8 V), which corresponds to the operation point of our LPC with the maximum power conversion efficiency ( 15%).
Autors: Shi, J.-W.;Tsai, C.-Y.;Yang, C.-S.;Kuo, F.-M.;Hsin, Y.-M.;Bowers, J. E.;Pan, C.-L.;
Appeared in: IEEE Electron Device Letters
Publication date: Apr 2012, volume: 33, issue:4, pages: 561 - 563
Publisher: IEEE
 
» Pattern Run-Length for Test Data Compression
Abstract:
This paper presents a new pattern run-length compression method whose decompressor is simple and easy to implement. It encodes 2|n| runs of compatible or inversely compatible patterns, either inside a single test data segment or across multiple test data segments. Experimental results show that it can achieve an average compression ratio of 67.64% and considerable test application time savings.
Autors: Lung-Jen Lee;Wang-Dauh Tseng;Rung-Bin Lin;Cheng-Ho Chang;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Apr 2012, volume: 31, issue:4, pages: 644 - 648
Publisher: IEEE
 
» Laser Power Converter With Undercut Mesa for Simultaneous High-Speed Data Detection and DC Electrical Power Generation
Abstract:
We demonstrate novel high-speed laser power converters (LPCs), which not only can detect the envelope of incoming high-speed optical data but also can efficiently convert its optical dc component to dc electrical power. By utilizing the graded p-type GaAs and n-type layers as photoabsorption (P) and collector (C) layers, respectively, the problem of slow-motion holes under 830-nm-optical-wavelength excitation and the conduction-band-offset-induced electron blocking effect between the P/C layers, which seriously limit the high-speed performance of LPC, can both be eliminated. Furthermore, by using the undercut mesa structure of the C layer to further reduce the large junction capacitance under forward operation, we can achieve invariable high-speed performance ( 9 GHz) from zero to near turn-on voltage ( 0.8 V), which corresponds to the operation point of our LPC with the maximum power conversion efficiency ( 15%).
Autors: Shi, J.-W.;Tsai, C.-Y.;Yang, C.-S.;Kuo, F.-M.;Hsin, Y.-M.;Bowers, J. E.;Pan, C.-L.;
Appeared in: IEEE Electron Device Letters
Publication date: Apr 2012, volume: 33, issue:4, pages: 561 - 563
Publisher: IEEE
 
» Multiple Quantum-Well Discrete-Mode Laser Diode Emitting at 2
Abstract:
A discrete-mode laser diode fabricated in the InGaAs/InP multiple quantum-well system and emitting single mode at is reported. The laser had an ex-facet output power at 25 and the laser operated mode-hop free in the temperature range .
Autors: Phelan, R.;O'Carroll, J.;Byrne, D.;Herbert, C.;Somers, J.;Kelly, B.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Apr 2012, volume: 24, issue:8, pages: 652 - 654
Publisher: IEEE
 
» A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS
Abstract:
This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40 nm CMOS process achieves 46.8 dB SNDR and 58.2 dB SFDR with 1.1 MS/sec at 0.5 V power supply. The FoM is 6.3-fJ/conversion step and the chip die area is only .
Autors: Shikata, A.;Sekimoto, R.;Kuroda, T.;Ishikuro, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 1022 - 1030
Publisher: IEEE
 
» A 1.2V, 130nm CMOS parallel continuous-time ?? ADC for OFDM UWB receivers
Abstract:


Autors:

Graphical Abstract

image
Appeared in: Microelectronics Journal
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» A 1.5-V Current Mirror Double-Balanced Mixer With 10-dBm IIP3 and 9.5-dB Conversion Gain
Abstract:
This brief presents the design of a double-balanced mixer for linearity-stringent communication systems. The proposed mixer is based on a current-mirror structure embedded with a switching pair. By utilizing the linear duplication characteristic of current mirrors, an improved linearity is achieved. The mixer is designed and fabricated in 0.18- 1P6M radio-frequency CMOS process, operating in the frequency band from 0.5 to 3 GHz. Measurement results indicate a peak conversion gain of 9.5 dB, a high input 3rd order intercept point (IIP3) of 10 dBm and a moderate noise figure (NF) of 16.5 dB. In addition, due to the folded structure, the mixer can be applicable in low-supply-voltage applications. The whole mixer has a compact die area of 0.1 , and the power dissipation is 5.4 mW under 1.5-V supply voltage.
Autors: Shi, L. X.;Chen, C.;Wu, J. H.;Zhang, M.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2012, volume: 59, issue:4, pages: 204 - 208
Publisher: IEEE
 
» A 1.6-V 25- A 5-ppm/ C Curvature-Compensated Bandgap Reference
Abstract:
A high precision high-order curvature-compensated bandgap reference (BGR) compatible with standard BiCMOS process is presented in this paper that is capable of working down to input voltages of 1.6 V with 1.285 V output voltage. High-order curvature correction for this reference is accomplished by a novel piecewise technique, which realizes exponential curvature compensation in temperature range, and a logarithmic compensation term proportional to in higher temperature range through simple structures. Experimental results of the proposed BGR implemented in 0.5- m BiCMOS process demonstrate that a temperature coefficient (TC) of 5 ppm/ C is realized at 3.6 V power supply, a power-supply noise attenuation (PSNA) of 70 dB is achieved without filtering capacitors, and the line regulation is better than 0.47 mV/V from 1.6 V to 5 V supply voltage while dissipating a maximum supply current of 25 A. The active area of the presented BGR is 180 m 220 m.
Autors: Zhou, Z.-K.;Shi, Y.;Huang, Z.;Zhu, P.-S.;Ma, Y.-Q.;Wang, Y.-C.;Chen, Z.;Ming, X.;Zhang, B.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2012, volume: 59, issue:4, pages: 677 - 684
Publisher: IEEE
 
» A 1.6-V 25- A 5-ppm/ C Curvature-Compensated Bandgap Reference
Abstract:
A high precision high-order curvature-compensated bandgap reference (BGR) compatible with standard BiCMOS process is presented in this paper that is capable of working down to input voltages of 1.6 V with 1.285 V output voltage. High-order curvature correction for this reference is accomplished by a novel piecewise technique, which realizes exponential curvature compensation in temperature range, and a logarithmic compensation term proportional to in higher temperature range through simple structures. Experimental results of the proposed BGR implemented in 0.5- m BiCMOS process demonstrate that a temperature coefficient (TC) of 5 ppm/ C is realized at 3.6 V power supply, a power-supply noise attenuation (PSNA) of 70 dB is achieved without filtering capacitors, and the line regulation is better than 0.47 mV/V from 1.6 V to 5 V supply voltage while dissipating a maximum supply current of 25 A. The active area of the presented BGR is 180 m 220 m.
Autors: Zhou, Z.-K.;Shi, Y.;Huang, Z.;Zhu, P.-S.;Ma, Y.-Q.;Wang, Y.-C.;Chen, Z.;Ming, X.;Zhang, B.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Apr 2012, volume: 59, issue:4, pages: 677 - 684
Publisher: IEEE
 
» A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS
Abstract:
This paper presents a low-power mixed-signal adaptive 60 GHz baseband in 65 nm CMOS. The design integrates variable gain amplifiers, analog phase rotator, 40-coefficient I/Q decision feedback equalizers (DFEs), clock generation and data recovery circuits, and adaptation hardware. The baseband achieves 10 Gb/s operation with while consuming 53 mW (adaptation on)/45 mW (adaptation off), of which the core signal processing circuits consume only 29 mW.
Autors: Thakkar, C.;Kong, L.;Jung, K.;Frappe, A.;Alon, E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 952 - 968
Publisher: IEEE
 
» A 10 tesla table-top controlled waveform magnet
Abstract:
Controlled waveform magnets (CWMs) are a class of pulsed magnets whose pulse shape with time can be programmed by the user. With a CWM, the user gains control not only over the magnitude of the field but also over its rate of change. In this work we present a table-top CWM, driven by a capacitor bank, capable of producing virtually any user-shaped magnetic field waveform up to 10 tesla. Insulated gate bipolar transistor chips have been paralleled to form the high current switch and paralleled chips of SiC Schottky diodes form the crowbar diode module. Sample controlled waveforms including flat-tops up to 10 tesla and some triangular magnetic field pulses have been successfully generated for 10–20 ms with a ripple <1%.
Autors: Roy Choudhury, Aditya N.;Venkataraman, V.;
Appeared in: Review of Scientific Instruments
Publication date: Apr 2012, volume: 83, issue:4, pages: 045103 - 045103-7
Publisher: IEEE
 
» A 10-Bit Multichannel Digitizer ASIC for Detectors in Particle Physics Experiments
Abstract:
The design and measurement results of a multichannel power scalable 10-bit digitizer ASIC developed for the luminosity detector at the future linear colliders (ILC/CLIC) are discussed. The 8 channel prototype with different modes of output data serialization was designed and fabricated in a 0.35 m CMOS technology. The ASIC works for sampling rates from about 10 kS/s to 25 MS/s (50 MS/s in single channel mode) allowing linear scaling of ADCs and serializer power consumption (0.8 mW/MS/s ADC core, 1.2 mW/MS/s total per channel). A wide spectrum of static and dynamic measurements confirm very good ADC resolution ( bits), excellent channel uniformity and negligible crosstalk. To profit from non-continuous detector operation in linear collider experiments and to save power consumption, fast periodic power pulsing is implemented.
Autors: Idzik, M.;Swientek, K.;Fiutowski, T.;Kulis, S.;Przyborowski, D.;
Appeared in: IEEE Transactions on Nuclear Science
Publication date: Apr 2012, volume: 59, issue:2, pages: 294 - 302
Publisher: IEEE
 
» A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor
Abstract:
We demonstrate a novel adaptive look-ahead decision feedback equalizer (LADFE) that uses the measured eye diagram for equalization adaptation and verification. The eye diagram is obtained with a new type of eye-opening monitor (EOM), which measures the magnitude of the received signals having different data patterns and, using this, estimates intersymbol interference and determines the amount of adaptation needed for the LADFE. A 10-Gb/s adaptive two-tap LADFE with an EOM is fabricated in 90-nm CMOS technology. The eye diagrams for equalized signals are successfully obtained, and adaptation of the LADFE is achieved for PCB channels up to 40 cm. The LADFE core occupies and consumes 11 mW at 1.2-V supply voltage.
Autors: Seong, C.-K.;Rhim, J.;Choi, W.-Y.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2012, volume: 59, issue:4, pages: 209 - 213
Publisher: IEEE
 
» A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm and 500 mW in 40 nm Digital CMOS
Abstract:
A 12-bit 3 GS/s 40 nm two-way time-interleaved pipeline analog-to-digital converter (ADC) is presented. The proposed adaptive power/ground architecture eliminates the headroom limitations due to the deeply scaled power supply in nanometer CMOS technologies, while preserving the intrinsic speed of thin-oxide MOSFETs with minimum channel length for key analog blocks. Moreover, in terms of the signal swing, the proposed reference extrapolation scheme offers a smooth transition between the multiplying digital-to-analog converter stages and the last flash stage. With these two techniques, the ADC achieves a SNR of 61 dB and a DNL of 0.5 0.5 LSB, while consuming 500 mW at a 3 GS/s sampling rate and occupying an area of 0.4 mm in 40 nm CMOS process.
Autors: Chen, C.-Y.;Wu, J.;Hung, J.-J.;Li, T.;Liu, W.;Shih, W.-T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 1013 - 1021
Publisher: IEEE
 
» A 12-Pole K-Band Wideband High-Temperature Superconducting Microstrip Filter
Abstract:
A 12-pole wideband high-temperature superconducting (HTS) microstrip bandpass filter is reported in this paper. The filter has a center frequency of 23 GHz and a bandwidth of 4.2 GHz. The filter was fabricated on a 2-in-diameter 0.25-mm-thick MgO wafer with double-sided YBCO films. Both edge and end coupling structures were employed in this paper to achieve the desired bandwidth. An insert coupling structure was used for input/output coupling to realize the remarkably strong coupling. A microwave-absorbing material was used to eliminate cavity resonances. The measured results show a midband insertion loss of 1.3 dB, a return loss better than 9.5 dB and an out-of-band rejection of over 55 dB on both sides of the passband.
Autors: Guo, J.;Sun, L.;Zhou, S.;Bian, Y.;Wang, J.;Cui, B.;Li, C.;Zhang, X.;Li, H.;Zhang, Q.;Wang, X.;Gu, C.;He, Y.;
Appeared in: IEEE Transactions on Applied Superconductivity
Publication date: Apr 2012, volume: 22, issue:2, pages: 1500106 - 1500106
Publisher: IEEE
 
» A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface
Abstract:
This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memories at 6.4 and 1.6 Gbps, respectively, with no package change. The interface is equipped with a compact voltage-mode driver with 1-tap pre-emphasis, in the WRITE direction, and a linear equalizer (LEQ) and 1-tap decision feedback equalizer (DFE), in the READ direction, to compensate for channel inter-symbol interference (ISI). The receiver front-end contains a supply noise tracking scheme to mitigate reference voltage (VREF) noise. A tri-VCO PLL and an efficient global clock distribution scheme support a wide range of operating frequencies at low power consumption. Finally, the interface also incorporates two overhead links per byte for data-bus encoding (DBE) experiments to mitigate simultaneous switching noise (SSN). Implemented in a 40-nm CMOS process, the 16 tri-modal interface achieves an energy efficiency of better than 5.0 mW/Gbps per data link at 12.8 Gbps.
Autors: Amirkhany, A.;Wei, J.;Mishra, N. K.;Shen, J.;Beyene, W. T.;Chen, C.;Chin, T.;Dressler, D.;Huang, C.;Gadde, V. P.;Hekmat, M.;Kaviani, K.;Lan, H.;Le, P.;Mahabaleshwara,;Madden, C.;Mukherjee, S.;Raghavan, L.;Saito, K.;Secker, D.;Sendhil, A.;Schmitt, R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 911 - 925
Publisher: IEEE
 
» A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder
Abstract:
To satisfy the requirement of application heterogeneities, the latest H.264/AVC based video coding standard called scalable video coding additional includes temporal, SNR, and spatial scalabilities for frame rate, quality, and frame resolution adaptation. However, these inclusions significantly increase chip design difficulties such as decoding time, memory bandwidth, and area cost. This paper presents an H.264/AVC scalable high profile decoder realization with several optimization techniques to provide high throughput video decoding. For decoding flow, this paper proposes an one-pass macroblock-based quality layer decoding flow for SNR scalability and 71% of external memory bandwidth and 66% of macroblock processing cycles can be saved. For texture padding in interlayer intra prediction, the modified padding flow can save 26% of decoding time. For interlayer predictor design, this paper proposes a centralized concept for accumulation-based calculation of corresponding spatial position, simplified poly-phase interpolator, and efficient motion vector generator to save area cost and decoding time. Furthermore, the residual reconstruction path with the parallel-pipeline architecture is also proposed to cope with the additional decoding complexity and thus leads to 54% of gate count savings compared to the traditional serial-pipeline architecture. Finally, the proposed H.264/AVC scalable high profile decoder design is implemented with 90 nm CMOS technology and it costs 542 k gate count and 39.66 Kbytes on-chip memory while is capable to decode 60 frames/s for resolution with three quality layers at 135 MHz operating frequency.
Autors: Li, G.-L.;Chen, Y.-C.;Liao, Y.-H.;Hsu, P.-Y.;Wen, M.-H.;Chang, T.-S.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Apr 2012, volume: 22, issue:4, pages: 626 - 635
Publisher: IEEE
 
» A 15 GHz, 182 dBc/Hz/mW FOM, Rotary Traveling Wave VCO in 90 nm CMOS
Abstract:
This letter presents a phase-noise-centric design methodology of a rotary traveling wave voltage controlled oscillator (RTW VCO). Based upon this methodology, a 15 GHz multiphase RTW VCO is realized in a standard 90 nm CMOS process. Particularly, shielded coplanar striplines are exploited to provide better shielding protection and higher characteristic impedance with comparable Q-factor than conventional coupled transmission lines. Measured results of the proposed RTW VCO demonstrates the frequency tuning range of 2 GHz, the output power level of 11.3 dBm, the phase noise of 109.6 dBc/Hz at 1 MHz offset, the clock RMS jitter of 2 , and the power dissipation of 12 mW from a single 1.2-V supply. The chip core occupies the area of 0.2 .
Autors: Zhang, C.;Wang, Z.;Zhao, Y.;Park, S. M.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2012, volume: 22, issue:4, pages: 206 - 208
Publisher: IEEE
 
» A 15 GHz, 182 dBc/Hz/mW FOM, Rotary Traveling Wave VCO in 90 nm CMOS
Abstract:
This letter presents a phase-noise-centric design methodology of a rotary traveling wave voltage controlled oscillator (RTW VCO). Based upon this methodology, a 15 GHz multiphase RTW VCO is realized in a standard 90 nm CMOS process. Particularly, shielded coplanar striplines are exploited to provide better shielding protection and higher characteristic impedance with comparable Q-factor than conventional coupled transmission lines. Measured results of the proposed RTW VCO demonstrates the frequency tuning range of 2 GHz, the output power level of 11.3 dBm, the phase noise of 109.6 dBc/Hz at 1 MHz offset, the clock RMS jitter of 2 , and the power dissipation of 12 mW from a single 1.2-V supply. The chip core occupies the area of 0.2 .
Autors: Zhang, C.;Wang, Z.;Zhao, Y.;Park, S. M.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2012, volume: 22, issue:4, pages: 206 - 208
Publisher: IEEE
 
» A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
Abstract:


Autors:

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Appeared in: Computers & Electrical Engineering
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» A 1V, 69-73GHz CMOS power amplifier based on improved Wilkinson power combiner
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping TDC
Abstract:
This paper presents a low-power noise-shaping time-to-digital converter (TDC) and its application to a fractional-N digital PLL. With a simple structure of single-delay-stage modulator followed by a charge pump based modulator, a wide range of TDC input is converted to modulated single bit stream without loss of signal information. The architecture of TDC effectively improves the conversion performance of linearity and resolution while handling a large input range due to the operation of the dual-modulus divider. In addition, with a downscaling of the amount of the single delay in modulator, the signal and noise transfer characteristics of TDC can be profiled to suppress the out-band noises at the input to the loop filter, resulting in easy filtering without any extra noise cancelling scheme. The DPLL is fabricated with a 0.13 CMOS technology. With a loop bandwidth of 1 MHz, DPLL shows an in-band phase noise of 107 dBc/Hz at 500 kHz offset and an out-of-band phase noise of 118.5 dBc/Hz at 3 MHz offset. The TDC consumes 1 mA.
Autors: Jee, D.-W.;Seo, Y.-H.;Park, H.-J.;Sim, J.-Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 875 - 883
Publisher: IEEE
 
» A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder
Abstract:
This paper presents a (491,3,6) time-varying low-density parity check convolutional code (LDPC-CC) decoder chip. This work combines the algorithm level, node level, and bit level optimizations to achieve over 2 Gb/s throughput with acceptable hardware cost and power. The algorithm level optimization is the on-demand variable node activation scheduling with concealing channel values, which can not only achieve twice faster decoding convergence speed than log-belief propagation (log-BP) algorithm, but also reduce the 17% message storage capacity. The node level optimization duplicates the check node units and variable node units and unfolds the message storage first-in–first-outs (FIFOs) so that the throughput becomes twelve multiplying with clock frequency. In the meantime, the bit level optimization is employed to retime the critical path such that the higher clock frequency can be achieved and message storage size is slightly reduced. Furthermore, a novel hybrid-partitioned FIFO is proposed to provide sufficient memory bandwidth to processing units and alleviate power consumption. With these schemes, a test chip of proposed LDPC-CC decoder has been fabricated in 90 nm CMOS technology with core area of . Maximum throughput 2.37 Gb/s is measured under 1.2 V supply with energy efficiency of 0.024 nJ/bit/proc. Depending on the operation mode, power can be scaled down to 90.2 mW while maintaining 1.58 Gb/s at 0.8 V supply.
Autors: Chen, C.-L.;Lin, Y.-H.;Chang, H.-C.;Lee, C.-Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 817 - 831
Publisher: IEEE
 
» A 2.45-GHz 20-dBm Fast Switching Class-E Power Amplifier With 43% PAE and a 18-dB-Wide Power Range in 0.18- CMOS
Abstract:
In this brief, the losses in Class-E power amplifiers (PAs) with finite dc-feed inductance are analyzed. This analysis results in practical analytical expressions, which significantly simplify the design and optimization of Class-E PAs. To demonstrate their applicability, the design of a state-of-the-art 2.45-GHz differential cascode Class-E PA in 0.18- CMOS with on-chip dc-feed inductor is presented. By the proposed combination of a dynamic supply voltage and a dynamic cascode bias voltage, high drain efficiency is achieved over a wide power control range, covering from 2.2 up to 20 dBm. At 20 dBm, a power-added efficiency as high as 43.6% was measured. Additionally, fast envelope switching is obtained by adding a single switch to the common–gate nodes of both the Class-E stage and the second driver stage. Measurements show a rise time of merely 2.5 ns and a 73-dB isolation between the on- and off-states. These figures enable ranging applications with submeter accuracy.
Autors: Li, Z.;Torfs, G.;Bauwelinck, J.;Yin, X.;Vandewege, J.;Van Praet, C.;Spiessens, P.;Tubbax, H.;Stubbe, F.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2012, volume: 59, issue:4, pages: 224 - 228
Publisher: IEEE
 
» A 2.45-GHz 20-dBm Fast Switching Class-E Power Amplifier With 43% PAE and a 18-dB-Wide Power Range in 0.18- CMOS
Abstract:
In this brief, the losses in Class-E power amplifiers (PAs) with finite dc-feed inductance are analyzed. This analysis results in practical analytical expressions, which significantly simplify the design and optimization of Class-E PAs. To demonstrate their applicability, the design of a state-of-the-art 2.45-GHz differential cascode Class-E PA in 0.18- CMOS with on-chip dc-feed inductor is presented. By the proposed combination of a dynamic supply voltage and a dynamic cascode bias voltage, high drain efficiency is achieved over a wide power control range, covering from 2.2 up to 20 dBm. At 20 dBm, a power-added efficiency as high as 43.6% was measured. Additionally, fast envelope switching is obtained by adding a single switch to the common–gate nodes of both the Class-E stage and the second driver stage. Measurements show a rise time of merely 2.5 ns and a 73-dB isolation between the on- and off-states. These figures enable ranging applications with submeter accuracy.
Autors: Li, Z.;Torfs, G.;Bauwelinck, J.;Yin, X.;Vandewege, J.;Van Praet, C.;Spiessens, P.;Tubbax, H.;Stubbe, F.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2012, volume: 59, issue:4, pages: 224 - 228
Publisher: IEEE
 
» A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS
Abstract:
A low-power receiver circuit in 32 nm SOI CMOS is presented, which is intended to be used in a source-synchronous link configuration. The design of the receiver was optimized for power owing to the assumption that a link protocol enables a periodic calibration during which the circuit does not have to deliver valid data. In addition, it is shown that the transceiver power and the effect of high-frequency transmit jitter can be reduced by implementing a linear equalizer only on the receive side and avoiding a transmit feed-forward equalizer (TX-FFE). On the circuit level, the receiver uses a switched-capacitor (SC) approach for the implementation of an 8-tap decision-feedback equalizer (DFE). The SC-DFE improves the timing margin relative to previous DFE implementations with current feedback, and leads to a digital-style circuit implementation with compact layout. The receiver was measured at data rates up to 13.5 Gb/s, where error free operation was verified with a PRBS-31 sequence and a channel with 32 dB attenuation at Nyquist. With the clock generation circuits amortized over eight lanes, the receiver circuit consumes 2.6 mW/Gbps from a 1.1 V supply while running at 12.5 Gb/s.
Autors: Toifl, T.;Menolfi, C.;Ruegg, M.;Reutemann, R.;Dreps, D.;Beukema, T.;Prati, A.;Gardellini, D.;Kossel, M.;Buchmann, P.;Brandli, M.;Francese, P. A.;Morf, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 897 - 910
Publisher: IEEE
 
» A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface
Abstract:
A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed.
Autors: Kim, C. B.;Ryu, J. R.;Lee, T. S.;Kim, H. G.;Lim, J. W.;Jeong, J. Y.;Seo, S. H.;Jeon, H. S.;Kim, B. K.;Lee, I. Y.;Lee, D. S.;Kwak, P. S.;Cho, S. S.;Yim, Y. S.;Cho, C. H.;Jeong, W. P.;Park, K. I.;Han, J.-M.;Song, D. H.;Kyung, K. H.;Lim, Y.-H.;Jun, Y.-H
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 981 - 989
Publisher: IEEE
 
» A 24-GHz CMOS UWB Radar Transmitter With Compressed Pulses
Abstract:
A fully integrated 24-GHz CMOS ultra-wideband (UWB) radar transmitter for short-range automotive application is presented. For high-range resolution and improved signal-to-noise ratio, a pulse compression technique using binary phase code is adopted. Design issues of UWB radar transmitter are investigated based on fundamental pulse theory. A pulse former, which operates as a switch to generate a pulse modulated carrier signal and a bi-phase modulator for pulse compression, is proposed. The proposed transmitter achieves 4-GHz output signal bandwidth, which means a minimum range resolution of 7.5 cm, and the total dc power dissipation is 63 mW.
Autors: Yang, J.;Pyo, G.;Kim, C.-Y.;Hong, S.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Apr 2012, volume: 60, issue:4, pages: 1117 - 1125
Publisher: IEEE
 
» A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines
Abstract:
AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay . The UDL can be used in any product without any need for customizing. In addition, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed scheme produces equivalent or less error to than does a conventional scheme that uses a single critical path replica as a delay monitor, even with simple monitor design. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.
Autors: Ikenaga, Y.;Nomura, M.;Suenaga, S.;Sonohara, H.;Horikoshi, Y.;Saito, T.;Ohdaira, Y.;Nishio, Y.;Iwashita, T.;Satou, M.;Nishida, K.;Nose, K.;Noguchi, K.;Hayashi, Y.;Mizuno, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 832 - 840
Publisher: IEEE
 
» A 2G/3G Cellular Analog Baseband Based on a Filtering ADC
Abstract:
A current-driven low-pass filter embedded in a sigma-delta analog-to-digital converter is presented. The implementation of a class-B feedback digital-to-analog converter, together with in-band noise reduction and passive filtering, gives the possibility to handle challenging wireless communication scenarios with low power consumption. The architecture is a suitable candidate to implement the entire baseband analog section of a Global System for Mobile Communications–Universal Mobile Telecommunications System (GSM–UMTS) reconfigurable receiver.
Autors: Sosio, M.;Liscidini, A.;Castello, R.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Apr 2012, volume: 59, issue:4, pages: 214 - 218
Publisher: IEEE
 
» A 3-DOF parallel manufacturing module and its kinematic optimization
Abstract:


Autors:
Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» A 30 T pulsed magnet with conical bore for synchrotron powder diffraction
Abstract:
We report on the design, construction, and operation of a horizontal field, 30 T magnet system with a conical bore optimized for synchrotron x-ray powder diffraction. The magnet offers ±31° optical access downstream of the sample, which allows to measure a sufficiently large number of Debye rings for an accurate crystal structure analysis. Combined with a 290 kJ generator, magnetic field pulses of 60 ms length were generated in the magnet, with a rise time of 4.1 ms and a repetition rate of 6 pulses/h at 30 T. The coil is mounted inside a liquid nitrogen bath. A liquid helium flow cryostat reaches into the coil and allows sample temperature between 5 and 250 K. The setup was used on the European Synchrotron Radiation Facility beamlines ID20 and ID06.
Autors: Billette, J.;Duc, F.;Frings, P.;Nardone, M.;Zitouni, A.;Detlefs, C.;Roth, T.;Crichton, W.;Lorenzo, J. E.;Rikken, G. L. J. A.;
Appeared in: Review of Scientific Instruments
Publication date: Apr 2012, volume: 83, issue:4, pages: 043904 - 043904-7
Publisher: IEEE
 
» A 300-kpixel Ultrahigh-Speed Charge-Coupled Device With a Dynamic Range of 48.6 dB at 1 Million Frames per Second
Abstract:
An ultrahigh-speed charge-coupled device (CCD) with an increased dynamic range at a frame rate above 200 kiloframes per second (kfps) was developed. The dynamic range of a CCD operating at extremely high speeds is reduced as a result of rounding of a sharp voltage waveform inside the device. The amount of rounding was estimated by using an equivalent circuit model of one kind of electrodes in a four-phase CCD memory. The simulation showed that the calculated voltage at a quarter period and the measured saturation signal level have similar dependence on the frame rate. To suppress the drop in voltage at a quarter period, the active pixels and the driving circuit were divided, and the resistance of the pixel wiring was reduced. A new ultrahigh-speed CCD, whose active pixels are divided into eight separately driven blocks and that employs dual wirings to each electrode of the four-phase CCD memory, was designed and fabricated. A driving evaluation experiment showed that the ultrahigh-speed CCD had a dynamic range of 48.6 dB at 1 000 000 fps. This range is equivalent to 8-bit digital and is 2.5 times higher than that of a previous ultrahigh-speed CCD.
Autors: Arai, T.;Kitamura, K.;Yonai, J.;Ohtake, H.;Hayashida, T.;Maruyama, H.;van Kuijk, H.;Etoh, T. G.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Apr 2012, volume: 59, issue:4, pages: 1107 - 1113
Publisher: IEEE
 
» A 3D shape segmentation approach for robot grasping by parts
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Autors:
Appeared in: Robotics and Autonomous Systems
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» A 5 GHz 0.95 dB NF Highly Linear Cascode Floating-Body LNA in 180 nm SOI CMOS Technology
Abstract:
A 5 GHz CMOS LNA featuring a record 0.95 dB noise-figure is reported. Using an inductively-degenerated cascode topology combined with floating-body transistors and high-Q passives on an SOI substrate, record noise figure and superior linearity performance at 5 GHz are obtained. The low-noise amplifier (LNA) achieves up to 11 dB of gain while consuming 12 mW dc power, and is capable of supporting 802.11a WLAN applications. The impact of SOI body-contact on the LNA RF performance is described and linked to improved intermodulation performance.
Autors: Madan, A.;McPartlin, M. J.;Masse, C.;Vaillancourt, W.;Cressler, J. D.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Apr 2012, volume: 22, issue:4, pages: 200 - 202
Publisher: IEEE
 
» A 52 mW Full HD 160-Degree Object Viewpoint Recognition SoC With Visual Vocabulary Processor for Wearable Vision Applications
Abstract:
A 1920 1080 160 object viewpoint recognition system-on-chip (SoC) is presented in this paper. The SoC design is dedicated to wearable vision applications, and we address several crucial issues including the low recognition accuracy due to the use of low resolution images and dramatic changes in object viewpoints, and the high power consumption caused by the complex computations in existing computer vision object recognition systems. The human-centered design (HCD) mechanism is proposed in order to maintain a high recognition rate in difficult situations. To overcome the degradation of accuracy when dramatic changes to the object viewpoint occur, the object viewpoint prediction (OVP) engine in the HCD provides 160 object viewpoint invariance by synthesizing various object poses from predicted object viewpoints. To achieve low power consumption, the visual vocabulary processor (VVP), which is based on bag-of-words (BoW) matching algorithm, is used to advance the matching stage from the feature-level to the object-level and results in a 97% reduction in the required memory bandwidth compared to previous recognition systems. Moreover, the matching efficiency of the VVP enables the system to support real-time full HD (1920 1080) processing, thereby improving the recognition rate for detecting a traffic light at a distance of 50 m to 95% compared to the 29% recognition rate for VGA (640 480) processing. The real-time 1920 1080 visual recognition chip is realized on a 6.38 mm $^{2}$ die with 65 nm CMOS technology. It achieves an average recognition rate of 94%, a power efficiency of 1.18 TOPS/W, and an area efficiency of 25.9 GOPS/mm while only dissipating 52 mW at 1.0 V .
Autors: Su, Y.-C.;Huang, K.-Y.;Chen, T.-W.;Tsai, Y.-M.;Chien, S.-Y.;Chen, L.-G.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 797 - 809
Publisher: IEEE
 
» A 5MSps 13.25?W 8-bit SAR ADC with single-ended or differential input
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Appeared in: Microelectronics Journal
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» A 6-DOF adaptive parallel manipulator with large tilting capacity
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Autors:
Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» A 64 64 CMOS Image Sensor With On-Chip Moving Object Detection and Localization
Abstract:
This paper presents a 64 64 CMOS image sensor with on-chip moving object detection and localization capability. Pixel-level storage elements (capacitors) enable the sensor to simultaneously output two consecutive frames, with temporal differences digitalized into binary events by a global differentiator. An on-chip, hardware-implemented, clustering-based algorithm processes events on the fly and localizes up to three moving objects in the scene. The sensor can automatically switch to region of interest mode and capture a picture of the object. The proposed image sensor was implemented using UMC 0.18 CMOS technology with a die area of 1.5 mm 1.5 mm, and power consumption was only 0.4 mW at 100 FPS.
Autors: Zhao, B.;Zhang, X.;Chen, S.;Low, K.-S.;Zhuang, H.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Apr 2012, volume: 22, issue:4, pages: 581 - 588
Publisher: IEEE
 
» A 64 64 CMOS Image Sensor With On-Chip Moving Object Detection and Localization
Abstract:
This paper presents a 64 64 CMOS image sensor with on-chip moving object detection and localization capability. Pixel-level storage elements (capacitors) enable the sensor to simultaneously output two consecutive frames, with temporal differences digitalized into binary events by a global differentiator. An on-chip, hardware-implemented, clustering-based algorithm processes events on the fly and localizes up to three moving objects in the scene. The sensor can automatically switch to region of interest mode and capture a picture of the object. The proposed image sensor was implemented using UMC 0.18 CMOS technology with a die area of 1.5 mm 1.5 mm, and power consumption was only 0.4 mW at 100 FPS.
Autors: Zhao, B.;Zhang, X.;Chen, S.;Low, K.-S.;Zhuang, H.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Apr 2012, volume: 22, issue:4, pages: 581 - 588
Publisher: IEEE
 
» A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz BiCMOS Process
Abstract:
We present a complete signal generator with integrated digital-to-analog convertor (DAC) on a chip which can generate complex waveforms at up to 7.2 GSa/s with 14 bit resolution or at up to 12 GSa/s with 12 bit resolution. The 3 dB bandwidth is 4.4 GHz. The chip includes digital signal processing (DSP) logic for agile generation of wideband modulated RF signals (up to 480 MHz modulation bandwidth) as well as high fidelity chirp and continuous wave signals. There is also DSP for integral non-linearity error reduction and suppression of clock sub-harmonics. The DAC uses a segmented architecture with 4 unary most significant bits and an R/2R ladder for the 10 binary least significant bits. Distributed resampling is applied to all current sources to improve the dynamic performance. At 7.2 GSa/s it delivers at least 67 dB spurious free dynamic range (SFDR) across the whole Nyquist region and an SNR of 62 dB. It demonstrates 157 dBc/Hz phase noise at 10 kHz offset from a 1 GHz carrier, 22 dB better than known synthesized signal generation instruments. The chip is built in a 165 GHz , 130 nm BiCMOS process and is packaged in a 780 ball BGA.
Autors: Van de Sande, F.;Lugil, N.;Demarsin, F.;Hendrix, Z.;Andries, A.;Brandt, P.;Anklam, W.;Patterson, J. S.;Miller, B.;Rytting, M.;Whaley, M.;Jewett, B.;Liu, J.;Wegman, J.;Poulton, K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 1003 - 1012
Publisher: IEEE
 
» A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With -Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control
Abstract:
A battery-free nano-power buck converter with a proposed dynamic on/off time (DOOT) control can achieve high conversion efficiency over a wide load range. The DOOT control can predict the on/off time at different input voltages without a power consuming zero current detection (ZCD) circuit, as well as suppress static power in idle periods. To adapt to the fluctuations in a harvesting system, the proposed -calibration scheme guarantees accurate ZCD over process, voltage variation, and temperature (PVT) in the DOOT to improve power conversion efficiency. Furthermore, the adaptive phase lead (APL) mechanism can improve inherent propagation delay attributable to low-power and non-ideal comparator, thus improving load regulation by a maximum of 30 mV. The test chip was implemented in 0.25- m CMOS process with a die area of 0.39 mm . Experimental results showed 95% peak efficiency, low static power of 217 nW and good load regulation of 0.1 mV/mA, which are suitable for RF energy harvesting applications.
Autors: Huang, T.-C.;Hsieh, C.-Y.;Yang, Y.-Y.;Lee, Y.-H.;Kang, Y.-C.;Chen, K.-H.;Huang, C.-C.;Lin, Y.-H.;Lee, M.-W.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Apr 2012, volume: 47, issue:4, pages: 852 - 862
Publisher: IEEE
 
» A Bayesian approach for place recognition
Abstract:


Autors:
Appeared in: Robotics and Autonomous Systems
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» A Bayesian estimation for single target tracking based on state mixture models
Abstract:


Autors:
Appeared in: Signal Processing
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» A Big Payoff
Abstract:
This column examines Google's and Apple's different paths to profitability.
Autors: Greenstein, Shane;
Appeared in: IEEE Micro
Publication date: Apr 2012, volume: 32, issue:2, pages: 64 - 64
Publisher: IEEE
 
» A Binary Space-Time Code for MIMO Systems
Abstract:
In this paper, we introduce a simple bit-interleaved binary space-time code (B-STC) for a coded multi-input multi-output (MIMO) system to obtain an increase in information rate, where two transmit and two receive antennas are used. We derive a probability density function (pdf) of log-likelihood ratio (LLR) for the B-STC decoder output and approximate it with the pdf of MIMO detector output having the degraded SNR. The average bit error probability at the i-th iteration is represented in terms of moment generating function with differently distributed SNRs. Although the iterative decoder in the B-STC structure increases the computational complexity, the number of iterations i is not large (i≤3). Because the proposed B-STC scheme is a binary code for MIMO systems, different types of channel codes and various space-time codes can be concatenated. To achieve near-capacity performance on MIMO channels, an iterative receiver structure with a soft interference cancellation scheme can be also adopted as an outer iteration. And the proposed scheme can be extended to arbitrary number of transmit and receive antennas.
Autors: Song, Bongseop;Kim, Nanshik;Park, Hyuncheol;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Apr 2012, volume: 11, issue:4, pages: 1350 - 1357
Publisher: IEEE
 
» A Brave New World of Testing? An Interview with Google's James Whittaker
Abstract:
The increasing pervasiveness of cloud computing is changing the state of the practice in software testing. In an interview with James Whittaker, an engineering director at Google, editor in chief Forrest Shull explores some of the important trends in cloud computing and their implications. The conversation covers key technology changes, such as more pervasive access to monitoring frameworks, the ability to aggregate and act on feedback directly from massive user communities (the "crowdsourcing" of quality assurance), and the ability to know the exact machine configuration when bugs are discovered. All of these changes are having concrete impacts on which skills are important—and which no longer so—for software testers. An accompanying audio interview provides a complete recording of the conversation and more details on points such as privacy testing.
Autors: Shull, Forrest;
Appeared in: IEEE Software
Publication date: Apr 2012, volume: 29, issue:2, pages: 4 - 7
Publisher: IEEE
 
» A broadband and compact asymmetrical backward coupled-line coupler with high coupling level
Abstract:


Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Apr 2012
Publisher: Elsevier B.V.
 
» A Broadband and Vialess Vertical Microstrip-to-Microstrip Transition
Abstract:
A novel, broadband, vialess, and vertical microstrip-to-microstrip transition is proposed in this paper. The transition consists of two open-circuited microstrip resonators and a U-shaped resonant-slot on the common ground plane. A physics-based equivalent-circuit model is developed for interpreting its working mechanism and facilitating the design process. The transition is analogous to a three-pole resonator filter. Based on the equivalent-circuit model, the coupling coefficients of the physical circuit can be calculated from the group delay information of two segregated electromagnetic models. To effectively control the couplings, a modified configuration is also proposed. A prototype transition is designed using the proposed design formulas. The fabricated circuit is measured to validate the proposed transition and the equivalent-circuit model. Good agreement is obtained between not only the measured and the simulated performance, but also the designed and the extracted-circuit model. In addition to the wide bandwidth, the features of vialess and easy fabrication make the novel transition very attractive for system-on-package applications.
Autors: Huang, X.;Wu, K.-L.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Apr 2012, volume: 60, issue:4, pages: 938 - 944
Publisher: IEEE
 
» A Capacitive Fringing Field Sensor Design for Moisture Measurement Based on Printed Circuit Board Technology
Abstract:
Interdigitated electrode capacitive fringing field sensors have been utilized in numerous applications. Although various technologies are used to realize these types of sensors, printed circuit board technology is particularly advantageous for realizing this type of sensor through fabricating the interdigitated electrode structures in the patterned Cu foil. Additionally, the solder mask coating can insulate the electrodes to prevent shorting in the presence of water. Using this approach, prototype sensors were designed, simulated, fabricated, and successfully evaluated. Applications include water detection and quantity measurement and soil moisture content measurement.
Autors: Dean, R. N.;Rane, A. K.;Baginski, M. E.;Richard, J.;Hartzog, Z.;Elton, D. J.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Apr 2012, volume: 61, issue:4, pages: 1105 - 1112
Publisher: IEEE
 
» A categorical, improper probability method for combining NDVI and LiDAR elevation information for potential cotton precision agricultural applications
Abstract:


Autors:
Appeared in: Computers and Electronics in Agriculture
Publication date: Apr 2012
Publisher: Elsevier B.V.
 

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