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Electrical and Electronics Engineering publications abstract of: 03-2013 sorted by title, page: 0
» 1-D Cell Generation With Printability Enhancement
Abstract:
As process technologies advance to the subwavelength era, the 1-D design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. To improve the printability of 1-D cell design, it is essential to insert dummy patterns and optimize line-end gap distribution for each layer. This paper presents novel 1-D cell generation algorithms that simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, minimize used routing tracks, insert sufficient dummy patterns, and eliminate stage-like line-end gaps without power and timing overhead. Consequently, the 1-D cell area is minimized and the printability of the cell is enhanced. To the best of our knowledge, this is also the first work in the literature that considers line-end gap distribution during 1-D cell generation.
Autors: Wu, P.-H.;Lin, M. P.-H.;Chen, T.-C.;Ho, T.-Y.;Chen, Y.-C.;Siao, S.-R.;Lin, S.-H.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Mar 2013, volume: 32, issue:3, pages: 419 - 432
Publisher: IEEE
 
» 1.4-kV AlGaN/GaN HEMTs on a GaN-on-SOI Platform
Abstract:
We demonstrate high-voltage depletion-mode and enhancement-mode (E-mode) AlGaN/GaN high-electron-mobility transistors (HEMTs) on a GaN-on-silicon-on-insulator (SOI) platform. The GaN-on-SOI wafer features GaN epilayers grown by metal–organic chemical vapor deposition on a p-type (111) Si SOI substrate with a p-type (100) Si handle wafer. Micro-Raman spectroscopy significantly reveals reduced stress in the GaN epilayers, which is a result expected from the compliant SOI substrate. E-mode HEMTs fabricated by fluorine plasma implantation technique deliver high on/off current ratio , large breakdown voltage (1471 V with floating substrate), and low on-resistance (3.92 .
Autors: Jiang, Q.;Liu, C.;Lu, Y.;Chen, K. J.;
Appeared in: IEEE Electron Device Letters
Publication date: Mar 2013, volume: 34, issue:3, pages: 357 - 359
Publisher: IEEE
 
» 10-bit 30-MS/s SAR ADC Using a Switchback Switching Method
Abstract:
This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital converter (ADC) that uses a power efficient switchback switching method. With respect to the monotonic switching method, the input common-mode voltage variation reduces which improves the dynamic offset and the parasitic capacitance variation of the comparator. The proposed switchback switching method does not consume any power at the first digital-to-analog converter switching, which can reduce the power consumption and design effort of the reference buffer. The prototype was fabricated in a 90-nm 1P9M CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves an sequenced neighbor double reservation of 56.89 dB and consumes 0.98 mW, resulting in a figure-of-merit (FOM) of 57 fJ/conversion-step. The ADC core occupies an active area of only 190 525 .
Autors: Huang, G.-Y.;Chang, S.-J.;Liu, C.-C.;Lin, Y.-Z.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Mar 2013, volume: 21, issue:3, pages: 584 - 588
Publisher: IEEE
 
» 10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids
Abstract:
The ANSI S1.11 1/3-octave filter bank is suitable for digital hearing aids, but its large group delay and high computational complexity complicate matters considerably. This study presents a 10-ms 18-band quasi-ANSI S1.11 1/3-octave filter bank for processing 24 kHz audio signals. We first discuss a filter order optimization algorithm to define the quasi-ANSI filters. The group delay constraint of filters is limited to 10 ms. The proposed design adopts an efficient prescription-fitting algorithm to reduce inter-band interference, enabling the proposed quasi-ANSI filter bank to compensate any type of hearing loss (HL) using the NAL-NL1 or HSE prescription formulas. Simulation results reveal that the maximum matching error in the prescriptions of the mild HL, moderate HL, and severe-to-profound HL is less than 1.5 dB. This study also investigates the complexity-effective multirate IFIR quasi-ANSI filter bank. For an 18-band digital hearing aid with a 24 kHz sampling rate, the proposed architecture eliminates approximately 93% of the multiplications and up to 74% of the storage elements, compared with a parallel FIR filters architecture. The proposed analysis filter bank (AFB) was designed in UMC 90 nm CMOS high-VT technology, and on the basis of post-layout simulations, it consumes 73 W V). By voltage scaling (to 0.6 V), the simulation results show that the power consumption decreases to 27 W, which is approximately 30% of that consumed by the most energy-efficient AFB available in the literature for use in hearing aids.
Autors: Liu, C.-W.;Chang, K.-C.;Chuang, M.-H.;Lin, C.-H.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Mar 2013, volume: 60, issue:3, pages: 638 - 649
Publisher: IEEE
 
» 130-nm CMOS -Band Two-Element Differential Power-Combining Oscillators
Abstract:
A power-combining structure at -band is proposed. The proposed structure, consisted of a multisection of Marchand baluns in series configuration, combines multiple pairs of balanced signals into a single unbalanced port. The active devices, in a differential cross-coupled pair configuration, are then combined with the multibalun structure forming the CMOS multiple element oscillator. The power-combining mechanism is investigated through - and -parameters. The power-combination oscillators are implemented in 0.13- CMOS technology, demonstrating the ability of monolithic integration. One and two cross-coupled-pair design of oscillator are measured. Experiment results for the oscillators are presented, showing maximum power-combining efficiency of 76.0%.
Autors: Yang, S.-H.;Tzuang, C.-K.C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2013, volume: 61, issue:3, pages: 1174 - 1185
Publisher: IEEE
 
» 2-D electrohydrodynamic simulations towards zero offset voltage with corona ionisers
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Autors:

Highlights

Appeared in: Journal of Electrostatics
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» 20-pJ/Pulse 250 Mbps Low-Complexity CMOS UWB Transmitter for 3–5 GHz Applications
Abstract:
This letter presents a CMOS on-off keying 3–5 GHz ultra-wideband (UWB) transmitter with low complexity, low power and high speed. In the transmitter, a new differential narrow triangular pulse generator using push and pull integrating technique was designed for reducing quiescent current and common-mode interference, and a new complementary switch mode on-off voltage controlled ring oscillator (VCRO) was proposed by breaking the oscillation loop instead of breaking the power to avoid base-band energy without extra shaping filter. Without using delay resistor and capacitor in the VCRO, the transient response speed of the transmitter can be increased by only utilizing the parasitic resistances and capacitances. The design was successfully implemented with a 0.18 CMOS technology. The test results show that the new UWB transmitter can obtain a sidelobe rejection of more than 20 dB, a low energy consumption of 20 pJ/pulse at 250 Mbps, and a small core chip size of 0.08 .
Autors: Zhao, M.J.;Li, B.;Wu, Z.H.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Mar 2013, volume: 23, issue:3, pages: 158 - 160
Publisher: IEEE
 
» 2012 Gathering of Region 8 MTT-S Chapter Representatives in Amsterdam [Around the Globe]
Abstract:
Autors: Machac, J.;Pasquet, D.;
Appeared in: IEEE Microwave Magazine
Publication date: Mar 2013, volume: 14, issue:2, pages: 114 - 118
Publisher: IEEE
 
» 20Gb/s WDM-OFDM-PON over 20-km single fiber uplink transmission using optical millimeter-wave signal seeding with rate adaptive bit-power loading
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Highlights

Appeared in: Optical Fiber Technology
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» 29th WWRF Meeting [From the Guest Editors]
Abstract:
Autors: Mohr, W.;Vinodrai, C.(.;Wong, M.;
Appeared in: IEEE Vehicular Technology Magazine
Publication date: Mar 2013, volume: 8, issue:1, pages: 21 - 23
Publisher: IEEE
 
» 3-D Unitary ESPRIT: Accurate attitude estimation for unmanned aerial vehicles with a hexagon-shaped ESPAR array
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Autors:
Appeared in: Digital Signal Processing
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» 3-Phase 4-leg unified series-parallel active filter system with ultracapacitor energy storage for unbalanced voltage sag mitigation
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Highlights

Appeared in: International Journal of Electrical Power & Energy Systems
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» 32 dBm Power Amplifier on 45 nm SOI CMOS
Abstract:
A silicon metal-semiconductor-field-effect-transistor (MESFET) power amplifier operating at 900 MHz fabricated on a 45 nm silicon-on-insulator CMOS process with no changes to the process flow is presented. The soft breakdown of the MESFET is 20 times that of the MOSFET and allowed a single transistor amplifier based on Class A bias conditions to operate at up to 32 dBm output power with an 8 V drain bias. The amplifier had a peak power added efficiency of 37.6%, gain of 11.1 dB, OIP3 of 39.3 dBm and 1 dB compression point at an output power of 31.6 dBm. The device required only 0.125 mm of active area. Additionally, the depletion mode operation of the MESFET enables a simple input bias approach using an inductor to ground at the gate of the device.
Autors: Wilk, S.J.;Lepkowski, W.;Thornton, T.J.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Mar 2013, volume: 23, issue:3, pages: 161 - 163
Publisher: IEEE
 
» 36 SSCS Members Elevated to IEEE Senior Grade in September, October, and December [People]
Abstract:
Autors: Olstein, K.;
Appeared in: IEEE Solid-State Circuits Magazine
Publication date: Mar 2013, volume: 5, issue:1, pages: 102 - 102
Publisher: IEEE
 
» 3D CBIR with sparse coding for image-guided neurosurgery
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Highlights

Appeared in: Signal Processing
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» 3D Imaging Techniques and Multimedia Applications [Guest editor's introduction]
Abstract:
With the advances in sensing, transmission, and visualization technology, 3D information has become increasingly incorporated into real-world applications, from architecture, entertainment, and manufacturing to security. One of the fundamental requirements of these applications is the estimation of scene depth information, preferably in real time. Fields such as computer vision, computer graphics, and robotics have studied the extraction of 3D information for more than three decades, but it remains a challenging problem. Multimedia researchers must take the imperfectness of depth information and other multisensory information into consideration when designing their systems, making it a unique research opportunity. This special issue offers an overview of recent advances in 3D acquisition systems and the many multimedia applications that can benefit from 3D integration and understanding.
Autors: Bajcsy, Ruzena;Yang, Ruigang;Zanuttigh, Pietro;Zhang, Cha;
Appeared in: IEEE Multimedia
Publication date: Mar 2013, volume: 20, issue:1, pages: 14 - 16
Publisher: IEEE
 
» 4D Reconstruction of the Beating Embryonic Heart From Two Orthogonal Sets of Parallel Optical Coherence Tomography Slice-Sequences
Abstract:
Current methods to build dynamic optical coherence tomography (OCT) volumes of the beating embryonic heart involve synchronization of 2D+time slice-sequences acquired over separate heartbeats. Temporal registration of these sequences is performed either through gating or postprocessing. While synchronization algorithms that exclusively rely on image- intrinsic signals allow forgoing external gating hardware, they are prone to error accumulation, require operator-supervised correction, or lead to nonisotropic resolution. Here, we propose an image-based, retrospective reconstruction technique that uses two sets of parallel 2D+T slice-sequences, acquired perpendicularly to each other, to yield accurate and automatic reconstructions with isotropic resolution. The method utilizes the similarity of the data at the slice intersections to spatio-temporally register the two sets of slice sequences and fuse them into a high-resolution 4D volume. We characterize our method by using 1) simulated heart phantom datasets and 2) OCT datasets acquired from the beating heart of live cultured E9.5 mouse and E10.5 rat embryos. We demonstrate that while our method requires greater acquisition and reconstruction time compared to methods that use slices from a single direction, it produces more accurate and self-validating reconstructions since each set of reconstructed slices acts as a reference for the slices in the perpendicular set.
Autors: Bhat, S.;Larina, I.V.;Larin, K.V.;Dickinson, M.E.;Liebling, M.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Mar 2013, volume: 32, issue:3, pages: 578 - 588
Publisher: IEEE
 
» 50+ years of intrinsic breakdown
Abstract:
The basic quantum mechanical theory for intrinsic breakdown was developed by von Hippel and Fröhlich over 70 years ago, but only now can we exploit their ideas accurately through the use of computational quantum mechanics. As shown above, von Hippel's low energy criterion for intrinsic breakdown provides remarkably good agreement with measured data for a range of both ionic and covalently bonded materials. We can correlate intrinsic breakdown with both bandgap and phonon cutoff frequency, although the relationships differ for different groups of materials. The challenge going forward is to move from intrinsic breakdown to engineering breakdown through inclusion of effects caused by morphology, chemical impurities (impurity states in the bandgap), and defects such as nanocavities. We believe that inclusion of these phenomena is possible using Monte Carlo computations with parameters computed using first principles methods, and we are pursuing this approach.
Autors: Ying Sun;Bealing, C.;Boggs, S.;Ramprasad, R.;
Appeared in: IEEE Electrical Insulation Magazine
Publication date: Mar 2013, volume: 29, issue:2, pages: 8 - 15
Publisher: IEEE
 
» 60-GHz 5-bit Phase Shifter With Integrated VGA Phase-Error Compensation
Abstract:
A 57–64-GHz low phase-error 5-bit switch-type phase shifter integrated with a low phase-variation variable gain amplifier (VGA) is implemented through TSMC 90-nm CMOS low-power technology. Using the phase compensation technique, the proposed VGA can provide appropriate gain tuning with almost constant phase characteristics, thus greatly reducing the phase-tuning complexity in a phased-array system. The measured root mean square (rms) phase error of the 5-bit phase shifter is 2 at 62 GHz. The phase shifter has a low group-delay deviation (phase distortion) of 8.5 ps and an excellent insertion loss flatness of 0.8 dB for a specific phase-shifting state, across 57–64 GHz. For all 32 states, the insertion loss is 14.6 3 dB, including pad loss at 60 GHz. For the integrated phase shifter and VGA, the VGA can provide 6.2-dB gain tuning range, which is wide enough to cover the loss variation of the phase shifter, with only 1.86 phase variation. The measured rms phase error of the 5-bit phase shifter and VGA is 3.8 at 63 GHz. The insertion loss of all 32 states is 5.4 dB, including pad loss at 60 GHz, and the loss flatness is 0.8 dB over 57–64 GHz. To the best of our knowledge, the 5-bit phase shifter presents the best rms phase error at center frequency among the -band switch-type phase shifter.
Autors: Li, W.-T.;Chiang, Y.-C.;Tsai, J.-H.;Yang, H.-Y.;Cheng, J.-H.;Huang, T.-W.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2013, volume: 61, issue:3, pages: 1224 - 1235
Publisher: IEEE
 
» 80ns/45GHz Pulsed measurement system for DC and RF characterization of high speed microwave devices
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Highlights

Appeared in: Solid-State Electronics
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» 9-(Pyridin-3-yl)-9H-carbazole derivatives as host materials for green phosphorescent organic light-emitting diodes
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Appeared in: Organic Electronics
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» Passivation for Low Surface Recombination Velocity on Ge Surface
Abstract:
We report that passivation reduces surface recombination on Ge through both the reduction of interface state density and the field effect of the oxide charge. Furthermore, the photoluminescence intensity increases with increasing thickness, mainly because of the reduction in interface state density since the fixed charge density remains almost constant. The direct-to-indirect band-gap emission ratio also remains unchanged after passivation. The p-Ge (1–3 ) lifetime is 65 , as determined from the quasi-steady-state photoconductance on Ge wafers with different thicknesses. A 47-nm-thick layer can reduce the surface recombination velocity on Ge to 70 cm/s.
Autors: Chen, Y.-Y.;Chang, H.-C.;Chi, Y.-H.;Huang, C.-H.;Liu, C. W.;
Appeared in: IEEE Electron Device Letters
Publication date: Mar 2013, volume: 34, issue:3, pages: 444 - 446
Publisher: IEEE
 
» Passivation for Low Surface Recombination Velocity on Ge Surface
Abstract:
We report that GeO2 passivation reduces surface recombination on Ge through both the reduction of interface state density and the field effect of the oxide charge. Furthermore, the photoluminescence intensity increases with increasing GeO2 thickness, mainly because of the reduction in interface state density since the fixed charge density remains almost constant. The direct-to-indirect band-gap emission ratio also remains unchanged after passivation. The p-Ge (1-3 Ω·cm) lifetime is 65 μs, as determined from the quasi-steady-state photoconductance on Ge wafers with different thicknesses. A 47-nm-thick GeO2 layer can reduce the surface recombination velocity on Ge to 70 cm/s.
Autors: Yen-Yu Chen;Chang, H.;Chi, Y.;Huang, C.;Liu, C.W.;
Appeared in: IEEE Electron Device Letters
Publication date: Mar 2013, volume: 34, issue:3, pages: 444 - 446
Publisher: IEEE
 
» -Mode Dielectric-Resonator Filters With Controllable Transmission Zeros
Abstract:
A method to design -mode dielectric-resonator (DR) filters with transmission zeros is proposed. The feeding probes, extended along ring DRs, are used to excite the mode and introduce transmission zeros. By rotating the angle of the feeding position, transmission zeros can be shifted to the lower or the upper stopband. Thus, -mode DR filters with quasi-elliptic responses are realized with only iris coupling components. Based on this method, second- and fourth-order filters with different responses are designed and fabricated. Measured results confirm the predicted performance.
Autors: Chu, Q.-X.;Ouyang, X.;Wang, H.;Chen, F.-C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2013, volume: 61, issue:3, pages: 1086 - 1094
Publisher: IEEE
 
» A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver
Abstract:
This paper describes a low-power receiver front-end in a bidirectional near-ground source-series terminated (SST) interface implemented in a 40-nm CMOS process, which supports low-common mode differential NRZ signaling up to 16-Gb/s data rates. The high-speed operation is enabled by utilizing a common-gate amplifier stage with replica transconductance impedance calibration that accurately terminates the channel in the presence of receiver input loading. The near-ground low-impedance receiver also incorporates common-mode gain cancellation and in-situ equalization calibration to achieve reliable data reception at 16 Gb/s with better than 0.4 mW/Gb/s power efficiency over a memory link with more than 15 dB loss at the Nyquist frequency.
Autors: Kaviani, K.;Amirkhany, A.;Huang, C.;Le, P.;Beyene, W. T.;Madden, C.;Saito, K.;Sano, K.;Murugan, V. I.;Chang, K.;Yuan, X.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2013, volume: 48, issue:3, pages: 636 - 648
Publisher: IEEE
 
» A 0.6-V 4 dBm IIP3 Folded Cascode CMOS LNA With Linearization
Abstract:
This brief presents the design guidelines of LNAs under low-supply-voltage condition with respect to linearity and demonstrates an LNA that has excellent performance even with an extremely low supply voltage. Under a low supply voltage, the drain conductance nonlinearity, which can be ignored in a high supply voltage, is important, as well as the transconductance nonlinearity. Therefore, this brief linearizes transconductance using the multiple-gated transistor (MGTR) technique and tries to obtain high drain conductance linearity with the folded cascode configuration. The proposed 900-MHz LNA is designed with a 130-nm CMOS process. The measurement results show a gain of 15.4 dB, a noise figure of 1.74 dB, and an IIP3 of 4.09 dBm, which is the result of the 4.94-dB improvement over a conventional folded cascode LNA at 5.16-mW power consumption with a 0.6-V supply voltage.
Autors: Kim, Y.M.;Han, H.;Kim, T.W.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Mar 2013, volume: 60, issue:3, pages: 122 - 126
Publisher: IEEE
 
» A 0.8-V 4096-Pixel CMOS Sense-and-Stimulus Imager for Retinal Prosthesis
Abstract:
This paper presents a 0.8-V CMOS imager with 4096 pixels and an integrated sense-and-stimulus (SAS) function for retinal prosthesis. The pixel consists of a photon-to-biphasic-current converter (sense) and a balanced current-mode stimulator (stimulus) to achieve a highly integrated and low-power solution for high-resolution vision recovery. Three operation modes, that is, test mode, programming (PG) mode, and implanted (IP) mode, have been implemented for various purposes. In test mode, the internal signals are multiplexed out serially for chip verification. In PG mode, the output pattern of the current stimulator array is programmable by external addresses for patterned electrical stimulus experiments of retina. In IP mode, the chip is fully functional with a minimized number of input/output as four optimized for in vivo operation. A prototype chip with a 64 64 SAS-pixel array, a pixel size, and a 33.3% fill factor was designed and fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18- CMOS image sensor technology. The proposed chip was operational under a wide supply range from 0.8 to 1.8 V. The measured conversion gains and maximal biphasic current amplitudes are 144 nA/lx (1.8 V), 21 nA/lx (0.8 V), (1.8 V), and (0.8 V), respectively. The proposed SAS CMOS imager presents an integrated SAS solution for artificial retina with the highest array resolution of 4096 pixels and a low power consumption of 0.18 mW at 12.5 ft/s and a 0.8-V supply under 300-lx illumination.
Autors: Lee, C.-L.;Hsieh, C.-C.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Mar 2013, volume: 60, issue:3, pages: 1162 - 1168
Publisher: IEEE
 
» A 10 mK scanning tunneling microscope operating in ultra high vacuum and high magnetic fields
Abstract:
We present design and performance of a scanning tunneling microscope (STM) that operates at temperatures down to 10 mK providing ultimate energy resolution on the atomic scale. The STM is attached to a dilution refrigerator with direct access to an ultra high vacuum chamber allowing in situ sample preparation. High magnetic fields of up to 14 T perpendicular and up to 0.5 T parallel to the sample surface can be applied. Temperature sensors mounted directly at the tip and sample position verified the base temperature within a small error margin. Using a superconducting Al tip and a metallic Cu(111) sample, we determined an effective temperature of 38 ± 1 mK from the thermal broadening observed in the tunneling spectra. This results in an upper limit for the energy resolution of ΔE = 3.5kBT = 11.4 ± 0.3 μeV. The stability between tip and sample is 4 pm at a temperature of 15 mK as demonstrated by topography measurements on a Cu(111) surface.
Autors: Assig, Maximilian;Etzkorn, Markus;Enders, Axel;Stiepany, Wolfgang;Ast, Christian R.;Kern, Klaus;
Appeared in: Review of Scientific Instruments
Publication date: Mar 2013, volume: 84, issue:3, pages: 033903 - 033903-9
Publisher: IEEE
 
» A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier
Abstract:
A semidigital Gm-based amplifier is proposed for a low-power pipelined analog-to-digital converter (ADC). The amplifier performs a class-AB operation by smoothly changing between a comparator-like semidigital driver and a continuous-time high-gain amplifier according to the input voltage difference. A 10-bit pipelined ADC with 2.5-bit/stage architecture is implemented in a 0.13- CMOS. The ADC consumes 1.25 mW at a sampling rate of 25 MS/s and achieves a Nyquist-rate figure-of-merit of 139 and 232 fJ/c-s without and with power consumption from a resistor ladder, respectively.
Autors: Suh, Y.;Lee, J.;Kim, B.;Park, H.-J.;Sim, J.-Y.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Mar 2013, volume: 60, issue:3, pages: 142 - 146
Publisher: IEEE
 
» A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation
Abstract:
A 10-bit pipelined ADC was fabricated using a 65 nm CMOS technology. To reduce power consumption, switching opamps are used. These switching opamps are designed to have a short turn-on time. Digital background calibration is employed to correct the A/D conversion error caused by the low dc gain of the opamps. The biasing voltages in each opamp are automatically generated using digital circuits. This bias scheme can maintain the settling behavior of the opamp against process-voltage-temperature variations. At 300 MS/s sampling rate, the ADC consumes 26.6 mW from a 1 V supply. Its measured DNL and INL are 0.52/ 0.4 LSB and 0.99/ 1.65 LSB respectively. Its measured SNDR and SFDR are 55.4 dB and 67.2 dB respectively. The chip active area is 0.36 mm .
Autors: Fang, B.-N.;Wu, J.-T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2013, volume: 48, issue:3, pages: 670 - 683
Publisher: IEEE
 
» A 10-Bit DAC With 1.6-Bit Interpolation Cells for Compact LCD Column Driver ICs
Abstract:
This paper proposes a 10-bit DAC for LCD column driver ICs. This architecture achieves 10-bit resolution with a compact die size smaller than that of a conventional 8-bit resistor-string DAC (RDAC). The proposed DAC combines a 6-bit RDAC and a 4-bit DAC-embedded op with 1.6-bit current-mode interpolation cells. The 6-bit RDAC uses a one-voltage selector instead of a two-voltage selector; therefore, it requires a smaller silicon die area for the voltage selector. Fewer differential pairs are required for the voltage interpolation because the DAC-embedded op uses 1.6-bit interpolation cells with binary-weighted reference voltages. This further reduces the silicon die area. The 10-bit DAC prototype was realized in 0.35- CMOS technology with the worst DNL/INL of 0.45/0.93 LSB. The 10-bit DAC occupies only 64% of the conventional 8-bit RDAC area.
Autors: Lu, C.-W.;Hsiao, C.-M.;Lin, Y.-S.;Chang, M.-C. F.;
Appeared in: Journal of Display Technology
Publication date: Mar 2013, volume: 9, issue:3, pages: 176 - 183
Publisher: IEEE
 
» A 10GHz wideband VCO with low KVCO variation
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Autors:
Appeared in: Microelectronics Journal
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines
Abstract:
This paper presents a high data rate, non-contact interface using a coupled transmission line (CTL) composed of two differential transmission lines. The proposed CTL can achieve a measured loss of dB and a 3-db bandwidth of 3.4–9.0 GHz as a non-contact channel for a 1-mm communication distance. This wideband characteristic makes it possible to achieve high-speed communication using a single channel. The hysteresis buffer-based receiver recovers the transmitted data from the distorted waveforms derived from the AC coupling characteristics of the channel. The interference from the power delivery coil to the CTL is also evaluated. The simulated results showed that the interference was less than dB at 13.56 MHz. The system could achieve a communication speed of 12 Gb/s with a at a communication distance of 1 mm both with and without a wireless power supply of 75 mA . The timing margin with the wireless power supply was 41 ps ( UI).
Autors: Takeya, T.;Nan, L.;Nakano, S.;Miura, N.;Ishikuro, H.;Kuroda, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2013, volume: 48, issue:3, pages: 790 - 800
Publisher: IEEE
 
» A 128 128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers
Abstract:
Dynamic Vision Sensors (DVS) have recently appeared as a new paradigm for vision sensing and processing. They feature unique characteristics such as contrast coding under wide illumination variation, micro-second latency response to fast stimuli, and low output data rates (which greatly improves the efficiency of post-processing stages). They can track extremely fast objects (e.g., time resolution is better than 100 kFrames/s video) without special lighting conditions. Their availability has triggered a new range of vision applications in the fields of surveillance, motion analyses, robotics, and microscopic dynamic observations. One key DVS feature is contrast sensitivity, which has so far been reported to be in the 10–15% range. In this paper, a novel pixel photo sensing and transimpedance pre-amplification stage makes it possible to improve by one order of magnitude contrast sensitivity (down to 1.5%) and power (down to 4 mW), reduce the best reported FPN (Fixed Pattern Noise) by a factor of 2 (down to 0.9%), while maintaining the shortest reported latency (3 ) and good Dynamic Range (120 dB), and further reducing overall area (down to 30 31 per pixel). The only penalty is the limitation of intrascene Dynamic Range to 3 decades. A 128 128 DVS test prototype has been fabricated in standard 0.35 CMOS and extensive experimental characterization results are provided.
Autors: Serrano-Gotarredona, T.;Linares-Barranco, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2013, volume: 48, issue:3, pages: 827 - 838
Publisher: IEEE
 
» A 15–40 GHz CMOS True-Time Delay Circuit for UWB Multi-Antenna Systems
Abstract:
A CMOS true-time delay (TTD) circuit operating from 15 to 40 GHz is presented for integrated UWB multi-antenna systems. The TTD circuit employs a distributed active switching structure in which eight cascode switches are distributed along transmission lines, leading to 3-bit variations of the group delay. The size of the switches and the characteristic impedance of the transmission lines are carefully scaled so as to minimize loss variation among the different delay states, while maintaining flat delay performance over a wide bandwidth. The circuit is implemented in a bulk 0.13- m CMOS technology and exhibits a total variable group delay of 40 ps with an average resolution of 5 ps from 15 to 40 GHz. The insertion loss was 14 dB with a maximum RMS variation of 1.6 dB, while the input and output return loss was better than 10 dB over the operating bandwidth.
Autors: Park, S.;Jeon, S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Mar 2013, volume: 23, issue:3, pages: 149 - 151
Publisher: IEEE
 
» A 2.24 mW 74 dB -Gain, dc to 600 MHz-BW Differential Baseband Amplifier for 60 GHz Wireless Applications
Abstract:
Pub DtlA low power, wideband and high linearity current-mode based differential baseband amplifier with a bandwidth from dc to 600 MHz applied for 60 GHz zero-IF RF receiver is presented. The wideband differential baseband amplifier is realized in a 90 nm CMOS process. A series-series feedback technique and a Q-enhanced active inductor are adopted in the current-mode baseband amplifier for achieving wideband and high linearity under a small current consumption. The measured maximum BW of 600 MHz, gain of 74 dB and OIP3 of dBV are realized with power consumption of only 2.24 mW under a supply voltage of 1.4 V. The measured performance shows the baseband amplifier fulfills the requirements for 60 GHz zero-IF RF transceivers.
Autors: Shih, H.-Y.;Chen, C.-F.;Lin, S.-K.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Mar 2013, volume: 23, issue:3, pages: 152 - 154
Publisher: IEEE
 
» A 2.8–3.2-GHz Fractional- Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO
Abstract:
A 2.8–3.2-GHz fractional- digital PLL, implemented in 0.18- CMOS, is presented. The PLL architecture has the form of a classic delta-sigma fractional- PLL. A PFD generates up and down pulses from the reference and divided-down digitally controlled oscillator (DCO) clock. The time-to-digital converter (TDC) converts the width of up pulses to digital words. The quantization noise introduced by a third-order delta-sigma modulator through the multi-modulus divider is canceled at the TDC output. A resistively interpolated ADC is employed to boost TDC resolution by a factor of five. A dither-less DCO with an inductively coupled fine-tuned varactor bank improves tuning step-size by a factor of 16.6, to 20 kHz. With a 52-MHz reference clock, a 3.2-GHz output clock, and a loop-bandwidth of 950 kHz, this prototype achieves 230-fs rms jitter, integrated from a 1-kHz to 40-MHz offset, while drawing 17 mW from a 1.8-V supply. The in-band phase noise floor is at a 500-kHz offset. The reference spur is and the worst-case fractional- spur, by sweeping the multiplication ratio near 61, is . An FOM of is achieved, and this design occupies a core area of 0.62 .
Autors: Yao, C.-W.;Willson, A. N.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2013, volume: 48, issue:3, pages: 698 - 710
Publisher: IEEE
 
» A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface
Abstract:
Among the stacked dies using through silicon via (TSV), data conflictions occur due to process mismatches, which decrease the data valid window and consume unwanted power due to the short circuit current. This paper presents the DLL-based data self-aligner (DBDA), which reduces data conflictions among stacked dies. The stacked dies employing the proposed DBDAs automatically align their data output timings without relying on any control signals from the master die or an extra signal among the stacked die. The DBDA reduces the data confliction time (tDC) due to process, voltage and temperature (PVT) variations from 500 ps to 50 ps and thereby reduces the short current from 3.62 mA to 0.41 mA. The proposed DBDA has two operation modes: the synchronous self-align mode (SSAM), in which the data is aligned in the external clock domain and the asynchronous self-align mode (ASAM). The lock time of DBDA is less than 20 cycles in SSAM. Additionally, the lock detector (LD) and proposed re-calibrator help the DBDA to find the optimal calibration period under temperature variation. They also reduce the calibration current of DBDA by 45.5%. A prototype DBDA implemented in 130 nm CMOS technology dissipates 247 µW for 800 Mb/s/pin. For reduction of the leakage current during the power down mode or the self-refresh mode, this paper proposes a leakage current controller, which reduces the leakage power by 90.5%.
Autors: Lim, S.-B.;Lee, H.-W.;Song, J.;Kim, C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2013, volume: 48, issue:3, pages: 711 - 723
Publisher: IEEE
 
» A 25-Gb/s 5-mW CMOS CDR/Deserializer
Abstract:
The demand for higher data rates in serial links has exacerbated the problem of power consumption, motivating extensive work on receiver and transmitter building blocks. This paper presents a half-rate clock and data recovery circuit and a deserializer that employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UI at 5 MHz jitter frequency.
Autors: Jung, J. W.;Razavi, B.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2013, volume: 48, issue:3, pages: 684 - 697
Publisher: IEEE
 
» A 2D MEMS grating based CMOS compatible poly-SiGe variable optical attenuator
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Appeared in: Microelectronic Engineering
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A 2×VDD output buffer with PVT detector for slew rate compensation
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Appeared in: Microelectronics Journal
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A 3 Megapixel 100 Fps 2.8 m Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers
Abstract:
This paper presents a 3 megapixel 100 fps 2.8 m pixel pitch CMOS image sensor (CIS) layer with built-in self-test (BIST) for three-dimensional (3D) integrated imagers. A modular CIS sub-array is proposed with new readout and control scheme. It needs only one micro-bump ( ) per sub-array, instead of per-pixel or per-column, to release the design rule restriction of the 3D stacking process. The proposed readout structure with in-pixel two-dimensional (2D) decoding function achieves high spatial resolution, without degrading the frame rate. A BIST circuit is also proposed to filter out unqualified CIS layer before chip stacking, improving the yield performance of the final 3D integrated imagers, without adding extra transistor in the pixel. A CIS chip with 16 8 sub-arrays and a pixel size of 2.8 2.8 was fabricated in TSMC 0.18 CIS process. The experimental results demonstrate the successful parallel output images of 3 megapixels with 16 8 modules at 100 fps. This shows that the imaging resolution is expandable by the proposed modular sub-array design and is expected to achieve 100 fps at multi-mega imaging for high-speed HDTV camera applications.
Autors: Yeh, S.-F.;Hsieh, C.-C.;Yeh, K.-Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2013, volume: 48, issue:3, pages: 839 - 849
Publisher: IEEE
 
» A 3- to 5-GHz Wideband Array of Connected Dipoles With Low Cross Polarization and Wide-Scan Capability
Abstract:
A wideband, wide-scan phased array of connected dipoles has been designed and fabricated. Measured results from a 7 7 prototype demonstrator are presented for experimental validation. In order to avoid common-mode resonances that typically affect this type of array, loop-shaped transformers are included in the feed network. The common-mode rejection implemented by these transformers allow maintaining the cross-polarization levels to values lower than over a 30% relative bandwidth, for an elevation angle up to 45 in all azimuth planes. The array exhibits a measured voltage standing-wave ratio (VSWR) lower than 2.5 from 3 to 5 GHz for broadside radiation. The VSWR maintains levels lower than 3 within a scan volume of 45 from broadside in all planes.
Autors: Cavallo, D.;Neto, A.;Gerini, G.;Micco, A.;Galdi, V.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Mar 2013, volume: 61, issue:3, pages: 1148 - 1154
Publisher: IEEE
 
» A 3-D U-Shaped Meander-Line Slow-Wave Structure for Traveling-Wave-Tube Applications
Abstract:
A novel 3-D U-shaped meander-line (ML) slow-wave structure (SWS) is proposed for traveling-wave-tube applications. This 3-D structure has the potential to have a better performance than the corresponding 2-D ML SWSs proposed in the literature. Simulation results at S-band obtained using CST Microwave Studio are presented to compare the phase velocity, interaction impedance, and circuit attenuation of the proposed structure with those of a recently reported symmetric double V-shaped microstrip ML SWS, showing advantages with respect to circuit attenuation, bandwidth, and feed design. Particle-in-cell simulations are also carried out for the proposed structure for a cylindrical electron beam using CST Particle Studio. The saturated gain and electronic efficiency of the 3-D U-shaped ML SWS is significantly higher than that of the symmetric double V-shaped ML SWS. The proposed structure has been designed and fabricated with a microstrip-line feed at S-band. The measured return loss, phase velocity, and circuit attenuation match well with the simulation results. By using microfabrication techniques, the proposed SWS has the potential to operate at millimeter-wave and higher frequencies.
Autors: Chua, C.;Aditya, S.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Mar 2013, volume: 60, issue:3, pages: 1251 - 1256
Publisher: IEEE
 
» A 30-V transmitter front-end IC for ultrasound medical imaging applications
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Appeared in: Microelectronics Journal
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A 33 W 64 64 Pixel Vision Sensor Embedding Robust Dynamic Background Subtraction for Event Detection and Scene Interpretation
Abstract:
A 64 64-pixel ultra-low power vision sensor is presented, performing pixel-level dynamic background subtraction as the low-level processing layer of an algorithm for scene interpretation. The pixel embeds two digitally-programmable Switched-Capacitors Low-Pass Filters (SC-LPF) and two clocked comparators, aimed at detecting any anomalous behavior of the current photo-generated signal with respect to its past history. The 45 T, 26 m square pixel has a fill-factor of 12%. The vision sensor has been fabricated in a 0.35 m 2P3M CMOS process, powered with 3.3 V, and consumes 33 W at 13 fps, which corresponds to 620 pW/frame.pixel.
Autors: Cottini, N.;Gottardi, M.;Massari, N.;Passerone, R.;Smilansky, Z.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2013, volume: 48, issue:3, pages: 850 - 863
Publisher: IEEE
 
» A 4.4- W Wake-Up Receiver Using Ultrasound Data
Abstract:
In wireless sensor nodes, using a wake-up receiver to duty-cycle the main receiver significantly reduces the overall power consumption of the node, as long as the power consumption of the always-ON wake-up receiver is very low. We demonstrate line-of-sight ultrasound data communications for ultra-low power wireless wake-up in sensor networks. The 65-nm CMOS 0.6-V receiver prototype achieves a BER of better than 10 measured for a 250-bps free-space 8.6-m link in an indoor environment while dissipating only 4.4 W and requiring only 18 dBm electrical power to be delivered to the transmit transducer.
Autors: Yadav, K.;Kymissis, I.;Kinget, P. R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2013, volume: 48, issue:3, pages: 649 - 660
Publisher: IEEE
 
» A 5.6-GHz UWB Position Measurement System
Abstract:
This paper describes the design and realization of a 5.6-GHz ultrawide-bandwidth-based position measurement system. The system was entirely made using off-the-shelf components and achieves centimeter-level accuracy in an indoor environment. It is based on asynchronous modulated pulse round-trip time measurements. Both system level and realization details are described along with experimental results including estimates of measurement uncertainties.
Autors: Cazzorla, A.;De Angelis, G.;Moschitta, A.;Dionigi, M.;Alimenti, F.;Carbone, P.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Mar 2013, volume: 62, issue:3, pages: 675 - 683
Publisher: IEEE
 
» A 60-GHz Power Amplifier Design Using Dual-Radial Symmetric Architecture in 90-nm Low-Power CMOS
Abstract:
An innovative on-chip 3-D power amplifier (PA) architecture for -way power-combined CMOS PAs by using the proposed dual-radial symmetric architecture is presented. It provides design freedom of impedance selection of power device in transformer-based millimeter-wave PA design. This idea also makes distinguished breakthrough to the traditional 2-D PA architecture without compromising symmetry and compact size of layout. To demonstrate the feasibility of this idea, a 60-GHz PA is fabricated in 90-nm low-power CMOS process. It is also equipped with multi-mode operation. It achieves an output power of 18.5 dBm and a power-added efficiency of 10.2% with 1.2-V supply voltage. At 6-dB/10-dB power back-off operation, the drain efficiencies of power stage can be enhanced from 5.9%/2.4% to 11.9%/8%, respectively, by enabling the multi-mode operation.
Autors: Yeh, J.-F.;Tsai, J.-H.;Huang, T.-W.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2013, volume: 61, issue:3, pages: 1280 - 1290
Publisher: IEEE
 
» A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS
Abstract:
This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively.
Autors: Lin, Y.-Z.;Liu, C.-C.;Huang, G.-Y.;Shyu, Y.-T.;Liu, Y.-T.;Chang, S.-J.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Mar 2013, volume: 60, issue:3, pages: 570 - 581
Publisher: IEEE
 
» A 96-GHz Oscillator by High- Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS
Abstract:
A 96-GHz CMOS oscillator is demonstrated in this brief with the use of a high- metamaterial resonator. The proposed metamaterial resonator is constructed by a differential transmission line (T-line) loaded with complementary split-ring resonator engraved on the T-line. A negative real part of permittivity, i.e., , is observed near the resonance frequency, which introduces a sharp stopband and, thus, leads to a high- resonance. This brief is the first in literature to explore CMOS on-chip metamaterial resonator for oscillator design at the millimeter-wave frequency region. Compared with the existing oscillators with a -tank-based resonator at around 100 GHz, the proposed 96-GHz oscillator with high- metamaterial resonator shows much lower phase noise of 111.5 dBc/Hz at 10-MHz offset and figure-of-merit of 182.4 dBc/Hz.
Autors: Fei, W.;Yu, H.;Shang, Y.;Cai, D.;Ren, J.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Mar 2013, volume: 60, issue:3, pages: 127 - 131
Publisher: IEEE
 
» A -Band Dual Polarization Hybrid-Mode Horn Antenna Enabled by Printed-Circuit-Board Metasurfaces
Abstract:
Metamaterials with properly engineered surface properties have been recently proposed for application in the design of broadband hybrid-mode horn antennas, such as soft and hard horns. In this paper, we present the design, fabrication, and measured results of a square dual-polarization horn antenna with thin metasurfaces lining the four walls, demonstrating broadband, negligible-loss hybrid-mode operation. By employing a powerful genetic-algorithm (GA) design optimization technique, we have dispersion-engineered low-index metaliners whose surface impedances satisfy the balanced hybrid condition across the -band. The optimized metaliners were synthesized based on conventional printed-circuit board technology, leading to a lightweight and low-cost construction. To improve the cross-polarization response, a simple dielectric plug was placed in the throat of the horn to perform effective mode conversion. Measurements showed that the fabricated horn antenna prototype provided low sidelobes, low cross-polarization levels, and radiation patterns that are approximately independent of polarization. Excellent agreement was found between measured and simulated results across the entire band of operation. Both the far-field radiation patterns and the aperture field distributions confirm the hybrid-mode operation of the horn, validating the balanced metasurface design. This metamaterial-enabled antenna represents a low-cost alternative to other types of soft feed horns, such as corrugated horns.
Autors: Wu, Q.;Scarborough, C.P.;Martin, B.G.;Shaw, R.K.;Werner, D.H.;Lier, E.;Wang, X.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Mar 2013, volume: 61, issue:3, pages: 1089 - 1098
Publisher: IEEE
 
» A Back-Gate Coupling Quadrature Voltage-Control Oscillator Embedded With Self Body-Bias Schema
Abstract:
Pub DtlA quadrature voltage-controlled oscillator was designed with back-gate coupling and embedded self body-biasing and implemented with the TSMC 0.18 1P6M CMOS technology. Without using any extra negative bias-pin in the current-reuse structure, this embedded body-bias schema makes the switching transistors become forward body-biased in the duration of turn-on. It is not only beneficial for low-voltage operation, but also achieves a high oscillating output power ( ) with less supply power (2.5 mW). The percentage of frequency tuning range is 17.5% (from 4.60 to 5.48 GHz). The phase noise is at 1-MHz offset from the carrier frequency of 5.48 GHz.
Autors: Wu, J.-W.;Wu, H.-H.;Hsu, K.-C.;Chen, C.-C.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Mar 2013, volume: 23, issue:3, pages: 146 - 148
Publisher: IEEE
 
» A Background Calibration in Pipelined ADCs
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Autors:
Appeared in: AEU - International Journal of Electronics and Communications
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A balanced combination of Tikhonov and total variation regularizations for reconstruction of piecewise-smooth signals
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Highlights

Appeared in: Signal Processing
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A Bayesian approach to SAR imaging
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Appeared in: Digital Signal Processing
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A beamforming study for implementation of vibro-acoustography with a 1.75-D array transducer
Abstract:
Vibro-acoustography (VA) is an ultrasoundbased imaging modality that uses radiation force produced by two cofocused ultrasound beams separated by a small frequency difference, Δf, to vibrate tissue at Δf. An acoustic field is created by the object vibration and measured with a nearby hydrophone. This method has recently been implemented on a clinical ultrasound system using 1-D linear-array transducers. In this article, we discuss VA beamforming and image formation using a 1.75-D array transducer. A 1.75-D array transducer has several rows of elements in the elevation direction which can be controlled independently for focusing. The advantage of the 1.75-D array over a 1-D linear-array transducer is that multiple rows of elements can be used for improving elevation focus for imaging formation. Six configurations for subaperture design for the two ultrasound beams necessary for VA imaging were analyzed. The point-spread functions for these different configurations were evaluated using a numerical simulation model. Four of these configurations were then chosen for experimental evaluation with a needle hydrophone as well as for scanning two phantoms. Images were formed by scanning a urethane breast phantom and an ex vivo human prostate. VA imaging using a 1.75-D array transducer offers several advantages over scanning with a linear-array transducer, including improved image resolution and contrast resulting from better elevation focusing of the imaging point-spread function.
Autors: Urban, M.W.;Chalek, C.;Haider, B.;Thomenius, K.E.;Fatemi, M.;Alizad, A.;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Mar 2013, volume: 60, issue:3, pages: 535 - 551
Publisher: IEEE
 
» A behaviour sequencing and composition architecture based on ontologies for entertainment humanoid robots
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Appeared in: Robotics and Autonomous Systems
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A binary SFLA for probabilistic three-phase load flow in unbalanced distribution systems with technical constraints
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Appeared in: International Journal of Electrical Power & Energy Systems
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A bottleneck Steiner tree based multi-objective location model and intelligent optimization of emergency logistics systems
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Highlights

Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A Brain–Machine Interface to Navigate a Mobile Robot in a Planar Workspace: Enabling Humans to Fly Simulated Aircraft With EEG
Abstract:
This paper presents an interface for navigating a mobile robot that moves at a fixed speed in a planar workspace, with noisy binary inputs that are obtained asynchronously at low bit-rates from a human user through an electroencephalograph (EEG). The approach is to construct an ordered symbolic language for smooth planar curves and to use these curves as desired paths for a mobile robot. The underlying problem is then to design a communication protocol by which the user can, with vanishing error probability, specify a string in this language using a sequence of inputs. Such a protocol, provided by tools from information theory, relies on a human user's ability to compare smooth curves, just like they can compare strings of text. We demonstrate our interface by performing experiments in which twenty subjects fly a simulated aircraft at a fixed speed and altitude with input only from EEG. Experimental results show that the majority of subjects are able to specify desired paths despite a wide range of errors made in decoding EEG signals.
Autors: Akce, A.;Johnson, M.;Dantsker, O.;Bretl, T.;
Appeared in: IEEE Transactions on Neural Systems and Rehabilitation Engineering
Publication date: Mar 2013, volume: 21, issue:2, pages: 306 - 318
Publisher: IEEE
 
» A Built-In Self-Test (BIST) system with non-intrusive TPG and ORA for FPGA test and diagnosis
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Autors:
Appeared in: Microelectronics Reliability
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A Channel Reuse Strategy with Adaptive Channel Allocation for All-Optical WDM Networks
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Appeared in: Optical Switching and Networking
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A charge-based capacitance model for AlGaAs/GaAs HEMTs
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Highlights

Appeared in: Solid-State Electronics
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A Circuit-Based Model for the Interpretation of Perfect Metamaterial Absorbers
Abstract:
A popular absorbing structure, often referred to as Perfect Metamaterial Absorber, comprising metallic periodic pattern over a thin low-loss grounded substrate is studied by resorting to an efficient transmission line model. This approach allows the derivation of simple and reliable closed formulas describing the absorption mechanism of the subwavelength structure. The analytic form of the real part of the input impedance is explicitly derived in order to explain why moderate losses of the substrate is sufficient to achieve matching with free space, that is, perfect absorption. The effect of the constituent parameters for tuning the working frequency and tailoring the absorption bandwidth is addressed. It is also shown that the choice of highly capacitive coupled elements allows obtaining the largest possible bandwidth whereas a highly frequency selective design is achieved with low capacitive elements like a cross array. Finally, the angular stability of the absorbing structure is investigated.
Autors: Costa, F.;Genovesi, S.;Monorchio, A.;Manara, G.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Mar 2013, volume: 61, issue:3, pages: 1201 - 1209
Publisher: IEEE
 
» A Circularly Polarized Cylindrical Dielectric Resonator Antenna Using a Helical Exciter
Abstract:
A novel circularly polarized cylindrical dielectric resonator antenna excited by an external tape helix is presented. The helix is fed by a coaxial line through a small hole on a finite size ground plane. The configuration offers a compact and easy to fabricate feeding network providing a 3 dB axial-ratio bandwidth of 6.4%. A prototype of the proposed configuration is fabricated and measured. Measured and simulated return loss, axial-ratio, radiation pattern, and realized gain are presented and discussed together with design guidelines.
Autors: Motevasselian, A.;Ellgardt, A.;Jonsson, B.L.G.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Mar 2013, volume: 61, issue:3, pages: 1439 - 1443
Publisher: IEEE
 
» A class of quaternion valued affine projection algorithms
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Highlights

Appeared in: Signal Processing
Publication date: Mar 2013
Publisher: Elsevier B.V.
 
» A CMOS Bidirectional 32-Element Phased-Array Transceiver at 60 GHz With LTCC Antenna
Abstract:
Fully integrated 32-element symmetrical TX/RX 60-GHz RF integrated circuit (RFIC) with built-in self-test is presented. The RF bidirectional power-combining architecture with shared blocks and less than 1-dB millimeter-wave transmit/receive (T/R) switch loss achieves record size and power consumption. The RFIC features an 8-dB noise figure and 28-dBm IP1 dB in RX mode, 10-dB power gain, and of 3.5 dBm per chain in TX mode. Further included are a 2-bit phase shifter, an IF converter to/from 12 GHz, and an integrated frac- synthesizer with push–push voltage-controlled oscillator having a-93 dBc@1-MHz phase noise at 48-GHz local oscillator port. A novel high dynamic range phase and power detector is presented with 2° and 1-dB accuracy over PVT in phase and power. A detailed analysis of both phase quantization and power distribution is presented. Array impairments such as mismatch and coupling were compared for different topologies. The RFIC is packaged on alumina for testing and on low-temperature co-fired ceramic (LTCC) for antenna integration. The 6 6 patch antenna on LTCC including four dummies achieves a gain of 19 dBi with scanning of 30°. The total root mean square amplitude and phase error of the array is 0.8 dB and 6 , respectively, resulting in a maximum array beam degradation of 1.4 dB for 2-bit quantization. The RFIC area is 29 mm $^{{{2}}}$ and it consumes 1.2 W/0.85 W at TX/RX, with a 29-dBm effective isotropic radiated power at 19-dB error vector magnitude.
Autors: Cohen, E.;Ruberto, M.;Cohen, M.;Degani, O.;Ravid, S.;Ritter, D.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2013, volume: 61, issue:3, pages: 1359 - 1375
Publisher: IEEE
 
» A Colpitts CMOS Quadrature VCO Using Direct Connection of Substrates for Coupling
Abstract:
A new low-phase noise low-power quadrature voltage-controlled oscillator (QVCO) using differential Colpitts oscillator is presented. The proposed QVCO is composed of two identical current-switching differential Colpitts VCOs in which the first core VCO is coupled to the second in an in-phase manner, and the second core VCO is coupled to the first in an anti-phase manner. To couple the two core VCOs, the substrates of the cross-connected transistors as well as the substrates of MOS varactors are used; alleviating the need for any extra elements for coupling, which could add noise and increase power dissipation. A linear (sinusoidal) analysis is presented that confirms that the proposed circuit generates quadrature waveforms. The proposed coupling technique can be generalized to differential Colpitts VCOs for multiphase signals generation.
Autors: Ebrahimi, E.;Naseh, S.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Mar 2013, volume: 21, issue:3, pages: 571 - 574
Publisher: IEEE
 
» A compact 45 kV curve tracer with picoampere current measurement capability
Abstract:
This paper discusses a compact high voltage curve tracer for high voltage semiconductor device characterization. The system sources up to 3 mA at up to 45 kV in dc conditions. It measures from 328 V to 60 kV with 15 V resolution and from 9.4 pA to 4 mA with 100 fA minimum resolution. Control software for the system is written in Microsoft Visual C# and features real-time measurement control and IV plotting, arc-protection and detection, an electrically isolated universal serial bus interface, and easy data exporting capabilities. The system has survived numerous catastrophic high voltage device-under-test arcing failures with no loss of measurement capability or system damage. Overall sweep times are typically under 2 min, and the curve tracer system was used to characterize the blocking performance of high voltage ceramic capacitors, high voltage silicon carbide photoconductive semiconductor switches, and high voltage coaxial cable.
Autors: Sullivan, W.W.;Mauch, D.;Bullick, A.;Hettler, C.;Neuber, A.;Dickens, J.;
Appeared in: Review of Scientific Instruments
Publication date: Mar 2013, volume: 84, issue:3, pages: 034702 - 034702-5
Publisher: IEEE
 
» A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology
Abstract:
This paper presents an all-digital phase-locked loop (ADPLL) clock generator for globally asynchronous locally synchronous (GALS) multiprocessor systems-on-chip (MPSoCs). With its low power consumption of 2.7 mW and ultra small chip area of 0.0078 mm it can be instantiated per core for fine-grained power management like DVFS. It is based on an ADPLL providing a multiphase clock signal from which core frequencies from 83 to 666 MHz with 50% duty cycle are generated by phase rotation and frequency division. The clock meets the specification for DDR2/DDR3 memory interfaces. Additionally, it provides a dedicated high-speed clock up to 4 GHz for serial network-on-chip data links. Core frequencies can be changed arbitrarily within one clock cycle for fast dynamic frequency scaling applications. The performance including statistical analysis of mismatch has been verified by a prototype in 65-nm CMOS technology.
Autors: Hoppner, S.;Eisenreich, H.;Henker, S.;Walter, D.;Ellguth, G.;Schuffny, R.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Mar 2013, volume: 21, issue:3, pages: 566 - 570
Publisher: IEEE
 
» A Compact Model for Organic Field-Effect Transistors With Improved Output Asymptotic Behaviors
Abstract:
Here, we propose an advanced compact analytical current–voltage model for organic field-effect transistors (OFETs), which can be incorporated into SPICE-type circuit simulators. We improved the output saturation behavior by introducing a new asymptotic function that also enables more precise low-voltage current and conductance fitting. A new expression for the subthreshold current was suggested to cover all operation regimes of OFETs. All model parameters were extracted by a systematic method, and the comparison of the modeled current with the experimental data on pentacene-based OFETs confirmed the validity of the model over a wide operation range.
Autors: Kim, C. H.;Castro-Carranza, A.;Estrada, M.;Estrada, A.;Horowitz, Y.;Horowitz, G.;Iniguez, B.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Mar 2013, volume: 60, issue:3, pages: 1136 - 1141
Publisher: IEEE
 
» A Comparative Study of Different Physics-Based NBTI Models
Abstract:
Different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data. Models that focus exclusively on hole trapping in gate-insulator-process-related preexisting traps are found to be inconsistent with direct experimental evidence of interface trap generation. Models that focus exclusively on interface trap generation are incapable of predicting ultrafast measurement data. Models that assume strong correlation between interface trap generation and hole trapping in switching hole traps cannot simultaneously predict long-time dc stress, recovery, and ac stress and cannot estimate gate insulator process impact. Uncorrelated contributions from generation and recovery of interface traps, together with hole trapping and detrapping in preexisting and newly generated bulk insulator traps, are invoked to comprehensively predict dc stress and recovery, ac duty cycle and frequency, and gate insulator process impact of NBTI. The reaction–diffusion model can accurately predict generation and recovery of interface traps for different devices and experimental conditions. Hole trapping/detrapping is modeled using a two-level energy well model.
Autors: Mahapatra, S.;Goel, N.;Desai, S.;Gupta, S.;Jose, B.;Mukhopadhyay, S.;Joshi, K.;Jain, A.;Islam, A. E.;Alam, M. A.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Mar 2013, volume: 60, issue:3, pages: 901 - 916
Publisher: IEEE
 

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