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Electrical and Electronics Engineering publications abstract of: 03-2012 sorted by title, page: 0
» 'Fingerprinting for food stamps' row triggers North American privacy debate
Abstract:


Autors:
Appeared in: Biometric Technology Today
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 'Tis Not! 'Tis So! [From the Editor's Desk]
Abstract:
Autors: Wood, J.;
Appeared in: IEEE Microwave Magazine
Publication date: Mar 2012, volume: 13, issue:2, pages: 6 - 6
Publisher: IEEE
 
» (ε, δ)-Approximate Aggregation Algorithms in Dynamic Sensor Networks
Abstract:
Aggregation operations are important in WSN applications. Since large numbers of applications only require approximate aggregation results rather than the exact ones, some approximate aggregation algorithms have been proposed to save energy. However, the error bounds of these algorithms are fixed and it is impossible to adjust the error bounds automatically, so they cannot meet the requirement of arbitrary precision required by various users. Thus, a uniform sampling-based algorithm was proposed by the authors of this paper to satisfy arbitrary precision requirement. Unfortunately, this uniform sampling-based algorithm is only suitable for static sensor networks. To overcome the shortcoming of the uniform sampling-based algorithm, this paper proposes four Bernoulli sampling-based and distributed approximate aggregation algorithms to process the snapshot and continuous aggregation queries in dynamic sensor networks. Theoretical analysis and experimental results show that the proposed algorithms have high performance in terms of accuracy and energy consumption.
Autors: Jianzhong Li;Siyao Cheng;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Mar 2012, volume: 23, issue:3, pages: 385 - 396
Publisher: IEEE
 
» (Quasi 3D) Numerical simulation of operation of a capacitive type nanoparticle counter
Abstract:


Autors:
Appeared in: Journal of Electrostatics
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 100G in the network of Deutsche Telekom
Abstract:


Autors:
Appeared in: Optical Fiber Technology
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 100G optical transport based on polarization and/or subcarrier multiplexed modulation formats
Abstract:


Autors:
Appeared in: Optical Fiber Technology
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 100GbE and beyond for warehouse scale computing interconnects
Abstract:


Autors:
Appeared in: Optical Fiber Technology
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 120-GHz-Band Wireless Link Technologies for Outdoor 10-Gbit/s Data Transmission
Abstract:
Our progress in 120-GHz-band wireless link technologies enables us to transmit 10-Gbit/s data transmission over a distance of more than 1 km. The 120-GHz-band wireless link uses high-speed uni-traveling carrier photodiodes (UTC-PD) and InP high-electron mobility transistor (HEMT) millimeter-wave (MMW) monolithic integrated circuits (MMICs) for the generation of MMW signals. We investigate the maximum output power of these devices and compare the phase noise of MMW signals generated by UTC-PDs and InP HEMT MMICs. We describe the antennas we used and their operation technologies. Finally, we investigate the dependence of transmission distance on availability using the statistical rain attenuation data. The calculation results show that the 120-GHz-band wireless link can transmit 10-Gbit/s data over a distance of 1 km with availability of 99.999%.
Autors: Hirata, A.;Kosugi, T.;Takahashi, H.;Takeuchi, J.;Togo, H.;Yaita, M.;Kukutsu, N.;Aihara, K.;Murata, K.;Sato, Y.;Nagatsuma, T.;Kado, Y.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2012, volume: 60, issue:3, pages: 881 - 895
Publisher: IEEE
 
» 13 GHz CMOS Active Inductor LC VCO
Abstract:
A 13 GHz active inductor LC voltage controlled oscillator (VCO) has been realized in 90 nm CMOS technology by ST-Microelectronics. The VCO consists of two complementary cross-coupled pairs, an active LC tank implemented by means of a differential high- low-noise active inductor and two p-MOSFET varicaps, and an output buffer stage. The measurements show a phase noise of at 1 MHz frequency offset. The current consumption of the VCO core and differential boot-strapped inductor amount to 0.7 and 1.8 mA, respectively, from a 1.2 V supply voltage.
Autors: Zito, D.;Pepe, D.;Fonte, A.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Mar 2012, volume: 22, issue:3, pages: 138 - 140
Publisher: IEEE
 
» 19 Rules for Transmission: Lessons Learned in Wind Generation [In My View]
Abstract:
In 2002 when the midwest independent Transmission System Operator (MISO) started to address wind integration issues, dominate attitudes prevailed that wind was too intermittent to be a major source of power and energy. Wind was forecast to never provide more than 10,000 MW of connected generation in the MISO and SPP areas. Today, MISO alone has 10,000 MW of wind connected to the transmission system. The major driver was that MISO and others adopted the attitude to determine what could be done with wind generation and not what could not be done with wind generation. The lessons learned to date are discussed in this article.
Autors: Osborn, D.;
Appeared in: IEEE Power and Energy Magazine
Publication date: Mar 2012, volume: 10, issue:2, pages: 104 - 102
Publisher: IEEE
 
» 19-Gb/s adaptively modulated optical OFDM transmission by separated I/Q baseband delivery using 1GHz RSOAs
Abstract:


Autors:
Appeared in: Optical Fiber Technology
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 2011 A-SSCC Solid-State Circuits Society Student Travel Grant Award Winners [Conference Reports]
Abstract:
Autors: Chiueh, T.-D.;Huang, Y.-H.;
Appeared in: IEEE Solid-State Circuits Magazine
Publication date: Mar 2012, volume: 4, issue:1, pages: 63 - 63
Publisher: IEEE
 
» 20nm Gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2 source/drain
Abstract:


Autors:
Appeared in: Solid-State Electronics
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 224-Gb/s POLMUX-RZ-16QAM for next generation high-capacity optical transmission systems
Abstract:


Autors:
Appeared in: Optical Fiber Technology
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 23-Level Inverter for Electric Vehicles Using a Single Battery Pack and Series Active Filters
Abstract:
Cascaded H-bridge (CHB) multilevel inverters have been conceived as an alternative to reduce total harmonic distortion (THD) in medium-voltage drives. The reduced THD makes them useful for electric vehicle (EV) applications, but the main problem with the CHB is the large amount of isolated power sources required to feed each of the H-bridges. An improved variant known as the asymmetrical CHB (ACHB) inverter uses H-bridges of different sizes and then needs fewer isolated power sources than the CHB. However, in battery-powered EVs, only one power supply (fuel cell or battery pack) is desirable. This work presents a solution to solve the problem, operating some of the small H-bridges ( -bridges) as series active filters and using a small high-frequency link (HFL). With this solution, only one dc source is required to feed the inverter, and if the control is adjusted to work at particular switching points, more than 98% of power is transferred through the larger H-bridges ( bridges). The proposed ACHB topology can produce any number of levels, and the bridges always commutate at fundamental frequency. As the number of levels must remain constant for all output voltages, a variable dc source is required to control the amplitude of the motor voltage. This work shows some simulations and experiments on a 2-kW 27-level ACHB working with only 23 levels. The concept is being implemented in a small EV with an ACHB drive of 18 kW.
Autors: Pereda, J.;Dixon, J.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Mar 2012, volume: 61, issue:3, pages: 1043 - 1051
Publisher: IEEE
 
» 25-Gb/s 100-m MMF Transmission Using a Prototype 1.3- -Range CMOS-Based Transceiver for Optical Interconnections
Abstract:
A prototype transceiver composed of a 1.3- -range lens-integrated laser diode and photodiode as well as a complementary metal–oxide–semiconductor (CMOS) laser diode driver and a CMOS transimpedance amplifier for high-speed optical interconnections was developed. It demonstrated 25-Gb/s error-free 100-m multimode fiber transmission, with power dissipation of only 9 mW/Gb/s, for the first time.
Autors: Lee, Y.;Kawamura, D.;Takai, T.;Kogo, K.;Adachi, K.;Sugawara, T.;Chujo, N.;Matsuoka, Y.;Hamamura, S.;Yamazaki, K.;Ishigami, Y.;Takemoto, T.;Yuki, F.;Yamashita, H.;Tsuji, S.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Mar 2012, volume: 24, issue:6, pages: 467 - 469
Publisher: IEEE
 
» 2D Phononic Crystal Sensor with Normal Incidence of Sound
Abstract:


Autors:
Appeared in: Sensors and Actuators A: Physical
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 3D 'atomistic' simulations of dopant induced variability in nanoscale implant free In0.75Ga0.25As MOSFETs
Abstract:


Autors:
Appeared in: Solid-State Electronics
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 3D flowerlike ZnO micro-nanostructures via site-specific second nucleation in the zinc-ethylenediamine-hexamethylenetetramine tertiary system
Abstract:


Autors:
Appeared in: Materials Science in Semiconductor Processing
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 3D thermal-aware floorplanner using a MILP approximation
Abstract:


Autors:
Appeared in: Microprocessors and Microsystems
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 3D transient temperature field analysis of the stator of a hydro-generator under the sudden short-circuit condition
Abstract:
In this study, Finite Element Method (FEM) is applied to calculate the 3D transient temperature field of the stator of a hydro-generator, SF125-96/15600, under the sudden short-circuit condition. 3D transient equation of the heat conduction and its equivalent functional equations are firstly presented. Then the sudden short current and transient heat generation of the stator are analysed and calculated. Moreover, all the parameters for the simulation such as the heat conductivity coefficients of the iron core and stator coils, heat convection coefficients of each surface as well as iron and copper losses are deduced. These parameters are verified to be reasonable by comparing the simulated temperature results with the measured in the stable state. Finally, the 3D transient stator temperature field of the hydro-generator under the sudden short-circuit condition is simulated. The variation of the temperature field and temperature rise of the key components is also predicted, on which online thermal monitoring of the stator and optimum design can be carried out.
Autors: Fan, Y.;Wen, X.;Jafri, S.A.K.S.;
Appeared in: IET Electric Power Applications
Publication date: Mar 2012, volume: 6, issue:3, pages: 143 - 148
Publisher: IEEE
 
» 3D-interconnect: Visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy
Abstract:


Autors:

Graphical Abstract

image
Appeared in: Microelectronic Engineering
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 40-Gb/s DPSK Data Transmission Through a Silicon Microring Switch
Abstract:
We experimentally demonstrate switching of a 40-Gb/s differential-phase-shift-keyed (DPSK) signal through a coupled silicon photonic microring switch. By simultaneously electro-optically biasing both microring cavities, we achieve 14-dB extinction ratio for signals egressing from both output ports of the switch. Packetized transmission of the 40-Gb/s DPSK signal is achieved with power penalties of 0.6 and 2.4 dB for through port and drop port signals, respectively. The effects of a coupled silicon microring are investigated, showing a broad bandwidth and a linear phase response for the drop port are necessary characteristics for routing 40-Gb/s data through the switch for photonic interconnection networks.
Autors: Xu, L.;Zhang, W.;Li, Q.;Chan, J.;Lira, H. L. R.;Lipson, M.;Bergman, K.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Mar 2012, volume: 24, issue:6, pages: 473 - 475
Publisher: IEEE
 
» 6 DOF Force and Torque Sensor for Micro-manipulation Applications
Abstract:


Autors:
Appeared in: Sensors and Actuators A: Physical
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» 60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process
Abstract:
Pub DtlAThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital control interface (DCI). The 2 2 TX/RX phased arrays have been packaged with four antennas in low-temperature co-fired ceramic modules through flip-chip bonding and underfill process, and phased-array beam steering have been demonstrated. The entire beam-steering functions are digitally controllable, and individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in TX and 180 mW in RX and occupies an area of 3.74 mm in the TX integrated circuit (IC) and 4.18 mm in the RX IC. The beam-steering measurement results show acceptable agreement of the synthesized and measured array pattern.
Autors: Kuo, J.-L.;Lu, Y.-F.;Huang, T.-Y.;Chang, Y.-L.;Hsieh, Y.-K.;Peng, P.-J.;Chang, I.-C.;Tsai, T.-C.;Kao, K.-Y.;Hsiung, W.-Y.;Wang, J.;Hsu, Y. A.;Lin, K.-Y.;Lu, H.-C.;Lin, Y.-C.;Lu, L.-H.;Huang, Y.-W.;Wu, R.-B.;Wang, H.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2012, volume: 60, issue:3, pages: 743 - 756
Publisher: IEEE
 
» 60-GHz LTCC Integrated Circularly Polarized Helical Antenna Array
Abstract:
A 60-GHz wideband circularly polarized (CP) helical antenna array of 4 4 elements is designed and fabricated using low temperature cofired ceramic (LTCC) technology. The flexible via hole distribution is fully utilized to achieve a helical antenna array to obtain good circular polarization performance. Meanwhile, grounded coplanar waveguide (GCPW) to stripline is utilized for probe station measurement. Unlike traditional helical antennas, the proposed helical antenna array is convenient for integrated applications. The fabricated antenna array has dimension of . The simulated and measured impedance, axial ratio (AR) and radiation pattern are studied and compared. The proposed antenna array shows a wide measured impedance bandwidth from 52.5 to 65.5 GHz for , wideband measured AR bandwidth from 54 to 66 GHz for AR 3 dB, respectively.
Autors: Liu, C.;Guo, Y.-X.;Bao, X.;Xiao, S.-Q.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Mar 2012, volume: 60, issue:3, pages: 1329 - 1335
Publisher: IEEE
 
» 7 Billion Milestone [From the Editor's Desk]
Abstract:
Autors: Floyd, L.;
Appeared in: IEEE Industry Applications Magazine
Publication date: Mar 2012, volume: 18, issue:2, pages: 2 - 2
Publisher: IEEE
 
» Adaptive Controller for Uncertain Nonlinear Multi-Input Multi-Output Systems With Input Quantization
Abstract:
We study the merits of the adaptive controller for nonlinear uncertain Multi-Input Multi-Output (MIMO) systems in the presence of significant unmodeled dynamics and input quantization. We show that with both logarithmic quantization and uniform quantization, if the quantization is sufficiently dense, the adaptive controller ensures that the output of the MIMO system follows a desired reference signal with uniform transient and steady-state performance bounds. Compared with the same feedback architecture without quantization, the uniform performance bounds have an additional positive additive term, linear in the quantization constant, which can be reduced by increasing the quantization density. Simulations illustrate the performance of the adaptive controller in the presence of quantization.
Autors: Sun, H.;Hovakimyan, N.;Basar, T.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Mar 2012, volume: 57, issue:3, pages: 565 - 578
Publisher: IEEE
 
» Extraction From Conductance-Frequency Measurements using a Transmission-Line Model in Weak Inversion of nMOSFETs
Abstract:
The density of interface states in metal-gate/high- dielectric MOSFETs is investigated in weak inversion from small-signal capacitance and conductance measurements using a transmission-line model. A presence of both, a large , and a high channel resistance, i.e., the latter exacerbated by poor effective mobility, are demonstrated in capacitance–voltage ( ) characteristics by a comparison of experiments with simulations using a Schrodinger–Poisson solver. Using a transmission-line network, the channel response and the density of interface states can be accurately modeled from the conductance-frequency characteristics. This technique is applied to dielectric MOSFETs with polysilicon and poly/TiN metal gates deposited and annealed at identical temperature. In such a condition, the density of interface states is twice as large as for a TiN metal gate.
Autors: Sicre, é;De Souza, M. M.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Mar 2012, volume: 59, issue:3, pages: 827 - 834
Publisher: IEEE
 
» -Based Resistive Memory With MIS Structure Formed on Ge Layer
Abstract:
Resistive random access memory (RRAM) cells with a thin oxygen-deficient film topped by a Ti oxygen-gettering layer and a Pt electrode were fabricated on n-Ge layer, and the switching mechanism, as well as electrical characteristics, was explored. The RRAM cells demonstrate a stable bipolar switching behavior without the requirement of a forming process. Because of the existence of a larger amount of interface traps which would trap carriers and help build a favorable electric field for the drift of oxygen vacancies, the RRAM cells possess lower SET and RESET voltages compared to those fabricated on n-Si layer. With many promising properties such as a large sensing margin of 300 times, a high operation speed of 250 ns, a robust endurance of , and a long data retention time of up to 10 years, the -based RRAM cells exhibit a promising perspective as nonvolatile memory devices for Ge-based technology.
Autors: Wu, Y.-H.;Wu, J.-R.;Hou, C.-Y.;Lin, C.-C.;Wu, M.-L.;Chen, L.-L.;
Appeared in: IEEE Electron Device Letters
Publication date: Mar 2012, volume: 33, issue:3, pages: 435 - 437
Publisher: IEEE
 
» -Band Total Power Radiometer Performance Optimization in an SiGe HBT Technology
Abstract:
A -band SiGe HBT total power radiometer is reported with a peak responsivity of 28 MV/W, a noise equivalent power (NEP) of 14–18 , and a temperature resolution better than 0.35 K for an integration time of 3.125 ms. The noise corner of the radiometer is lower than 200 Hz. Fabricated in a developmental technology with 270-GHz and 330-GHz , it includes a five-stage low-noise amplifier (LNA) with 4–7-GHz bandwidth and over 35 dB of gain centered at 165 GHz, along with a square-law detector with an NEP below 6 up to 170 GHz. An average system noise temperature of 1645 K is obtained using the -factor method and a noise bandwidth of 10 GHz calculated from the measured characteristics of the radiometer. The reduced noise corner frequency in the presence of the amplifier, compared to that of the detector, appears to indicate that, unlike in III–V radiometers, LNA gain fluctuations are not a problem in SiGe HBT radiometers. The circuit consumes 95 mW and occupies . Wafer mapping of the radiometer sensitivity and of the amplifier gain was performed across different process splits. The mapping results demonstrate that the radiometer can be employed as a r- latively simple and area-efficient transistor noise-measure monitor, useful in SiGe HBT vertical profile optimization.
Autors: Dacquay, E.;Tomkins, A.;Yau, K. H. K.;Laskin, E.;Chevalier, P.;Chantre, A.;Sautreuil, B.;Voinigescu, S. P.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2012, volume: 60, issue:3, pages: 813 - 826
Publisher: IEEE
 
» -Band Amplifiers With 6-dB Noise Figure and Milliwatt-Level 170–200-GHz Doublers in 45-nm CMOS
Abstract:
This paper presents low-noise -band amplifiers and milliwatt-level 170–200-GHz output doublers in 45-nm semiconductor-on-insulator (SOI) CMOS technology. The transistors are modeled using R/C extraction and full electromagnetic modeling. The measured of a 30 1- transistor is 200–210 GHz at a bias current of 0.3–0.5 . A three-stage -band amplifier shows a record noise figure of 6.0 dB and a saturated output power of 7.5–8.0 dBm with a power-added efficiency of 9%, all at 95 GHz. The -band balanced doubler results in an output power of 1 mW at 180 GHz. A -band amplifier/ -band doubler chip is also demonstrated, with a peak output power of 0.5–1 mW at 170–195 GHz and a conversion gain from to . This paper shows that 45-nm SOI CMOS, built for digital and mixed-signal applications, results in state-of-the-art performance at - and -band.
Autors: Cetinoneri, B.;Atesal, Y. A.;Fung, A.;Rebeiz, G. M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2012, volume: 60, issue:3, pages: 692 - 701
Publisher: IEEE
 
» -Band Total Power Radiometer Performance Optimization in an SiGe HBT Technology
Abstract:
A D-band SiGe HBT total power radiometer is reported with a peak responsivity of 28 MV/W, a noise equivalent power (NEP) of 14-18 fW/Hz1/2, and a temperature resolution better than 0.35 K for an integration time of 3.125 ms. The 1/f noise corner of the radiometer is lower than 200 Hz. Fabricated in a developmental technology with 270-GHz fT and 330-GHz/max, it includes a five-stage low-noise amplifier (LNA) with 4-7-GHz bandwidth and over 35 dB of gain centered at 165 GHz, along with a square-law detector with an NEP below 6 pW/Hz1/2 up to 170 GHz. An average system noise temperature of 1645 K is obtained using the Y-factor method and a noise bandwidth of 10 GHz calculated from the measured S21(f) characteristics of the radiometer. The reduced 1/f noise corner frequency in the presence of the amplifier, compared to that of the detector, appears to indicate that, unlike in III-V radiometers, LNA gain fluctuations are not a problem in SiGe HBT radiometers. The circuit consumes 95 mW and occupies 765 × 490 μm2. Wafer mapping of the radiometer sensitivity and of the amplifier gain was performed across different process splits. The mapping results demonstrate that the radiometer can be employed as a relatively simple and area-efficient transistor noise-measure monitor, useful in SiGe HBT vertical profile optimization.
Autors: Dacquay, E.;Tomkins, A.;Yau, K.H.K.;Laskin, E.;Chevalier, P.;Chantre, A.;Sautreuil, B.;Voinigescu, S.P.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2012, volume: 60, issue:3, pages: 813 - 826
Publisher: IEEE
 
» Extraction From Conductance-Frequency Measurements using a Transmission-Line Model in Weak Inversion of nMOSFETs
Abstract:
The density of interface states Dit in metal-gate/high-k dielectric MOSFETs is investigated in weak inversion from small-signal capacitance and conductance measurements using a transmission-line model. A presence of both, a large Dit, and a high channel resistance, i.e., the latter exacerbated by poor effective mobility, are demonstrated in capacitance-voltage ( CV) characteristics by a comparison of experiments with simulations using a Schrodinger-Poisson solver. Using a transmission-line network, the channel response and the density of interface states can be accurately modeled from the conductance-frequency characteristics. This technique is applied to HfO2/SiO2 dielectric MOSFETs with polysilicon and poly/TiN metal gates deposited and annealed at identical temperature. In such a condition, the density of interface states is twice as large as for a TiN metal gate.
Autors: Sicre, S.B.F.;De Souza, M.M.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Mar 2012, volume: 59, issue:3, pages: 827 - 834
Publisher: IEEE
 
» -Based Resistive Memory With MIS Structure Formed on Ge Layer
Abstract:
Resistive random access memory (RRAM) cells with a thin oxygen-deficient ZrTiOx, film topped by a Ti oxygen- gettering layer and a Pt electrode were fabricated on n-Ge layer, and the switching mechanism, as well as electrical characteristics, was explored. The RRAM cells demonstrate a stable bipolar switching behavior without the requirement of a forming process. Because of the existence of a larger amount of interface traps which would trap carriers and help build a favorable electric field for the drift of oxygen vacancies, the RRAM cells possess lower SET and RESET voltages compared to those fabricated on n-Si layer. With many promising properties such as a large sensing margin of 300 times, a high operation speed of 250 ns, a robust endurance of 105 cycles, and a long data retention time of up to 10 years, the ZrTiOx-based RRAM cells exhibit a promising perspective as nonvolatile memory devices for Ge-based technology.
Autors: Yung-Hsien Wu;Jia-Rong Wu;Chin-Yao Hou;Chia-Chun Lin;Min-Lin Wu;Lun-Lun Chen;
Appeared in: IEEE Electron Device Letters
Publication date: Mar 2012, volume: 33, issue:3, pages: 435 - 437
Publisher: IEEE
 
» Time Algorithm for Optimal Buffer Insertion of Nets With Sinks
Abstract:
Buffer insertion is an effective technique to reduce interconnect delay. In this paper, we give a simple O(mn) time algorithm for optimal buffer insertion, where m is the number of sinks and n is the number of buffer positions. When m is small, our algorithm is a significant improvement over the recent O(nlog2n) time algorithm by Shi and Li, and the O(n2) time algorithm of van Ginneken. For b buffer types, our algorithms runs in O(b2n+bmn) time, an improvement of the recent O(bn2) algorithm by Li and Shi. The improvement is made possible by an innovative linked list that can perform addition of a wire, addition of a buffer in amortized O(1) time, and smart design of pointers. We then present the extension of our algorithm for the buffer cost minimization problem, which improves the previous best algorithm. On industrial test cases, the new algorithms is faster than previous best algorithms by an order of magnitude.
Autors: Zhuo Li;Ying Zhou;Weiping Shi;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Mar 2012, volume: 31, issue:3, pages: 437 - 441
Publisher: IEEE
 
» -Band Amplifiers With 6-dB Noise Figure and Milliwatt-Level 170–200-GHz Doublers in 45-nm CMOS
Abstract:
This paper presents low-noise -band amplifiers and milliwatt-level 170-200-GHz output doublers in 45-nm semiconductor-on-insulator (SOI) CMOS technology. The transistors are modeled using R/C extraction and full electromagnetic modeling. The measured of a 30 1- transistor is 200-210 GHz at a bias current of 0.3-0.5 . A three-stage -band amplifier shows a record noise figure of 6.0 dB and a saturated output power of 7.5-8.0 dBm with a power-added efficiency of 9%, all at 95 GHz. The -band balanced doubler results in an output power of 1 mW at 180 GHz. A -band amplifier/ -band doubler chip is also demonstrated, with a peak output power of 0.5-1 mW at 170-195 GHz and a conversion gain from to . This paper shows that 45-nm SOI CMOS, built for digital and mixed-signal applications, results in state-of-the-art performance at - and -band.
Autors: Cetinoneri, B.;Atesal, Y.A.;Fung, A.;Rebeiz, G.M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2012, volume: 60, issue:3, pages: 692 - 701
Publisher: IEEE
 
» : A Spectral and Spatial Measure of Local Perceived Sharpness in Natural Images
Abstract:
This paper presents an algorithm designed to measure the local perceived sharpness in an image. Our method utilizes both spectral and spatial properties of the image: For each block, we measure the slope of the magnitude spectrum and the total spatial variation. These measures are then adjusted to account for visual perception, and then, the adjusted measures are combined via a weighted geometric mean. The resulting measure, i.e., S3 (spectral and spatial sharpness), yields a perceived sharpness map in which greater values denote perceptually sharper regions. This map can be collapsed into a single index, which quantifies the overall perceived sharpness of the whole image. We demonstrate the utility of the S3 measure for within-image and across-image sharpness prediction, no-reference image quality assessment of blurred images, and monotonic estimation of the standard deviation of the impulse response used in Gaussian blurring. We further evaluate the accuracy of S3 in local sharpness estimation by comparing S3 maps to sharpness maps generated by human subjects. We show that S3 can generate sharpness maps, which are highly correlated with the human-subject maps.
Autors: Vu, C.T.;Phan, T.D.;Chandler, D.M.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Mar 2012, volume: 21, issue:3, pages: 934 - 945
Publisher: IEEE
 
» A (64,45) Triple Error Correction Code for Memory Applications
Abstract:
Memories are commonly protected with error correction codes to avoid data corruption when a soft error occurs. Traditionally, per-word single error correction (SEC) codes are used. This is because they are simple to implement and provide low latency. More advanced codes have been considered, but their main drawback is the complexity of the decoders and the added latency. Recently, the use of one-step majority logic decodable codes has been proposed for memory protection. One-step majority logic decoding enables the use of low-complexity decoders, and low latency can also be achieved with moderate complexity. The main issue is that there are only a few codes that are one-step majority logic decodable. This restricts the choice of word lengths and error correction capabilities. In this paper, a method to derive new codes from a class of one-step majority logic decodable codes known as difference-set codes is proposed. The derived codes can also be efficiently implemented. As an example, a (64,45) triple error correction (TEC) code is derived and compared with existing SEC and TEC codes. The results presented enable a wider choice of word lengths and error correction capabilities that will be useful for memory designs.
Autors: Reviriego, P.;Flanagan, M.;Maestro, J. A.;
Appeared in: IEEE Transactions on Device and Materials Reliability
Publication date: Mar 2012, volume: 12, issue:1, pages: 101 - 106
Publisher: IEEE
 
» A 0.5-V 35- W 85-dB DR Double-Sampled Modulator for Audio Applications
Abstract:
This paper presents a 0.5-V 1.5-bit double-sampled modulator for audio applications. Unlike existing double-sampled designs, the proposed double-sampled modulator employs an input-feedforward topology to reduce internal signal swings, thereby relaxing design requirements for the low-voltage building blocks and reducing distortion. Moreover, in order to avoid instability and noise shaping degradation, the proposed architecture restores the noise transfer function (NTF) of the double-sampled modulator to its single-sampled equivalent with the help of compensation loops. In the circuit implementation, the proposed fully-differential amplifier adopts an inverter output stage and a common-mode feedback (CMFB) circuit with a global feedback loop in order to reduce power consumption. A resistor-string-reference switch matrix based on a direct summation quantizer is used to simplify the analog compensation loop. The chip prototype has been fabricated in a 0.13- CMOS technology with a core area of 0.57 . The measured results show that when operating from a 0.5-V supply and clocked at 1.25 MHz, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 81.7 dB, a peak signal-to-noise ratio (SNR) of 82.4 dB and a dynamic range (DR) of 85.0 dB while consuming 35.2 for a 20-kHz signal bandwidth.
Autors: Yang, Z.;Yao, L.;Lian, Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2012, volume: 47, issue:3, pages: 722 - 735
Publisher: IEEE
 
» A 0.5-V 35- W 85-dB DR Double-Sampled Modulator for Audio Applications
Abstract:
This paper presents a 0.5-V 1.5-bit double-sampled ΔΣ modulator for audio applications. Unlike existing double-sampled designs, the proposed double-sampled ΔΣ modulator employs an input-feedforward topology to reduce internal signal swings, thereby relaxing design requirements for the low-voltage building blocks and reducing distortion. Moreover, in order to avoid instability and noise shaping degradation, the proposed architecture restores the noise transfer function (NTF) of the double-sampled modulator to its single-sampled equivalent with the help of compensation loops. In the circuit implementation, the proposed fully-differential amplifier adopts an inverter output stage and a common-mode feedback (CMFB) circuit with a global feedback loop in order to reduce power consumption. A resistor-string-reference switch matrix based on a direct summation quantizer is used to simplify the analog compensation loop. The chip prototype has been fabricated in a 0.13-μm CMOS technology with a core area of 0.57 mm2. The measured results show that when operating from a 0.5-V supply and clocked at 1.25 MHz, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 81.7 dB, a peak signal-to-noise ratio (SNR) of 82.4 dB and a dynamic range (DR) of 85.0 dB while consuming 35.2 μW for a 20-kHz signal bandwidth.
Autors: Zhenglin Yang;Libin Yao;Yong Lian;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2012, volume: 47, issue:3, pages: 722 - 735
Publisher: IEEE
 
» A 1 W 104 dB SNR Filter-Less Fully-Digital Open-Loop Class D Audio Amplifier With EMI Reduction
Abstract:
This paper presents the design and implementation of a high-performance fully-digital PWM DAC and switching output stage which can drive a speaker in portable devices, including cellular phones. Thanks to the quaternary pulse-width modulation scheme, filter-less implementation are possible. A pre-modulation DSP algorithm eliminates the harmonic distortion inherent to the employed modulation process, and an oversampling noise shaper reduces the modulator clock speed to facilitate the hardware implementation while keeping high-fidelity quality. Radiated electromagnetic field emission of the class D amplifier is reduced thanks to a clock spreading technique with only a minor impact on audio performance characteristics. Clock jitter effects on the audio amplifier performance are presented, showing very low degradation for jitter value up to a few nanoseconds. The digital section works with a 1.2 V power supply voltage, while the output switching stage and its driver are supplied from a high-efficiency DC-DC converter either at 3.6 V or 5 V. An output power of 0.5 W at 3.6 V and 1 W at 5 V over an 8 load with efficiency (digital section included) of about 79% and 81%, respectively, has been achieved. The total harmonic distortion (THD) at maximum output level is about 0.2%, while the dynamic range is 104 dB A-weighted. The active area is about 0.94 mm in a 0.13 m single-poly, five-metal, N-well digital CMOS technology with double-oxide option (0.5 m minimum length).
Autors: Guanziroli, F.;Bassoli, R.;Crippa, C.;Devecchi, D.;Nicollini, G.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2012, volume: 47, issue:3, pages: 686 - 698
Publisher: IEEE
 
» A 1.25 ps Resolution 8b Cyclic TDC in 0.13 m CMOS
Abstract:
This paper describes the first implementation of the well-known cyclic ADC architecture into a time-to-digital converter. With an asynchronous clocking scheme, an all-digital 1.5b time-domain multiplying DAC (MDAC) is repetitively used for 8b conversion. The MDAC is based on a 2 time amplifier with an offset-compensated gain calibration scheme. The proposed cyclic TDC, fabricated in a 0.13 CMOS, shows a resolution of 1.25 ps with a total conversion range of 160 ps, the maximum operating frequency of 100 MHz, and a power consumption of 4.3 mW at 50 MHz. The measured DNL and INL are 0.7 LSB and 3 to 1 LSB, respectively.
Autors: Seo, Y.-H.;Kim, J.-S.;Park, H.-J.;Sim, J.-Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2012, volume: 47, issue:3, pages: 736 - 743
Publisher: IEEE
 
» A 1.2V, 130nm CMOS parallel continuous-time ?? ADC for OFDM UWB receivers
Abstract:


Autors:

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Appeared in: Microelectronics Journal
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» A 1.9–3.8 GHz Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency
Abstract:
A fast and high-precision all-digital automatic calibration circuit that is highly suited for fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range. A high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with a sub- frequency resolution of in a time period of . The on-chip detected VCO frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain and uses it to precisely control the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate modulator to achieve sub- calibration resolution, which makes this technique much accurate and faster than the conventional ones. A 1.9–3.8 GHz fractional-N synthesizer is implemented in 0.13 m CMOS, demonstrating that the loop bandwidth calibration is completed in 1.1–6.0 s with ${pm}2- hbox{%}$ accuracy and the VCO frequency calibration is completed in 1.225–4.025 s, all across the entire octave tuning range.
Autors: Shin, J.;Shin, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2012, volume: 47, issue:3, pages: 665 - 675
Publisher: IEEE
 
» A 1.9–3.8 GHz Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency
Abstract:
A fast and high-precision all-digital automatic calibration circuit that is highly suited for ΔΣ fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range. A high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with a sub-fREF frequency resolution of fREF/k in a time period of k·TREF. The on-chip detected VCO frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain KVCO and uses it to precisely control the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate ΔΣ modulator to achieve sub- fREF calibration resolution, which makes this technique much accurate and faster than the conventional ones. A 1.9-3.8 GHz ΔΣ fractional-N synthesizer is implemented in 0.13 μm CMOS, demonstrating that the loop bandwidth calibration is completed in 1.1-6.0 μs with ±2% accuracy and the VCO frequency calibration is completed in 1.225-4.025 μs, all across the entire octave tuning range.
Autors: Jaewook Shin;Hyunchol Shin;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2012, volume: 47, issue:3, pages: 665 - 675
Publisher: IEEE
 
» A 10-b 100-kS/s 1-mW General-Purpose ADC for Cellular Telephones
Abstract:
An on-demand general-purpose analog-to-digital converter (GPADC), which achieves a 10-b accuracy of up to 100-kS/s request rate, is presented. The GPADC can process single-ended signals with selectable input ranges up to the battery voltage. The range selection accuracy is 1 LSB. The DAC architecture presents the benefits of a differential approach while sampling single-ended input signals. Built-in reference buffer and oscillator are included. An external clock source is not needed; only a conversion request signal is necessary. Dedicated low-power design solutions have been introduced to reduce power consumption at the maximum conversion request speed to about 1 mW at a 2.0-V supply voltage. New design solutions have been introduced to comply with system-level requirements, such as scaling and shifting of the battery voltage, buffering low-frequency input signals with high source impedance, and to cope with the presence of input signals with voltage levels higher than the GPADC supply voltage when the battery is discharged. The active area is about 0.58 in a 0.35- single-poly 5-metal CMOS technology with a MIM capacitor option.
Autors: Zamprogno, M.;Minuti, A.;Girardi, F.;Confalonieri, P.;Nicollini, G.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Mar 2012, volume: 59, issue:3, pages: 138 - 142
Publisher: IEEE
 
» A 12-bit 20 MS/s 56.3 mW Pipelined ADC With Interpolation-Based Nonlinear Calibration
Abstract:
The linearity of a high-resolution pipelined analog- to-digital converter (ADC) is mainly limited by the capacitor mismatch and the finite operational amplifier (OPAMP) gain in the multiplying-digital-to-analog converter (MDAC). Therefore, high resolution pipelined ADCs usually require high-gain OPAMP and large capacitors, which causes large ADC power. In recent years, various nonlinear calibration techniques have been developed to compensate both linear and nonlinear error from MDCAs so that low-power MDACs with small capacitors and low-gain OPAMP can be used. Hence, the ADC power can be greatly reduced. This paper introduces a novel interpolation- based digital self-calibration architecture for pipelined ADC. Compared to previous techniques, the new architecture is free of adaptation. Hence, long convergence is not needed. The complexity of the digital processor is also considerably lower. The new architecture does not use backend ADC to measure MDACs. Hence, it is free of the accumulation of measurement error, which leads to more accurate calibration. A prototype ADC with the calibration architecture is fabricated in a 0.35 3.3 V CMOS process. The ADC samples at 20 MS/s. The calibration improves the ADC DNL and INL from 1.47 LSB and 7.85 LSB to 0.2 LSB and 0.27 LSB. For a 590 kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio(SNDR) and spurious-free dynamic range (SFDR) from 41.3 dB and 52.1 dB to 72.5 dB and 84.4 dB respectively. The 11.8-ENOB 20 MS/s ADC consumes 56.3 mW power with 3.3 V supply. The 0.78 pJ/step figure-of-merit (FOM) is low for designs in 0.35 CMOS processes. At the Nyquist frequency, SNDR of the calibrated ADC drops 8 dB due to the slow settling of the first pipeline stage.
Autors: Yuan, J.;Fung, S. W.;Chan, K. Y.;Xu, R.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Mar 2012, volume: 59, issue:3, pages: 555 - 565
Publisher: IEEE
 
» A 15 MHz to 600 MHz, 20 mW, 0.38 mm Split-Control, Fast Coarse Locking Digital DLL in 0.13 m CMOS
Abstract:
A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40 ) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (9 ps rms @ 600 MHz) and tracks process, voltage, and temperature (PVT) variations. The false harmonic locking detector, the frequency range and the jitter performance among other design considerations are analyzed in detail. The DLL consumes 20 mW and occupies a 470 in 0.13 m CMOS.
Autors: Hoyos, S.;Tsang, C. W.;Vanderhaegen, J.;Chiu, Y.;Aibara, Y.;Khorramabadi, H.;Nikolic, B.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Mar 2012, volume: 20, issue:3, pages: 564 - 568
Publisher: IEEE
 
» A 16- Audio Amplifier With 93.8-mW Peak Load Power and 1.43-mW Quiescent Power Consumption
Abstract:
A low-distortion three-stage class-AB audio amplifier is designed to drive a 16- headphone speaker load. High power efficiency is achieved using fully differential internal stages with local common-mode feedback and replica biasing of the output stage. The threshold voltage of nMOS transistors was made comparable to that of pMOS transistors by negatively biasing the p-substrate in order to achieve high linearity. Multiple compensation networks guarantee the stability of the audio amplifier when driving a wide range of capacitive loads from 10 pF to 5 nF. Peak power delivered to the load is measured as 93.8 mW (corresponding to 46.9 mW RMS) with 77.9-dB total harmonic distortion; quiescent power is only 1.43 mW. The power-supply rejection ratio from both 1.5-V supplies exceeds 63 dB over the entire audio frequency range. The design is implemented in a 0.5- CMOS process and occupies 0.34 of area.
Autors: Mohan, C.;Furth, P. M.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Mar 2012, volume: 59, issue:3, pages: 133 - 137
Publisher: IEEE
 
» A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
Abstract:


Autors:

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Appeared in: Computers & Electrical Engineering
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» A 1V, 69-73GHz CMOS power amplifier based on improved Wilkinson power combiner
Abstract:


Autors:
Appeared in: Microelectronics Journal
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation
Abstract:
A 2.4 GHz reference-less single chip wireless receiver for 1 Mbps QPSK demodulation is presented. The receiver accomplishes LO carrier recovery and data demodulation directly from the RF received signal without resort to resonator based reference, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, postamplifier, and digital demodulator on a single chip, the total power consumption is 20.4 mW. The measured phase noise from a recovered carrier at 2.432 GHz is about dBc/Hz at 1 MHz offset. The chip size is 1.75 1.55 mm .
Autors: Chen, W.-Z.;Lu, T.-Y.;Ou, W.-W.;Chou, S.-T.;Yang, S.-Y.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Mar 2012, volume: 59, issue:3, pages: 505 - 514
Publisher: IEEE
 
» A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS
Abstract:
An ultra-low voltage switched-capacitor (SC) converter running at a record low supply voltage of only 250 mV is introduced. System level aspects are discussed and special circuit techniques described, that enable robust operation at such a low supply voltage. Using a SC biasing approach, inverter-based integrators are realized with overdrives close to the transistor threshold voltage while compensating for process, voltage and temperature (PVT) variation. Biasing voltages are generated on-chip using a novel level shifting circuit, that overcomes headroom limitations due to saturation voltage . With an oversampling ratio (OSR) of 70 and a sampling frequency of 1.4 MHz at 250 mV power supply the converter achieves 61 dB SNDR in 10 kHz bandwidth while consuming a total power of 7.5 .
Autors: Michel, F.;Steyaert, M. S. J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2012, volume: 47, issue:3, pages: 709 - 721
Publisher: IEEE
 
» A 3–5 GHz Current-Reuse -Boosted CG LNA for Ultrawideband in 130 nm CMOS
Abstract:
This paper presents a low-power CMOS transconductance “ ” boosted common gate (CG) ultrawideband (UWB) low noise amplifier (LNA) architecture, operating in the 3–5 GHz range, employing current-reuse technique. This proposed UWB CG LNA utilizes a common source (CS) amplifier as the -boosting stage which shares the bias current with the CG amplifying stage. A detailed mathematical analysis of the LNA is carried out and the different design tradeoffs are analyzed. The LNA circuit was designed and fabricated using the 130-nm IBM CMOS process and it achieved input return loss and output return loss variations of respectively 8.4 to 40 dB and 14 to 15 dB within the pass-band. The LNA exhibits almost flat forward power gain of 13 dB and a reverse isolation variation of 55 dB to 40 dB, along with a noise figure (NF) ranging between 3.5 and 4.5 dB. The complete circuit (with output buffer) draws only 3.4 mW from a 1 V supply voltage.
Autors: Khurram, M.;Hasan, S. M. R.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Mar 2012, volume: 20, issue:3, pages: 400 - 409
Publisher: IEEE
 
» A 3-DOF parallel manufacturing module and its kinematic optimization
Abstract:


Autors:
Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» A 3.6 mW 125.7–131.9 GHz Divide-by-4 Injection-Locked Frequency Divider in 90 nm CMOS
Abstract:
A divide-by-4 injection-locked frequency divider (ILFD) is realized in a 90 nm CMOS process. By using the coupled inductors, the locking range of the proposed divide-by-4 ILFD is enhanced. This ILFD has a measured locking range of 125.7–131.9 GHz. Its power consumption is 3.6 mW for a supply of 1.2 V. To the authors' best knowledge, this is the first CMOS divide-by-4 ILFD operated over 130 GHz.
Autors: Lee, I. T.;Wang, C.-H.;Ko, C.-L.;Juang, Y.-Z.;Liu, S.-I.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Mar 2012, volume: 22, issue:3, pages: 132 - 134
Publisher: IEEE
 
» A 3D shape segmentation approach for robot grasping by parts
Abstract:


Autors:
Appeared in: Robotics and Autonomous Systems
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O
Abstract:
This paper presents a novel all-digital CDR scheme in 90 nm CMOS. Two independently adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase is placed in the middle of the eye to recover the data (“data clock”) and the other is swept across the delay line (“search clock”). As the search clock is swept, its samples are compared against the data samples to generate eye information. This information is used to determine the best phase for data recovery. After placing the search clock at this phase, search and data functions are traded between clocks and eye monitoring repeats. By trading functions, infinite delay range is realized using only a calibrated delay line, instead of a PLL or DLL. Since each clock generates its own alignment information, mismatches in clock distribution can be tolerated. The scheme's generalized sampling and retiming architecture is used in an efficient sharing technique that reduces the number of clocks required, saving power and area in high-density interconnect. The shared CDR is implemented using static CMOS logic in a 90 nm bulk process, occupying 0.15 mm . It operates from 6 to 9 Gb/s, and consumes 2.5 mW/Gb/s of power at 6 Gb/s and 3.8 mW/Gb/s at 9 Gb/s.
Autors: Loh, M.;Emami-Neyestanak, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2012, volume: 47, issue:3, pages: 641 - 651
Publisher: IEEE
 
» A 4-GHz Active Scatterer in 130-nm CMOS for Phase Sweep Amplify-and-Forward
Abstract:
This article demonstrates the cooperative diversity improvement achieved using a 120- active scatterer built in 130-nm CMOS technology. The low-power all-analog device acts as a repeater, or relay, for phase sweep amplify-and-forward cooperative transmission. The device relies on microwave reflection to amplify, dynamically phase modulate, and reradiate the incident signal. This reduces the duration of the fades experienced in the indoor radio channel and improves error correction code performance. Radio channel propagation measurements collected using the relay prototype clearly show the effect of the phase modulation on fading and system level simulations conducted using the propagation data show a fivefold increase in coverage area.
Autors: Bousquet, J.-F.;Magierowski, S.;Messier, G. G.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Mar 2012, volume: 59, issue:3, pages: 529 - 540
Publisher: IEEE
 
» A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS
Abstract:
A low-power, 40-Gb/s optical transceiver front-end is demonstrated in a 45-nm silicon-on-insulator (SOI) CMOS process. Both single-ended and differential optical modulators are demonstrated with floating-body transistors to reach output swings of more than 2 and 4 , respectively. A single-ended gain of 7.6 dB is measured over 33 GHz. The optical receiver consists of a transimpedance amplifier (TIA) and post-amplifier with 55 dB of transimpedance over 30 GHz. The group-delay variation is 3.9 ps over the 3-dB bandwidth and the average input-referred noise density is 20.5 . The TIA consumes 9 mW from a 1-V supply for a transimpedance figure of merit of 1875 /pJ. This represents the lowest power consumption for a transmitter and receiver operating at 40 Gb/s in a CMOS process.
Autors: Kim, J.;Buckwalter, J. F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Mar 2012, volume: 47, issue:3, pages: 615 - 626
Publisher: IEEE
 
» A 44–46-GHz 16-Element SiGe BiCMOS High-Linearity Transmit/Receive Phased Array
Abstract:
This paper presents a 16-element -band transmit/receive phased array with high receive linearity and low power consumption. The design is based on the all-RF architecture with passive phase shifters and a 1:16 Wilkinson network. An input from to and a noise figure of 10–11.5 dB at 44–46 GHz is achieved in the receive mode with a power consumption of 0.95 W. In the transmit mode, each channel has an output of 3–2 dBm and of 6–4 dBm at 44–46 GHz with a power consumption of 1.16 W. The design results in a low root mean square (rms) gain error due to a high-resolution variable gain amplifier in each channel. Measurements on multiple channels show near-identical gain and phase response in both the transmit and receive mode due to the use of a symmetrical passive combiner. The measured on-chip coupling is and results in insignificant additional rms and phase error.
Autors: Kim, C.-Y.;Kang, D.-W.;Rebeiz, G. M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Mar 2012, volume: 60, issue:3, pages: 730 - 742
Publisher: IEEE
 
» A 4D Statistical Model of Wrist Bone Motion Patterns
Abstract:
Direct imaging of ligament damage in the wrist remains a challenge. Still, such damage can be assessed indirectly through the analysis of changes in wrist pose and motion pattern. For this purpose we built a statistical reference model that describes healthy motion patterns. We show that such a model can also be used to detect and quantify pathologies. A model that only describes the global translations and rotations of the carpal bones is insufficiently accurate due to size and shape variations of the bones. We present a local statistical motion model that minimizes the influence of size and shape differences by analyzing the coordinate differences of pairs of points on adjacent bone surfaces. These differences are determined in a set of 14 healthy example wrists imaged in a range of poses by means of 4D-RX imaging. The distribution of the differences as a function of the pose form the local statistical motion model (LSMM). Translations of 2 mm and rotations of 20 with respect to the healthy example wrists are detected as outliers in the point pair distributions. An evaluation involving wrists with a damaged ligament between scaphoid and lunate shows that not only joint space widenings can be detected, but also shifts of congruent bone surfaces. The LSMM is also used to perform a virtual reconstruction of the most likely healthy wrist after a simulated perturbation of bones. The reconstruction precision is shown to be about 1 mm. Therefore, the presented 4D statistical model of wrist bone movement may become a valuable clinical tool for diagnosis and surgical planning.
Autors: van de Giessen, M.;Foumani, M.;Vos, F. M.;Strackee, S. D.;Maas, M.;Van Vliet, L. J.;Grimbergen, C. A.;Streekstra, G. J.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Mar 2012, volume: 31, issue:3, pages: 613 - 625
Publisher: IEEE
 
» A 6-DOF adaptive parallel manipulator with large tilting capacity
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Autors:
Appeared in: Robotics and Computer-Integrated Manufacturing
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» A 60 dB Harmonic Rejection Mixer for Digital Terrestrial TV Tuner
Abstract:
A harmonic rejection mixer has been designed for DVB-T reception in VHFIII frequency band. It exhibits 21.3 dB noise figure, 29 dBm input IP3, and 67 dBm input IP2 over the 48–300 MHz frequency range. The third and fifth harmonics are suppressed by more than 60 dB thanks to phase error calibration.The 0.39 active die is fabricated in 40-GHz Bi-CMOS process consuming 38 mA from a 3.3 V supply including the LO chain.
Autors: Bouhamame, M.;Coco, L. L.;Amiot, S.;Toutain, S.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Mar 2012, volume: 59, issue:3, pages: 471 - 478
Publisher: IEEE
 
» A 60 GHz Current-Reuse LO-Boosting Mixer in 90 nm CMOS
Abstract:
This letter presents a 60 GHz direct down-conversion mixer in a 90 nm CMOS. The mixer consists of an RF transconductance stage, a switching stage, an LO amplification stage, a balun and a buffer amplifier, and employs a current-reuse LO-boosting technique for low power consumption with small LO input power. The measured conversion gain of the differential IF output is 12 dB at an input LO power of 13 dBm. The mixer consumes 8.8 mW and the measured 3 dB IF bandwidth is greater than 1.2 GHz. To the best of our knowledge, this mixer achieves the highest conversion gain with the lowest LO input power of all published 60 GHz band CMOS mixers.
Autors: Byeon, C. W.;Lee, J. J.;Song, I. S.;Park, C. S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Mar 2012, volume: 22, issue:3, pages: 135 - 137
Publisher: IEEE
 
» A Balanced Resource Scheduling Scheme With Adaptive Priority Thresholds for OFDMA Downlink Systems
Abstract:
This paper proposes a new balanced resource scheduling (BRS) scheme with adaptive priority thresholds for orthogonal frequency-division multiple-access (OFDMA) downlink systems. The BRS scheme achieves an excellent balance between quality-of-service (QoS) requirement guarantee and system throughput enhancement, whereas conventional schemes cannot explicitly and accurately control this tradeoff. Based on the adaptive priority threshold of each user, the BRS scheme first performs a priority-based resource allocation (RA) algorithm for users whose priority value is larger than its priority threshold to fulfill the QoS requirement. The BRS scheme then performs a channel-state-information (CSI)-based RA algorithm for the remaining users to enhance system throughput. To achieve balance between QoS guarantee and throughput enhancement, a fuzzy inference priority threshold generator adaptively and intelligently adjusts the priority threshold of each user. Simulation results show that the proposed BRS scheme with adaptive priority threshold enhances the system throughput by 16%, 8.5%, 8.2%, and 46.8% at traffic load of 0.93, compared with conventional adaptive radio RA (RRA), utility-based RRA, utility-based throughput maximization and complexity reduction scheduling, and fairness and QoS guarantee scheduling with fuzzy controls schemes, respectively, under a QoS requirement guarantee. This approach also outperforms the BRS scheme with fixed priority ''"" --thresholds in both throughput enhancement and QoS guarantee.
Autors: Chung, Y.-H.;Chang, C.-J.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Mar 2012, volume: 61, issue:3, pages: 1276 - 1286
Publisher: IEEE
 
» A band-separated, bidirectional amplifier based on erbium-doped bismuth fiber for long-reach hybrid DWDM-TDM passive optical networks
Abstract:
We propose a band-separated, bidirectional amplifier based on a bismuth-based erbium-doped fiber for use in long-reach hybrid dense wavelength division multiplexing-time division multiplexing passive optical networks (DWDM-TDM-PONs). We also propose a long-reach hybrid DWDM-TDM-PON architecture in which the proposed amplifier can be effectively used. The feasibility of using the proposed amplifier for long-reach hybrid DWDM-TDM-PONs is experimentally investigated by performing a series of signal transmission experiments with an exemplary PON configuration having a total reach of 75 km and 8 split users. Error-free bidirectional signal transmission at a line rate of 10 Gbit/s is successfully demonstrated. A theoretical investigation also shows that the reach/split limitation issue associated with an insufficient WDM signal gain in the experimental demonstration can be easily solved by optimizing the amplifier.
Autors: Jung, Minwan;Chang, You Min;Lee, Ju Han;
Appeared in: IEEE/OSA Journal of Optical Communications and Networking
Publication date: Mar 2012, volume: 4, issue:3, pages: 165 - 172
Publisher: IEEE
 
» A Bayesian approach for place recognition
Abstract:


Autors:
Appeared in: Robotics and Autonomous Systems
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» A Bayesian estimation for single target tracking based on state mixture models
Abstract:


Autors:
Appeared in: Signal Processing
Publication date: Mar 2012
Publisher: Elsevier B.V.
 
» A Bayesian Framework for Automated Cardiovascular Risk Scoring on Standard Lumbar Radiographs
Abstract:
Pub DtlWe present a fully automated framework for scoring a patient's risk of cardiovascular disease (CVD) and mortality from a standard lateral radiograph of the lumbar aorta. The framework segments abdominal aortic calcifications for computing a CVD risk score and performs a survival analysis to validate the score. Since the aorta is invisible on X-ray images, its position is reasoned from 1) the shape and location of the lumbar vertebrae and 2) the location, shape, and orientation of potential calcifications. The proposed framework follows the principle of Bayesian inference, which has several advantages in the complex task of segmenting aortic calcifications. Bayesian modeling allows us to compute CVD risk scores conditioned on the seen calcifications by formulating distributions, dependencies, and constraints on the unknown parameters. We evaluate the framework on two datasets consisting of 351 and 462 standard lumbar radiographs, respectively. Promising results indicate that the framework has potential applications in diagnosis, treatment planning, and the study of drug effects related to CVD.
Autors: Petersen, K.;Ganz, M.;Mysling, P.;Nielsen, M.;Lillemark, L.;Crimi, A.;Brandt, S. S.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Mar 2012, volume: 31, issue:3, pages: 663 - 676
Publisher: IEEE
 
» A Behavior-Grounded Approach to Forming Object Categories: Separating Containers From Noncontainers
Abstract:
This paper introduces a framework that allows a robot to form a single behavior-grounded object categorization after it uses multiple exploratory behaviors to interact with objects and multiple sensory modalities to detect the outcomes that each behavior produces. Our robot observed acoustic and visual outcomes from six different exploratory behaviors performed on 20 objects (containers and noncontainers). Its task was to learn 12 different object categorizations (one for each behavior–modality combination), and then to unify these categorizations into a single one. In the end, the object categorization acquired by the robot matched closely the object labels provided by a human. In addition, the robot acquired a visual model of containers and noncontainers based on its unified categorization, which it used to label correctly 29 out of 30 novel objects.
Autors: Griffith, S.;Sinapov, J.;Sukhoy, V.;Stoytchev, A.;
Appeared in: IEEE Transactions on Autonomous Mental Development
Publication date: Mar 2012, volume: 4, issue:1, pages: 54 - 69
Publisher: IEEE
 

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