Electrical and Electronics Engineering publications abstract of: 01-2016 sorted by title, page: 0

» $100 million seti initiative starts listening for E.T.
Abstract:
The search for extraterrestrial intelligence??? SETI???has a checkered history, and even its most ardent proponents accept that positive results are unlikely anytime soon. So it???s no wonder that SETI researchers often struggle to find funding. But last year the Russian billionaire Yuri Milner offered to support SETI efforts over the next 10 years with US $100 million. The first radio observations, through a program called Breakthrough Listen, will be made sometime in the next few months. And one of the early targets may be a star system that has already shown suggestions of possibly being the home of a technologically advanced alien civilization. While the chances for actually picking up signals from an E.T. remain slim, the adventure will surely be fun to watch as it unfolds this year.
Autors: Schneider, D.;
Appeared in: IEEE Spectrum
Publication date: Jan 2016, volume: 53, issue:1, pages: 41 - 42
Publisher: IEEE
 
» “Polynomial Time Verification of Decentralized Diagnosability of Discrete Event Systems” Versus “Decentralized Failure Diagnosis of Discrete Event Systems”: A Critical Appraisal
Abstract:
In [1], the authors claim that there is an oversight in [2], in the sense that the proposed verifier is, in general, nondeterministic and the computational complexity analysis is incorrect. The authors in [1] also claim that the complexity of the verification algorithm presented in [3] is reduced when considering the more restrictive setting of projection masks, in contrast to the more general non-projection masks case, and equals the complexity of the verification algorithm presented in [2]. In this note, we show that the computational complexity analysis of [2] is actually correct and that the complexity of the verification algorithm presented in [3] is not reduced without additional modification of the algorithm (not yet proposed in the literature) if projection masks are used, and, therefore, is not equal to the complexity of the algorithm presented in [2].
Autors: Moreira, M.V.;Basilio, J.C.;Cabral, F.G.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Jan 2016, volume: 61, issue:1, pages: 178 - 181
Publisher: IEEE
 
» “See Something, Say Something” Crowdsourced Enforcement of Spectrum Policies
Abstract:
As sharing agreements are being ratified by the Federal Communications Commission (FCC) for various spectrum bands for commercial broadband use, it also opens up an equally challenging problem of enforcing these policies. The efficacy of an enforcement system greatly depends on the accuracy of evidential information and the speed of adjudication. The inherent unguided and unbounded nature of radio wave propagation allows spectrum infractions to cause widespread damage and makes it hard to locate at the same time. On the other hand, it also lends itself to distributed methods for efficient enforcement of spectrum etiquette. We leverage a crowd of mobile users to implement a paradigm of “eye-witness” for detecting violations of spectrum policies. We design and analyze the crowdsourced enforcement architecture and show three main results: 1) it detects an infraction with a consistent high degree of accuracy ( ); 2) it is able to accurately locate the source of infraction and 3) it lowers the frequency of policy infractions over time.
Autors: Dutta, A.;Chiang, M.;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Jan 2016, volume: 15, issue:1, pages: 67 - 80
Publisher: IEEE
 
» ℓ1 LS and ℓ2 MMSE-Based Hybrid Channel Estimation for Intermittent Wireless Connections
Abstract:
Broadband wireless channels observed at a receiver cannot fully exhibit dense nature in a low to moderate signal-to-noise ratio (SNR) regime, if the channels follow a typical propagation scenario such as Vehicular-A or Pedestrian-B. It is hence expected that ℓ1-regularized channel estimation methods can improve channel estimation performance in the broadband wireless channels. However, it is well-known that the ℓ2 multiburst (MB) channel estimation achieves the Cramér–Rao bound (CRB) asymptotically. This is because the ℓ2 MB technique formulated as a minimum-mean-square-error (MMSE) problem improves the mean squared error (MSE) performance by utilizing the subspace projection. Performance analysis shows that ℓ1-regularized channel estimation does not improve the MSE performance significantly over the ℓ2 MB technique so far as the subspace channel model assumption is correct. We demonstrate, however, a receiver with ℓ1-regularized channel estimation can improve bit error rate (BER) performance if the assumption is not always correct. For this purpose, we focus on intermittent transmission (TX) scenario which is defined as a generalized TX sequence having arbitrary length interruption between two continuous TX bursts. A receiver with the ℓ2 MB method suffers from BER deterioration in an intermittent TX scenario having abrupt channel changes. As a solution to the problem, we propose a new algorithm which is a hybrid of ℓ1-regularized least square (LS) and ℓ2 MMSE channel estimation techniques. Simulation results show that the receiver with the proposed algorithm achieves a significant BER gain over that of the ℓ2 MB technique in the intermittent TX scenario.
Autors: Takano, Y.;Juntti, M.;Matsumoto, T.;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Jan 2016, volume: 15, issue:1, pages: 314 - 328
Publisher: IEEE
 
» (Sub-)Optimality of Treating Interference as Noise in the Cellular Uplink With Weak Interference
Abstract:
Despite the simplicity of the scheme of treating interference as noise (TIN), it was shown to be sum-capacity optimal in the Gaussian interference channel (IC) with very-weak (noisy) interference. In this paper, the two-user IC is altered by introducing an additional transmitter that wants to communicate with one of the receivers of the IC. The resulting network thus consists of a point-to-point channel interfering with a multiple access channel (MAC) and is denoted by PIMAC. The sum-capacity of the PIMAC is studied with main focus on the optimality of TIN. It turns out that TIN in its naive variant, where all transmitters are active and both receivers use TIN for decoding, is not the best choice for the PIMAC. In fact, a scheme that combines both time division multiple access and TIN (TDMA–TIN) strictly outperforms the naive-TIN scheme. Furthermore, it is shown that in some regimes, TDMA–TIN achieves the sum-capacity for the deterministic PIMAC and the sum-capacity within a constant gap for the Gaussian PIMAC. In addition, it is shown that, even for very-weak interference, there are some regimes where a combination of interference alignment with power control and TIN at the receiver side outperforms TDMA–TIN. As a consequence, on the one hand, TIN in a cellular uplink is approximately optimal in certain regimes. On the other hand, those regimes cannot be simply described by the strength of interference.
Autors: Gherekhloo, S.;Chaaban, A.;Di, C.;Sezgin, A.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2016, volume: 62, issue:1, pages: 322 - 356
Publisher: IEEE
 
» 2.07-kV AlGaN/GaN Schottky Barrier Diodes on Silicon With High Baliga’s Figure-of-Merit
Abstract:
In this letter, we demonstrate high-performance AlGaN/GaN Schottky barrier diodes (SBDs) on Si substrate with a recessed-anode structure for reduced turn-on voltage . The impact of the surface roughness after the recessed-anode formation on device characteristics is investigated. An improved surface condition can reduce the leakage current and enhance the breakdown voltage simultaneously. A low turn-on voltage of only 0.73 V can be obtained with a 50-nm recess depth. In addition, the different lengths of Schottky extension acting like a field plate are investigated. A high reverse breakdown voltage of 2070 V and a low specific ON-resistance of 3.8 yield an excellent Baliga’s figure of merit of 1127 MW/cm2, which can be attributed to the low surface roughness of only 0.6 nm and also a proper Schottky extension of 2 to alleviate the peak electric field intensity in the SBDs.
Autors: Tsou, C.;Wei, K.;Lian, Y.;Hsu, S.S.H.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2016, volume: 37, issue:1, pages: 70 - 73
Publisher: IEEE
 
» 2015 IMS Student Design Competitions
Abstract:
Presents information on MTTS 2015 IMS Student Design competitions.
Autors: Shilimkar, V.;Wang, G.;
Appeared in: IEEE Microwave Magazine
Publication date: Jan 2016, volume: 17, issue:1, pages: 40 - 41
Publisher: IEEE
 
» 2016 IMS Student Design Competitions
Abstract:
Presents information on MTTS 2016 IMS Student Design competitions.
Autors: Wong, K.;He, Q.;Barnett, R.;Caverly, R.;
Appeared in: IEEE Microwave Magazine
Publication date: Jan 2016, volume: 17, issue:1, pages: 42 - 43
Publisher: IEEE
 
» 2016 Outlook: Humans in the Technology Loop
Abstract:
Computer's digital offerings will change in 2016, and this Outlook issue offers a glimpse into the future of computing technologies. Some of the brightest spots are ubiquitous computing, human-centered software engineering, cyber-physical systems, OS design changes, and advances that will revolutionize personal medical device development.
Autors: Helal, Sumi;
Appeared in: Computer
Publication date: Jan 2016, volume: 49, issue:1, pages: 7 - 9
Publisher: IEEE
 
» 3-D-Stacked 16-Mpixel Global Shutter CMOS Image Sensor Using Reliable In-Pixel Four Million Microbump Interconnections With 7.6- Pitch
Abstract:
We have developed a 3-D-stacked 16-Mpixel, 3.8- pitch, and global shutter (GS) CMOS image sensor with a 2-Mpixel 10 000-frames/s high-speed image-capturing mode, with four million reliable microbump interconnections. This sensor consists of a photodiode (PD) substrate and an in-pixel storage node substrate. The four PDs in the unit pixel circuit on the top substrate share one microbump interconnection in 7.6- pitch. Each signal of the PDs is transferred to the corresponding storage node on the bottom substrate via the interconnection to achieve a GS function. The ratio of the parasitic light sensitivity of an in-pixel storage node and the light sensitivity of a PD is −180 dB, which is the best record for a CMOS image sensor with 3.8- pixels. The image sensor was fabricated with a wafer-on-wafer bonding process technology. We confirmed that the bonding process did not harm the pixel or the MOS transistor characteristics and required no extra area, which means no restrictions on the layout design of microbumps or circuits. No reliability problems were observed in either a heat cycle test or a high temperature and high humidity test.
Autors: Kondo, T.;Takazawa, N.;Takemoto, Y.;Tsukimura, M.;Saito, H.;Kato, H.;Aoki, J.;Kobayashi, K.;Suzuki, S.;Gomi, Y.;Matsuda, S.;Tadaki, Y.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2016, volume: 63, issue:1, pages: 128 - 137
Publisher: IEEE
 
» 4D Ultrasound Tracking of Liver and its Verification for TIPS Guidance
Abstract:
In this work we describe a 4D registration method for on the fly stabilization of ultrasound volumes for improving image guidance for transjugular intrahepatic portosystemic shunt (TIPS) interventions. The purpose of the method is to enable a continuous visualization of the relevant anatomical planes (determined in a planning stage) in a free breathing patient during the intervention. This requires registration of the planning information to the interventional images, which is achieved in two steps. In the first step tracking is performed across the streaming input. An approximate transformation between the reference image and the incoming image is estimated by composing the intermediate transformations obtained from the tracking. In the second step a subsequent registration is performed between the reference image and the approximately transformed incoming image to account for the accumulation of error. The two step approach helps in reducing the search range and is robust under rotation. We additionally present an approach to initialize and verify the registration. Verification is required when the reference image (containing planning information) is acquired in the past and is not part of the (interventional) 4D ultrasound sequence. The verification score will help in invalidating the registration outcome, for instance, in the case of insufficient overlap or information between the registering images due to probe motion or loss of contact, respectively. We evaluate the method over thirteen 4D US sequences acquired from eight subjects. A graphics processing unit implementation runs the 4D tracking at 9 Hz with a mean registration error of 1.7 mm.
Autors: Banerjee, J.;Klink, C.;Niessen, W.J.;Moelker, A.;van Walsum, T.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Jan 2016, volume: 35, issue:1, pages: 52 - 62
Publisher: IEEE
 
» 4H-SiC p-i-n diode as Highly Linear Temperature Sensor
Abstract:
The linear dependence on temperature of the voltage drop across a forward-biased 4H-SiC p-i-n diode is investigated experimentally. The results show that the fabricated temperature sensor has a high degree of linearity in the range from room temperature up to 573 K corresponding to a root-mean-square error lower than 0.5%. A maximum sensitivity of 2.66 mV/K was calculated. The low saturation current of the p-i-n diode, well below the forward biasing current also at high temperatures, reduces the nonlinear effects in the – characteristic allowing the design and fabrication of highly linear sensors operating in a wider temperature range.
Autors: Rao, S.;Pangallo, G.;Della Corte, F.G.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2016, volume: 63, issue:1, pages: 414 - 418
Publisher: IEEE
 
» 4K Real-Time and Parallel Software Video Decoder for Multilayer HEVC Extensions
Abstract:
Two High Efficiency Video Coding (HEVC) extensions, namely, the scalable HEVC (SHVC) extension and multiview HEVC (MV-HEVC) extension, have been finalized in July 2014 by the Moving Picture Experts Group and Video Coding Experts Group. These two extensions enable additional features not covered in the first version of the HEVC standard such as spatial, fidelity, bitdepth, and color gamut scalability, as well as stereoscopic and multiview representations. In this paper, we propose a software parallel decoder architecture for the HEVC standard and its multilayer extensions, including SHVC and MV-HEVC extensions. The decoder consists of multiple instances of the OpenHEVC decoder, one instance to decode each layer with a communication between dependent layers to perform inter-layer predictions. The proposed multilayer HEVC decoder is parallel friendly and supports both wavefront parallelism to simultaneously process adjacent rows of the frame and frame-based parallelism to decode a set of temporal and spatial frames in parallel. Moreover, the most time-consuming operation introduced in the SHVC extension, namely, the resampling of the inter-layer reference picture in spatial scalability, is optimized in single instruction multiple data for x86 platform. We assess the complexity of the multilayer HEVC decoder with respect to the simulcast configuration. The multilayer decoder decoding two SHVC layers introduces in average 40%–71% additional complexity compared with the single layer HEVC decoder. Moreover, the low level optimizations with a hybrid parallel processing solution enable a real-time decoding of 4Kp60 enhancement layer on a 6-core Intel i7 processor running at 3.4 GHz.
Autors: Hamidouche, W.;Raulet, M.;Deforges, O.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Jan 2016, volume: 26, issue:1, pages: 169 - 180
Publisher: IEEE
 
» 4K Real-Time HEVC Decoder on an FPGA
Abstract:
With the popularization of a quad high-definition/4K video being dependent on the availability of real-time High Efficiency Video Coding (HEVC) decoders, hardware implementations have become more appealing due to their superior performance and low power consumption. In this paper, a field-programmable gate array (FPGA)-based hardware implementation of a 4K 30 frames/s real-time HEVC decoder is presented. An elastically pipelined decoder architecture is used to absorb variations in processing time and each pipeline stage is optimized to use available FPGA primitives. FPGA-specific challenges in managing critical path delays to achieve a target operating frequency of 150 MHz required many architectural novelties, such as exploitation of the sparsity of transformed coefficient matrix, single-cycle reference pixel processing in intra prediction, and flexible block ordering in deblocking filter/sample adaptive offset filter. A high-throughput latency-aware cache architecture was used to reduce the external dynamic RAM access bandwidth by 70%. This work is compliant with the HEVC main profile at level 5 of the HEVC standard and only consumes 126K lookup tables, 58K registers, and 335 18-kb block RAMs when implemented on Xilinx Zynq 7045.
Autors: Abeydeera, M.;Karunaratne, M.;Karunaratne, G.;De Silva, K.;Pasqual, A.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Jan 2016, volume: 26, issue:1, pages: 236 - 249
Publisher: IEEE
 
» 802 Standards
Abstract:
Computer Society celebrates its 70th anniversary by looking back at the accomplishments of its members and volunteers. This issue celebrates the volunteers who helped create the 802 Standards.
Autors: Nikolich, Paul;Christensen, Kenneth;Cameron, Lori;
Appeared in: Computer
Publication date: Jan 2016, volume: 49, issue:1, pages: 10 - 10
Publisher: IEEE
 
» -Regularized Least Squares and Critical Path
Abstract:
This paper elucidates the underlying structures of -regularized least squares problems in the nonconvex case of . The difference between two formulations is highlighted (which does not occur in the convex case of ): 1) an -constrained optimization ( ) and 2) an -penalized (unconstrained) optimization . It is shown that the solution path of is discontinuous and also a part of the solution path of ( ). As an alternative to the solution path, a critical path is considered, which is a maximal continuous curve consisting of critical points. Critical paths are piecewise smooth, as can be seen from the viewpoint of the variational method, and generally contain non-optimal points, such as saddle points and local maxima as well as global/local minima. Our study reveals multiplicity (non-monotonicity) in the correspondence between the regularization parameters of and . Two particular paths of critical points connecting the origin and an ordinary least squares (OLS) solution a- e studied further. One is a main path starting at an OLS solution, and the other is a greedy path starting at the origin. Part of the greedy path can be constructed with a generalized Minkowskian gradient. This paper of greedy path leads to a nontrivial close-link between the optimization problem of -regularized least squares and the greedy method of orthogonal matching pursuit.
Autors: Yukawa, M.;Amari, S.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2016, volume: 62, issue:1, pages: 488 - 502
Publisher: IEEE
 
» LS and MMSE-Based Hybrid Channel Estimation for Intermittent Wireless Connections
Abstract:
Broadband wireless channels observed at a receiver cannot fully exhibit dense nature in a low to moderate signal-to-noise ratio (SNR) regime, if the channels follow a typical propagation scenario such as Vehicular-A or Pedestrian-B. It is hence expected that -regularized channel estimation methods can improve channel estimation performance in the broadband wireless channels. However, it is well-known that the multiburst (MB) channel estimation achieves the Cramér–Rao bound (CRB) asymptotically. This is because the MB technique formulated as a minimum-mean-square-error (MMSE) problem improves the mean squared error (MSE) performance by utilizing the subspace projection. Performance analysis shows that -regularized channel estimation does not improve the MSE performance significantly over the MB technique so far as the subspace channel model assumption is correct. We demonstrate, however, a receiver with -regularized channel estimation can improve bit error rate (BER) performance if the assumption is not always correct. For this purpose, we focus on intermittent transmission (TX) scenario which is defined as a generalized TX sequence having arbitrary length interruption between two continuous TX bursts. A receiver with the MB method suffers from BER deterioration in an intermittent TX scenario having abrupt channel changes. As a solution to the problem, we propose a new algorithm which is a hybrid- of -regularized least square (LS) and MMSE channel estimation techniques. Simulation results show that the receiver with the proposed algorithm achieves a significant BER gain over that of the MB technique in the intermittent TX scenario.
Autors: Takano, Y.;Juntti, M.;Matsumoto, T.;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Jan 2016, volume: 15, issue:1, pages: 314 - 328
Publisher: IEEE
 
» NNVWC: An Efficient -Nearest Neighbors Approach Based on Various-Widths Clustering
Abstract:
The -nearest neighbor approach ( -NN) has been extensively used as a powerful non-parametric technique in many scientific and engineering applications. However, this approach incurs a large computational cost. Hence, this issue has become an active research field. In this work, a novel -NN approach based on various-widths clustering, named NNVWC, to efficiently find -NNs for a query object from a given data set, is presented. NNVWC does clustering using various widths, where a data set is clustered with a global width first and each produced cluster that meets the predefined criteria is recursively clustered with its own local width that suits its distribution. This reduces the clustering time, in addition to balancing the number of produced clusters and their respective sizes. Maximum efficiency is achieved by using triangle inequality to prune unlikely clusters. Experimental results demonstrate that $k$ NNVWC performs well in finding -NNs for query objects compared to a number of -NN search algorithms, especially for a data set with high dimensions, various distributions and large size.
Autors: Almalawi, A.M.;Fahad, A.;Tari, Z.;Cheema, M.A.;Khalil, I.;
Appeared in: IEEE Transactions on Knowledge and Data Engineering
Publication date: Jan 2016, volume: 28, issue:1, pages: 68 - 81
Publisher: IEEE
 
» LS and MMSE-Based Hybrid Channel Estimation for Intermittent Wireless Connections
Abstract:
Broadband wireless channels observed at a receiver cannot fully exhibit dense nature in a low to moderate signal-to-noise ratio (SNR) regime, if the channels follow a typical propagation scenario such as Vehicular-A or Pedestrian-B. It is hence expected that -regularized channel estimation methods can improve channel estimation performance in the broadband wireless channels. However, it is well-known that the multiburst (MB) channel estimation achieves the Cramér–Rao bound (CRB) asymptotically. This is because the MB technique formulated as a minimum-mean-square-error (MMSE) problem improves the mean squared error (MSE) performance by utilizing the subspace projection. Performance analysis shows that -regularized channel estimation does not improve the MSE performance significantly over the MB technique so far as the subspace channel model assumption is correct. We demonstrate, however, a receiver with -regularized channel estimation can improve bit error rate (BER) performance if the assumption is not always correct. For this purpose, we focus on intermittent transmission (TX) scenario which is defined as a generalized TX sequence having arbitrary length interruption between two continuous TX bursts. A receiver with the MB method suffers from BER deterioration in an intermittent TX scenario having abrupt channel changes. As a solution to the problem, we propose a new algorithm which is a hybrid- of -regularized least square (LS) and MMSE channel estimation techniques. Simulation results show that the receiver with the proposed algorithm achieves a significant BER gain over that of the MB technique in the intermittent TX scenario.
Autors: Takano, Y.;Juntti, M.;Matsumoto, T.;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Jan 2016, volume: 15, issue:1, pages: 314 - 328
Publisher: IEEE
 
» Fk Domain Imaging for Synthetic Aperture Sequential Beamforming
Abstract:
Spatial resolution in medical ultrasound images is a key component in image quality and an important factor for clinical diagnosis. In early systems, the lateral resolution was optimal in the focus but rapidly decreased outside the focal region. Improvements have been found in, e.g., dynamic-receive beamforming, in which the entire image is focused in receive, but this requires complex processing of element data and is not applicable for mechanical scanning of single-element images. This paper exploits the concept of two-stage beamforming based on virtual source–receivers, which reduces the front-end computational load while maintaining a similar data rate and frame rate compared to dynamic-receive beamforming. We introduce frequency–wavenumber domain data processing to obtain fast second-stage data processing while having similarly high lateral resolution as dynamic-receive beamforming and processing in time-space domain. The technique is very suitable in combination with emerging technologies such as application-specific integrated circuits (ASICs), hand-held devices, and wireless data transfer. The suggested method consists of three steps. In the first step, single-focused RF line data are shifted in time to relocate the focal point to a new origin . This new origin is considered as an array of virtual source/receiver pairs, as has been suggested previously in literature. In the second step, the dataset is efficiently processed in the wavenumber–frequency domain to form an image that is in focus throughout its entire depth. In the third step, the data shift is undone to obtain a correct depth axis in the image. The method has been tested first with a single-element scanning system and second in a tissue-mimicking phantom using a linear array. In both setups, the method resulted in a $- {6}{text{-dB}}- lateral point spread function (PSF) which was constant over the entire depth range, and similar to dynamic-receive beamforming and synthetic aperture sequential beamforming. The signal-to-noise ratio increased by 6 dB in both the near field and far field. These results show that the second-stage processing algorithm effectively produces a focused image over the entire depth range from a single-focused ultrasound field.
Autors: Vos, H.J.;van Neer, P.L.M.J.;Mota, M.M.;Verweij, M.D.;van der Steen, A.F.W.;Volker, A.W.F.;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Jan 2016, volume: 63, issue:1, pages: 60 - 71
Publisher: IEEE
 
» In Vivo Quantification of the Nonlinear Shear Modulus in Breast Lesions: Feasibility Study
Abstract:
Breast cancer detection in the early stages is of great importance since the prognosis, and the treatment depends more on this. Multiple techniques relying on the mechanical properties of soft tissues have been developed to help in early detection. In this study, we implemented a technique that measures the nonlinear shear modulus (NLSM) ( ) in vivo and showed its utility to detect breast lesions from healthy tissue. The technique relies on the acoustoelasticity theory in quasi-incompressible media. In order to recover , static elastography and supersonic shear imaging are combined to subsequently register strain maps and shear modulus maps while the medium is compressed. Then, can be recovered from the relationship between the stress, deduced from strain maps, and the shear modulus. For this study, a series of five nonlinear phantoms were built using biological tissue (pork liver) inclusions immersed in an agar-gelatin gel. Furthermore, 11 in vivo acquisitions were performed to characterize the NLSM of breast tissue. The phantom results showed a very good differentiation of the liver inclusions when measuring with a mean value of compared to for the gelatin. Meanwhile, values for the shear modulus for the liver and the gelatin were very similar, 3.7 and 3.4 kPa, respectively. In vivo NLSM mean value for the healthy breast tissue was of $- {{95}};{text{kPa}}$, while mean values of the benign and the malignant lesions were and with a strong variability, respectively. This study shows the potential of the acoustoelasticity theory in quasi-incompressible medium to bring a new parameter for breast cancer diagnosis.
Autors: Bernal, M.;Chammings, F.;Couade, M.;Bercoff, J.;Tanter, M.;Gennisson, J.;
Appeared in: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
Publication date: Jan 2016, volume: 63, issue:1, pages: 101 - 109
Publisher: IEEE
 
» A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13- CMOS Process
Abstract:
This brief presents a fully integrated frequency synthesizer for software-defined radios covering not only all the existing wireless standards from 47 MHz to 10 GHz [including 14-band multiband orthogonal frequency-division modulation (MB-OFDM) ultrawideband (UWB)] but also the gigabits per second wireless communication around 60 GHz. A dual-band quadrature output voltage-controlled oscillatior reconfigurable as either a one-port oscillator for low power consumption or a two-port oscillator for low phase noise is employed as the core to generate all the frequencies from 47 MHz to 6 GHz. A multimode x3/x5/x7 injection-locked frequency multiplier and a single-sideband mixer with a tunable transformer-based narrow-band load are proposed to generate the carrier frequencies for the 14 MB-OFDM and impulse UWB bands with fast settling time, low power, and small chip area. An automatic amplitude calibration (APC) technique is proposed to greatly increase the locking range of the subharmonic injection-locked oscillators with achieving a given output amplitude. Implemented in a 0.13- CMOS process, the synthesizer prototype occupies an active area of 3 , consumes 33–83 mW in total, and measures phase noise of −139.6 dBc/Hz at 3-MHz offset from a 1.7-GHz carrier.
Autors: Rong, S.;Yin, J.;Luong, H.C.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2016, volume: 63, issue:1, pages: 109 - 113
Publisher: IEEE
 
» A 0.20 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS
Abstract:
Miniature -sized sensor nodes have a very tight power budget, in particular, when a long operational lifetime is required, which is the case, e.g., for implantable devices or unobtrusive IoT nodes. This paper presents a fully integrated signal acquisition IC for these emerging applications. It integrates an amplifier with 32 dB gain and 370 Hz bandwidth that includes positive feedback to enhance input impedance and dc offset compensation. The IC includes also a 10 bit 1 kS/s SAR ADC as well as a clock generator and voltage and current biasing circuits. The overall system achieves an input noise of , consumes 3 nW from a 0.6 V supply, occupies in 65 nm CMOS, and has a single-wire data interface. The amplifier achieves an noise-efficiency factor (NEF) of 2.1 and the ADC has a figure-of-merit (FoM) of 1.5 fJ/conversion-step. Measurements confirm reliable operation for supplies from 0.50 to 0.70 V and temperatures in the range of 0–85 °C. As an application example, an ECG recording is successfully performed with the system while a photodiode array provides its power supply in indoor lighting conditions.
Autors: Harpe, P.;Gao, H.;Dommele, R.v.;Cantatore, E.;van Roermund, A.H.M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 240 - 248
Publisher: IEEE
 
» A 0.20 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS
Abstract:
Miniature -sized sensor nodes have a very tight power budget, in particular, when a long operational lifetime is required, which is the case, e.g., for implantable devices or unobtrusive IoT nodes. This paper presents a fully integrated signal acquisition IC for these emerging applications. It integrates an amplifier with 32 dB gain and 370 Hz bandwidth that includes positive feedback to enhance input impedance and dc offset compensation. The IC includes also a 10 bit 1 kS/s SAR ADC as well as a clock generator and voltage and current biasing circuits. The overall system achieves an input noise of , consumes 3 nW from a 0.6 V supply, occupies in 65 nm CMOS, and has a single-wire data interface. The amplifier achieves an noise-efficiency factor (NEF) of 2.1 and the ADC has a figure-of-merit (FoM) of 1.5 fJ/conversion-step. Measurements confirm reliable operation for supplies from 0.50 to 0.70 V and temperatures in the range of 0–85 °C. As an application example, an ECG recording is successfully performed with the system while a photodiode array provides its power supply in indoor lighting conditions.
Autors: Harpe, P.;Gao, H.;Dommele, R.v.;Cantatore, E.;van Roermund, A.H.M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 240 - 248
Publisher: IEEE
 
» A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications
Abstract:
A 4 K 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.49 1.45 mm die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content features leading to over 68.5% and 83% of complexity reduction in intra and inter coding, respectively. A fully parallel processing element (PE) array is adopted in SAO and IP/ME, which reduce number of accesses to SRAM by 48.7% and 78.4%, respectively. A shared memory management unit (MMU) including line-store SRAM pool (LSSP) and data bus translation (DBT) techniques efficiently reuses and packs the neighboring pixels which contribute 71.6% of external bandwidth reduction. This chip achieves 4096 2160@30 fps HEVC encoding/decoding and consumes 126.73 mW, 0.5 nJ/pixel of energy efficiency, under 494 MHz and 350 MHz of clock frequency, enabling 4 K video services for smart-phone applications.
Autors: Ju, C.-C.;Liu, T.-M.;Lee, K.-B.;Chang, Y.-C.;Chou, H.-L.;Wang, C.-M.;Wu, T.-H.;Lin, H.-M.;Huang, Y.-H.;Cheng, C.-Y.;Lin, T.-A.;Chen, C.-C.;Lin, Y.-K.;Chiu, M.-H.;Li, W.-C.;Wang, S.-J.;Lai, Y.-C.;Chao, P.;Chien, C.-D.;Hu, M.-J.;Wang, P.-H.;Huang, Y.-C
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 56 - 67
Publisher: IEEE
 
» A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling
Abstract:
In energy-efficient processing platforms, such as wearable sensors and implantable medical devices, dynamic voltage and frequency scaling allows optimizing the energy efficiency under various modes of operation. The clock generator used in these platforms should be capable of achieving a faster settling time and has a wider operating voltage range. In this brief, a fast lock-in all-digital phase-locked loop (ADPLL) with two operation modes (0.52/1 V) is presented. The proposed ADPLL can quickly compute the desired digitally controlled oscillator control code with high accuracy. Therefore, the proposed ADPLL can achieve a fast setting time with frequency errors <5% within four clock cycles. The proposed ADPLL is implemented using a standard performance 90-nm CMOS process. The output frequency of the ADPLL ranges from 60 to 600 MHz at 1 V, and from 30 to 120 MHz at 0.52 V. The power consumption of the proposed ADPLL is 0.92 mW at (1 V, 600 MHz), and 37 at (0.52 V, 120 MHz).
Autors: Chung, C.;Su, W.;Lo, C.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2016, volume: 24, issue:1, pages: 408 - 412
Publisher: IEEE
 
» A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry
Abstract:
A 0.6–1.1 V, 84 Mb pipelined SRAM array design implemented in 14 nm FinFET CMOS technology is presented. Two array architectures featuring a high-density 0.0500 µm 2 6T SRAM bitcell and a 0.0588 µm 2 6T SRAM bitcell targeting low voltage operation are detailed. The high-density array design reaches 2.7 GHz at 1.1 V with 14.5 Mb/mm 2 bit density, while the low voltage optimized array can operate at 0.6 V, 1.5 GHz under typical process conditions. A capacitive charge-share transient voltage collapse write-assist circuit (CS-TVC) enables a 24% reduction in write energy compared to previous techniques by eliminating bias currents during operation. Technology and assist co-optimization enable 50 mV reduction in V and a 1.81× increase in density over a 22 nm design.
Autors: Karl, E.;Guo, Z.;Conary, J.;Miller, J.;Ng, Y.-G.;Nalam, S.;Kim, D.;Keane, J.;Wang, X.;Bhattacharya, U.;Zhang, K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 222 - 229
Publisher: IEEE
 
» A 1.7-in, 33-Mpixel, 120-frames/s CMOS Image Sensor With Depletion-Mode MOS Capacitor-Based 14-b Two-Stage Cyclic A/D Converters
Abstract:
A 1.7-in, 33-Mpixel, 120-frames/s, 14-bit CMOS image sensor has been developed. The 7936 (H) (V) pixel CMOS image sensor, which uses 14-b depletion-mode MOS (DMOS) capacitor-based two-stage cyclic A/D converters (ADCs) and 64 parallel scalable low-voltage signaling output ports, operates at a data rate of 63.8 Gb/s. DMOS capacitors have a high capacitance density, but it is difficult to achieve high bit resolutions in ADCs with these capacitors because their capacitance depends on the applied voltage. Column-parallel two-stage cyclic ADCs overcome this difficulty using a split-sampling DMOS capacitors architecture. The two-stage cyclic ADC with the DMOS capacitors at a 6.4- column pitch exhibited a differential nonlinearity of 0.95/−0.80 least significant bit (LSB); the integral nonlinearity was 2.57/−28.27 LSB at a 14-b resolution. The CMOS image sensor implemented with a 90-/65-nm technology exhibited a sensitivity of 5.22 V/lx and a random noise of 3.6 with a gain of 3.3 at 120 frames/s while dissipating 3.2 W.
Autors: Yasue, T.;Kitamura, K.;Watabe, T.;Shimamoto, H.;Kosugi, T.;Watanabe, T.;Aoyama, S.;Monoi, M.;Wei, Z.;Kawahito, S.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2016, volume: 63, issue:1, pages: 153 - 161
Publisher: IEEE
 
» A 10 ps Time-Resolution CMOS Image Sensor With Two-Tap True-CDS Lock-In Pixels for Fluorescence Lifetime Imaging
Abstract:
A CMOS lock-in pixel image sensor with embedded storage diodes and lateral electric field modulation (LEFM) of photo-generated charge is developed for fluorescence lifetime imaging. The time-resolved CMOS image sensor (CIS) with two-tap lock-in pixels achieves a very high time resolution of 10 ps when images are averaged over 30 frames, a very short intrinsic response time of 180 ps at 374 nm, and a low temporal random noise of with true correlated double sampling (CDS) operation. In addition, by using the LEFM and optimized process, a very high extinction ratio of approximately 94% at 472 nm laser diode is achieved. The usefulness of the proposed CIS is demonstrated for fluorescence lifetime imaging with the simulation and measurement results.
Autors: Seo, M.;Kagawa, K.;Yasutomi, K.;Kawata, Y.;Teranishi, N.;Li, Z.;Halin, I.A.;Kawahito, S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 141 - 154
Publisher: IEEE
 
» A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate
Abstract:
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as shorter tPROG, lower power consumption and higher endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, we succeed in developing 128 Gb 3b/cell Vertical NAND with 32 stack WL layers for the first time, which is the smallest 128 Gb NAND Flash. The die size is 68.9 mm , program time is 700 us and I/O rate is 1 Gb/s.
Autors: Jeong, W.;Im, J.-w.;Kim, D.-H.;Nam, S.-W.;Shim, D.-K.;Choi, M.-H.;Yoon, H.-J.;Kim, D.-H.;Kim, Y.-S.;Park, H.-W.;Kwak, D.-H.;Park, S.-W.;Yoon, S.-M.;Hahn, W.-G.;Ryu, J.-H.;Shim, S.-W.;Kang, K.-T.;Ihm, J.-D.;Kim, I.-M.;Lee, D.-S.;Cho, J.-H.;Kim, M.-S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 204 - 212
Publisher: IEEE
 
» A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access
Abstract:
A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with deep-trench capacitor cell. A Gated-feedback sense amplifier enables a high voltage gain of a power-gated inverter at mid-level input voltage, while supporting 66 cells per local bit-line. A dynamic-and-gate-thin-oxide word-line driver that tracks standard logic process variation improves the eDRAM array performance with reduced area. The 1.1 Mb macro composed of 8 2 72 Kb subarrays is organized with a center interface block architecture, allowing 1 ns access latency and 1 ns bank interleaving operation using two banks, each having 2 ns random access cycle. 5 GHz operation has been demonstrated in a system prototype, which includes 6 instances of 1.1 Mb eDRAM macros, integrated with an array-built-in-self-test engine, phase-locked loop (PLL), and word-line high and word-line low voltage generators. The advantage of the 14 nm FinFET array over the 22 nm array was confirmed using direct tester control of the 1.1 Mb eDRAM macros integrated in 16 Mb inline monitor.
Autors: Fredeman, G.;Plass, D.W.;Mathews, A.;Viraraghavan, J.;Reyer, K.;Knips, T.J.;Miller, T.;Gerhard, E.L.;Kannambadi, D.;Paone, C.;Lee, D.;Rainey, D.J.;Sperling, M.;Whalen, M.;Burns, S.;Tummuru, R.R.;Ho, H.;Cestero, A.;Arnold, N.;Khan, B.A.;Kirihata, T.;I
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 230 - 239
Publisher: IEEE
 
» A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range
Abstract:
A 16 nm all-digital auto-calibrating adaptive clock distribution (ACD) enhances processor core performance and energy efficiency by mitigating the adverse effects of high-frequency supply voltage droops. The ACD integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in core paths for multiple cycles after a droop occurs to provide a sufficient response time for clock frequency adaptation. A dynamic variation monitor (DVM) detects the onset of the droop and interfaces with an adaptive control unit and clock divider to reduce in half at the TLD output to avoid path timing-margin failures. An auto-calibration circuit enables in-field, low-latency tuning of the DVM to accurately detect droops across a wide range of operating conditions. The auto-calibration circuit maximizes the -droop tolerance of the ACD while eliminating the overhead from tester calibration. From 109 die measurements across a wafer, the auto-calibrating ACD recovers a minimum of 90% of the throughput loss due to a 10% droop in a conventional design for 100% of the dies. ACD measurements demonstrate simultaneous throughput gains and energy reductions ranging from 13% and 5% at 0.9 V to 30% and 13% at 0.6 V, respectively.
Autors: Bowman, K.A.;Raina, S.;Bridges, J.T.;Yingling, D.J.;Nguyen, H.H.;Appel, B.R.;Kolla, Y.N.;Jeong, J.;Atallah, F.I.;Hansquine, D.W.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 8 - 17
Publisher: IEEE
 
» A 2- InGaP/GaAs Class-J Power Amplifier for Multi-Band LTE Achieving 35.8-dB Gain, 40.5% to 55.8% PAE and 28-dBm Linear Output Power
Abstract:
This paper describes the first linear multistage class-J power amplifier (PA) fabricated in a 2- InGaP/GaAs HBT process for multi-band long-term evolution (LTE) applications. It includes a three-stage topology composed by a pre-driver, driver, and a class-J main stage, to optimize the output power and power-added efficiency (PAE) over 1.7–2.05 GHz, thus encapsulating the LTE bands 1 to 4, 9 to 10, 33 to 37, and 39. This is achieved through a novel analog pre-distorter linearizer, which features two sub-circuits for AM–AM and AM–PM linearization. The PA prototype meets the standard’s adjacent channel leakage ratio at a maximum linear output power of 28 dBm. Tested at 2.05 GHz and for a 16-QAM scheme, the maximum error vector magnitude is 3.38% at a 28-dBm output power, which corresponds to a PAE of 40.5%–55.8% across bands. The input return loss is 15 dB and the maximum power gain is 35.8 dB, while demonstrating an unconditional stable characteristic from dc up to 5 GHz. The die area is . The performance metrics compare favorably with the state-of-the-art.
Autors: Jagadheswaran, U.R.;Ramiah, H.;Mak, P.-I.;Martins, R.P.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2016, volume: 64, issue:1, pages: 200 - 209
Publisher: IEEE
 
» A 2- InGaP/GaAs Class-J Power Amplifier for Multi-Band LTE Achieving 35.8-dB Gain, 40.5% to 55.8% PAE and 28-dBm Linear Output Power
Abstract:
This paper describes the first linear multistage class-J power amplifier (PA) fabricated in a 2- InGaP/GaAs HBT process for multi-band long-term evolution (LTE) applications. It includes a three-stage topology composed by a pre-driver, driver, and a class-J main stage, to optimize the output power and power-added efficiency (PAE) over 1.7–2.05 GHz, thus encapsulating the LTE bands 1 to 4, 9 to 10, 33 to 37, and 39. This is achieved through a novel analog pre-distorter linearizer, which features two sub-circuits for AM–AM and AM–PM linearization. The PA prototype meets the standard’s adjacent channel leakage ratio at a maximum linear output power of 28 dBm. Tested at 2.05 GHz and for a 16-QAM scheme, the maximum error vector magnitude is 3.38% at a 28-dBm output power, which corresponds to a PAE of 40.5%–55.8% across bands. The input return loss is 15 dB and the maximum power gain is 35.8 dB, while demonstrating an unconditional stable characteristic from dc up to 5 GHz. The die area is . The performance metrics compare favorably with the state-of-the-art.
Autors: Jagadheswaran, U.R.;Ramiah, H.;Mak, P.-I.;Martins, R.P.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2016, volume: 64, issue:1, pages: 200 - 209
Publisher: IEEE
 
» A 2.5 pJ/b Binary Image Sensor as a Pathfinder for Quanta Image Sensors
Abstract:
This paper presents a pathfinder binary image sensor for exploring low-power dissipation needed for future implementation of gigajot single-bit quanta image sensor (QIS) devices. Using a charge-transfer amplifier design in the readout signal chain and pseudostatic clock gating units for row and column addressing, the 1-Mpixel binary image sensor operating at 1000 frames/s dissipates only 20-mW total power consumption, including I/O pads. The gain and analog-to-digital converter stages together dissipate 2.5 pJ/b, successfully paving the way for future gigajot QIS sensor designs.
Autors: Masoodian, S.;Rao, A.;Ma, J.;Odame, K.;Fossum, E.R.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2016, volume: 63, issue:1, pages: 100 - 105
Publisher: IEEE
 
» A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses
Abstract:
A low-power object recognition (OR) system with intuitive gaze user interface (UI) is proposed for battery-powered smart glasses. For low-power gaze UI, we propose a low-power single-chip gaze estimation sensor, called gaze image sensor (GIS). In GIS, a novel column-parallel pupil edge detection circuit (PEDC) with new pupil edge detection algorithm XY pupil detection (XY-PD) is proposed which results in power reduction with larger resolution compared to previous work. Also, a logarithmic SIMD processor is proposed for robust pupil center estimation, error, with low-power floating-point implementation. For OR, low-power multicore OR processor (ORP) is implemented. In ORP, task-level pipeline with keypoint-level scoring is proposed to reduce the number of cores as well as the operating frequency of keypoint-matching processor (KMP) for low-power consumption. Also, dual-mode convolutional neural network processor (CNNP) is designed for fast tile selection without external memory accesses. In addition, a pipelined descriptor generation processor (DGP) with LUT-based nonlinear operation is newly proposed for low-power OR. Lastly, dynamic voltage and frequency scaling (DVFS) for dynamic power reduction in ORP is applied. Combining both of the GIS and ORP fabricated in 65 nm CMOS logic process, only 75 mW average power consumption is achieved with real-time OR performance, which is lower power than the previously published work.
Autors: Hong, I.;Bong, K.;Shin, D.;Park, S.;Jason Lee, K.;Kim, Y.;Yoo, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 45 - 55
Publisher: IEEE
 
» A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing
Abstract:
In the near future, the ability to solve combinatorial optimization problems will be a key technique to enable the IoT era. A new computing architecture called Ising computing and implemented using CMOS circuits is proposed. This computing maps the problems to an Ising model, a model to express the behavior of magnetic spins, and solves combinatorial optimization problems efficiently exploiting its intrinsic convergence properties. In the computing, “CMOS annealing” is used to find a better solution for the problems. A 20k-spin prototype Ising chip is fabricated in 65 nm process. The Ising chip achieves 100 MHz operation and its capability of solving combinatorial optimization problems using an Ising model is confirmed. The power efficiency of the chip can be estimated to be 1800 times higher than that of a general purpose CPU when running an approximation algorithm.
Autors: Yamaoka, M.;Yoshimura, C.;Hayashi, M.;Okuyama, T.;Aoki, H.;Mizuno, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 303 - 309
Publisher: IEEE
 
» A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170 C
Abstract:
First-ever 28 nm embedded split-gate MONOS (SG-MONOS) flash macros have been developed to increase memory capacity embedded in micro controller units and to improve performance over wide junction temperature range from to 170 as demanded strongly in automotive uses. Much attention has been paid to the degradation of the reliability characteristics along with the process shrinkage. Temperature-adjusted word-line overdrive scheme improves random read access frequency by 15% and realizes both of 6.4 GB/s read throughput by 200 MHz no-wait random access of code flash macros and more than ten times longer TDDB lifetime of WL drivers. Temperature-adaptive step pulse erase control (TASPEC) improves the TDDB lifetime of dielectric films between metal interconnect layers by three times. TASPEC is particularly useful for a data flash macro with one million rewrite cycles. Source-side injection (SSI) program with negative back-bias voltage achieves 63% reduction of program pulse time and, consequently, realizes 2.0 MB/s write throughput of code flash macros. A spread spectrum clock generation and a clock phase shift technique are introduced for charge pump clock generation in order to suppress EMI noise due to high write throughput of code flash macros, and peak power of EMI noise is reduced by 19 dB.
Autors: Taito, Y.;Kono, T.;Nakano, M.;Saito, T.;Ito, T.;Noguchi, K.;Hidaka, H.;Yamauchi, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 213 - 221
Publisher: IEEE
 
» A 3-Axis Gyroscope for Electronic Stability Control With Continuous Self-Test
Abstract:
A three-axis automotive gyroscope ASIC for electronic stability control (ESC) with noise density that is less than in a 80 Hz bandwidth and an offset drift lower than over the automotive temperature range , without any temperature compensation, is reported. A closed-loop, force-feedback architecture along with electromechanical quadrature cancellation enables the low noise and low offset-drift performance. The application of this work needs to meet the ASIL-D automotive safety standard which requires the highest level of automotive safety. Therefore, this work also presents a low-overhead approach for implementing accurate continuous safety monitoring to monitor defects, which can develop in the field, and can give rise to a false output. To achieve this, two test signals are injected into the quadrature cancellation loop to traverse the entire signal path. The system is clocked by a low-phase noise PLL, which allows the coexistence of the test signals and the measured signal in close proximity, without a noise penalty. The architecture of the drive loop is chosen to not only achieve low-phase noise but also robustness to parasitic mechanical modes of the sensor.
Autors: Balachandran, G.K.;Petkov, V.P.;Mayer, T.;Balslink, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 177 - 186
Publisher: IEEE
 
» A 3-D Finite-Element Analysis of Giant Magnetoimpedance Thin-Film Magnetic Sensors
Abstract:
Giant magnetoimpedance (GMI) thin-film magnetic sensors are modeled and evaluated using 3-D physical simulations. In the presented simulation model, the analytical multi-physics equations of MI phenomena are solved with the help of the advanced finite-element method software. In this paper, Co72Si12B6 is considered as the GMI material, forming a tri-layer of Co72Si12B6/Au/Co72Si12B6. The effects of changes in frequency and external magnetic field are discussed in detail. The geometrical dependence of thin-film GMI sensors is also studied. A batch of thin-film sensors is fabricated and tested. The measured data are in good agreement with the simulation results obtained by the proposed model.
Autors: Nazari Nejad, S.;Mansour, R.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Jan 2016, volume: 52, issue:1, pages: 1 - 8
Publisher: IEEE
 
» A 30 ppm < 80 nJ Ring-Down-Based Readout Circuit for Resonant Sensors
Abstract:
This paper presents an energy-efficient readout circuit for micro-machined resonant sensors. It operates by briefly exciting the sensor at a frequency close to its resonance frequency, after which resonance frequency and quality factor are determined from a single ring-down transient. The circuit employs an inverter-based trans-impedance amplifier to sense the ring-down current, with a programmable feedback network to enable the readout of different resonant sensors. An inverter-based comparator with dynamically-adjusted threshold levels tracks the ring-down envelope to measure quality factor, and detects zero crossings to measure resonance frequency. The excitation frequency is dynamically adjusted to accommodate large resonance frequency shifts. Experimental results obtained with a prototype fabricated in 0.35 µm standard CMOS technology and three different SiN resonators are in good agreement with conventional impedance analysis. The prototype achieves a frequency resolution better than 30 ppm while consuming less than 80 nJ/meas from a 1.8 V supply, which is 7.8x less than the state-of-the-art.
Autors: Jiang, H.;Chang, Z.Y.;Pertijs, M.A.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 187 - 195
Publisher: IEEE
 
» A 370 CMOS MedRadio Receiver Front-End With Inverter-Based Complementary Switching Mixer
Abstract:
A low-power CMOS RF receiver front-end is proposed for medical device radiocommunications service (MedRadio) applications. The proposed MedRadio receiver front-end design incorporates an AC-coupled current reuse inverter in order to reduce power consumption and increase transconductance gm. The proposed RF front-end comprises a current-reuse low noise amplifier with ac coupling inverter topology and an inverter-based single-balanced mixer with complementary switching. The proposed RF front-end is implemented in a 0.18 μm CMOS process and draws 370 μA from a 1 V supply voltage. It shows a gain of more than 29 dB, NF of less than 5.2 dB, and IIP3 of more than -19.5 dBm for all MedRadio bands.
Autors: Chihoon Choi;Kuduck Kwon;Ilku Nam;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2016, volume: 26, issue:1, pages: 73 - 75
Publisher: IEEE
 
» A 370 CMOS MedRadio Receiver Front-End With Inverter-Based Complementary Switching Mixer
Abstract:
A low-power CMOS RF receiver front-end is proposed for medical device radiocommunications service (MedRadio) applications. The proposed MedRadio receiver front-end design incorporates an AC-coupled current reuse inverter in order to reduce power consumption and increase transconductance . The proposed RF front-end comprises a current-reuse low noise amplifier with ac coupling inverter topology and an inverter-based single-balanced mixer with complementary switching. The proposed RF front-end is implemented in a 0.18 CMOS process and draws 370 from a 1 V supply voltage. It shows a gain of more than 29 dB, NF of less than 5.2 dB, and IIP3 of more than 19.5 dBm for all MedRadio bands.
Autors: Choi, C.;Kwon, K.;Nam, I.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2016, volume: 26, issue:1, pages: 73 - 75
Publisher: IEEE
 
» A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging
Abstract:
This paper presents an adaptive and resilient domino register file design featuring in-situ timing margin and error detection for the performance-critical domino read path. Voltage/frequency is adapted for slow-changing variations such as low-frequency supply noise, temperature fluctuation, and aging-induced degradation. Dynamic adaptation is combined with error detection and recovery for fast voltage droops and random data access patterns in the presence of within-die process variations. Throughput and energy efficiency gains are higher than the replica/canary based critical path approach. Timing margin is tracked by double-sampling the read output and its delayed version at the same clock edge. Timing errors are detected by double-sampling and comparing the read output within a clock window. The sensing errors in the precharge/evaluate domino read path are converted into timing errors using a conditional delayed-bitline precharge technique that does not impact the subsequent precharge operation. The proposed techniques incur 6–13% area overhead and 0.2–0.3% power overhead for a 4 Kb sub-array. The measurement results from a 22 nm tri-gate CMOS testchip demonstrate 21% throughput and 67% energy efficiency improvement with a peak energy efficiency of 409 GOPS/W.
Autors: Kulkarni, J.P.;Tokunaga, C.;Aseron, P.A.;Nguyen, T.;Augustine, C.;Tschanz, J.W.;De, V.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 117 - 129
Publisher: IEEE
 
» A 47 Million Pixel High-Performance Interline CCD Image Sensor
Abstract:
A 47-million-pixel (47Mp) interline charge-coupled-device (CCD) image sensor, the world’s highest resolution interline-transfer CCD, has been developed for industrial, machine vision, and aerial photography applications. The sensor features a 5.5- pixel, 16-output low-noise amplifier and a low-smear, fast-dump gate, horizontal lateral overflow drain, and ON-chip temperature sensor. One challenge to manufacture this large sensor is stitching the sensor with different lithography tools, while still achieving equal or better image performance than its predecessor.
Autors: Wang, S.;Carpenter, D.A.;DeJager, A.;DiBella, J.A.;Doran, J.E.;Fabinski, R.P.;Garland, A.;Johnson, J.A.;Yaniga, R.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2016, volume: 63, issue:1, pages: 174 - 181
Publisher: IEEE
 
» A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ADC With AntiPole-Splitting Opamp and Digital / Calibration
Abstract:
A dual-mode second-order reconfigurable quadrature bandpass continuous-time delta–sigma modulator is presented for a low-IF global navigation satellite system receiver to simplify the entire architecture. The proposed modulator is capable of supporting both narrowband of 5-MHz bandwidth (BW) and wideband of 20-MHz BW. An amplifier topology with active feed-forward and antipole-splitting compensation schemes is proposed. The flexible amplifiers in active-RC integrators and preamplifiers in comparators are implemented with power scaling technique to effectively adjust the power consumption for both BWs. A 1-bit digitally switched current digital-to-analog converter structure with gate-leakage compensation and low-latency dynamic element matching is proposed to cover large current variations and mitigate the gate-leakage issue. Digital / self-calibration algorithm is realized to improve the image-rejection ratio (IRR). Implemented in 65-nm CMOS, the modulator achieves 67.8-/61.4-dB dynamic range, 65.9-/53.7-dB signal-to-noise-plus-distortion ratio, and >60-dB IRR after calibration across 5-/20-MHz BW with center frequencies of 4/12 MHz, respectively. Powered by a 1.2 V supply, the modulator only consumes 4.2/8.1 mW, resulting in measured figure-of-merits of 0.26/0.51 pJ/conversion step.
Autors: Xu, Y.;Zhang, Z.;Chi, B.;Qi, N.;Cai, H.;Wang, Z.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2016, volume: 24, issue:1, pages: 243 - 255
Publisher: IEEE
 
» A 6 Bit Vector-Sum Phase Shifter With a Decoder Based Control Circuit for X-Band Phased-Arrays
Abstract:
This letter presents a 6 bit vector-sum phase shifter with a novel control circuitry for X-band phased-arrays using a 0.25 m SiGe BiCMOS technology. A balanced active balun and highly accurate I/Q network are employed to generate the reference in-phase and quadrature vectors. The desired phase is synthesized by modulating and summing the generated reference vectors using current steering VGAs that are controlled by a decoder based control circuit. The phase shifter resulted in a measured RMS phase error between 9.6–11.7 GHz and between 8.2–12 GHz, achieving 6 bit phase resolution. The chip size is 1.87 0.88 mm , excluding pads. To the best of authors' knowledge, this is the first demonstration of a digitally controlled 6 bit vector-sum phase shifter for X-band.
Autors: Cetindogan, B.;Ozeren, E.;Ustundag, B.;Kaynak, M.;Gurbuz, Y.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2016, volume: 26, issue:1, pages: 64 - 66
Publisher: IEEE
 
» A 65 nm CMOS 330 Mb/s Microwave Backscatter Link at 2.4 to 2.9 GHz With Ambient Blocker Cancellation
Abstract:
This letter discusses the implementation of microwave backscatter links in CMOS technology which are similar to existing systems at mid-UHF for RFID, but intended for use at the 2.4 GHz ISM band towards higher data-rate wireless connectivity solutions. The demonstrated microwave backscatter link uses CMOS RFIC implementation as opposed to discrete components, enabling low power consumption, while maintaining a high modulation bandwidth. Similar to RFID readers, the prototype link also cancels the carrier self-leakage and ambient reflection with internal calibration within a base-station chip. The demonstrated link is implemented and characterized in a 65 nm CMOS technology and is shown to provide 330 Mb/s of raw data-rate with BERs better than} over distances up to 2.5 m.
Autors: Tang, A.;Kim, Y.;Chang, M.-C.F.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2016, volume: 26, issue:1, pages: 61 - 63
Publisher: IEEE
 
» A 65-nm CMOS DAC Based on a Differentiating Arbitrary Waveform Generator Architecture for 5G Handset Transmitter
Abstract:
The data rate expected for the forthcoming 5G standard induces stringent constraints for handset transceivers. Wideband carrier aggregation will be handled with flexible and low-power architectures implemented in low-cost technologies. An architecture of a wideband signal generator intended to target sub-6-GHz 5G transmission requirements is presented. The architecture is based on a differential pulse code modulation coding scheme and a custom integrating DAC named the Riemann pump. It performs a 9-dB improvement of the signal-to-noise ratio per doubling of the oversampling ratio while ensuring a flat quantization noise floor over the whole multigigahertz conversion band. Its inherent ability to generate synchronous signals allows us to address carrier aggregation purposes; the generation of 10 synchronized 64-QAM modulated signals between 1.8 and 3.6 GHz is simulated. Postlayout simulations of the Riemann pump implemented in 65-nm CMOS technology fit the exposed theoretical features with a submilliwatt-level power consumption.
Autors: Veyrac, Y.;Rivet, F.;Deval, Y.;Dallet, D.;Garrec, P.;Montigny, R.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2016, volume: 63, issue:1, pages: 104 - 108
Publisher: IEEE
 
» A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a 100 kb/s Super-Regenerative Transceiver for Body Channel Communication
Abstract:
A low-energy 40/160 MHz dual-band full duplex body channel communication (BCC) transceiver and a 13.56 MHz R-C oscillator-based super-regenerative transceiver are integrated in 65 nm CMOS mixed mode process for both entertainment and healthcare applications. The on-chip R-C duplexer uses notch filters for full duplex communication with 40 Mb/s data rate and combined dual-band operation shows 80 Mb/s data rate with half duplex communication. 40 MHz sine wave and 160 MHz rectangular wave are adopted for modulation in the dual-band transmitter with 30 dB SNR improvement, and shared-loop BPSK receiver reduces the power consumption by 25%. The proposed super-regenerative transceiver including an OOK transmitter and an R-C oscillator-based receiver achieves interference rejection with 100 kb/s data rate and power consumption under the 0.8 V supply.
Autors: Cho, H.;Kim, H.;Kim, M.;Jang, J.;Lee, Y.;Lee, K.J.;Bae, J.;Yoo, H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 310 - 317
Publisher: IEEE
 
» A 90 nm CMOS, Power-Proportional Acoustic Sensing Frontend for Voice Activity Detection
Abstract:
This work presents a acoustic frontend for speech/non-speech classification in a voice activity detection (VAD) in 90 nm CMOS. Power consumption of the VAD system is minimized by architectural design around a new power-proportional sensing paradigm and the use of machine-learning-assisted moderate-precision analog analytics for classification. Power-proportional sensing allows for hierarchical and context-aware scaling of the frontend’s power consumption depending on the complexity of the ongoing information extraction, while the use of analog analytics brings increased power efficiency through switching on/off the computation of individual features depending on the features’ usefulness in a particular context. The proposed VAD system reduces the power consumption by as compared to state-of-the-art (SotA) systems and yet achieves an 89% average hit rate (HR) for a 12 dB signal-to-acoustic-noise ratio (SANR) in babble context, which is at par with software-based VAD systems.
Autors: Badami, K.M.H.;Lauwereins, S.;Meert, W.;Verhelst, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 291 - 302
Publisher: IEEE
 
» A 90 nm CMOS, Power-Proportional Acoustic Sensing Frontend for Voice Activity Detection
Abstract:
This work presents a acoustic frontend for speech/non-speech classification in a voice activity detection (VAD) in 90 nm CMOS. Power consumption of the VAD system is minimized by architectural design around a new power-proportional sensing paradigm and the use of machine-learning-assisted moderate-precision analog analytics for classification. Power-proportional sensing allows for hierarchical and context-aware scaling of the frontend’s power consumption depending on the complexity of the ongoing information extraction, while the use of analog analytics brings increased power efficiency through switching on/off the computation of individual features depending on the features’ usefulness in a particular context. The proposed VAD system reduces the power consumption by as compared to state-of-the-art (SotA) systems and yet achieves an 89% average hit rate (HR) for a 12 dB signal-to-acoustic-noise ratio (SANR) in babble context, which is at par with software-based VAD systems.
Autors: Badami, K.M.H.;Lauwereins, S.;Meert, W.;Verhelst, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 291 - 302
Publisher: IEEE
 
» A Pixel Analog-Counting Single-Photon Imager With Time-Gating and Self-Referenced Column-Parallel A/D Conversion for Fluorescence Lifetime Imaging
Abstract:
A single-photon, time-gated, pixel imager is presented for its application in fluorescence lifetime imaging microscopy. Exploiting single-photon avalanche diodes and an extremely compact pixel circuitry—only seven MOSFETs and one MOSCAP—the imager is capable of gathering information about photon position, number, and time distribution, enabling cost-effective devices for scientific imaging applications. This is achieved thanks to the photon counting and time-gating capabilities implemented in the analog domain, which in turn enable a pixel with a 21% fill-factor. A reconfigurable column circuitry supports both the analog conventional readout and a self-referenced analog-to-digital conversion, able to cancel out the pixel-to-pixel nonuniformities, and speeding up the framerate to 486 fps. The imager, featuring also a delay locked loop to stabilize the internal waveform generation for reliable timing performance, has been implemented in a standard high-voltage CMOS technology. Measurements in a fluorescent lifetime setup have been performed, comparing the results with single-point acquisitions made with commercial time-correlated equipment.
Autors: Perenzoni, M.;Massari, N.;Perenzoni, D.;Gasparini, L.;Stoppa, D.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 155 - 167
Publisher: IEEE
 
» A Pixel Analog-Counting Single-Photon Imager With Time-Gating and Self-Referenced Column-Parallel A/D Conversion for Fluorescence Lifetime Imaging
Abstract:
A single-photon, time-gated, pixel imager is presented for its application in fluorescence lifetime imaging microscopy. Exploiting single-photon avalanche diodes and an extremely compact pixel circuitry—only seven MOSFETs and one MOSCAP—the imager is capable of gathering information about photon position, number, and time distribution, enabling cost-effective devices for scientific imaging applications. This is achieved thanks to the photon counting and time-gating capabilities implemented in the analog domain, which in turn enable a pixel with a 21% fill-factor. A reconfigurable column circuitry supports both the analog conventional readout and a self-referenced analog-to-digital conversion, able to cancel out the pixel-to-pixel nonuniformities, and speeding up the framerate to 486 fps. The imager, featuring also a delay locked loop to stabilize the internal waveform generation for reliable timing performance, has been implemented in a standard high-voltage CMOS technology. Measurements in a fluorescent lifetime setup have been performed, comparing the results with single-point acquisitions made with commercial time-correlated equipment.
Autors: Perenzoni, M.;Massari, N.;Perenzoni, D.;Gasparini, L.;Stoppa, D.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 155 - 167
Publisher: IEEE
 
» A Bio-Inspired Vision Sensor With Dual Operation and Readout Modes
Abstract:
This paper presents a novel event-based vision sensor with two operation modes: 1) intensity mode and spatial contrast detection. They can be combined with two different readout approaches: 1) pulse density modulation and time-to-first spike. The sensor is conceived to be a node of an smart camera network made up of several independent an autonomous nodes that send information to a central one. The user can toggle the operation and the readout modes with two control bits. The sensor has low latency (below 1 ms under average illumination conditions), low power consumption (19 mA), and reduced data flow, when detecting spatial contrast. A new approach to compute the spatial contrast based on inter-pixel event communication less prone to mismatch effects than diffusive networks is proposed. The sensor was fabricated in the standard AMS4M2P 0.35- process. A detailed system-level description and experimental results are provided.
Autors: Lenero-Bardallo, J.A.;Hafliger, P.;Carmona-Galan, R.;Rodriguez-Vazquez, A.;
Appeared in: IEEE Sensors Journal
Publication date: Jan 2016, volume: 16, issue:2, pages: 317 - 330
Publisher: IEEE
 
» A Blind-Zone Detection Method Using a Rear-Mounted Fisheye Camera With Combination of Vehicle Detection Methods
Abstract:
This paper proposes a novel approach for detecting and tracking vehicles to the rear and in the blind zone of a vehicle, using a single rear-mounted fisheye camera and multiple detection algorithms. A maneuver that is a significant cause of accidents involves a target vehicle approaching the host vehicle from the rear and overtaking into the adjacent lane. As the overtaking vehicle moves toward the edge of the image and into the blind zone, the view of the vehicle gradually changes from a front view to a side view. Furthermore, the effects of fisheye distortion are at their most pronounced toward the extremities of the image, rendering detection of a target vehicle entering the blind zone even more difficult. The proposed system employs an AdaBoost classifier at distances of 10–40 m between the host and target vehicles. For detection at short distances where the view of a target vehicle has changed to a side view and the AdaBoost classifier is less effective, identification of vehicle wheels is proposed. Two methods of wheel detection are employed: at distances between 5 and 15 m, a novel algorithm entitled wheel arch contour detection (WACD) is presented, and for distances less than 5 m, Hough circle detection provides reliable wheel detection. A testing framework is also presented, which categorizes detection performance as a function of distance between host and target vehicles. Experimental results indicate that the proposed method results in a detection rate of greater than 93% in the critical range (blind zone) of the host.
Autors: Dooley, D.;McGinley, B.;Hughes, C.;Kilmartin, L.;Jones, E.;Glavin, M.;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Jan 2016, volume: 17, issue:1, pages: 264 - 278
Publisher: IEEE
 
» A Boosting-Based Spatial-Spectral Model for Stroke Patients’ EEG Analysis in Rehabilitation Training
Abstract:
Studies have shown that a motor imagery electro encephalogram (EEG)-based brain-computer interface (BCI) system can be used as a rehabilitation tool for stroke patients. Efficient classification of EEG from stroke patients is fundamental in the BCI-based stroke rehabilitation systems. One of the most successful algorithms for EEG classification is the common spatial patterns (CSP). However, studies have reported that the performance of CSP heavily relies on its operational frequency band and channels configuration. To the best of our knowledge, there is no agreed upon clinical conclusion about motor imagery patterns of stroke patients. In this case, it is not available to obtain the active channels and frequency bands related to brain activities of stroke patients beforehand. Hence, for using the CSP algorithm, we usually set a relatively broad frequency range and channels, or try to find subject-related frequency bands and channels. To address this problem, we propose an adaptive boosting algorithm to perform autonomous selection of key channels and frequency band. In the proposed method, the spatial-spectral configurations are divided into multiple preconditions, and a new heuristic supervisor of stochastic gradient boost strategy is utilized to train weak classifiers under these preconditions. Extensive experiment comparisons have been performed on three datasets including two benchmark datasets from the famous BCI competition III and BCI competition IV as well as one self-acquired dataset from stroke patients. Results show that our algorithm yields relatively higher classification accuracies compared with seven state-of-the-art approaches. In addition, the spatial patterns (spatial weights) and spectral patterns (bandpass filters) determined by the algorithm can also be used for further analysis of the data, e.g., for brain source localization and physiological knowledge exploration.
Autors: Liu, Y.;Zhang, H.;Chen, M.;Zhang, L.;
Appeared in: IEEE Transactions on Neural Systems and Rehabilitation Engineering
Publication date: Jan 2016, volume: 24, issue:1, pages: 169 - 179
Publisher: IEEE
 
» A Brain–Computer Interface (BCI) for the Detection of Mine-Like Objects in Sidescan Sonar Imagery
Abstract:
Detection of mine-like objects (MLOs) in sidescan sonar imagery is a problem that affects our military in terms of safety and cost. The current process involves large amounts of time for subject matter experts to analyze sonar images searching for MLOs. The automation of the detection process has been heavily researched over the years and some of these computer vision approaches have improved dramatically, providing substantial processing speed benefits. However, the human visual system has an unmatched ability to recognize objects of interest. This paper posits a brain–computer interface (BCI) approach, that combines the complementary benefits of computer vision and human vision. The first stage of the BCI, a Haar-like feature classifier, is cascaded in to the second stage, rapid serial visual presentation (RSVP) of images chips. The RSVP paradigm maximizes throughput while allowing an electroencephalography (EEG) interest classifier to determine the human subjects' recognition of objects. In an additional proposed BCI system we add a third stage that uses a trained support vector machine (SVM) based on the Haar-like features of stage one and the EEG interest scores of stage two. We characterize and show performance improvements for subsets of these BCI systems over the computer vision and human vision capabilities alone.
Autors: Barngrover, C.;Althoff, A.;DeGuzman, P.;Kastner, R.;
Appeared in: IEEE Journal of Oceanic Engineering
Publication date: Jan 2016, volume: 41, issue:1, pages: 123 - 138
Publisher: IEEE
 
» A Brief History: The Common Information Model [In My View]
Abstract:
TThe history behind the Common Information Model (CIM ) is one of an industry searching for solutions to problems that had long been recognized by vendors and electric utility customers alike. The efforts of many groups went into the solution, and often these groups completed one stage of the solution and another group picked up the work with little continuity. The first such group to take up the effort was the Energy Management System Architecture Task Force. This task force, under the IEEE Power Engineering Society???s Working Group 73-3, had as it purpose to think about and make recommendations on the energy management system (EMS ) architecture of the future.
Autors: Wollenberg, B.;Britton, J.;Dobrowolski, E.;Podmore, R.;Resek, J.;Scheidt, J.;Russell, J.;Saxton, T.;Ivanov, C.;
Appeared in: IEEE Power and Energy Magazine
Publication date: Jan 2016, volume: 14, issue:1, pages: 128 - 126
Publisher: IEEE
 
» A Broadband Dual Circularly Polarized Square Slot Antenna
Abstract:
A novel coplanar waveguide-fed broadband dual circularly polarized square slot antenna is presented. The antenna consists of a square slot, two asymmetric T-shaped feed lines in orthogonal direction protrude from signal lines, and an inverted-L grounded strip with three straight strips at the corner of the slot adjacent to both the feed lines. The circular polarization is obtained due to orthogonal feed lines. Axial ratio (AR) bandwidth is significantly enhanced because of inverted-L grounded strip with attached three straight strips. The 3-dB AR bandwidth of the antenna is about 60% in which return loss, and isolation are better than 10 and 15 dB, respectively.
Autors: Saini, R.K.;Dwari, S.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2016, volume: 64, issue:1, pages: 290 - 294
Publisher: IEEE
 
» A Cellular Network Architecture With Polynomial Weight Functions
Abstract:
Emulations of cellular nonlinear networks on digital reconfigurable hardware are renowned for an efficient computation of massive data, exceeding the accuracy and flexibility of full-custom designs. In this contribution, a digital implementation with polynomial coupling weight functions is proposed for the first time, establishing novel fields of application, e.g., in the medical signal processing and in the solution of partial differential equations. We present an architecture that is capable of processing large-scale networks with a high degree of parallelism, implemented on state-of-the-art field-programmable gate arrays.
Autors: Muller, J.;Muller, J.;Braunschweig, R.;Tetzlaff, R.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2016, volume: 24, issue:1, pages: 353 - 357
Publisher: IEEE
 
» A Charge Transfer Model for CMOS Image Sensors
Abstract:
Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect.
Autors: Han, L.;Yao, S.;Theuwissen, A.J.P.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2016, volume: 63, issue:1, pages: 32 - 41
Publisher: IEEE
 
» A Color-Tunable Polychromatic Organic-Light-Emitting-Diode Device With Low Resistive Intermediate Electrode for Roll-to-Roll Manufacturing
Abstract:
A flexible organic-light-emitting diode (OLED) with capability to show 16 million colors is fabricated on plastic barrier-film substrate, which can produce arbitrary shape with arbitrary colors, suitable for artistic expressions. Independently controlled red, green, and blue light-emitting layers are stacked vertically, so that no visible structure can be observed even with magnifiers from right-in-front measurement. In the past, large voltage drop of intermediate electrode was preventing this approach to be applied to actual electronic devices. However, according to the surface mobility control using Fick’s law analysis, low sheet resistance 7.34 /□ on plastic film is developed, so that 7.17-cm2 area emission is successfully achieved. With optical length optimization for each color stack, more than 100% color reproduction in National Television Committee Standard is achieved by stack design. The device can be used for colored illumination, as well as for organic-light-emitting display pixels for three times emission than the conventional pixel design. The device is fabricated on plastic substrate, so that the polychromatic OLED device is manufacturable with roll-to-roll production line.
Autors: Tsujimura, T.;Hakii, T.;Noda, S.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2016, volume: 63, issue:1, pages: 402 - 407
Publisher: IEEE
 
» A Column-Parallel Inverter-Based Cyclic ADC for CMOS Image Sensor With Capacitance and Clock Scaling
Abstract:
This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18- technology with 110 column-parallel ADC channels and 10.08- - column pitch. The 3.5/−2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2- sampling rate with 120- power consumption per channel.
Autors: Tang, F.;Wang, B.;Bermak, A.;Zhou, X.;Hu, S.;He, X.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2016, volume: 63, issue:1, pages: 162 - 167
Publisher: IEEE
 
» A Comment on “Fast Bloom Filters and Their Generalization”
Abstract:
A Bloom filter is a data structure that provides probabilistic membership checking. Bloom filters have many applications in computing and communications systems. The performance of a Bloom filter is measured by false positive rate, memory size requirement, and query (or memory look-up) overhead. A recent paper by Qiao et al. proposes the Fast Bloom Filter, also called Bloom-1, which requires only a single memory look-up for a membership test. Bloom-1 achieves a reduced query overhead at the expense of a slightly higher false positive rate for a given memory size. The false positive rate of Bloom-1 has been analyzed theoretically by Qiao et al. relying on a well-known, but flawed, approximation for the false positive rate for a Bloom filter. In this comment paper we show that the Qiao et al. analysis of Bloom-1 under-estimates the false positive rate for low loads. We provide a correct analysis of Bloom-1 yielding an expression for the exact false positive rate.
Autors: Reviriego, P.;Christensen, K.;Maestro, J.A.;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Jan 2016, volume: 27, issue:1, pages: 303 - 304
Publisher: IEEE
 
» A Compact Yagi-Uda Type Pattern Diversity Antenna Driven by CPW-Fed Pseudomonopole
Abstract:
This paper presents two end-fed compact Yagi-Uda-type pattern diversity antennas, which use a coplanar-waveguide (CPW)-fed printed pseudomonopole antenna (PPMA) as the driver element. The balun-less driver PPMA behaves like a folded strip dipole and adds to its compactness. A common mode/differential mode (CM/DM) decomposition of antenna current on PPMA is carried out to show that the CM current distribution is similar to the current distribution of an asymmetrically fed dipole. The designed three-element Yagi-Uda antenna operates in the 2.4-GHz band with F/B ratio of about 23 dB and gain of 7.3 dBi. The compact pattern diversity antennas are realized by using two Yagi-Uda antennas separated by a common reflector. Two diversity antennas are realized using two different arrangements of Yagi-Uda antennas. The separation between the constituent PPMAs is varied to study its effect on the isolation and element embedded efficiency. The better of the two diversity antennas has overall footprint area of and the separation between two radiating elements is only 34 mm or . The simulated and measured port isolation ( ) between two diversity branches is about 35 and 27 dB, respectively. The signal envelope correlation is 0.018 and the embedded efficiency is about 93%.
Autors: Bhattacharya, R.;Garg, R.;Bhattacharyya, T.K.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2016, volume: 64, issue:1, pages: 25 - 32
Publisher: IEEE
 
» A Comprehensive Study on Willingness Maximization for Social Activity Planning with Quality Guarantee
Abstract:
Studies show that a person is willing to join a social group activity if the activity is interesting, and if some close friends also join the activity as companions. The literature has demonstrated that the interests of a person and the social tightness among friends can be effectively derived and mined from social networking websites. However, even with the above two kinds of information widely available, social group activities still need to be coordinated manually, and the process is tedious and time-consuming for users, especially for a large social group activity, due to complications of social connectivity and the diversity of possible interests among friends. To address the above important need, this paper proposes to automatically select and recommend potential attendees of a social group activity, which could be very useful for social networking websites as a value-added service. We first formulate a new problem, named Willingness mAximization for Social grOup (WASO). This paper points out that the solution obtained by a greedy algorithm is likely to be trapped in a local optimal solution. Thus, we design a new randomized algorithm to effectively and efficiently solve the problem. Given the available computational budgets, the proposed algorithm is able to optimally allocate the resources and find a solution with an approximation ratio. We implement the proposed algorithm in Facebook, and the user study demonstrates that social groups obtained by the proposed algorithm significantly outperform the solutions manually configured by users.
Autors: Shuai, H.;Yang, D.;Yu, P.S.;Chen, M.;
Appeared in: IEEE Transactions on Knowledge and Data Engineering
Publication date: Jan 2016, volume: 28, issue:1, pages: 2 - 16
Publisher: IEEE
 
» A Configurable 12–237 kS/s 12.8 mW Sparse-Approximation Engine for Mobile Data Aggregation of Compressively Sampled Physiological Signals
Abstract:
Compressive sensing (CS) is a promising technology for realizing low-power and cost-effective wireless sensor nodes (WSNs) in pervasive health systems for 24/7 health monitoring. Due to the high computational complexity (CC) of the reconstruction algorithms, software solutions cannot fulfill the energy efficiency needs for real-time processing. In this paper, we present a 12—237 kS/s 12.8 mW sparse-approximation (SA) engine chip that enables the energy-efficient data aggregation of compressively sampled physiological signals on mobile platforms. The SA engine chip integrated in 40 nm CMOS can support the simultaneous reconstruction of over 200 channels of physiological signals while consuming of a smartphone’s power budget. Such energy-efficient reconstruction enables two-to-three times energy saving at the sensor nodes in a CS-based health monitoring system as compared to traditional Nyquist-based systems, while providing timely feedback and bringing signal intelligence closer to the user.
Autors: Ren, F.;Markovic, D.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2016, volume: 51, issue:1, pages: 68 - 78
Publisher: IEEE
 
» A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards
Abstract:
IEEE 802.11ac (WiFi) and IEEE 802.11ad (60-GHz WiGig) are emerging gigabit-per-second standards providing complementary services but different nature of signals. The 802.11ac targets high-resolution and narrow-to-medium bandwidth channels, while 802.11ad aims to provide broadband communications with simple modulation schemes. This work proposes a single-physical-layer transmitter baseband architecture for both 11ac and 11ad standards. The core of the proposed transmitter is a configurable mixed-signal digital-to-analog converter (DAC), which has an embedded semidigital filtering tailored for four WiFi modes (20, 40, 80, and 160 MHz) and the 1.76-GHz bandwidth of the 60-GHz WiGig standard. The DAC operates on the oversampled WiFi and raw WiGig data at a common 3.52-GHz clock frequency. System-level simulations of the finite impulse response DAC-based architecture show that the requirements of the standards can be met with maximum hardware sharing and reduced area penalty.
Autors: Gebreyohannes, F.T.;Frappe, A.;Kaiser, A.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2016, volume: 63, issue:1, pages: 9 - 13
Publisher: IEEE
 
» A Connectivity-Aware Approximation Algorithm for Relay Node Placement in Wireless Sensor Networks
Abstract:
In two-tiered wireless sensor networks (WSNs), relay node placement is one of the key factors impacting the network energy consumption and the system overhead. In this paper, a novel connectivity-aware approximation algorithm for relay node placement in the WSNs is proposed to offer a major step forward in saving system overhead. In particular, a unique local search approximation algorithm (LSAA) is introduced to solve the relay node single cover (RNSC) problem. In this proposed LSAA approach, the sensor nodes are allocated into groups and then a local set cover (SC) for each group is achieved by a local search algorithm. The union set of all the local SCs constitutes a SC of the RNSC problem. The approximation ratio and the time complexity of the LSAA are analyzed by rigorous proof. In addition, the LSAA approach has been extended to solve the relay node double cover problem. Then, a relay location selection algorithm (RLSA) is proposed to utilize the resulting SC from the LSAA in combining RLSA with the minimum spanning tree heuristic to build the high-tier connectivity. As the RLSA searches for a nearest location to the sink node for each relay node, the high-tier network built by the RLSA becomes denser than that by existing works. As a result, the number of added relay nodes for building the connectivity of the high-tier WSN can be significantly saved. Simulation results clearly demonstrate that the proposed LSAA outperforms the approaches reported in literature and the RLSA-based algorithm can noticeably save relay nodes newly deployed for the high-tier connectivity.
Autors: Ma, C.;Liang, W.;Zheng, M.;Sharif, H.;
Appeared in: IEEE Sensors Journal
Publication date: Jan 2016, volume: 16, issue:2, pages: 515 - 528
Publisher: IEEE
 
» A Consensus-Based Coverage Algorithm For Self-Organizing Femtocell Networks
Abstract:
In this letter, a consensus-based distributed coverage algorithm is proposed for self organization in two-tier femtocell networks. One key feature of the algorithm is that it achieves fairness among users in terms of signal quality without relying on any predefined target values. The stability of the proposed algorithm is investigated using quadratic Lyapunov functions, which also allow us to analyze its convergence rate properties. The simulation results are not only in agreement with the theoretical analysis, but also demonstrate significant improvement in terms of overall network performance.
Autors: Senel, K.;Akar, M.;
Appeared in: IEEE Communications Letters
Publication date: Jan 2016, volume: 20, issue:1, pages: 141 - 144
Publisher: IEEE
 
» A Construction of Permutation Codes From Rational Function Fields and Improvement to the Gilbert–Varshamov Bound
Abstract:
Due to recent applications to communications over powerlines, multilevel flash memories, and block ciphers, permutation codes have received a lot of attention from both coding and mathematical communities. One of the benchmarks for good permutation codes is the Gilbert–Varshamov bound. Although there have been several constructions of permutation codes, the Gilbert–Varshamov bound still remains to be the best asymptotical lower bound except for a recent improvement in the case of constant minimum distance. In this paper, we present an algebraic construction of permutation codes from rational function fields, and it turns out that, for a prime number of a symbol length, this class of permutation codes improves the Gilbert–Varshamov bound by a factor asymptotically for a minimum distance with . Furthermore, for a constant minimum distance , we improve the Gilbert–Varshamov bound by a factor as well as the recent one given by Gao et al. by a factor asymptotically for all sufficiently large .
Autors: Jin, L.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2016, volume: 62, issue:1, pages: 159 - 162
Publisher: IEEE
 
» A Continuous Time Markov Chain Based Sequential Analytical Approach for Composite Power System Reliability Assessment
Abstract:
This paper proposes a continuous time Markov chain (CTMC) based sequential analytical approach for composite generation and transmission systems reliability assessment. The basic idea is to construct a CTMC model for the composite system. Based on this model, sequential analyses are performed. Various kinds of reliability indices can be obtained, including expectation, variance, frequency, duration and probability distribution. In order to reduce the dimension of the state space, traditional CTMC modeling approach is modified by merging all high order contingencies into a single state, which can be calculated by Monte Carlo simulation (MCS). Then a state mergence technique is developed to integrate all normal states to further reduce the dimension of the CTMC model. Moreover, a time discretization method is presented for the CTMC model calculation. Case studies are performed on the RBTS and a modified IEEE 300-bus test system. The results indicate that sequential reliability assessment can be performed by the proposed approach. Comparing with the traditional sequential Monte Carlo simulation method, the proposed method is more efficient, especially in small scale or very reliable power systems.
Autors: Hou, K.;Jia, H.;Xu, X.;Liu, Z.;Jiang, Y.;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jan 2016, volume: 31, issue:1, pages: 738 - 748
Publisher: IEEE
 
» A Continuous Toroidal Winding SRM With 6- or 12-Switch DC Converter
Abstract:
A new toroidally wound switched reluctance machine (TSRM) with a single continuous multitapped winding is presented. This machine may be driven by a 6-switch asymmetric converter that supplies unipolar coil currents or by a 12-switch voltage source converter that supplies bipolar coil currents. The TSRM magnetic design and power electronic control is described, and its performance is compared with a conventional switched reluctance motor (CSRM) and with a previously reported toroidal format switched reluctance machine that utilizes six discrete winding coils in a three-phase wye connection (WSRM) driven by a voltage source inverter. A fixed 6–4 CSRM magnetic circuit design is selected for the comparative analysis of the three machine topologies by static and dynamic finite-element simulations.
Autors: Marlow, R.;Schofield, N.;Emadi, A.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Jan 2016, volume: 52, issue:1, pages: 189 - 198
Publisher: IEEE
 
» A Convex Optimization Framework for Service Rate Allocation in Finite Communications Buffers
Abstract:
We study the convexity of loss probability in communications and networking optimization problems that involve finite buffers, where the arrival process has a general distribution. Examples of such problems include scheduling, energy management and revenue, and cost optimization problems. To achieve a computationally tractable optimization framework, we propose to adjust an existing nonconvex loss probability formula for G/D/1 queues to present a convex and even more accurate loss probability model. We then use empirical data and computer simulations to examine the performance of the proposed design.
Autors: Ghamkhari, M.;Mohsenian-Rad, H.;
Appeared in: IEEE Communications Letters
Publication date: Jan 2016, volume: 20, issue:1, pages: 69 - 72
Publisher: IEEE
 
» A Cross-Coherence Method for Detecting Oscillations
Abstract:
Oscillations threaten the stability of a power system. Timely detecting oscillations can improve operators' situational awareness of system stability and enable remedial reactions. To detect oscillations during their early stages, this paper proposes a cross-coherence method using multiple-channel phasor measurement unit (PMU) data. Oscillations are related to the peaks in coherence spectra and can be detected by visual inspection and setting up a threshold. Using simulation data, it is shown that the proposed coherence method can detect oscillations even under low signal-to-noise ratios. Three algorithms for estimating coherence spectra are implemented and evaluated. Their performances are compared using Monte Carlo methods. Based on the comparison, this paper makes some recommendations for proper use of the algorithms.
Autors: Zhou, N.;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jan 2016, volume: 31, issue:1, pages: 623 - 631
Publisher: IEEE
 
» A Cross-Modality Learning Approach for Vessel Segmentation in Retinal Images
Abstract:
This paper presents a new supervised method for vessel segmentation in retinal images. This method remolds the task of segmentation as a problem of cross-modality data transformation from retinal image to vessel map. A wide and deep neural network with strong induction ability is proposed to model the transformation, and an efficient training strategy is presented. Instead of a single label of the center pixel, the network can output the label map of all pixels for a given image patch. Our approach outperforms reported state-of-the-art methods in terms of sensitivity, specificity and accuracy. The result of cross-training evaluation indicates its robustness to the training set. The approach needs no artificially designed feature and no preprocessing step, reducing the impact of subjective factors. The proposed method has the potential for application in image diagnosis of ophthalmologic diseases, and it may provide a new, general, high-performance computing framework for image segmentation.
Autors: Li, Q.;Feng, B.;Xie, L.;Liang, P.;Zhang, H.;Wang, T.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Jan 2016, volume: 35, issue:1, pages: 109 - 118
Publisher: IEEE
 
» A Current-Induced Channel Organic Thin-Film Transistor
Abstract:
An organic thin-film transistor structure is proposed in which a channel is created through formation of an electric dipole layer at the semiconductor–insulator interface. The dipole is composed of mobile carriers, electrons, and holes and results from the modification of gate insulator to allow controlled amounts of gate current to flow in the ON-state. 2-D device simulations are used to show that the proposed structure offers the potential for obtaining significantly higher channel charge and current without requiring higher voltages. It is also shown that these advantages come while maintaining OFF-current and unity gain frequency comparable with conventional transistors.
Autors: Gangwar, A.;Mazhari, B.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2016, volume: 63, issue:1, pages: 459 - 464
Publisher: IEEE
 
» A Decade of Enterprise Integration Patterns: A Conversation with the Authors
Abstract:
Department editors Olaf Zimmerman and Cesare Pautasso interview Gregor Hohpe and Bobby Woolf, authors of Enterprise Integration Patterns. They discuss the book's impact, pattern language design, message-oriented middleware, integration technology's evolution, and the authors' future plans.
Autors: Zimmermann, Olaf;Pautasso, Cesare;Hohpe, Gregor;Woolf, Bobby;
Appeared in: IEEE Software
Publication date: Jan 2016, volume: 33, issue:1, pages: 13 - 19
Publisher: IEEE
 
» A Decomposition Approach to Quality-Driven Multiuser Video Streaming in Cellular Cognitive Radio Networks
Abstract:
We tackle the challenging problem of streaming multiuser videos over the downlink of a cellular cognitive radio network (CRN), where each cognitive user (CU) can sense and access multiple channels at a time. Spectrum sensing, channel assignment, and power allocation strategies are jointly optimized to maximize the quality of service (QoS) for the CUs. We show that the formulated mixed integer nonlinear programming (MINLP) problem can be decomposed into two subproblems: 1) SP1 for the optimal spectrum sensing strategy and 2) SP2 for the optimal channel assignment and power allocation, without sacrificing optimality. We show that SP1 can be optimally solved if there is no restriction on the sensing capability for each CU, and develop a column generation (CG)-based algorithm to solve SP2 iteratively in a distributed manner. We also develop a heuristic algorithm for spectrum sensing with greatly reduced requirement on CU hardware, while still achieving a highly competitive sensing performance. We analyze the proposed algorithms with respect to complexity and time efficiency, and derive a performance upper bound. The proposed algorithms are validated with simulations.
Autors: He, Z.;Mao, S.;Kompella, S.;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Jan 2016, volume: 15, issue:1, pages: 728 - 739
Publisher: IEEE
 
» A Design Approach for Two Stages GaN MMIC PAs With High Efficiency and Excellent Linearity
Abstract:
A novel design methodology for two stages microwave monolithic integrated circuit (MMIC) power amplifier (PA) is presented. The proposed solution allows to almost null the phase distortions (AM/PM) without worsening other key features of the PA, such as amplitude distortion (AM/AM) and efficiency. The derived approach is verified presenting the design and the experimental characterization of a two stages GaN MMIC PA for Microwave Backhaul radio links. The MMIC has been developed in a commercial GaN power process, resulting in a chip area. At 7 GHz, the realized module shows 6 W of saturated output power, 17 dB of gain, 63% of power added efficiency and less than 1.5 degree of phase distortion. Moreover, when tested with modulated signals (i.e., 256 QAM modulation scheme, 7 dB of PAPR), the PA shows a spectral regrow lower than at 32 dBm of average output power without any predistortion, while the average efficiency is around 30%.
Autors: Giofre, R.;Colantonio, P.;Giannini, F.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2016, volume: 26, issue:1, pages: 46 - 48
Publisher: IEEE
 

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