Pages: 012345678910111213


Electrical and Electronics Engineering publications abstract of: 01-2015 sorted by title, page: 0
» “Split ADC” Background Linearization of VCO-Based ADCs
Abstract:
A lookup-table digital correction technique using “split ADC” calibration is used for linearization of VCO-based ADCs. Simulation results in a 45 nm CMOS process targeting 10 b and 12 b resolutions show ENOB of 9.58 b and 11.5 b, with convergence times for background calibration adaptation of 380 ms and 5.7 s, respectively. The background LMS procedure is tolerant of different input signals and provides linearity calibration over the range covered by the input signal excursion. An input dither of 3% of the ADC reference enables absolute accuracy in scale factor calibration. Design tradeoffs related to the VCO V-to- characteristic, lookup table size, and convergence properties of the LMS adaptation loop are discussed.
Autors: McNeill, J.A.;Majidi, R.;Gong, J.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2015, volume: 62, issue:1, pages: 49 - 58
Publisher: IEEE
 
» 0.5 V Supply Voltage Operation of In0.65Ga0.35As/GaAs0.4Sb0.6 Tunnel FET
Abstract:
In this letter, we demonstrate using fast current-voltage measurements, low switching slope of 64 mV/decade over a drain current range between and A/ m in staggered-gap In0.65Ga0.35As/GaAs0.4Sb0.6 tunneling field-effect transistors (TFETs) at V. This is achieved through a combination of low damage mesa sidewall etch and improvement in electrical quality of the high- gate-stack. Benchmarking our results against experimentally demonstrated TFETs, we conclude that, the staggered-gap TFETs are capable of achieving simultaneously high drive current and low switching slope.
Autors: Rajamohanan, B.;Pandey, R.;Chobpattana, V.;Vaz, C.;Gundlach, D.;Cheung, K.P.;Suehle, J.;Stemmer, S.;Datta, S.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2015, volume: 36, issue:1, pages: 20 - 22
Publisher: IEEE
 
» 10 Gb/s hetsnets with millimeter-wave communications: access and networking - challenges and protocols
Abstract:
Heterogeneous and small cell networks (Het- SNets) increase spectral efficiency and throughput via hierarchical deployments. In order to meet the increasing requirements in capacity for future 5G wireless networks, millimeter-wave (mmWave) communications with unprecedented spectral resources have been suggested for 5G HetSNets. While the mmWave physical layer is well understood, major challenges remain for its effective and efficient implementation in Het- SNets from an access and networking point of view. Toward this end, we introduce a novel but 3GPP backwards-compatible frame structure, based on time-division duplex, which facilitates both high-capacity access and backhaul links. We then discuss networking issues arising from the multihop nature of the mmWave backhauling mesh. Finally, system-level simulations evaluate the performance of HetSNets with mmWave communications and corroborate the possibility of having capacities of tens of gigabits per second in emerging 5G systems.
Autors: Zheng, K.;Zhao, L.;Mei, J.;Dohler, M.;Xiang, W.;Peng, Y.;
Appeared in: IEEE Communications Magazine
Publication date: Jan 2015, volume: 53, issue:1, pages: 222 - 231
Publisher: IEEE
 
» 10 Gbit/s delay modulation using a directly modulated DFB laser for a TWDM PON with converged services [invited]
Abstract:
A 10 Gbit/s transmission with delay modulation is demonstrated using directly modulated lasers for time- and wavelength-division-multiplexed passive optical networks (TWDM PONs), and error-free performance is achieved over 20 km standard single-mode fiber with a small dispersion penalty. Delay modulation can also mitigate the crosstalk from the TWDM PON downstream signals to the coexisting RF video signal because of its small power spectral density at low frequencies. The carrier-to-crosstalk ratio of the RF video signal is improved by about 10 dB using delay modulation, instead of nonreturn-to-zero (NRZ) modulation, for 10 Gbit/s downstream transmissions in a TWDM PON. Furthermore, using low-pass-filtered 2.5 Gbit/s NRZ modulation and bandpass-filtered 10 Gbit/s delay modulation, dual-rate transmission is demonstrated for converged services in a TWDM PON. Experimental results exhibit 37.7 and 25.7 dB power budgets, respectively, for simultaneous 2.5 and 10 Gbit/s transmissions over 20 km standard single-mode fiber.
Autors: Cheng, Ning;Zhou, Min;Effenberger, Frank J.;
Appeared in: IEEE/OSA Journal of Optical Communications and Networking
Publication date: Jan 2015, volume: 7, issue:1, pages: A87 - A96
Publisher: IEEE
 
» 100-Gb/s Hybrid Multiband CAP/QAM Signal Transmission Over a Single Wavelength
Abstract:
Hybrid multiband (HMB) CAP/QAM transmitter/receiver systems are proposed for the first time. Simulation results are provided to show the feasibility of 100 Gb Ethernet links employing a single-laser source transmitting HMB CAP-16/QAM-16, CAP-32/QAM-32, and CAP-64/QAM-64 signals. The proposed hybrid scheme has low sensitivity to directly modulated laser nonlinearities. We found that QAM receivers bring about identical jitter tolerance to ideally phase compensated CAP receivers, and QAM receivers are more practical since no phase tracking and compensation are required. Compared with the case of using a standard non phase compensated CAP receiver, the use of the modified QAM-16/32/64 receiver significantly lowers system timing jitter sensitivity in the multiband, as well as single-band case. Results also show that the use of increasing number of bands causes increased system power margin. For practical jitter conditions of ±6 ps, three HMB CAP/QAM systems with optimum band counts are identified to be capable of supporting single-laser 100 Gb/s transmission over 15-km SMF.
Autors: Wei, J.;Cheng, Q.;Cunningham, D.G.;Penty, R.V.;White, I.H.;
Appeared in: Journal of Lightwave Technology
Publication date: Jan 2015, volume: 33, issue:2, pages: 415 - 423
Publisher: IEEE
 
» 100G Superchannel Transmission Using Gb/s Subcarriers on a 25-GHz Grid
Abstract:
We demonstrate the transmission of a 100G superchannel, composed of -Gb/s duobinary subcarriers placed on a 25-GHz grid, over 580 km of SSMF with three 25-GHz reconfigurable add-drop multiplexer nodes. The direct-detect 100G superchannel has moderate optical signal to noise ratio requirements and significant tolerance to the different optical impairments. The robustness, low-power consumption, cost effectiveness, and spectral efficiency of this 100G system makes it a very strong candidate for today’s datacenter- and metro-networks.
Autors: Alfiad, M.;Tibuleac, S.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2015, volume: 27, issue:2, pages: 157 - 160
Publisher: IEEE
 
» 2-D Entropy and Short-Time Fourier Transform to Leverage GPR Data Analysis Efficiency
Abstract:
Accurate detection of singular region using ground-penetrating radar (GPR) is very useful in assessing roadway pavement, bridge deck concrete structure, and railroad ballast conditions. To locate an object within the large radargram involves extensive computational resources and time, especially when the data of interests only possess a small portion of the whole big data set. Therefore, an efficient GPR signal-processing technique is highly demanded. This paper proposes the use of 2-D entropy analysis to narrow down the data scope to the interested regions, which can considerably reduce computational cost for more sophisticated data postprocessing. Joint time-frequency analysis using short-time Fourier transform is then performed for singular region location detection and refinement. The proposed methodology is tested with different laboratory setups. The analysis results show good agreement with physical configurations.
Autors: Yu Zhang;Candra, P.;Guoan Wang;Tian Xia;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Jan 2015, volume: 64, issue:1, pages: 103 - 111
Publisher: IEEE
 
» 2014 - A Year in Review
Abstract:
Autors: Leung, K.W.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2015, volume: 63, issue:1, pages: 3 - 6
Publisher: IEEE
 
» 2014—A Year in Review
Abstract:
Autors: Leung, K.W.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2015, volume: 63, issue:1, pages: 3 - 6
Publisher: IEEE
 
» 2014: a great year for COMSOC [The President's Page]
Abstract:
A year has passed, and it is time for a first analysis of the main actions undertaken by ComSoc leadership. The five Com- Soc Vice Presidents will describe their main achievements in 2014, but before leaving the floor to them, I would like to give a concise description of the whole picture.
Autors: Benedetto, S.;
Appeared in: IEEE Communications Magazine
Publication date: Jan 2015, volume: 53, issue:1, pages: 6 - 11
Publisher: IEEE
 
» 3-D Finite Element Monte Carlo Simulations of Scaled Si SOI FinFET With Different Cross Sections
Abstract:
Nanoscaled Si SOI FinFETs with gate lengths of and nm are simulated using 3-D finite element Monte Carlo (MC) simulations with 2-D Schrödinger-based quantum corrections. These nonplanar transistors are studied for two cross sections: rectangular-like and triangular-like, and for two channel orientations: and . The -nm gate length rectangular-like FinFET is also simulated using the 3-D nonequilibrium Green’s functions (NEGF) technique and the results are compared with MC simulations. The and nm gate length rectangular-like FinFETs give larger drive currents per perimeter by about 33–37% than the triangular-like shaped but are outperformed by the triangular-like ones when normalised by channel area. The devices with a channel orientation deliver a larger drive current by about % more than their counterparts with a channel when scaled to nm and to nm gate lengths. charact- ristics obtained from the 3-D NEGF simulations show a remarkable agreement with the MC results at low drain bias. At a high drain bias, the NEGF overestimates the on-current from about V because the NEGF simulations do not include the scattering with interface roughness and ionized impurities.
Autors: Nagy, D.;Elmessary, M.A.;Aldegunde, M.;Valin, R.;Martinez, A.;Lindberg, J.;Dettmer, W.G.;Peric, D.;Garcia-Loureiro, A.J.;Kalna, K.;
Appeared in: IEEE Transactions on Nanotechnology
Publication date: Jan 2015, volume: 14, issue:1, pages: 93 - 100
Publisher: IEEE
 
» 3-D PIC Simulation of Gyrotwystron Amplifier Using MAGIC
Abstract:
In this paper, a 3-D electromagnetic (EM) and particle simulation of an -band high power gyrotwystron has been reported. The EM (cold) and the electron beam and RF wave interaction (hot) behavior have been studied using a commercially available 3-D particle-in-cell code MAGIC. The EM field analysis guarantees that the RF circuit operation is in the desired TE011 at the input cavity and TE01 circular electric waveguide mode at the output with the desired frequency of operation of 9.8 GHz. The hot simulation demonstrates the particles phase space behavior along the interaction circuit and the energy transfer phenomena. The present gyrotwystron develops an output power MW with an electronic efficiency of % and a bandwidth of 10% for ideal electron beam velocity.
Autors: Thottappan, M.;Yuvaraj, S.;Jain, P.K.;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Jan 2015, volume: 43, issue:1, pages: 398 - 404
Publisher: IEEE
 
» 3-D Registration of Biological Images and Models: Registration of microscopic images and its uses in segmentation and annotation
Abstract:
The registration, segmentation, and annotation of microscopy images and respective biological objects (e.g., cells) are distinct challenges often encountered in bioimage informatics. Here we present several studies in widely used model systems of the fruit fly, zebrafish, and C. elegans to demonstrate how registration methods have been employed to align three-dimensional (3-D) brain images at a very large scale and to solve challenging segmentation and annotation problems for 3-D cellular images. Specifically, we consider two types of registration between images and models: image-to-image registration and model-to-image registration, where a model consists of a description of the geometrical shape or the spatial layout of biological objects in the respective images.
Autors: Qu, L.;Long, F.;Peng, H.;
Appeared in: IEEE Signal Processing Magazine
Publication date: Jan 2015, volume: 32, issue:1, pages: 70 - 77
Publisher: IEEE
 
» 32 dB Gain 28 nm Bulk CMOS W-Band LNA
Abstract:
A high gain W-band low noise amplifier for radiometric applications in 28 nm bulk CMOS technology is presented. Pads, inductors, capacitors and coplanar waveguides have been custom designed. The parasitic effects of the transistor layout have been evaluated by means of electromagnetic simulations and calculations based on data reported in the design rule manual of the technology. The amplifier consists of six cascode stages with input, output and interstage conjugate matching for maximum power transfer. Measurement results show a peak gain of 32 dB and a noise figure of 5.3 dB at 91 GHz.
Autors: Pepe, D.;Zito, D.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2015, volume: 25, issue:1, pages: 55 - 57
Publisher: IEEE
 
» 37.5 km urban field trial of OFDMA-PON using colorless ONUs with dynamic bandwidth allocation and TCM [invited]
Abstract:
The orthogonal frequency division multiple access (OFDMA)-based passive optical network (PON) is a potential candidate to meet the flexibility requirements for next-generation optical access networks. We propose an OFDMA-based PON with a transmission employing intensity modulation/direct detection in the downstream and a remodulation of a remotely seeded carrier provided by the optical line terminal with coherent detection in the upstream, which enables cost-effective colorless optical network units (ONUs). Furthermore, an OFDMA-PON field trial using the proposed scheme over 37.5 km feeder fiber is demonstrated. A power budget supporting 32 ONUs with dynamic bandwidth allocation and trellis coded modulation (TCM) is reported.
Autors: Ruprecht, Christian;Chen, Yingkan;Fritzsche, Daniel;von Hoyningen-Huene, Johannes;Hanik, Norbert;Weis, Erik;Breuer, Dirk;Rosenkranz, Werner;
Appeared in: IEEE/OSA Journal of Optical Communications and Networking
Publication date: Jan 2015, volume: 7, issue:1, pages: A153 - A161
Publisher: IEEE
 
» 3D Object Retrieval With Multitopic Model Combining Relevance Feedback and LDA Model
Abstract:
View-based 3D model retrieval uses a set of views to represent each object. Discovering the complex relationship between multiple views remains challenging in 3D object retrieval. Recent progress in the latent Dirichlet allocation (LDA) model leads us to propose its use for 3D object retrieval. This LDA approach explores the hidden relationships between extracted primordial features of these views. Since LDA is limited to a fixed number of topics, we further propose a multitopic model to improve retrieval performance. We take advantage of a relevance feedback mechanism to balance the contributions of multiple topic models with specified numbers of topics. We demonstrate our improved retrieval performance over the state-of-the-art approaches.
Autors: Leng, B.;Zeng, J.;Yao, M.;Xiong, Z.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Jan 2015, volume: 24, issue:1, pages: 94 - 105
Publisher: IEEE
 
» 3D Ultrasonic Rangefinder on a Chip
Abstract:
An ultrasonic 3D rangefinder uses an array of AlN MEMS transducers and custom readout electronics to localize targets over a field of view up to 1 m away. The rms position error at 0.5 m range is 0.4 mm, 0.2 , and 0.8 for the range, x-angle, and y-angle axes, respectively. The 0.18 CMOS ASIC comprises 10 independent channels with separate high voltage transmitters, readout amplifiers, and switched-capacitor bandpass ADCs with built-in continuous time anti-alias filtering. For a 1 m maximum range, power dissipation is 400 at 30 fps. For a 0.3 m maximum range, the power dissipation scales to 5 at 10 fps.
Autors: Przybyla, R.J.;Tang, H.-Y.;Guedes, A.;Shelton, S.E.;Horsley, D.A.;Boser, B.E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 320 - 334
Publisher: IEEE
 
» 400 Gb/s real-time trial using rate-adaptive transponders for next-generation flexible-grid networks [invited]
Abstract:
We experimentally demonstrate real-time error-free transmission for longer than 65 h using a 400G rate-adaptive flexible-grid transponder in a metro regional Telecom Italia multivendor environment. Transmission over a G.652 field link and G.655 E-LEAF path with legacy dense wavelength division multiplexing equipment and co-propagating commercial coherent 40G and 100G channels was successfully achieved with a spectral efficiency of 5.33 b/s/Hz.
Autors: Pagano, Annachiara;Riccardi, Emilio;Bertolini, Marco;Farelli, Vitaliano;Van De Velde, Tony;
Appeared in: IEEE/OSA Journal of Optical Communications and Networking
Publication date: Jan 2015, volume: 7, issue:1, pages: A52 - A58
Publisher: IEEE
 
» 42-GHz/500-kW Electron Cyclotron Resonance Heating System on Tokamak SST-1
Abstract:
The 42-GHz electron cyclotron resonance heating (ECRH) system on SST-1 is used to carry out ECRH-assisted preionization, breakdown, start-up, and heating experiments at 0.75-T (second harmonic) and 1.5-T (fundamental harmonic) operation. The gyrotron delivers 500-kW power at 42-GHz frequency at −50-kV beam voltage, 20-A beam current, and 19-kV anode voltage. The gyrotron has been commissioned successfully on dummy load for full parameters (500 kW/500 ms). The transmission line consists of matching optic unit, circular corrugated waveguide, miter bend with bidirectional coupler, waveguide switches, polarizer, bellows, dc breaks, and an uptaper. Approximately 20-m-long transmission line is used to launch the power from gyrotron to tokamak, and the burn pattern at the exit of line near the tokamak ensures a good Gaussian beam. A composite launcher [consisting of four mirrors (two profiled and two plane), two gate valves, and two vacuum barrier windows] is used to connect two ECRH systems (42 and 82.6 GHz). The 82.6-GHz/200-kW ECRH system is also planned for SST-1 to carry out experiments at 3-T magnetic field. The 42-GHz ECRH system has been commissioned with tokamak SST-1, ECRH power has been launched in tokamak, and successful ECRH-assisted breakdown is achieved at second harmonic.
Autors: Shukla, B.K.;Patel, P.J.;Patel, J.;Babu, R.;Patel, H.;Dhorajia, P.;Singh, P.;Sumod, C.B.;Thakkar, D.P.;Gupta, L.N.;Barua, U.K.;Jha, R.;Bora, D.;Shmelev, M.;Irkhin, V.;Khozin, M.;Belousov, V.;Soluyanova, E.;Tai, E.;Gasainiev, Z.;Denisov, G.;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Jan 2015, volume: 43, issue:1, pages: 485 - 489
Publisher: IEEE
 
» 60-GHz Direct Modulation-Direct Detection OFDM-RoF System Using Gain-Switched Laser
Abstract:
We propose a 60-GHz orthogonal frequency-division multiplexing radio over fiber system based on direct modulation-direct detection using an externally injected gain-switched distributed feedback (DFB) laser. External injection from a master laser into the gain-switched DFB laser is used to mitigate chirp in the directly modulated DFB laser and 25-km fiber transmission is investigated. Power fading due to multipath transmission induced by fiber chromatic dispersion is theoretically analyzed and experimentally demonstrated.
Autors: Shao, T.;Martin, E.P.;Anandarajah, P.M.;Barry, L.P.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2015, volume: 27, issue:2, pages: 193 - 196
Publisher: IEEE
 
» 802.11mc: Using Packet Collision as an Opportunity in Heterogeneous MIMO-Based Wi-Fi Networks
Abstract:
Multiple-input–multiple-output (MIMO) technology boosts 802.11 Wi-Fi system capacities by using concurrent transmission of multiple streams from multiple antennas. The MIMO system in 802.11 Wi-Fi, however, typically requires request-to-send/clear-to-send (RTS/CTS)-like control message exchanges to fully realize the advantages of MIMO, although they incur nontrivial overhead. Furthermore, uncontrolled packet collisions severely limit the concurrent transmission gain of the MIMO nodes and the throughput of legacy single-input–single-output (SISO) nodes. In this paper, we propose a new distributed medium access control (MAC) protocol called 802.11 MIMO-based collision resolution (802.11mc). The 802.11mc protocol not only resolves the packet collisions but actually extracts channel information from collided frames as well to use it for concurrent MIMO transmissions. In particular, 802.11mc attaches a postamble after an RTS frame such that the channel information can be obtained, even when RTS frames collide. This information is used for interference alignment (IA) and cancelation for the interpretations of simultaneous frames. To show the feasibility of our proposal, we prototyped the scheme on the Universal Software Radio Peripheral (USRP) N210 testbed. Through both USRP experiments and NS-2-based simulations, we prove that 802.11mc improves the throughput gain of both MIMO and SISO nodes significantly.
Autors: Lee, K.;Yoo, J.;Kang, Y.;Kim, C.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Jan 2015, volume: 64, issue:1, pages: 287 - 302
Publisher: IEEE
 
» 94-GHz Large-Signal Operation of AlInN/GaN High-Electron-Mobility Transistors on Silicon With Regrown Ohmic Contacts
Abstract:
We report the first 94-GHz ( -band) large-signal performance of AlInN/GaN high-electron-mobility transistors (HEMTs) grown on high-resistivity silicon (111) substrates. A maximum output power density of 1.35 W/mm and peak power-added-efficiency of 12% are measured at 94 GHz. The devices exhibit a dc maximum current drain density of 1.6 A/mm and a peak transconductance of 650 mS/mm. In small-signal operation, cutoff frequencies GHz are achieved. The large-signal performance of our AlInN/GaN HEMTs on silicon at 94 GHz stills lags the best reported results one on SiC substrates but nevertheless confirms the tremendous interest of GaN-on-Si HEMT technology for low-cost millimeter-wave electronic applications.
Autors: Marti, D.;Tirelli, S.;Teppati, V.;Lugani, L.;Carlin, J.;Malinverni, M.;Grandjean, N.;Bolognesi, C.R.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2015, volume: 36, issue:1, pages: 17 - 19
Publisher: IEEE
 
» Lift: Multi-Label Learning with Label-Specific Features
Abstract:
Multi-label learning deals with the problem where each example is represented by a single instance (feature vector) while associated with a set of class labels. Existing approaches learn from multi-label data by manipulating with identical feature set, i.e. the very instance representation of each example is employed in the discrimination processes of all class labels. However, this popular strategy might be suboptimal as each label is supposed to possess specific characteristics of its own. In this paper, another strategy to learn from multi-label data is studied, where label-specific features are exploited to benefit the discrimination of different class labels. Accordingly, an intuitive yet effective algorithm named LIFT, i.e. multi-label learning with Label specific Features, is proposed. LIFT firstly constructs features specific to each label by conducting clustering analysis on its positive and negative instances, and then performs training and testing by querying the clustering results. Comprehensive experiments on a total of 17 benchmark data sets clearly validate the superiority of LIFT against other well-established multi-label learning algorithms as well as the effectiveness of label-specific features.
Autors: Min-Ling Zhang;Lei Wu;
Appeared in: IEEE Transactions on Pattern Analysis and Machine Intelligence
Publication date: Jan 2015, volume: 37, issue:1, pages: 107 - 120
Publisher: IEEE
 
» A 0.13 μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC
Abstract:
We introduce a 512 × 424 time-of-flight (TOF) depth image sensor designed in a TSMC 0.13 μm LP 1P5M CMOS process, suitable for use in Microsoft Kinect for XBOX ONE. The 10 μm × 10 μm pixel incorporates a TOF detector that operates using the quantum efficiency modulation (QEM) technique at high modulation frequencies of up to 130 MHz, achieves a modulation contrast of 67% at 50 MHz and a responsivity of 0.14 A/W at 860 nm. The TOF sensor includes a 2 GS/s 10 bit signal path, which is used for the high ADC bandwidth requirements of the system that requires many ADC conversions per frame. The chip also comprises a clock generation circuit featuring a programmable phase and frequency clock generator with 312.5-ps phase step resolution derived from a 1.6 GHz oscillator. An integrated shutter engine and a programmable digital micro-sequencer allows an extremely flexible multi-gain/multi-shutter and multi-frequency/multi-phase operation. All chip data is transferred using two 4-lane MIPI D-PHY interfaces with a total of 8 Gb/s input/output bandwidth. The reported experimental results demonstrate a wide depth range of operation (0.8–4.2 m), small accuracy error ( 1%), very low depth uncertainty ( 0.5% of actual distance), and very high dynamic range ( 64 dB).
Autors: Bamji, C.S.;O'Connor, P.;Elkhatib, T.;Mehta, S.;Thompson, B.;Prather, L.A.;Snow, D.;Akkaya, O.C.;Daniel, A.;Payne, A.D.;Perry, T.;Fenton, M.;Chan, V.-H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 303 - 319
Publisher: IEEE
 
» A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS
Abstract:
This paper presents a 10-bit ultra-low voltage energy-efficient SAR ADC. The proposed merge-and-split (MS) switching effectively reduces DAC switching energy by 83% compared with conventional one without the need of extra reference voltage and the issue of common-mode voltage variation. To maintain good input linearity, a new double-bootstrapped sample-and-hold (S/H) circuit is proposed under an ultra-low voltage of 0.3 V. In addition, by employing asymmetric logic in SAR control, the leakage power is reduced with the penalty of slight conversion speed degradation. The test chip fabricated in 90 nm CMOS occupied a core area of 0.03 . With a single 0.3 V supply and a Nyquist rate input, the prototype consumes 35 nW at 90 kS/s and achieves an ENOB of 8.38 bit and a SFDR of 78.2 dB, respectively. The operation frequency is scalable up to 2 MS/s and power supply range from 0.3 V to 0.5 V. The resultant FOMs are 1.17-to-1.78 fJ/conv.-step.
Autors: Lin, J.-Y.;Hsieh, C.-C.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2015, volume: 62, issue:1, pages: 70 - 79
Publisher: IEEE
 
» A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement
Abstract:
The proposed resistance-locked loop (RLL) can achieve high PSRR of 16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.
Autors: Chiu, C.-C.;Huang, P.-H.;Lin, M.;Chen, K.-H.;Lin, Y.-H.;Tsai, T.-Y.;Lee, C.C.-C.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2015, volume: 62, issue:1, pages: 59 - 69
Publisher: IEEE
 
» A 0.7-MHz–10-MHz Hybrid Baseband Chain With Improved Passband Flatness for LTE Application
Abstract:
A hybrid baseband chain for Long-Term Evolution (LTE) was implemented in a TSMC 65-nm CMOS process. It has an active area of 0.75 and a power consumption of 10.8 mW at a supply of 1.8 V. The proposed baseband chain consists of a continuous-time (CT) lowpass filter and a charge-domain discrete-time (DT) filter with a variable gain amplifier (VGA) and a DC-offset canceller (DCOC). The passband distortion of the DT filter is calibrated by varying the quality (Q)-factor of the CT filter, which is easily tuned by switched-resistors. The charge-domain DT filter is adopted for anti-aliasing filtering and efficient interferer rejection with small size and low power consumption. By combining the CT and the DT filters, the baseband chain acquires improved passband flatness with an in-band ripple of less than 1 dB from 0.7 MHz to 10 MHz. It also has a gain of 50.8 dB, input-referred noise of 22.8 , and an out-of-band IIP3 of 29 dBm.
Autors: Shin, S.-H.;Kweon, S.-J.;Jo, S.-H.;Choi, Y.-C.;Lee, S.;Yoo, H.-J.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2015, volume: 62, issue:1, pages: 244 - 253
Publisher: IEEE
 
» A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology
Abstract:
An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology using tri-gate high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed, which includes fully integrated programmable charge pumps to over- and underdrive wordlines with output voltage regulation. The die area is 77 mm and provides 64 GB/s Read and 64 GB/s Write at 1.05 V. 100 µs retention time is achieved at 95°C using the worst case memory array stress patterns. The 1 Gb eDRAM die is multi-chip-packaged with Haswell family Iris Pro™ die to achieve a high-end graphics part, which provides up to 75% performance improvement in silicon, across a wide range of workloads.
Autors: Hamzaoglu, F.;Arslan, U.;Bisnik, N.;Ghosh, S.;Lal, M.B.;Lindert, N.;Meterelliyoz, M.;Osborne, R.B.;Park, J.;Tomishima, S.;Wang, Y.;Zhang, K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 150 - 157
Publisher: IEEE
 
» A 1 TOPS/W Analog Deep Machine-Learning Engine With Floating-Gate Storage in 0.13 µm CMOS
Abstract:
An analog implementation of a deep machine-learning system for efficient feature extraction is presented in this work. It features online unsupervised trainability and non-volatile floating-gate analog storage. It utilizes a massively parallel reconfigurable current-mode analog architecture to realize efficient computation, and leverages algorithm-level feedback to provide robustness to circuit imperfections in analog signal processing. A 3-layer, 7-node analog deep machine-learning engine was fabricated in a 0.13 µm standard CMOS process, occupying 0.36 mm 2 active area. At a processing speed of 8300 input vectors per second, it consumes 11.4 µW from the 3 V supply, achieving 1×10 12 operation per second per Watt of peak energy efficiency. Measurement demonstrates real-time cluster analysis, and feature extraction for pattern recognition with 8-fold dimension reduction with an accuracy comparable to the floating-point software simulation baseline.
Autors: Lu, J.;Young, S.;Arel, I.;Holleman, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 270 - 281
Publisher: IEEE
 
» A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits
Abstract:
Motivated by a graphics memory system that achieves multiplied bandwidth by the number of memories per system, HBM DRAM adopts a brand new architecture, with many technical changes and challenges. The first main change in the architecture is the stacked memory structure with TSV array, which has independent bandwidth per slice. The second is semi-independent row, column command interface, which enhances effective performance. For supporting high bandwidth, this chip has fine pitch microbump interface. Methods for testing microbump are explained. 8 Gb stacked HBM is fabricated with chip-on-wafer process and tested with high-frequency wafer probing. Using chip-on-wafer test results, 128 GB/s at 1.2 V supply voltage is achieved.
Autors: Lee, D.U.;Kim, K.W.;Kim, K.W.;Lee, K.S.;Byeon, S.J.;Kim, J.H.;Cho, J.H.;Lee, J.;Chun, J.H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 191 - 203
Publisher: IEEE
 
» A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications
Abstract:
Real-time augmented reality (AR) is actively studied for the future user interface and experience in high-performance head-mounted display (HMD) systems. The small battery size and limited computing power of the current HMD, however, fail to implement the real-time markerless AR in the HMD. In this paper, we propose a real-time and low-power AR processor for advanced 3D-AR HMD applications. For the high throughput, the processor adopts task-level pipelined SIMD-PE clusters and a congestion-aware network-on-chip (NoC). Both of these two features exploit the high data-level parallelism (DLP) and task-level parallelism (TLP) with the pipelined multicore architecture. For the low power consumption, it employs a vocabulary forest accelerator and a mixed-mode support vector machine (SVM)-based DVFS control to reduce unnecessary external memory accesses and core activation. The proposed 4 mm 8 mm HMD AR processor is fabricated using 65 nm CMOS technology for a battery-powered HMD platform with real-time AR operation. It consumes 381 mW average power and 778 mW peak power at 250 MHz operating frequency and 1.2 V supply voltage. It achieves 1.22 TOPS peak performance and 1.57 TOPS/W energy efficiency, which are, respectively, and higher than the state of the art.
Autors: Kim, G.;Lee, K.;Kim, Y.;Park, S.;Hong, I.;Bong, K.;Yoo, H.-J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 113 - 124
Publisher: IEEE
 
» A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS
Abstract:
This paper presents a 12-bit energy-efficient successive approximation register analog-to-digital converter (ADC). By incorporating the proposed capacitor-swapping technique, which eliminates the problematic MSB mismatch transition of a binary-weighted capacitor digital-to-analog converter, the 12-bit linearity of the ADC is achieved without increasing the capacitor size for improved matching. The small capacitor size results in low power consumption. In addition, an on-the-fly programmable dynamic comparator is used for quick comparisons with low noise contributions within the limited power budget. The ADC is fabricated using a 110-nm CMOS process. It consumes 16.47 from a 0.9-V supply at a conversion-rate of 1 MS/s. The measured DNL and INL are within 0.3 LSB and 0.56 LSB, respectively. The measured SNDR and SFDR are at 67.3 dB and 87 dB, respectively. The ENOB performance is 10.92 b, which is equivalent to a figure-of-merit of 8.47 fJ/conversion-step.
Autors: Chung, Y.-H.;Wu, M.-H.;Li, H.-S.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2015, volume: 62, issue:1, pages: 10 - 18
Publisher: IEEE
 
» A 14 nm FinFET 128 Mb SRAM With V Enhancement Techniques for Low-Power Applications
Abstract:
Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 m and a 0.080 m 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 with 200 mV improvement by NBL, and 0.47 for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.
Autors: Song, T.;Rim, W.;Jung, J.;Yang, G.;Park, J.;Park, S.;Kim, Y.;Baek, K.-H.;Baek, S.;Oh, S.-K.;Jung, J.;Kim, S.;Kim, G.;Kim, J.;Lee, Y.;Sim, S.-P.;Yoon, J.S.;Choi, K.-M.;Won, H.;Park, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 158 - 169
Publisher: IEEE
 
» A 143 81 Mutual-Capacitance Touch-Sensing Analog Front-End With Parallel Drive and Differential Sensing Architecture
Abstract:
This paper presents an analog front-end (AFE) IC for mutual capacitance touch sensing with 224 sensor channels in 0.18 CMOS with 3.3 V drive voltage. A 32-in touch sensing system and a 70-in one having 37 dB SNR for 1 mm diameter stylus at 240 Hz reporting rate are realized with the AFE. The AFE adopts a parallel drive method to achieve the large format and the high SNR simultaneously. With the parallel drive method, the measured SNRs of the AFE stay almost constant at a higher level regardless of the number of sensor channels, which was impossible by conventional sequential drive methods. A novel differential sensing scheme which enhances the immunity against the noise from a display device is also realized in the AFE. While the coupled LCD is on and off, the differences between the measured SNRs are less than 2 dB.
Autors: Miyamoto, M.;Hamaguchi, M.;Nagao, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 335 - 343
Publisher: IEEE
 
» A 16 nm 128 Mb SRAM in High- Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications
Abstract:
A 128 Mb 0.07 6T high-density SRAM bitcell with write-assist circuitry has been successfully implemented using 16 nm high-k metal gate FinFET technology. This study proposes two write-assist techniques: 1) suppressed coupling signal negative bit-line (SCS-NBL) technique and 2) write recovery enhanced lower cell-VDD (WRE-LCV) technique to reduce the SRAM minimal supply voltage. The area overheads of these two techniques are 2% and 3%, respectively. The silicon data show that both of these techniques can improve overall SRAM performance by more than 300 mV at the 95th percentile.
Autors: Chen, Y.-H.;Chan, W.-M.;Wu, W.-C.;Liao, H.-J.;Pan, K.-H.;Liaw, J.-J.;Chung, T.-H.;Li, Q.;Lin, C.-Y.;Chiang, M.-C.;Wu, S.-Y.;Chang, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 170 - 177
Publisher: IEEE
 
» A 2 mW, 50 dB DR, 10 MHz BW 5 Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF
Abstract:
A 2 mW 50 dB-DR 10 MHz-BW bandpass (BP) delta-sigma modulator for a digital-IF receiver is presented. It is based on a power-efficient time-interleaved (TI) architecture, which uses a recursive loop and a feed-forward topology. To further improve its power-efficiency, the ADC employs inverter-based OTAs with the help of auxiliary inverters for extra gain. A 0.55 chip is fabricated in a 0.18 CMOS process. Measurements show that the prototype five-path TI BP modulator achieves 50 dB DR and 46 dB SNDR with 10 MHz bandwidth at 50 MHz IF while dissipating only 2 mW.
Autors: Lee, I.;Han, G.;Chae, Y.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2015, volume: 62, issue:1, pages: 80 - 89
Publisher: IEEE
 
» A 22 nm 15-Core Enterprise Xeon® Processor Family
Abstract:
This paper describes a 4.3B transistors, 15-cores, 30-threads enterprise Xeon® processor with a 37.5 MB shared L3 cache implemented in a 22 nm 9M Hi-K metal gate tri-gate process. A modular floorplan methodology enables easy chops to 10 and 6 cores. Multiple clock and voltage domains are used to reduce power consumption. The clock distribution uses a single PLL per column to save power and minimize deskew crossing points. Integrated PCIe Gen3 and Quick Path Interconnect® (QPI) ports operate at 8GT/s. The 4-channel memory interface supports both 1866 MT/s DDR3 and a new memory buffer interface running at 2667 MT/s on the same pins. The core, cache and I/O recovery techniques improve manufacturing yields and enable multiple product flavors from the same silicon die.
Autors: Rusu, S.;Muljono, H.;Ayers, D.;Tam, S.;Chen, W.;Martin, A.;Li, S.;Vora, S.;Varada, R.;Wang, E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 35 - 48
Publisher: IEEE
 
» A 220–320-GHz Vector-Sum Phase Shifter Using Single Gilbert-Cell Structure With Lossy Output Matching
Abstract:
This paper presents a wideband vector-sum phase shifter (VSPS) that operates over the entire WR-3 band (220–320 GHz). Compared to conventional VSPSs with double Gilbert cells, the proposed phase shifter employs a single Gilbert-cell structure for vector modulation. This reduces the output current combining ratio from 8:2 to 4:2, and boosts the impedance at the combining node, thus facilitating wideband output matching at upper millimeter-wave and terahertz bands. The simplified structure leads to a reduction in dc power consumption and chip area without sacrificing the 360 phase-shifting property. Lossy matching is applied at the Gilbert-cell output to further increase bandwidth and stability at the expense of relatively high loss. The phase shifter is implemented using a 250-nm InP DHBT technology that provides and exceeding 370 and 650 GHz, respectively. The measurements exhibit a wideband phase shift with continuous 360 coverage and average insertion loss ranging from 11.8 to 15.6 dB for the entire WR-3 band. The root mean square amplitude and phase error among different phase states are less than 1.2 dB and 10.2 , respectively. The input-referred 1-dB compression is measured at on average. The dc power consumption is 21.8–42.0 mW at different phase states.
Autors: Kim, Y.;Kim, S.;Lee, I.;Urteaga, M.;Jeon, S.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2015, volume: 63, issue:1, pages: 256 - 265
Publisher: IEEE
 
» A 26.8 dB Gain 19.7 dBm CMOS Power Amplifier Using 4-way Hybrid Coupling Combiner
Abstract:
This letter presents a novel compact 4-way hybrid coupling combiner applied in an mm-wave CMOS power amplifier (PA) design with wideband, large output power and high gain. Basing on the principle of both series and parallel combination concurrently working in a concentric distributed active transformer, the size of a 4-way power combiner can be dramatically reduced. Using the proposed power combiner, a four-stage common source PA is implemented in 65 nm CMOS process. In each stage, inductive source degeneration is employed to enhance transistor stability without reducing maximum stable gain. The measurement results show that the PA can offer 26.8 dB linear gain with 3 dB bandwidth of 51–67 GHz. At 1.2 V/1.4 V external supply voltage, the PA is able to deliver 17.5 dBm/19.7 dBm with 10.3%/13.4% power added efficiency (PAE). The chip size of the PA is only .
Autors: Han, J.-A.;Kong, Z.-H.;Ma, K.;Yeo, K.S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2015, volume: 25, issue:1, pages: 43 - 45
Publisher: IEEE
 
» A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications
Abstract:
This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-long- instruction-word (VLIW) machine optimized for low leakage and energy efficiency. It uses a clock distribution network, clock gating cells, and pulsed latches that are optimized for low switching energy. The processor can be powered using a low-dropout (LDO) voltage regulator or a head switch. It operates from 255 MHz at 0.60 V to 1.24 GHz at 1.05 V. When operating from the LDO, the power consumption of the core can be as low as 58 µW/MHz, which is two to three times lower than comparable cores optimized for ultra-low voltage operation.
Autors: Saint-Laurent, M.;Bassett, P.;Lin, K.;Mohammad, B.;Wang, Y.;Chen, X.;Alradaideh, M.;Wernimont, T.;Ayyar, K.;Bui, D.;Galbi, D.;Lester, A.;Pedrali-Noy, M.;Anderson, W.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 81 - 91
Publisher: IEEE
 
» A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores
Abstract:
This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The key design highlights are as follows. 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2 GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28 nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg), resulting in 24% leakage reduction of L1 cache. 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 20% dynamic power reduction, 29% leakage power reduction and 40 mV improvement of minimum operation voltage are achieved. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC voltage drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.
Autors: Igarashi, M.;Uemura, T.;Mori, R.;Kishibe, H.;Nagayama, M.;Taniguchi, M.;Wakahara, K.;Saito, T.;Fujigaya, M.;Fukuoka, K.;Nii, K.;Kataoka, T.;Hattori, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 92 - 101
Publisher: IEEE
 
» A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme
Abstract:
This paper presents a 3.5 GS/s 6-bit current-steering digital-to-analog converter (DAC) with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035 , making it suitable to embedding in VLSI systems, e.g., field-programmable gate array (FPGA). To cope with the IC process variability, a unit element approach is generally employed. The three most significant bit (MSBs) are implemented as seven unary D/A cells and the three least significant bits (LSBs) as three binary D/A cells, using appropriately reduced number of unit elements. Furthermore, all digital gates only make use of two basic unit blocks: a buffer and a multiplexer. For testing, a memory block of 5 kb is placed on-chip, which is externally loaded in a serial way but internally read in an time-interleaved way. The memory is organized around 48 clocked 104-bit shift-registers. It keeps the resulting switching disturbances signal-independent and hence avoids inducing output nonlinearity errors, even when a common power supply is shared with the DAC. This novelty allows reliable testing of the DAC core, while avoiding performance limitation risks of handling high-speed off-chip data streams. The DAC Spurious Free Dyanmic Range bandwidth is 0.8 GHz, while the bandwidth exceeds 1.3 GHz. The DAC consumes 53 mW of power and the design-for-test scheme .
Autors: Radulov, G.I.;Quinn, P.J.;van Roermund, A.H.M.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2015, volume: 23, issue:1, pages: 44 - 53
Publisher: IEEE
 
» A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator
Abstract:
Pub DtlThis paper describes the first 32 kHz low-power MEMS-based oscillator in production. The primary goal is to provide a small form-factor oscillator (1.5 × 0.8 mm 2 ) for use as a crystal replacement in space-constrained mobile devices. The oscillator generates an output frequency of 32.768 kHz and its binary divisors down to 1 Hz. The frequency stability over the industrial temperature range (–40 °C to 85 °C) is ±100 ppm as an oscillator (XO) or ±3 ppm with optional calibration as a temperature compensated oscillator (TCXO). Supply currents are 0.9 µA for the XO and 1.0 µA for the TCXO at supply voltages from 1.4 V to 4.5 V. The MEMS resonator is a capacitively-transduced tuning fork at 524 kHz. The circuitry is fabricated in 180 nm CMOS and includes low power sustaining circuit, fractional-N PLL, temperature sensor, digital control, and low swing driver.
Autors: Zaliasl, S.;Salvia, J.C.;Hill, G.C.;Chen, L.;Joo, K.;Palwai, R.;Arumugam, N.;Phadke, M.;Mukherjee, S.;Lee, H.;Grosjean, C.;Hagelin, P.M.;Pamarti, S.;Fiez, T.S.;Makinwa, K.A.A.;Partridge, A.;Menon, V.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 291 - 302
Publisher: IEEE
 
» A 3-D Stochastic FDTD Model of Electromagnetic Wave Propagation in Magnetized Ionosphere Plasma
Abstract:
A stochastic finite-difference time-domain (S-FDTD) algorithm is presented for electromagnetic-wave propagation in anisotropic magnetized plasma. This new algorithm efficiently calculates in a single simulation not only the mean electromagnetic field values, but also their variance as caused by the variability or uncertainty of the electron and ion content of the ionosphere. The structure of the ionosphere is often too variable and uncertain for electromagnetic-wave propagation problems to be solved using a deterministic formulation, particularly during space weather events. For these cases, the S-FDTD ionospheric plasma algorithm will serve as an important tool. For example, it could be used to determine the confidence level at which a communications or remote sensing or radar system will operate as expected under abnormal ionospheric conditions.
Autors: Nguyen, B.T.;Furse, C.;Simpson, J.J.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2015, volume: 63, issue:1, pages: 304 - 313
Publisher: IEEE
 
» A 3-Z-Network Boost Converter
Abstract:
A novel boost converter is proposed in this paper, which consists of three active Z-networks and is then named as a 3-Z-network boost converter. A distinct advantage of this proposal is that it can reach a high-gain voltage and well fulfill the stringent requirements from industry, particularly renewable power systems, to boost low voltage from clean sources such as photovoltaic (PV) arrays and fuel cells to high voltages for grid-connected converters. Corresponding to different states of the diodes and currents of the capacitors, six operational cases of the proposed converter, including two continuous-current modes (CCMs) and four discontinuous-current modes (DCMs), are analyzed. It is then followed with the parameters design. Finally, simulations and experiments are conducted to verify the effectiveness of the proposed converter.
Autors: Zhang, G.;Zhang, B.;Li, Z.;Qiu, D.;Yang, L.;Halang, W.A.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jan 2015, volume: 62, issue:1, pages: 278 - 288
Publisher: IEEE
 
» A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation
Abstract:
A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time interleaved latency and IO control circuits enable 1.0 V operation at target speed. To reach 3.2 Gbps with improved power efficiency over conventional mobile DRAMs, the following IO features are introduced: Low voltage swing terminated logic drivers with VOH level calibration and periodic ZQ calibration, unmatched DQ/DQS scheme and DQS oscillator for DQS tree delay tracking. This chip is fabricated in 25 nm DRAM process on 88.1 mm die area.
Autors: Oh, T.-Y.;Chung, H.;Park, J.-Y.;Lee, K.-W.;Oh, S.;Doo, S.-Y.;Kim, H.-J.;Lee, C.;Kim, H.-R.;Lee, J.-H.;Lee, J.-I.;Ha, K.-S.;Choi, Y.;Cho, Y.-C.;Bae, Y.-C.;Jang, T.;Park, C.;Park, K.;Jang, S.;Choi, J.S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 178 - 190
Publisher: IEEE
 
» A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS
Abstract:
A 16 × 16 mesh network-on-chip (NoC) is fabricated in 22 nm tri-gate CMOS for high-throughput, energy-efficient on-chip interconnect in multi-core processors and systems-on-chip. The NoC connects 256 nodes that are each in their own voltage and clock domain using 5-port routers and 112 b, 855 µm data links. Source-synchronous operation eliminates global clock distribution power and adapts to process, voltage, and temperature variations. Hybrid packet/circuit switching improves energy efficiency by removing intra-route data storage and increases throughput with parallel packet-switched channel setup and circuit-switched data transfer. The NoC achieves: i) 20.2 Tb/s total throughput at 0.9 V, 25 °C; ii) source-synchronous operation for a 2.7× increase in bisection bandwidth to 2.8 Tb/s and 93% reduction in circuit-switched latency at 407 ps/hop, compared to synchronous design; iii) hybrid packet/circuit switching for a 62% latency improvement and 55% increase in energy efficiency to 7.0 Tb/s/W, compared to packet switching; iv) a peak energy efficiency of 18.3 Tb/s/W for near-threshold operation at 430 mV, 25 °C; v) ultra-low-voltage operation down to 340 mV, 25 °C, with router power scaling to 363 µW.
Autors: Chen, G.;Anders, M.A.;Kaul, H.;Satpathy, S.K.;Mathew, S.K.;Hsu, S.K.;Agarwal, A.;Krishnamurthy, R.K.;De, V.;Borkar, S.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 59 - 67
Publisher: IEEE
 
» A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP
Abstract:
This paper presents a MUlti-SEnsor biomedical IC (MUSEIC). It features a high-performance, low-power analog front-end (AFE) and fully integrated DSP. The AFE has three biopotential readouts, one bio-impedance readout, and support for general-purpose analog sensors The biopotential readout channels can handle large differential electrode offsets ( 400 mV), achieve high input impedance ( 500 M ), low noise ( 620 nVrms in 150 Hz), and large CMRR ( 110 dB) without relying on trimming while consuming only 31 W/channel. In addition, fully integrated real-time motion artifact reduction, based on simultaneous electrode-tissue impedance measurement, with feedback to the analog domain is supported. The bio-impedance readout with pseudo-sine current generator achieves a resolution of 9.8 m / Hz while consuming just 58 W/channel. The DSP has a general purpose ARM Cortex M0 processor and an HW accelerator optimized for energy-efficient execution of various biomedical signal processing algorithms achieving 10 or more energy savings in vector multiply-accumulate executions.
Autors: Van Helleputte, N.;Konijnenburg, M.;Pettine, J.;Jee, D.-W.;Kim, H.;Morgado, A.;Van Wegberg, R.;Torfs, T.;Mohan, R.;Breeschoten, A.;de Groot, H.;Van Hoof, C.;Yazicioglu, R.F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 230 - 244
Publisher: IEEE
 
» A 4 GHz 60 dB Variable Gain Amplifier With Tunable DC Offset Cancellation in 65 nm CMOS
Abstract:
This letter presents a compact CMOS based variable gain amplifier with 60 dB gain control range and a feedback reconfigurable dc offset cancellation. The design is a four-stage fully differential cascaded amplifier implemented using a 65 nm CMOS process. The amplifier achieves a current controllable gain range from dB to dB, a voltage tunable lower cutoff frequency from dc to 200 kHz, a consistent 3 dB bandwidth better than 4 GHz, a maximum dc power consumption of 26 mW, a measured in-band group delay variation of 20 ps, and a noise figure from 10 to 27 dB. The proposed VGA design occupies a compact die area of only 75 m 80 m (excluding pads for measurement).
Autors: Kumar, T.B.;Ma, K.;Yeo, K.S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2015, volume: 25, issue:1, pages: 37 - 39
Publisher: IEEE
 
» A 4.9 mΩ-Sensitivity Mobile Electrical Impedance Tomography IC for Early Breast-Cancer Detection System
Abstract:
Pub DtlA mobile electrical impedance tomography (EIT) IC is proposed for early breast cancer detection personally at home. To assemble the entire system into a simple brassiere shape, EIT IC is integrated via a multi-layered fabric circuit board which includes 90 EIT electrodes and two reference electrodes for current stimulation and voltage sensing. The IC supports three operating modes; gain scanning, contact impedance monitoring, and EIT modes for the clear EIT image. A differential sinusoidal current stimulator (DSCS) is proposed for injection of low-distortion programmable current which has harmonics less than 59 dBc at a load impedance of 2 kΩ. To get high sensitivity, a 6-channel voltage sensing amplifier can adaptively control the gain up to a maximum of 60 dB, and has low input referred noise, 36 nV/ Hz. The 2.5 × 5 mm chip is fabricated in a 0.18 µm 1P6M CMOS process and consumes 53.4 mW on average. As a result, a sensitivity of 4.9 mΩ is achieved which enables the detection of a 5 mm cancer mass within an agar test phantom.
Autors: Hong, S.;Lee, K.;Ha, U.;Kim, H.;Lee, Y.;Kim, Y.;Yoo, H.-J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 245 - 257
Publisher: IEEE
 
» A 40 GHz 65 nm CMOS Phase-Locked Loop With Optimized Shunt-Peaked Buffer
Abstract:
A 40 GHz phase-locked loop (PLL) with an optimized shunt-peaked buffer is realized in Global Foundries 65 nm CMOS technology. The shunt-peaked buffer placed in the loop eliminates the capacitive loading of the frequency divider and enhances the drive capability. Hence it is possible to use an inductorless frequency divider to reduce potential parasitics in the layout. Thanks to the simplified topology and enhanced output swing, the proposed PLL achieves a good balance among silicon area, output range and phase noise. Measurement shows that the PLL works properly from 39.5 to 41.7 GHz with a phase noise of dBc/Hz at 1, 10, and 20 MHz offset from the carrier, respectively. It occupies a chip area of 0.4 mm including all the testing pads and consumes 87 mW from 1.5 V and 0.8 V supply voltage including the buffers.
Autors: Feng, C.;Yu, X.P.;Lim, W.M.;Yeo, K.S.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2015, volume: 25, issue:1, pages: 34 - 36
Publisher: IEEE
 
» A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking
Abstract:
Wide voltage range operation for DSPs brings more versatility to achieve high energy efficiency in mobile applications. This paper describes a 32 bits DSP fabricated in 28 nm Ultra Thin Body and Box FDSOI technology. Body Biasing Voltage (VBB) scaling from 0 V up to ±2 V decreases the core VDDMIN to 397 mV and increases clock frequency by +400%@500 mV and +114%@1.3 V. The DSP frequency measurements show 2.6 GHz@1.3 V(VDD)@2 V(VBB) and 460 MHz@397 mV(VDD)@2 V(VBB). The lowest peak energy efficiency is measured at 62 pJ/op at 0.53 V. In addition to technological gains, maximum frequency tracking design techniques are proposed for wide voltage range operation. On silicon, at 0.6 V, those techniques allow high energy gain of 40.6% w.r.t. a worst case corner approach.
Autors: Beigne, E.;Valentian, A.;Miro-Panades, I.;Wilson, R.;Flatresse, P.;Abouzeid, F.;Benoist, T.;Bernard, C.;Bernard, S.;Billoint, O.;Clerc, S.;Giraud, B.;Grover, A.;Le Coz, J.;Noel, J.-P.;Thomas, O.;Thonnart, Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 125 - 136
Publisher: IEEE
 
» A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler
Abstract:
A high-speed CMOS TSPC divide-by-16/17 dual modulus prescaler is proposed. The speed of the prescaler is improved in two aspects. First, by adopting a new pseudo divide-by-2/3 prescaler, the minimum working period is effectively reduced by half a NOR gate's delay. Second, by changing the connection of TSPC D-Flip-Flops, the minimum working period is further reduced by half an inverter's delay. Simulation results show that the maximum operating frequency of the proposed circuit is improved by compared with conventional circuit. Fabricated in 0.18- CMOS process, the proposed circuit is capable of operating up to 5.8 GHz. The power consumption is 2.6 mW at the maximum operating frequency under 1.6 V supply voltage.
Autors: Zhu, W.;Yang, H.;Gao, T.;Liu, F.;Yin, T.;Zhang, D.;Zhang, H.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2015, volume: 23, issue:1, pages: 194 - 197
Publisher: IEEE
 
» A 50–59 GHz CMOS Injection Locking Power Amplifier
Abstract:
The injection-locked power amplifier (ILPA) has demonstrated relatively high gain and high efficiency at millimeter-wave frequency. However, their application is still limited by its sensitivity to loading effect and narrow injection locking bandwidth. In this letter, a wide injection locking ILPA using buffered input and output has been proposed and implemented on 65 nm CMOS technology. The buffered input and output can improve the injection locking range and avoid load-to-tank pulling. The measured injection locking range is from 50 GHz to 59 GHz and the peak Power Added Efficiency (PAE) is 16.1% with a maximum output power of 11.39 dBm. Moreover, the die size is merely excluding pads.
Autors: Lin, J.;Boon, C.C.;Yi, X.;Feng, G.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2015, volume: 25, issue:1, pages: 52 - 54
Publisher: IEEE
 
» A 6 mW, 5,000-Word Real-Time Speech Recognizer Using WFST Models
Abstract:
We describe an IC that provides a local speech recognition capability for a variety of electronic devices. We start with a generic speech decoder architecture that is programmable with industry-standard WFST and GMM speech models. Algorithm and architectural enhancements are incorporated in order to achieve real-time performance amid system-level constraints on internal memory size and external memory bandwidth. A 2.5 × 2.5 mm test chip implementing this architecture was fabricated using a 65 nm process. The chip performs a 5,000 word recognition task in real-time with 13.0% word error rate, 6.0 mW core power consumption, and a search efficiency of approximately 16 nJ per hypothesis.
Autors: Price, M.;Glass, J.;Chandrakasan, A.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 102 - 112
Publisher: IEEE
 
» A -Si:H Thin-Film Phototransistor for a Near-Infrared Touch Sensor
Abstract:
This letter presents a highly sensitive near-infrared (IR) -Si:H phototransistor for touch sensor applications. The narrow bandgap of -Si exhibits a wideband spectrum response from IR to ultraviolet region, where the IR bandpass filter layers allow the -Si:H phototransistor to respond to the selective IR light uninterrupted by visible light. The time-resolved photoresponse and transfer – characteristics for the near-IR -Si:H phototransistor as a function of power at 785-nm illumination allow the observation of fast photoresponse ( ps), high external quantum efficiency (7.52), and high photoresponse. A prototype unit pixel structure for touch sensors composed of amorphous Si-based switching/amplification/near-IR phototransistors and a storage capacitor, is proposed and designed. The overall results suggest that the near-IR -Si:H phototransistor offers unique possibilities for user-friendly, low-cost, and large-area touch sensors, especially aimed at consumer applications and other areas of optoelectronics.
Autors: Lee, Y.;Omkaram, I.;Park, J.;Kim, H.;Kyung, K.;Park, W.;Kim, S.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2015, volume: 36, issue:1, pages: 41 - 43
Publisher: IEEE
 
» A Balanced Impulse Radiating Omnidirectional Ultrawideband Stacked Biconical Antenna
Abstract:
A compact symmetric discone antenna for the 3 GHz to 20 GHz frequency range is demonstrated. The antenna design is optimized for a good transient response with low angular dependency. This property reduces antenna distortions and simplifies antenna de-embedding. The design is based on the well-known biconical antenna, which has been radically enhanced with different geometric features. Far field modal analysis has been used for both the development and the verification of the concept that ensures a constant radiation pattern. A prototype of the balanced antenna with an improved feeding mechanism based on two separate discone antennas together with a three-port balun is also presented. Measurements in the time and in the frequency domain have been performed in order to characterize the antenna. Overall, the results show significantly improved impulse responses and input matching compared to a standard biconical antenna. Therefore, the new antenna is very well suited for advanced channel characterization, reference measurements, and system verifications.
Autors: Rostomyan, N.;Ott, A.T.;Blech, M.D.;Brem, R.;Eisner, C.J.;Eibert, T.F.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2015, volume: 63, issue:1, pages: 59 - 68
Publisher: IEEE
 
» A Beam-Steering Reconfigurable Antenna for WLAN Applications
Abstract:
A multifunctional reconfigurable antenna (MRA) capable of operating in nine modes corresponding to nine steerable beam directions in the semisphere space is presented. The MRA consists of an aperture-coupled driven patch antenna with a parasitic layer placed above it. The surface of the parasitic layer has a grid of 3 3 electrically-small square-shaped metallic pixels. The adjacent pixels are connected by PIN diode switches with ON/OFF status to change the geometry of the parasitic surface, which in turn changes the current distribution on the antenna, thus provides reconfigurability in beam steering direction. The MRA operates in the IEEE 802.11 frequency band (2.4—2.5 GHz) in each mode of operation. The antenna has been fabricated and measured. The measured and simulated impedance and radiation pattern results agree well indicating an average of dB realized gain in all modes of operation. System level experimental performance evaluations have also been performed, where an MRA equipped WLAN platform was tested and characterized in typical indoor environments. The results confirm that the MRA equipped WLAN systems could achieve an average of 6 dB Signal to Noise Ratio (SNR) gain compared to legacy omni-directional antenna equipped systems with minimal training overhead.
Autors: Li, Z.;Ahmed, E.;Eltawil, A.M.;Cetiner, B.A.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2015, volume: 63, issue:1, pages: 24 - 32
Publisher: IEEE
 
» A BL-CSC Converter-Fed BLDC Motor Drive With Power Factor Correction
Abstract:
This paper presents a power factor correction (PFC)-based bridgeless canonical switching cell (BL-CSC) converter-fed brushless dc (BLDC) motor drive. The proposed BL-CSC converter operating in a discontinuous inductor current mode is used to achieve a unity power factor at the ac mains using a single voltage sensor. The speed of the BLDC motor is controlled by varying the dc bus voltage of the voltage source inverter (VSI) feeding the BLDC motor via a PFC converter. Therefore, the BLDC motor is electronically commutated such that the VSI operates in fundamental frequency switching for reduced switching losses. Moreover, the bridgeless configuration of the CSC converter offers low conduction losses due to partial elimination of diode bridge rectifier at the front end. The proposed configuration shows a considerable increase in efficiency as compared with the conventional scheme. The performance of the proposed drive is validated through experimental results obtained on a developed prototype. Improved power quality is achieved at the ac mains for a wide range of control speeds and supply voltages. The obtained power quality indices are within the acceptable limits of IEC 61000-3-2.
Autors: Singh, B.;Bist, V.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jan 2015, volume: 62, issue:1, pages: 172 - 183
Publisher: IEEE
 
» A Blind Preprocessor for Modulation Classification Applications in Frequency-Selective Non-Gaussian Channels
Abstract:
This paper presents a new preprocessing stage that allows for the reliable classification of digital amplitude-phase modulated signals in a practical scenario where: 1) the classifier has no knowledge of the timing (symbol transition epochs) of the received signal; 2) the noise added in the channel is non-Gaussian; and 3) the fading experienced by the signal is frequency selective. The proposed preprocessor, which is based on the Gibbs sampling algorithm, is used to acquire timing information and to estimate the channel state and noise distribution parameters blindly, i.e., without knowledge of the received symbol sequence and the modulation scheme used. With the obtained estimates, in a second processing stage, the signal is then classified by using an appropriate (likelihood- or feature-based) classification algorithm. To quantify the performance of the proposed preprocessor, the probability of correct classification obtained by using the preprocessor with different classification algorithms is presented. It is shown that, by using the proposed preprocessor, modulation classification algorithms can perform well compared with clairvoyant classifiers assumed to be symbol synchronous with the received signal and to have perfect knowledge of the channel state and noise distribution.
Autors: Amuru, S.;da Silva, C.R.C.M.;
Appeared in: IEEE Transactions on Communications
Publication date: Jan 2015, volume: 63, issue:1, pages: 156 - 169
Publisher: IEEE
 
» A Bottom Fed Deployable Conical Log Spiral Antenna Design for CubeSat
Abstract:
A conical log spiral antenna is presented with a new feeding scheme. This antenna is proposed for deployment on a CubeSat platform where the new feeding technique allows for easier antenna deployment. The antenna is composed of two arms that are wrapped around each other in a log-periodic manner. It is designed on top of a ground plane allowing its bottom feeding property. The feeding network is composed of quarter-wavelengths transmission lines connected to a planar balun. The feeding network along with the balun provides the antenna with the appropriate impedance matching and phase shift between the two arms. The antenna is fabricated and tested. The measurement and simulation results show good agreement.
Autors: Ernest, A.J.;Tawk, Y.;Costantine, J.;Christodoulou, C.G.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2015, volume: 63, issue:1, pages: 41 - 47
Publisher: IEEE
 
» A Branch and Bound Algorithm for Cyclic Scheduling of Timed Petri Nets
Abstract:
A timed Petri net (TPN) has been widely used for modeling, scheduling, and analyzing discrete event dynamic systems. This study examines cyclic scheduling problems of a TPN to minimize the cycle time especially for automated manufacturing systems. Appropriate token routing at each conflict place can make a TPN repeat an identical firing sequence. We propose a systematic procedure to transform a TPN with such cyclic token routing into an equivalent timed event graph (TEG) for which the cycle time and firing schedules can be evaluated by a linear programming (LP). Based on the transformation procedure, we develop an efficient branch and bound algorithm to solve the scheduling problem. A partial solution is defined as a partial token route that has only a subset of token routes for determining the complete schedule. The lower bound of a partial solution is determined by the cycle time of a TEG that has the partial token route. The cycle time of a TEG with an additional token route for a new partial solution is computed by a dual-simplex algorithm which avoids solving the LP completely again. A dynamic branching strategy that prevents unnecessary branching for the scheduling decision is also proposed. We demonstrate the computational efficiency through intensive experiments of cluster tools and robotic flow shops.
Autors: Jung, C.;Kim, H.-J.;Lee, T.-E.;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Jan 2015, volume: 12, issue:1, pages: 309 - 323
Publisher: IEEE
 
» A Broadband Artificial Material for Gain Enhancement of Antipodal Tapered Slot Antenna
Abstract:
A broadband artificial material composed of non-resonant parallel-line unit cells is proposed to enhance the gain of an antipodal tapered slot antenna (ATSA). The artificial material, whose effective refractive index is lower than that of the substrate on which the antenna is printed, will act as a regular lens in beam focusing. In order to investigate the gain enhancement effect of the material, a combination of the proposed material with an ATSA is made by locating the material in front of the antenna. Simulation results indicate that the gain of the antenna has been enhanced significantly and increasing the dimension of the material in the radiation direction leads to a higher gain without destroying its broadband characteristic. The original and the artificial material loaded ATSAs are designed and fabricated with the measurement results showing that the gain of the original ATSA has been increased by 1.3–3.6 dB in the measurement bandwidth of 6–19 GHz.
Autors: Chen, L.;Lei, Z.;Yang, R.;Fan, J.;Shi, X.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2015, volume: 63, issue:1, pages: 395 - 400
Publisher: IEEE
 
» A buffer-aware HTTP live streaming approach for SDN-enabled 5G wireless networks
Abstract:
With increasing interest in the concept of 5G wireless networks and the popularization of mobile devices, users gradually watch videos through mobile devices in streaming mode rather than off-line mode. However, the latency and lags of mobile networks will reduce the quality of service. In HTTP live streaming services, when there are multiple sources for the same content stored in the streaming servers, the suited quality content is able to be selected for playing according to the networking bandwidth conditions between servers and user equipment, and the users can obtain appropriate streaming quality automatically. However, the selection policy is difficult to be approved between 5G wireless communication networks and SDNs. In this study a buffer-aware HTTP live streaming approach is proposed, which evaluates the weights of media segments to decide the transmitting priorities based on the current playing time and adjust the appropriate transmission path through the decision making network controller according to the utilization and stability of the routers and switches in SDN. Finally, the experimental results proved that the approach is able to correct the overall streaming source sequence with the buffer status to effectively upgrade overall streaming service quality, as well as maintain a certain level of streaming quality for SDN-enable 5G wireless networks.
Autors: Chin-Feng Lai;Ren-Hung Hwang;Han-Chieh Chao;Hassan, M.M.;Alamri, A.;
Appeared in: IEEE Network
Publication date: Jan 2015, volume: 29, issue:1, pages: 49 - 55
Publisher: IEEE
 
» A Building Block Approach for Designing Multilevel Coding Schemes
Abstract:
A novel building block (BB) design approach is presented for systematically constructing multilevel codes (MLCs) under the balanced distances rule (BDR). In contrast to the traditional method of starting from an overall signal constellation and then using a mapping policy, the BB approach starts by designing a BB constellation for the first level of the MLC and then uses two copies of this BB to construct a second level constellation. This process is continued to the highest level by constructing the next level constellation using multiple copies of the current level constellation as a BB. Compared to the traditional method of construction of MLCs according to the BDR, the BB approach provides additional flexibility in selecting component codes and is able to exactly balance the distances of all levels. Compared with MLCs constructed using the traditional BDR approach, MLCs constructed using the BB approach have the same decoding complexity and perform better in the error floor region, which is typically the operating region for MLCs constructed with convolutional component codes.
Autors: Naim, M.A.;Fonseka, J.P.;Dowling, E.M.;
Appeared in: IEEE Communications Letters
Publication date: Jan 2015, volume: 19, issue:1, pages: 2 - 5
Publisher: IEEE
 
» A Calculation Method of Photovoltaic Array's Operating Point for MPPT Evaluation Based on One-Dimensional Newton–Raphson Method
Abstract:
Comparison and evaluation of maximum power point tracking (MPPT) algorithms for photovoltaic (PV) arrays are often carried out by computer simulation because any irradiation and temperature condition can be set up and repeated. This paper proposes a new simple calculation method for computer simulation to evaluate any MPPT algorithm. The proposed method rapidly calculates the operating point of the PV array. The 1-D Newton–Raphson method is repeated, instead of expanding this method, in multidimensional cases. The proposed method is compared with the conventional combination methods. We confirm the adequate accuracy and short calculation time of the proposed method.
Autors: Uoya, M.;Koizumi, H.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Jan 2015, volume: 51, issue:1, pages: 567 - 575
Publisher: IEEE
 
» A Capacitive Rotary Encoder Based on Quadrature Modulation and Demodulation
Abstract:
This paper presents a capacitive rotary encoder for both angular position and angular speed measurements. The encoder is mainly composed of three parts: the transmitting segments; a pair of reflecting electrodes; and a pair of receiving electrodes. The transmitting segments together with four mutual quadrature carrier voltages provide a modulated electric field. The reflecting electrodes, which are patterned sinusoidally can encode the angular position to a phase/frequency modulated signal based on quadrature modulation. The modulated signal is then digitally decoded to the angular position in a field programmable gate array processor based on the quadrature demodulation and the coordinate rotational digital computer algorithm. Through a universal serial bus, the digital angular position is transmitted to a computer for further analysis in National Instruments' LabVIEW software. A prototype of the capacitive encoder shows that its precision is better than 0.006° and the resolution is 0.002°. The dynamic nonlinearity is evaluated at ±0.4° when the rotor is rotating at 1000 r/min.
Autors: Dezhi Zheng;Shaobo Zhang;Shuai Wang;Chun Hu;Xiaomeng Zhao;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Jan 2015, volume: 64, issue:1, pages: 143 - 153
Publisher: IEEE
 
» A Centralized Reactive Power Compensation System for LV Distribution Networks
Abstract:
A centralized reactive power compensation system is proposed for low voltage (LV) distribution networks. It can be connected with any bus which needs reactive power. The current industry practice is to locally install reactive power compensation system to maintain the local bus voltage and power factor. By centralizing capacitor banks together, it can help to maintain bus voltages and power factors as well as reduce the power cable losses. Besides, the centralized reactive power system can be easily expanded to meet any future load increase. A reasonably sized centralized reactive power compensation system will be capable of meeting the requirements of the network and the optimization algorithm proposed in this paper can help to find this optimal size by minimizing the expected total cost ( ). Different load situations and their respective probabilities are also considered in the proposed algorithm. The concept of the centralized reactive power compensation system is applied to a local shipyard power system to verify its effectiveness. The results show that an optimally sized centralized reactive power system exists and is capable of maintaining bus voltages as well as reducing the power losses in the distribution network. A significant power loss reduction can be obtained at the optimal capacity of the centralized reactive power compensation system in the case study.
Autors: Chen, S.X.;Foo.Eddy, Y.S.;Gooi, H.B.;Wang, M.Q.;Lu, S.F.;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jan 2015, volume: 30, issue:1, pages: 274 - 284
Publisher: IEEE
 
» A Characterization of Two-Weight Projective Cyclic Codes
Abstract:
We give necessary conditions for a two-weight projective cyclic code to be the direct sum of two one-weight irreducible cyclic subcodes of the same dimension, following the work of Wolfmann and Vega. This confirms Vega’s conjecture that all the two-weight cyclic codes of this type are the known ones in the projective case.
Autors: Feng, T.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2015, volume: 61, issue:1, pages: 66 - 71
Publisher: IEEE
 
» A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses
Abstract:
Memristor-based circuit architecture for multilayer neural networks is proposed. It is a first of its kind demonstrating successful circuit-based learning for multilayer neural network built with memristors. Though back-propagation algorithm is a powerful learning scheme for multilayer neural networks, its hardware implementation is very difficult due to complexities of the neural synapses and the operations involved in the learning algorithm. In this paper, the circuit of a multilayer neural network is designed with memristor bridge synapses and the learning is realized with a simple learning algorithm called Random Weight Change (RWC). Though RWC algorithm requires more iterations than back-propagation algorithm, we show that a circuit-based learning using RWC is two orders faster than its software counterpart. The method to build a multilayer neural network using memristor bridge synapses and a circuit-based learning architecture of RWC algorithm is proposed. Comparison between software-based and memristor circuit-based learning are presented via simulations.
Autors: Adhikari, S.P.;Kim, H.;Budhathoki, R.K.;Yang, C.;Chua, L.O.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2015, volume: 62, issue:1, pages: 215 - 223
Publisher: IEEE
 
» A Clinically Applicable Stochastic Approach for Noninvasive Estimation of Aortic Stiffness Using Computed Tomography Data
Abstract:
The degeneration of the vascular wall tissue induces a change of the arterial stiffness, i.e., the capability of the vessel to distend under the pulsatile hemodynamic load. In the literature, the aortic stiffness is usually computed following a simple deterministic approach, in which only the maximum and the minimum values of arterial diameter and blood pressure over the cardiac cycle are considered. In this paper, we propose a stochastic approach to assess the stiffness, and its spatial variation, of a given aortic region exploiting patient-specific geometrical data derived from computed tomography angiography (CTA). In particular, the arterial stiffness is computed linking the aortic kinematic information derived from CTA with pressure waveforms, generated using a lumped parameter model of the arterial circulation. The proposed method is able to include the uncertainty of the input variables as well as to use the entire diameter and blood pressure waveforms over the cardiac cycle rather than only their maximum and minimum values. Although the efficiency and accuracy of the proposed method are tested on a single patient-specific case, the proposed approach is powerful and already possesses the ability to evaluate regional changes of stiffness in human aorta using noninvasive data. The final objective of our paper is to support the adoption of techniques such as CTA as a standard tool for diagnosis and treatment planning of aortic diseases.
Autors: Auricchio, F.;Conti, M.;Ferrara, A.;Lanzarone, E.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Jan 2015, volume: 62, issue:1, pages: 176 - 187
Publisher: IEEE
 
» A CML Ring Oscillator-Based Supply-Insensitive PLL With On-Chip Calibrations
Abstract:
A 1.5–2.5 GHz current-mode logic (CML) ring oscillator-based supply-insensitive phase-locked loop (PLL) employing two different topologies of CML ring oscillators that compensate for the supply variations is presented. In addition, an on-chip calibration scheme is designed to ensure the voltage-controlled oscillators (VCOs) to operate at the optimum operating point where the PLL achieves nearly the best power supply rejection. This work shows more than 96% reduction in supply sensitivity of VCOs compared with the conventional topology. In addition, the sinusoidal jitter is improved by at least 70% closed-loop with the on-chip calibrations. The chip was fabricated in SMIC CMOS process.
Autors: Gui, X.;Gao, P.;Chen, Z.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2015, volume: 63, issue:1, pages: 233 - 243
Publisher: IEEE
 
» A Compact Bi-Direction Scannable a-Si:H TFT Gate Driver
Abstract:
An integrated a-Si:H thin-film transistors (TFTs) gate driver on array with both forward and backward scanning function is proposed. The single stage of the gate driver only consists of seven TFTs. The bi-direction scannable function is just realized by controlling the turning-on sequence of two input TFTs. Both scanning modes use the same driving TFT for pulling-up and pulling-down the output voltage and the same circuit unit for holding the low level. The proposed gate driver is fabricated in the 4.5 G TFT production line, and the measurements with the fabricated drivers verify the feasibility of the proposed driver.
Autors: Liao, C.;Hu, Z.;Dai, D.;Chung, S.;Jen, T.S.;Zhang, S.;
Appeared in: Journal of Display Technology
Publication date: Jan 2015, volume: 11, issue:1, pages: 3 - 5
Publisher: IEEE
 
» A Compact Dual-Channel Transceiver for Long-Range Passive Embedded Monitoring
Abstract:
A compact 3-D dual-channel transceiver for passive wireless sensor node design is described herein. The transceiver contains two harmonic repeaters, one to be connected to a sensor and one to provide a reference signal for remote channel calibration and node identification (ID). Each repeater consists of a diode-based frequency doubler and conjugate-matched receive and transmit meandered monopole antennas. The sensing repeater operates by receiving a 2.4-GHz signal and reradiating a modulated 4.8-GHz return signal. The reference and sensing repeaters are optimized for RF input power level ranges from to with zero dc power. The diagonal of the transceiver measures 0.25 at the fundamental frequency of 2.4 GHz and its measured conversion gain (CG) is with a 2% 3-dB CG bandwidth at input power. With this performance, the communication range using an interrogator with a 2-W effective isotropic radiated power is in a free-space environment. To the best of the authors' knowledge, the presented transceiver is the first completely passive design with built-in passive remote channel calibration and ID capability. The performance and size of the proposed design compare well with previously published passive single-channel harmonic repeaters.
Autors: Nassar, I.T.;Weller, T.M.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2015, volume: 63, issue:1, pages: 287 - 294
Publisher: IEEE
 
» A Comparison Between the NIST PJVS-Based Power Standard and the NRC Current- Comparator-Based Power Standard
Abstract:
This paper presents the results of a comparison of active/reactive power meter calibrations between the National Institute of Standards and Technology and National Research Council. The comparison was implemented using a transfer standard consisting of a highly stable commercial sampling-type power/energy meter. Active and reactive power measurements were made at 120 V, 5 A, 50 Hz, and 60 Hz. For active power, the measurements were made at applied current phase angles of 0°, +60°, and -60°. For reactive power, the measurements were made at applied current phase angles of +60°, +90°, -60°, and -90° . The results of the comparison indicate agreement to within the stated uncertainties of the participants.
Autors: Waltrip, B.C.;Nelson, T.L.;So, E.;Angelo, D.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Jan 2015, volume: 64, issue:1, pages: 14 - 18
Publisher: IEEE
 
» A Complete Blood Typing Device for Automatic Agglutination Detection Based on Absorption Spectrophotometry
Abstract:
Blood type determination is an important clinical test that should be performed before any blood transfusion. However, in emergency situations, due to the patient's condition, there may not be enough time to determine the patient's blood type. In these cases, the O negative blood type is administered, because it causes less incompatibility risk to the patient. This paper presents a low-cost and portable device for ABO, Rh phenotype, reverse, and Cross-matching human blood typing, based on a spectrophotometric approach of the agglutination detection, with a fast response time (results in <;5 min). These features allow the device operation in mobile emergency units, outside conventional clinical laboratories, and close to the patient. It avoids the risk of incompatibility between the donor's and receptor's blood, improving the quality in healthcare services.
Autors: Fernandes, J.;Pimenta, S.;Soares, F.O.;Minas, G.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Jan 2015, volume: 64, issue:1, pages: 112 - 119
Publisher: IEEE
 
» A Complete Characterization of the Maximal Contractively Invariant Ellipsoids of Linear Systems Under Saturated Linear Feedback
Abstract:
As level sets of quadratic Lyapunov functions, ellipsoids have been extensively used as estimates of the domain of attraction of a linear system under saturated linear feedback. For a linear system with a single input subject to actuator saturation, based on a convex hull representation of saturation functions, a necessary and sufficient condition for an ellipsoid to be contractively invariant was previously established, which, through the solution of an LMI problem, leads to the maximal ellipsoidal invariant set. In this technical note, for a linear system with multiple inputs subject to actuator saturation, we develop a complete characterization of the maximal ellipsoidal invariant set by algebraic computation. Simulation results demonstrate the effectiveness of our results.
Autors: Li, Y.;Lin, Z.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Jan 2015, volume: 60, issue:1, pages: 179 - 185
Publisher: IEEE
 
» A Computational Dynamic Trust Model for User Authorization
Abstract:
Development of authorization mechanisms for secure information access by a large community of users in an open environment is an important problem in the ever-growing Internet world. In this paper we propose a computational dynamic trust model for user authorization, rooted in findings from social science. Unlike most existing computational trust models, this model distinguishes trusting belief in integrity from that in competence in different contexts and accounts for subjectivity in the evaluation of a particular trustee by different trusters. Simulation studies were conducted to compare the performance of the proposed integrity belief model with other trust models from the literature for different user behavior patterns. Experiments show that the proposed model achieves higher performance than other models especially in predicting the behavior of unstable users.
Autors: Zhong, Y.;Bhargava, B.;Lu, Y.;Angin, P.;
Appeared in: IEEE Transactions on Dependable and Secure Computing
Publication date: Jan 2015, volume: 12, issue:1, pages: 1 - 15
Publisher: IEEE
 
» A Computational Model of the Short-Cut Rule for 2D Shape Decomposition
Abstract:
We propose a new 2D shape decomposition method based on the short-cut rule. The short-cut rule originates from cognition research, and states that the human visual system prefers to partition an object into parts using the shortest possible cuts. We propose and implement a computational model for the short-cut rule and apply it to the problem of shape decomposition. The model we proposed generates a set of cut hypotheses passing through the points on the silhouette, which represent the negative minima of curvature. We then show that most part-cut hypotheses can be eliminated by analysis of local properties of each. Finally, the remaining hypotheses are evaluated in ascending length order, which guarantees that of any pair of conflicting cuts only the shortest will be accepted. We demonstrate that, compared with state-of-the-art shape decomposition methods, the proposed approach achieves decomposition results, which better correspond to human intuition as revealed in psychological experiments.
Autors: Luo, L.;Shen, C.;Liu, X.;Zhang, C.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Jan 2015, volume: 24, issue:1, pages: 273 - 283
Publisher: IEEE
 
» A Covariance Approximation Method for Near-Field Coherent Sources Localization Using Uniform Linear Array
Abstract:
The covariance approximation (CA) multiple signal classification (MUSIC) is a novel near-field direction-of-arrival (DoA) estimation method for uniform linear array. In this paper, we show that the CA–MUSIC suffers from significant performance degeneration caused by coherent sources. The CA–MUSIC with coherent sources generates the image sources (IS), which cannot be distinguished from the real sources. To solve this problem, we propose a CA-based near-field coherent sources localization algorithm, which is robust to the IS effect. The proposed CA algorithm avoids errors caused by coherence between sources using searching radius restriction and zero-forcing MUSIC. Simulation results shows that the proposed CA algorithm offers superior root mean square error (RMSE) performances for near-field coherent sources.
Autors: Noh, H.;Lee, C.;
Appeared in: IEEE Journal of Oceanic Engineering
Publication date: Jan 2015, volume: 40, issue:1, pages: 187 - 195
Publisher: IEEE
 
» A Data-Driven Iterative Decoupling Feedforward Control Strategy With Application to an Ultraprecision Motion Stage
Abstract:
This paper develops a data-driven decoupling feedforward control scheme with iterative tuning to meet the challenge of the crosstalk problem in multiple-input multiple-output (MIMO) motion control systems. In contrast to model-based approaches, iterative tuning fully utilizes the available data to address the practical difficulty in obtaining an accurate dynamic model. The MIMO feedforward signal is iteratively updated by minimizing the developed crosstalk criterion. Specifically, to make the optimal problem convex, the MIMO feedforward controller is structuralized with a finite impulse response (FIR) filter and is parameterized by corresponding coefficients. A data-driven unbiased gradient approximation based on the Toeplitz matrix is then developed for updating the parameter vector. Furthermore, to deal with the Hessian inverse problem encountered in the numerical calculation of the update law, a stable inversion method combined with singular value decomposition is employed. The basic characteristics of the proposed scheme, including convergence accuracy and convergence rate, are illustrated through simulation. Finally, the proposed data-driven decoupling control scheme is applied to a developed ultraprecision motion stage, and the results show that the approach can significantly attenuate the servo error caused by the crosstalk problem. This simplicity and accuracy oriented control method without need of dynamic modeling is definitely suitable for industrial applications.
Autors: Jiang, Y.;Zhu, Y.;Yang, K.;Hu, C.;Yu, D.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jan 2015, volume: 62, issue:1, pages: 620 - 627
Publisher: IEEE
 
» A Data-Driven Process Controller for Energy-Efficient Variable-Speed Pump Operation in the Central Cooling Water System of Marine Vessels
Abstract:
In this paper, a data-driven process controller is designed and implemented onboard a typical marine vessel for optimal variable-speed pump operation, leading to the energy efficiency optimization of its central cooling water system. To match variable flow rate requirements due to changes in the vessel's operational profile with respect to plant limitations, real-time process measurements are used as feedback signals to adjust the parameters and set-points of a data-driven process controller with self-tuned proportional–integral–differential control loops, which is realized through a commercial programmable logic controller and regulates the speed of sea water cooling pumps in order to maximize power saving potential during sea-going and cargo unloading periods. Data-driven control establishes system dynamics according to process parameter variation and ensures system reliability through parameter monitoring, regardless of the controlled plant model. The plant power saving potential is initially examined through a practical case study, whereas experimental results provided after the proposed control system retrofit installation onboard a tanker vessel show significant power balance improvement and reduction of diesel generator fuel consumption compared to existing pump throttle control methods, verifying that marine industry can be greatly benefited from this energy efficiency upgrade.
Autors: Giannoutsos, S.V.;Manias, S.N.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jan 2015, volume: 62, issue:1, pages: 587 - 598
Publisher: IEEE
 
» A Differential-Mode Wideband Bandpass Filter on Slotline Multi-Mode Resonator With Controllable Bandwidth
Abstract:
This letter presents a novel differential-mode (DM) wideband bandpass filter (BPF) on slotline multi-mode resonator (MMR) with controllable bandwidth. The BPF consists of a cross-shaped slotline MMR etched on the ground plane and two pairs of microstrip feeding line. On the one hand, with proper placement of the slotline MMR, the coupling between the slotline MMR and DM feeding lines can be flexibly controlled to achieve the desired DM passband. On the other hand, the cross-shaped slotline MMR is fully broken or disconnected in the middle portion under the CM excitation, thereby obtaining the CM suppression over the DM passband. Moreover, the bandwidth of the DM passband can be freely adjusted through the impedance ratio of the slotline MMR. To verify the design concept, a filter sample has been designed and fabricated. Within the DM passband, the insertion loss of the CM signals is higher than 20.0 dB, the 3 dB fractional bandwidth of the DM passband achieves around 107.7%. The measured results are obtained in good agreement with the predicted ones.
Autors: Chen, D.;Bu, H.;Zhu, L.;Cheng, C.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2015, volume: 25, issue:1, pages: 28 - 30
Publisher: IEEE
 
» A Distributed Maximal Link Scheduler for Multi Tx/Rx Wireless Mesh Networks
Abstract:
The capacity of Wireless Mesh Networks (WMNs) has significantly increased with the recent addition of multiple transmit (Tx) and receive (Rx) (MTR) capability or smart antennas. This increase however is predicated on an effective link scheduler. The aim of any scheduler is to derive a superframe comprising the smallest number of slots that affords each link one or more transmission opportunities. In particular, the scheduler is required to solve an instance of the NP-complete, MAX-CUT problem, in each time slot. To this end, there are a number of centralized schedulers, but only a handful of distributed schedulers. However, each of these distributed schedulers has its own drawbacks; either they do not guarantee maximal activated links or do not guarantee all links are activated. Henceforth, in this paper, we add to the state-of-the-art by proposing a novel distributed scheduler, called Algo-d, which approximates the MAX-CUT problem in a distributed manner using only local information. In fact, this is the first distributed solution for MAX-CUT problem. Through theoretical analysis and simulation, we show that Algo-d achieves the following performance: 1) Algo-d schedules on average 12% fewer and 46.5% more links in each time slot than two centralized algorithms, and 2) Algo-d schedules 28% more links than ROMA and 270% more links than JazzyMAC; both state-of-the-art distributed schedulers for MTR WMNs.
Autors: Wang, H.;Chin, K.;Soh, S.;Raad, R.;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Jan 2015, volume: 14, issue:1, pages: 520 - 531
Publisher: IEEE
 
» A Doubly Degenerate Diffusion Model Based on the Gray Level Indicator for Multiplicative Noise Removal
Abstract:
Multiplicative noise removal is a challenging task in image processing. Inspired by the impressive performance of nonlinear diffusion models in additive noise removal, we address this problem in the view of nonlinear diffusion equation theories rather than the traditional variation methods. We develop a nonlinear diffusion filter denoising framework, which considers not only the information of the gradient of the image, but also the information of gray levels of the image. Furthermore, under this framework, we propose a doubly degenerate diffusion model for multiplicative noise removal, which is analyzed with respect to some of its properties and behavior in denoising process. In numerical aspects, we present an efficient scheme which uses a stabilization by fast explicit diffusion for the implementation of the multiplicative noise removal model. Finally, the experimental results illustrate effectiveness and efficiency of the proposed model.
Autors: Zhou, Z.;Guo, Z.;Dong, G.;Sun, J.;Zhang, D.;Wu, B.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Jan 2015, volume: 24, issue:1, pages: 249 - 260
Publisher: IEEE
 
» A Dual-Loop Antenna Design for Hepta-Band WWAN/LTE Metal-Rimmed Smartphone Applications
Abstract:
A simple direct-fed dual-loop antenna capable of providing hepta-band WWAN/LTE operation under surroundings of an unbroken metal rim in smartphone applications is proposed. The greatest highlight of this proposed antenna is that it provides a simple and effective multiband antenna solution for an unbroken metal-rimmed smartphone. The unbroken metal rim with 5 mm in height embraces the system circuit board of 130 70 mm . Two no-ground portions of 10 70 mm and 5 70 mm are set on the top and bottom edge of the system circuit board, respectively. In-between the two separate no-ground portions, there is a system ground of 115 70 mm connected with the unbroken metal rim via a small grounded patch which divides the unbroken metal rim into two strips. Finally, a dual-loop antenna is formed by combining the inner system ground and two strips. This proposed dual-loop antenna is capable of covering GSM850/900/DCS/PCS/UMTS2100/LTE 2300/2500 operating bands. Detailed design considerations of the proposed antenna are described and both experimental and simulation results are also presented and discussed.
Autors: Ban, Y.-L.;Qiang, Y.-F.;Chen, Z.;Kang, K.;Guo, J.-H.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2015, volume: 63, issue:1, pages: 48 - 58
Publisher: IEEE
 
» A Fast 3-D Deterministic Ray Tracing Coverage Simulator Including Creeping Rays Based On Geometry Voxelization Technique
Abstract:
A deterministic ray tracing simulator is described in this work which conveniently fulfills the requirements of a radar coverage, i.e., field distribution, simulator at 24 GHz or above. Very high performance is achieved by avoiding computational loops due to the usage of same-size matrices. The considered geometry is defined by a voxelization technique to improve the flexibility of this family of ray tracers. A reliable root finder which locates all roots of an equation simultaneously is used to efficiently find the intersections of the rays and the objects based on analytical geometry representations. Also, illumination matrices identify the contributing rays for all the observation points and simplify the process of field superposition. Creeping rays are included into the simulator for more accurate transitions from the illuminated to the deep shadow regions. Furthermore, the proposed simulator is capable of carrying out large bandwidth tasks such as channel impulse response computations. The results approve the capability of the simulator to be used as an optimization and design tool for complex and electrically large scenarios of a radar system including moving targets.
Autors: Azodi, H.;Siart, U.;Eibert, T.F.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2015, volume: 63, issue:1, pages: 210 - 220
Publisher: IEEE
 
» A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency
Abstract:
Integral image computing is an important part of many vision applications and is characterized by intensive computation and frequent memory accessing. This brief proposes an approach for fast integral image computing with high area and power efficiency. For the data flow of the integral image computation a dual-direction data-oriented integral image computing mechanism is proposed to improve the processing efficiency, and then a pipelined parallel architecture is designed to support this mechanism. The parallelism and time complexity of the approach are analyzed and the hardware implementation cost of the proposed architecture is also presented. Compared with the state-of-the-art methods this architecture achieves the highest processing speed with comparatively low logic resources and power consumption.
Autors: Ouyang, P.;Yin, S.;Zhang, Y.;Liu, L.;Wei, S.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2015, volume: 62, issue:1, pages: 75 - 79
Publisher: IEEE
 
» A Fast Parallel Solver for the Forward Problem in Electrical Impedance Tomography
Abstract:
Electrical impedance tomography (EIT) is a noninvasive imaging modality, where imperceptible currents are applied to the skin and the resulting surface voltages are measured. It has the potential to distinguish between ischaemic and haemorrhagic stroke with a portable and inexpensive device. The image reconstruction relies on an accurate forward model of the experimental setup. Because of the relatively small signal in stroke EIT, the finite-element modeling requires meshes of more than 10 million elements. To study the requirements in the forward modeling in EIT and also to reduce the time for experimental image acquisition, it is necessary to reduce the run time of the forward computation. We show the implementation of a parallel forward solver for EIT using the Dune-Fem C++ library and demonstrate its performance on many CPU's of a computer cluster. For a typical EIT application a direct solver was significantly slower and not an alternative to iterative solvers with multigrid preconditioning. With this new solver, we can compute the forward solutions and the Jacobian matrix of a typical EIT application with 30 electrodes on a 15-million element mesh in less than 15 min. This makes it a valuable tool for simulation studies and EIT applications with high precision requirements. It is freely available for download.
Autors: Jehl, M.;Dedner, A.;Betcke, T.;Aristovich, K.;Klofkorn, R.;Holder, D.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Jan 2015, volume: 62, issue:1, pages: 126 - 137
Publisher: IEEE
 
» A Fine-Grained Image Categorization System by Cellet-Encoded Spatial Pyramid Modeling
Abstract:
In this paper, a new fine-grained image categorization system that improves spatial pyramid matching is developed. In this method, multiple cells are combined into cellets in the proposed categorization model, which are highly responsive to an object's fine categories. The object components are represented by cellets that can connect spatially adjacent cells within the same pyramid level. Here, image categorization can be formulated as the matching between the cellets of corresponding images. Toward an effective matching process, an active learning algorithm that can effectively select a few representative cells for constructing the cellets is adopted. A linear-discriminant-analysis-like scheme is employed to select discriminative cellets. Then, fine-grained image categorization can be conducted with a trained linear support vector machine. Experimental results on three real-world data sets demonstrate that our proposed system outperforms the state of the art.
Autors: Zhang, L.;Gao, Y.;Xia, Y.;Dai, Q.;Li, X.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jan 2015, volume: 62, issue:1, pages: 564 - 571
Publisher: IEEE
 
» A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors
Abstract:
Fixed-point arithmetic datapaths with heterogeneous scaling and wordlengths are commonplace in resource, latency, or power constrained designs. This paper describes and proves correct a formal method for accurate high-level casting of optimal adders and subtractors. The proposed approach allows for an early accurate estimation of resource usage which is then available for high-level decision-taking in the design flow. As a result, decoupling between high-level and low-level synthesis is achieved. Results concerning the impact of the approach on resource estimates and a discussion on the wide applicability of the method are presented.
Autors: Sierra, R.;Carreras, C.;Caffarena, G.;Lopez Bario, C.A.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Jan 2015, volume: 34, issue:1, pages: 52 - 62
Publisher: IEEE
 
» A Frequency and Polarization Reconfigurable Circularly Polarized Antenna Using Active EBG Structure for Satellite Navigation
Abstract:
This paper presents a broadband frequency tunable and polarization reconfigurable circularly polarized (CP) antenna, using a novel active electromagnetic band gap (EBG) structure. The EBG surface employs identical metallic rectangular patch arrays on both sides of a thin substrate, but rotated by 90 from each other. The active bias circuits are also orthogonal for each surface, enabling the reflection phases for orthogonal incident waves to be tuned independently in a wide frequency range. By placing a wideband coplanar waveguide (CPW) fed monopole antenna above the EBG surface, and properly tuning the bias voltages across the varactors in each direction, CP waves can be generated at any desired frequency over a broad band. In accordance with simulations, the measured 3 dB axial ratio (AR) bandwidth reaches 40% (1.03–1.54 GHz), with good input matching and radiation patterns at six presented sampling frequencies. The polarization reconfigurability is verified by simulations and measurements, and shown to be capable of switching between left hand circular polarization (LHCP) and right hand circular polarization (RHCP).
Autors: Liang, B.;Sanz-Izquierdo, B.;Parker, E.A.;Batchelor, J.C.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2015, volume: 63, issue:1, pages: 33 - 40
Publisher: IEEE
 
» A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique
Abstract:
This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 µm × 60 µm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 µW DC power.
Autors: Deng, W.;Yang, D.;Ueno, T.;Siriburanon, T.;Kondo, S.;Okada, K.;Matsuzawa, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 68 - 80
Publisher: IEEE
 
» A Fully-Implantable Cochlear Implant SoC With Piezoelectric Middle-Ear Sensor and Arbitrary Waveform Neural Stimulation
Abstract:
A system-on-chip for an invisible, fully-implantable cochlear implant is presented. Implantable acoustic sensing is achieved by interfacing the SoC to a piezoelectric sensor that detects the sound-induced motion of the middle ear. Measurements from human cadaveric ears demonstrate that the sensor can detect sounds between 40 and 90 dB SPL over the speech bandwidth. A highly-reconfigurable digital sound processor enables system power scalability by reconfiguring the number of channels, and provides programmable features to enable a patient-specific fit. A mixed-signal arbitrary waveform neural stimulator enables energy-optimal stimulation pulses to be delivered to the auditory nerve. The energy-optimal waveform is validated with in-vivo measurements from four human subjects which show a 15% to 35% energy saving over the conventional rectangular waveform. Prototyped in a 0.18 µm high-voltage CMOS technology, the SoC in 8-channel mode consumes 572 µW of power including stimulation. The SoC integrates implantable acoustic sensing, sound processing, and neural stimulation on one chip to minimize the implant size, and proof-of-concept is demonstrated with measurements from a human cadaver ear.
Autors: Yip, M.;Jin, R.;Nakajima, H.H.;Stankovic, K.M.;Chandrakasan, A.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 214 - 229
Publisher: IEEE
 
» A GaAs-Based Hybrid Integration of a Tunneling Diode and a 1060-nm Semiconductor Laser
Abstract:
We report on a hybrid integrated tunneling diode, with a simple structure, and a quantum well laser diode, lasing at nm, on GaAs substrate. The low-frequency operation of the integrated circuit was measured and obvious negative differential resistance regions were shown in the electrical and optical output. The electrical and optical bistability were measured, and the peak and valley voltage were 2.03 and 2.17 V, respectively. A 140-mV-wide hysteresis loop and an optical on/off ratio of 21 dB were obtained. The device has potential applications in biomedicine and optical interconnects.
Autors: Mi, J.;Yu, H.;Wang, H.;Tan, S.;Chen, W.;Ding, Y.;Pan, J.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2015, volume: 27, issue:2, pages: 169 - 172
Publisher: IEEE
 
» A Generalized Voltage Droop Strategy for Control of Multiterminal DC Grids
Abstract:
This paper proposes a generalized voltage droop (GVD) control strategy for dc voltage control and power sharing in voltage source converter (VSC)-based multiterminal dc (MTDC) grids. The proposed GVD control is implemented at the primary level of a two-layer hierarchical control structure of the MTDC grid, and constitutes an alternative to the conventional voltage droop characteristics of voltage-regulating VSC stations, providing higher flexibility and, thus, controllability to these networks. As a difference with other methods, the proposed GVD control strategy can be operated in three different control modes, including conventional voltage droop control, fixed active power control, and fixed dc voltage control, by adjusting the GVD characteristics of the voltage-regulating converters. Such adjustment is carried out in the secondary layer of the hierarchical control structure. The proposed strategy improves the control and power-sharing capabilities of the conventional voltage droop, and enhances its maneuverability. The simulation results, obtained by employing a CIGRE B4 dc grid test system, demonstrate the efficiency of the proposed approach and its flexibility in active power sharing and power control as well as voltage control. In these analysis, it will be also shown how the transitions between the operating modes of the GVD control does not give rise to active power oscillations in the MTDC grids.
Autors: Rouzbehi, K.;Miranian, A.;Candela, J.I.;Luna, A.;Rodriguez, P.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Jan 2015, volume: 51, issue:1, pages: 607 - 618
Publisher: IEEE
 
» A Geometry Scalable Model for Nonlinear Thermal Impedance of Trench Isolated HBTs
Abstract:
This letter presents a geometry scalable approach for the calculation of temperature dependent thermal impedance ( ) in trench-isolated heterojunction bipolar transistors. The model is capable of predicting the at any desired temperature and bias points. The temperature dependency is derived by discretizing the heat flow region into number of elementary slices depending on the thermal gradient. Temperature dependent thermal resistances s and capacitances s for each of the slices are calculated in a self-consistent manner. Finally, the proposed model is validated with low-frequency measurements at different ambient temperatures ( ) for different transistor geometries and found to be in good agreement.
Autors: Sahoo, A.K.;Fregonese, S.;Desposito, R.;Aufinger, K.;Maneux, C.;Zimmer, T.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2015, volume: 36, issue:1, pages: 56 - 58
Publisher: IEEE
 
» A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters
Abstract:
A reconfigurable heterogeneous 3D-IC is assembled from two 28 nm FPGA die with 580 k logic cells and two 65 nm mixed signal die on a 65 nm interposer in a 35 mm 2 CS-BGA package. One mixed signal die consists of sixteen 16 bit current steering DACs, the other die consists of sixteen 13 bit pipelined ADCs. The interposer provides optimal system partitioning; noise isolation and high density interconnect between subsystems. Receive SNDR > 61.6 dBFS to Nyquist at 500 MS/s and transmit SFDR > 63.8 dBc to 400 MHz at 1.6 GS/s is measured. Ultralow FPGA to converter die interface power of 0.3 mW/Gb/s is achieved and measured digital to analog isolation > 92dB. The solution can be dynamically optimized for channel count, power and speed.
Autors: Erdmann, C.;Lowney, D.;Lynam, A.;Keady, A.;McGrath, J.;Cullen, E.;Breathnach, D.;Keane, D.;Lynch, P.;De La Torre, M.;De La Torre, R.;Lim, P.;Collins, A.;Farley, B.;Madden, L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2015, volume: 50, issue:1, pages: 258 - 269
Publisher: IEEE
 
» A Hierarchical Framework for Long-Term Power Planning Models
Abstract:
In this paper, we formulate a long-term planning model of transmission line expansion based on balancing investment cost and reducing consumer cost. We achieve this by formulating a hierarchical framework that is sensitive to different agents operating on different timelines, the relationships of which may be competitive, cooperative or somewhere in between. The advantage of this framework is that while it captures the complexity of long-term decision making, it maintains clarity of information flow between models, agents and timelines. For our purposes, we introduce an equilibrium model that combines grid operational concerns with the short-term competitive behavior of generation firms. An iterative solution technique is proposed to provide a Nash solution where each optimization problem is solved globally. This solution is then used to inform an overarching transmission planning model that we solve using derivative-free optimization. Using a de-congested network as a benchmark, numerical results indicate a non-alignment of the objectives of planning and operational entities, whereby easing line congestion may not offer monetary benefits to the wholesale consumer.
Autors: Tang, L.;Ferris, M.C.;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jan 2015, volume: 30, issue:1, pages: 46 - 56
Publisher: IEEE
 
» A High-Frequency-Link Single-Phase PWM Rectifier
Abstract:
This paper proposes a high-performance “cycloconverter-type” high-frequency-link (HFL) single-phase rectifier with an active voltage clamper, which provides bidirectional two-stage galvanic isolation ac–dc power conversion. Modulation strategy, modeling method, and control scheme are comprehensively developed for the HFL rectifier to guarantee its superior performances: 1) two-stage power conversion and soft-switching switch devices lead to high conversion efficiency; 2) complete elimination of voltage spikes during commutation ensures safe operation of high-frequency switching devices; and 3) it can equally function as a high-performance conventional Pulsewidth Modulation (PWM) rectifier: sinusoidal input current, constant dc output voltage, bidirectional power flows between dc side and ac side, and adjustable power factor. A prototype of the proposed HFL rectifier is built for evaluation. The experiment results demonstrate the efficacy of the soft-switching HFL rectifier and its highly promising control performance. The proposed rectifier offers a high-efficiency, high-power-density, and high-performance galvanic isolation power conversion solution to extensive applications.
Autors: Zhu, W.;Zhou, K.;Cheng, M.;Peng, F.;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jan 2015, volume: 62, issue:1, pages: 289 - 298
Publisher: IEEE
 

Publication archives by date

  2017:   January     February     March     April     May     June     July     August     September     October     November     December    

  2016:   January     February     March     April     May     June     July     August     September     October     November     December    

  2015:   January     February     March     April     May     June     July     August     September     October     November     December    

  2014:   January     February     March     April     May     June     July     August     September     October     November     December    

  2013:   January     February     March     April     May     June     July     August     September     October     November     December    

  2012:   January     February     March     April     May     June     July     August     September     October     November     December    

  2011:   January     February     March     April     May     June     July     August     September     October     November     December    

  2010:   January     February     March     April     May     June     July     August     September     October     November     December    

  2009:   January     February     March     April     May     June     July     August     September     October     November     December    

 
0-C     D-L     M-R     S-Z