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Electrical and Electronics Engineering publications abstract of: 01-2014 sorted by title, page: 0
» “Pretty Strong” Converse for the Quantum Capacity of Degradable Channels
Abstract:
We exhibit a possible road toward a strong converse for the quantum capacity of degradable channels. In particular, we show that all degradable channels obey what we call a “pretty strong” converse: when the code rate increases above the quantum capacity, the fidelity makes a discontinuous jump from 1 to at most , asymptotically. A similar result can be shown for the private (classical) capacity. Furthermore, we can show that if the strong converse holds for symmetric channels (which have quantum capacity zero), then degradable channels obey the strong converse. The above-mentioned asymptotic jump of the fidelity at the quantum capacity then decreases from 1 to 0.
Autors: Morgan, C.;Winter, A.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2014, volume: 60, issue:1, pages: 317 - 333
Publisher: IEEE
 
» (In,Ga)As/GaP electrical injection quantum dot laser
Abstract:
The paper reports on the realization of multilayer (In,Ga)As/GaP quantum dot (QD) lasers grown by gas source molecular beam epitaxy. The QDs have been embedded in (Al,Ga)P/GaP waveguide structures. Laser operation at 710 nm is obtained for broad area laser devices with a threshold current density of 4.4 kA/cm2 at a heat-sink temperature of 80 K.
Autors: Heidemann, M.;Hofling, S.;Kamp, M.;
Appeared in: Applied Physics Letters
Publication date: Jan 2014, volume: 104, issue:1, pages: 011113 - 011113-4
Publisher: IEEE
 
» 0.5 THz Performance of a Type-II DHBT With a Doping-Graded and Constant-Composition GaAsSb Base
Abstract:
A type-II GaAsSb Double Heterojunction Bipolar Transistor (DHBT) with an AlInP emitter, doping-graded GaAsSb base, and InP collector has been grown by molecular beam epitaxy. The 0.38 emitter devices have been fabricated by a triple-mesa wet etch process and demonstrated at and . This performance is comparable with composition-graded base devices with similar emitter width.
Autors: Xu, H.;Wu, B.;Iverson, E.W.;Low, T.S.;Feng, M.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2014, volume: 35, issue:1, pages: 24 - 26
Publisher: IEEE
 
» 1+1 Dedicated Optical-Layer Protection Strategy for Filterless Optical Networks
Abstract:
We propose a dedicated optical-layer protection strategy for filterless optical networks offering a 100% protection ratio by introducing a limited number of wavelength selective components at selected intermediate nodes. A comparison with conventional active photonic switching networks is presented. The results show that the proposed 1+1 protection for filterless networks exhibits a clear cost advantage at similar wavelength usage compared to active switching solutions.
Autors: Xu, Zhenyu;Archambault, Emile;Tremblay, Christine;Chen, Jiajia;Wosinska, Lena;Belanger, Michel P.;Littlewood, Paul;
Appeared in: IEEE Communications Letters
Publication date: Jan 2014, volume: 18, issue:1, pages: 98 - 101
Publisher: IEEE
 
» 2-D Electromagnetic and Fluid Models for Inductively Coupled Plasma for RF Ion Thruster Performance Evaluation
Abstract:
A numerical model for the inductively coupled plasma in radio frequency (RF) ion thruster discharge chamber is developed to evaluate the plasma parameters for a 2-D axisymetric domain. The spatial distributions of various plasma parameters are obtained. The ion thruster performance is evaluated by calculating the discharge loss per ion for different deposited RF power values. The geometry of RIT-15LP is applied as the thruster configuration and the results are shown to have the same tendency as presented in the literature. The results of this paper proved that above a certain RF power deposition into the discharge chamber, there is a tradeoff between the thrust obtained from the ion engine and the discharge loss per ion.
Autors: Turkoz, E.;Celik, M.;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Jan 2014, volume: 42, issue:1, pages: 235 - 240
Publisher: IEEE
 
» 2/4-POLE Split-Phase Capacitor Motor for Small Compressors: A Comprehensive Motor Characterization
Abstract:
Compressor electric motor drives play a key role in the energy consumption of residential refrigerators. Electrical efficiency, robustness to starting and overloads and speed variation range define the performance of compressor electric motor drives. Between the lowest cost fixed-speed split-phase capacitor grid-connected induction motor, with lower efficiency, and the higherefficiency grid-connected cage permanent-magnet (PM) rotor split-phase capacitor motor and the inverter fed variable speed PM synchronous motor of highest initial costs, we introduce in this paper a 2 speed grid-connected motor drive. The proposed topology uses a separate split-phase winding, cage-PM-4-pole rotor synchronous motor (PMSM) for low speed (4 poles) and a single-phase (main) winding for 2-pole operation. The tentative target is 85% efficiency at 50 W output for 4-poles (low speed) PMSM operation with good starting and about 60% efficiency in 2-pole (high speed) induction motor operation at 100 W, with smooth transients from low to high speed under full torque load. Circuit models for steady state and for transients with dedicated Matlab codes have been developed, with key FEM validation, to substantiate full scale experiments, and an optimal design methodology embedding both operation modes was put forward, as main theoretical contributions.
Autors: Haddad Kalluf, F.J.;Tutelea, L.N.;Boldea, I.;Espindola, A.;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Jan 2014, volume: 50, issue:1, pages: 356 - 363
Publisher: IEEE
 
» 20 Gbit/s data transmission over 2 km multimode fibre using 850 nm mode filter VCSEL
Abstract:
Error-free data transmission over 1.3 and 2 km multimode fibre at 25 and 20 Gbit/s, respectively, is demonstrated using a high-speed, single-mode, 850 nm vertical-cavity surface-emitting laser (VCSEL) with an integrated mode filter. This result represents a bitrate-distance product of 40 Gbit/s km, a new record for multimode fibre VCSELbased interconnects.
Autors: Safaisini, R.;Haglund, E.;Westbergh, P.;Gustavsson, J.S.;Larsson, A.;
Appeared in: Electronics Letters
Publication date: Jan 2014, volume: 50, issue:1, pages: 40 - 42
Publisher: IEEE
 
» 20 Gbit/s wireless bridge at 220 GHz connecting two fiber-optic links
Abstract:
The feasibility of a wireless link at 220 GHz based on electronic upconversion and downconversion is demonstrated, connecting two optical links at data rates of up to 20 Gbit/s. We use either non-return-to-zero on-off keying with data rates up to 20 Gbit/s or electrical orthogonal frequency division multiplexing with data rates up to 9 Gbit/s. The wireless bridge connects the gateways of two spatially separated fiber sections, each with a length of up to 20 km.
Autors: Koenig, Swen;Antes, Jochen;Lopez-Diaz, Daniel;Schmogrow, Rene;Zwick, Thomas;Koos, Christian;Freude, Wolfgang;Leuthold, Juerg;Kallfass, Ingmar;
Appeared in: IEEE/OSA Journal of Optical Communications and Networking
Publication date: Jan 2014, volume: 6, issue:1, pages: 54 - 61
Publisher: IEEE
 
» 2014 Editorial - A Concluding Remark of 2013
Abstract:
Autors: Leung, K.W.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2014, volume: 62, issue:1, pages: 3 - 6
Publisher: IEEE
 
» 2169 steel waveform measurements for equation of state and strength determination
Abstract:
In support of efforts to develop multiscale models of a variety of materials, we have performed a set of eleven gas gun impact experiments on 2169 steel, a high-strength austenitic stainless steel. These experiments provided carefully controlled shock, reshock, and release velocimetry data, with initial shock stresses ranging from 10 to 50 GPa. Both windowed and free-surface measurements on samples ranging in thickness from 1 to 5 mm were made to increase the utility of the data set. Target physical phenomena included the elastic/plastic transition (Hugoniot elastic limit), the Hugoniot, any phase transition phenomena, and the release/reshock paths (windowed and free-surface), with associated strength information. The Hugoniot is nearly linear in US–up space. Reshock tests with explosively welded impactors produced clean results, by contrast with earlier reshock tests with glued impactors which showed gap signatures. The free-surface samples, which were steps on a single piece of steel, showed lower wavespeeds for thin (1 mm) samples than for thicker (2 or 4 mm) samples. A preliminary strength analysis suggests the flow strength increases with stress from ∼1 GPa to ∼2.5 GPa over this range, consistent with other recent work but about 25% above the Steinberg model.
Autors: Furnish, M.D.;Alexander, C.S.;Brown, J.L.;Reinhart, W.D.;
Appeared in: Journal of Applied Physics
Publication date: Jan 2014, volume: 115, issue:3, pages: 033511 - 033511-9
Publisher: IEEE
 
» 3 μm aperture probes for near-field terahertz transmission microscopy
Abstract:
The transmission of electromagnetic waves through a sub-wavelength aperture is described by Bethe's theory. This imposes severe limitations on using apertures smaller than ∼1/100 of the wavelength for near-field microscopy at terahertz (THz) frequencies. Experimentally, we observe that the transmitted evanescent field within 1 μm of the aperture deviates significantly from the Bethe dependence of E ∝ a3. Using this effect, we realized THz near-field probes incorporating 3 μm apertures and we demonstrate transmission mode THz time-domain near-field imaging with spatial resolution of 3 μm, corresponding to λ/100 (at 1 THz).
Autors: Macfaden, Alexander J.;Reno, John L.;Brener, Igal;Mitrofanov, Oleg;
Appeared in: Applied Physics Letters
Publication date: Jan 2014, volume: 104, issue:1, pages: 011110 - 011110-5
Publisher: IEEE
 
» 30 years of the MAC the influence of the original Macintosh is still felt today [Dataflow]
Abstract:
Famously introduced by a Super Bowl TV ad directed by Ridley Scott, the first Macintosh went on sale in January 1984. Drawing on development efforts for the Xerox Alto and Apple??s own ill-fated Lisa computer, the Macintosh offered the first commercially successful graphical user interface. But that??s not the only innovation packed into the case.
Autors: Cass, S.;
Appeared in: IEEE Spectrum
Publication date: Jan 2014, volume: 51, issue:1, pages: 76 - 76
Publisher: IEEE
 
» 40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170 C
Abstract:
First-ever 40-nm embedded split-gate MONOS (SG-MONOS) flash macros for automotive micro-controller unit (MCU) have been successfully developed. A SG-MONOS cell realizes high performance with low power consumption and intrinsically high data reliability thanks to the combination of split-gate and charge-trapping structure. In addition, newly developed circuit techniques greatly enhance the advantages of SG-MONOS cells and enable fast and reliable operations even at the junction temperature (Tj) of 170 C with small peripheral circuit area; 1) a sense amplifier with digital offset cancellation (SA-DOC) provides fast read operation over 160 MHz; 2) adaptable program current control scheme (APCCS) and intelligent erase scheme (IES) significantly decrease the program and erase time, which also results in improving the memory cells' reliability; and, 3) 3-D stacked unit capacitors achieve area-efficient charge pump. Two types of embedded flash (eFlash) macros with these technologies, code macro of 2 MB and data macro of 64 KB, were fabricated in a 40-nm eFlash process. The code macro demonstrates the capability of 160-MHz random read operation at C, reaching 5.1 GB/s read throughput by simultaneous 256 bits read-out from two code macros. The data macro achieves the program/erase endurance over 10 million cycles at C without any software-assisted techniques.
Autors: Kono, T.;Ito, T.;Tsuruda, T.;Nishiyama, T.;Nagasawa, T.;Ogawa, T.;Kawashima, Y.;Hidaka, H.;Yamauchi, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 154 - 166
Publisher: IEEE
 
» 4G gets real
Abstract:
Have you ever called your cellphone carrier to report poor signal strength? Sure you have. And did that carrier do anything significant to fix the problem? Of course it didn't-unless you live in South Korea.
Autors: Bleicher, A.;
Appeared in: IEEE Spectrum
Publication date: Jan 2014, volume: 51, issue:1, pages: 38 - 62
Publisher: IEEE
 
» 50 years in icing performance of outdoor insulators
Abstract:
Outdoor insulators are exposed to a wide range of conditions, leading to build-up of pollution from the air by dry deposition. Following rain, most insulator surfaces are cleared of preexisting deposit, but the electrical conductivity of the rain itself may lead to wet flashover problems. Insulator standards and application guides suggest appropriate metal-to-metal dry-arc and leakage distances along the insulator profile to ensure that the normal ac line voltage does not follow a conductive path, across the surfaces or through a heavy cascade of water drops, from line to ground. Ice and snow accretion are special cases of exposure to pollution. There is usually no significant difference between the electrical conductivity of various forms of precipitation so that the same issues of wet flashover occur when icicles bridge the sheds of an insulator. Freezing will reduce the conductivity of a water jet by a factor of 100 or more, but the process will also reject all the impurities to the ice surface. A thin ice layer can also stabilize preexisting surface pollution, acting as an effective and thick nonsoluble deposit, and thus depressing flashover strength across insulator leakage distances.
Autors: Farzaneh, M.;Chisholm, W.A.;
Appeared in: IEEE Electrical Insulation Magazine
Publication date: Jan 2014, volume: 30, issue:1, pages: 14 - 24
Publisher: IEEE
 
» 50 years of Electronics Letters
Abstract:
In 1963 there was great interest in many aspects of microwave engineering in particular, and in the burgeoning fi eld of semiconductor electronics and circuit systems. The rapid communication of the latest advances in microwave components containing ferrite materials that offered nonreciprocal properties was served in part by the journal Applied Physics Letters but most other electronics-related activity in industry and universities had no outlet for rapid short announcements. Thus, a suggestion was made to the Council of the Institution of Electrical Engineers (IEE - now the Institution of Engineering and Technology, IET) that a new journal should be launched to fi ll the gap. It was agreed that Electronics Letters should be published bi-monthly and the fi rst Issue appeared in March 1964.
Autors: Clarricoats, P.;Ash, E.;
Appeared in: Electronics Letters
Publication date: Jan 2014, volume: 50, issue:1, pages: 3 - 3
Publisher: IEEE
 
» 50+ Years of impedance measurement and spectroscopy, and implementation of virtual spectroscopy based on finite element analysis
Abstract:
Dielectric spectra are usually discussed in the context of simplified circuit theory models. With the availability of numerous ??multiphysics?? programs based on finite element analysis (FEA) which support transient and transient nonlinear FEA, a virtual dielectric spectrometer can be implemented to compute the dielectric spectrum of anything which can be modeled using FEA. This allows comparison of measured dielectric spectra with detailed computational models which mimic the physical systems under study with much greater fidelity than circuit theory models. Once reasonable correspondence between the physical system and finite element model has been established, parameters can be varied in the finite element model to investigate the effect of changes to the physical system without having to formulate the materials of interest.
Autors: Ma, S.;Boggs, S.;
Appeared in: IEEE Electrical Insulation Magazine
Publication date: Jan 2014, volume: 30, issue:1, pages: 25 - 31
Publisher: IEEE
 
» 60 GHz grounded-coplanar-waveguide-tosubstrate- integrated-waveguide transition for rof transmitters
Abstract:
A novel transition from a grounded-coplanar waveguide to a substrate integrated-waveguide (SIW) is presented featuring a fully planar bias tee for the development of 60 GHz radio-over-fibre photonic transmitters for indoor applications. The transition is intended to serve as a connection between a 60 GHz photodiode chip and SIW antennas suitable for indoor data distribution. Simulations show that in the whole 57-4 GHz communication band, the return loss (RL) is at least 15 dB, whereas the insertion loss (IL), is < 0.9 dB. Measurements of a back-to-back configuration confirm the numerical results, with a IL of ~2 dB and a RL > 12 dB.
Autors: Flammia, I.;Khani, B.;Arafat, S.;Stohr, A.;
Appeared in: Electronics Letters
Publication date: Jan 2014, volume: 50, issue:1, pages: 34 - 35
Publisher: IEEE
 
» -Equivalence in Group Algebras and Minimal Abelian Codes
Abstract:
Let be a finite Abelian group and a field such that does not divide . Denote by the group algebra of over . A (semisimple) Abelian code is an ideal of . Two codes and of are -equivalent if there exists an automorphism of whose linear extension to maps onto . In this paper, we give a necessary and sufficient condition for minimal Abelian codes to be -equivalent and show how to correct some results in the literature.
Autors: Ferraz, R.A.;Guerreiro, M.;Polcino Milies, C.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2014, volume: 60, issue:1, pages: 252 - 260
Publisher: IEEE
 
» Based High- Inter-Gate Dielectrics for Planar NAND Flash Memory
Abstract:
We investigate the use of based high- materials as inter-gate dielectric in hybrid floating gate based memory cells for planar NAND flash. The incorporation of Al or Gd in the allows reaching higher values as compared with pure through different crystalline characteritics. However, a difficult compromise is to be found between the value and low leakage due to grain boudaries in a material with large crystalline proportions. Hence, HfGdO reaches a value as high as 23 but shows important leakage that translates into early program saturation and room temperature charge loss. The HfAlO has more moderate of but shows lower leakage leading to improved device performances. Finally, a three layer stack where a high- HfAlO layer is encapsulated into thinner layers shows overall best compromise in terms of program/erase window and retention.
Autors: Breuil, L.;Lisoni, J.G.;Blomme, P.;Van den Bosch, G.;Van Houdt, J.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2014, volume: 35, issue:1, pages: 45 - 47
Publisher: IEEE
 
» -Equivalence in Group Algebras and Minimal Abelian Codes
Abstract:
Let be a finite Abelian group and a field such that does not divide . Denote by the group algebra of over . A (semisimple) Abelian code is an ideal of . Two codes and of are -equivalent if there exists an automorphism of whose linear extension to maps onto . In this paper, we give a necessary and sufficient condition for minimal Abelian codes to be -equivalent and show how to correct some results in the literature.
Autors: Ferraz, R.A.;Guerreiro, M.;Polcino Milies, C.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2014, volume: 60, issue:1, pages: 252 - 260
Publisher: IEEE
 
» Based High- Inter-Gate Dielectrics for Planar NAND Flash Memory
Abstract:
We investigate the use of based high- materials as inter-gate dielectric in hybrid floating gate based memory cells for planar NAND flash. The incorporation of Al or Gd in the allows reaching higher values as compared with pure through different crystalline characteritics. However, a difficult compromise is to be found between the value and low leakage due to grain boudaries in a material with large crystalline proportions. Hence, HfGdO reaches a value as high as 23 but shows important leakage that translates into early program saturation and room temperature charge loss. The HfAlO has more moderate of but shows lower leakage leading to improved device performances. Finally, a three layer stack where a high- HfAlO layer is encapsulated into thinner layers shows overall best compromise in terms of program/erase window and retention.
Autors: Breuil, L.;Lisoni, J.G.;Blomme, P.;Van den Bosch, G.;Van Houdt, J.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2014, volume: 35, issue:1, pages: 45 - 47
Publisher: IEEE
 
» A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler
Abstract:
A noncontact and housing-less thin–thick connecting method was developed for mobile industry processor interface (MIPI) applications. This paper describes the world's first 0.15-mm-thick connector using a vertical directional coupler (VDC) which enables simultaneous two-link communication with one coupler without fatal performance degradation. We have analyzed the conditions for isolating two links in a coupler, and the design method is discussed. A fully balanced pulse transmitter implemented in 90-nm CMOS technology significantly suppressed electromagnetic interference (EMI), which agrees well with MIPI requirements. An experimental liquid crystal display interface system reached a maximum data rate of 2.3 Gb/s/link at a bit error rate of less than and a power consumption of 1.47 pJ/b. The timing margin of single link was 320 ps ( 64% U.I.) and of two links was 305 ps ( 61% U.I.) at 2.0 Gb/s.
Autors: Kosuge, A.;Mizuhara, W.;Shidei, T.;Takeya, T.;Miura, N.;Taguchi, M.;Ishikuro, H.;Kuroda, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 223 - 231
Publisher: IEEE
 
» A 0.18- m CMOS SoC for a 100-m-Range 10-Frame/s 200 96-Pixel Time-of-Flight Depth Sensor
Abstract:
With the emerging need for high-resolution light detection and ranging (LIDAR) technologies in advanced driver assistance systems (ADAS), we introduce a system-on-a-chip (SoC) that performs time-correlated single-photon counting and complete digital signal processing for a time-of-flight (TOF) sensor. At the core of the 0.18- m CMOS SoC, we utilize linear arrays of 16 TOF and 32 intensity-only macro-pixels based on single-photon avalanche diodes in an original look-ahead concept, thus acquiring active TOF and passive intensity images simultaneously. The SoC also comprises an array of circuits capable of generating precise triggers upon spatiotemporal correlation events, an array of 64 12-b time-to-digital converters, and 768 kb of SRAM memory. The SoC provides the system-level electronics with a serial and low-bit-rate digital interface for: 1) multi-echo distance; 2) distance reliability; 3) intensity; and 4) passive-only intensity, thus mitigating system-level complexity and cost. A proof-of-concept prototype that achieves depth imaging up to 100 m with a resolution of 202 96 pixels at 10 frames/s has been implemented. Quantitative evaluation of the TOF sensor under strong solar background illuminance, i.e., 70 klux, revealed a repeatability error of 14.2 cm throughout the distance range of 100 m, thus leading to a relative precision of 0.14%. Under the same conditions, the relative nonlinearity error was 0.11%. In order to show the suitability of our approach for ADAS-related applications, experimental results in which the depth sensor was operated in typical traffic situations have also been reported.
Autors: Niclass, C.;Soga, M.;Matsubara, H.;Ogawa, M.;Kagami, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 315 - 330
Publisher: IEEE
 
» A 0.18- m CMOS SoC for a 100-m-Range 10-Frame/s 200 96-Pixel Time-of-Flight Depth Sensor
Abstract:
With the emerging need for high-resolution light detection and ranging (LIDAR) technologies in advanced driver assistance systems (ADAS), we introduce a system-on-a-chip (SoC) that performs time-correlated single-photon counting and complete digital signal processing for a time-of-flight (TOF) sensor. At the core of the 0.18- m CMOS SoC, we utilize linear arrays of 16 TOF and 32 intensity-only macro-pixels based on single-photon avalanche diodes in an original look-ahead concept, thus acquiring active TOF and passive intensity images simultaneously. The SoC also comprises an array of circuits capable of generating precise triggers upon spatiotemporal correlation events, an array of 64 12-b time-to-digital converters, and 768 kb of SRAM memory. The SoC provides the system-level electronics with a serial and low-bit-rate digital interface for: 1) multi-echo distance; 2) distance reliability; 3) intensity; and 4) passive-only intensity, thus mitigating system-level complexity and cost. A proof-of-concept prototype that achieves depth imaging up to 100 m with a resolution of 202 96 pixels at 10 frames/s has been implemented. Quantitative evaluation of the TOF sensor under strong solar background illuminance, i.e., 70 klux, revealed a repeatability error of 14.2 cm throughout the distance range of 100 m, thus leading to a relative precision of 0.14%. Under the same conditions, the relative nonlinearity error was 0.11%. In order to show the suitability of our approach for ADAS-related applications, experimental results in which the depth sensor was operated in typical traffic situations have also been reported.
Autors: Niclass, C.;Soga, M.;Matsubara, H.;Ogawa, M.;Kagami, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 315 - 330
Publisher: IEEE
 
» A 0.5 V W CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor
Abstract:
A 0.5 V CMOS light-to-digital converter (LDC) based on a nonuniform quantizer and off-chip photodiode enables a photodiode bias current range spanning 4 nA to 3.5 A while consuming less than 4 W of power. Using an off-chip LED as a modulated light source, measurements with a photodiode current signal having modulation frequency of 1.2 Hz (72 beats per minute) and 0.5% peak-to-peak amplitude relative to performed at the low and high end of the range confirm over 30 dB of SNR for an integration bandwidth spanning 0.5 to 5 Hz. Using off-chip digital signal processing of the LDC output, instantaneous period jitter (a proxy for instantaneous heart rate) is measured to be less than 0.45% (rms) of the period, and the high sensitivity of the LDC allows detection of the heart-rate signal from a finger pressed against the off-chip photodiode using only ambient light. Key circuit components of the LDC include a wide range logarithmic digital-to-resistance converter (DRC) utilizing digital multibit modulation to achieve fine resolution and a nonuniform quantizer based on a laddered inverter quantizer (LIQAF) which also acts as a low-noise front-end amplifier and filter.
Autors: Alhawari, M.;Albelooshi, N.A.;Perrott, M.H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 271 - 288
Publisher: IEEE
 
» A 0.5 V W CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor
Abstract:
A 0.5 V CMOS light-to-digital converter (LDC) based on a nonuniform quantizer and off-chip photodiode enables a photodiode bias current range spanning 4 nA to 3.5 A while consuming less than 4 W of power. Using an off-chip LED as a modulated light source, measurements with a photodiode current signal having modulation frequency of 1.2 Hz (72 beats per minute) and 0.5% peak-to-peak amplitude relative to performed at the low and high end of the range confirm over 30 dB of SNR for an integration bandwidth spanning 0.5 to 5 Hz. Using off-chip digital signal processing of the LDC output, instantaneous period jitter (a proxy for instantaneous heart rate) is measured to be less than 0.45% (rms) of the period, and the high sensitivity of the LDC allows detection of the heart-rate signal from a finger pressed against the off-chip photodiode using only ambient light. Key circuit components of the LDC include a wide range logarithmic digital-to-resistance converter (DRC) utilizing digital multibit modulation to achieve fine resolution and a nonuniform quantizer based on a laddered inverter quantizer (LIQAF) which also acts as a low-noise front-end amplifier and filter.
Autors: Alhawari, M.;Albelooshi, N.A.;Perrott, M.H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 271 - 288
Publisher: IEEE
 
» A 0.8/2.4 GHz Tunable Active Band Pass Filter in InP/Si BiCMOS Technology
Abstract:
A tunable active band pass filter (BPF) has been designed in a chip-scale heterogeneous integration technology, which intimately integrates InP HBTs on a deep scaled CMOS technology. The BPF test chip consists of a programmable gain amplifier (PGA), a BPF core, and a buffer. The chip features a frequency tuning range from 0.8 to 2.4 GHz with 150 MHz pass band and four gain steps: 0, 6, 12, and 16 dB. The BPF core employs active-RC architecture for high linearity by leveraging the 300 GHz of InP HBTs and the programmability of CMOS. The test chip occupies area including pads and draws 85/110 mA from a 3.5 V power supply for 0.8/2.4 GHz bands, respectively. In addition, it demonstrates out-of-band IIP3s of 21.97/16.87 dBm for 0.8/2.4 GHz bands at the high gain mode, which suggests the BPF core delivers 37.97/32.87 dBm out-of-band IIP3s.
Autors: Xu, Z.;McArdle-Moore, J.;Oh, T.C.;Kim, S.;Chen, S.T.W.;Royter, Y.;Lau, M.;Valles, I.;Hitko, D.A.;Li, J.C.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2014, volume: 24, issue:1, pages: 47 - 49
Publisher: IEEE
 
» A 1-kW 32–34-GHz Folded Waveguide Traveling Wave Tube
Abstract:
Folded waveguide (FWG) traveling wave tubes (TWTs) are potential sources of wideband, high-power millimeter and terahertz wave radiation. However, low efficiency limits its application. In this paper, we discuss a design strategy to improve efficiency of the FWG TWT meanwhile how to avoid instability is also discussed. The critical factors for the slow-wave structure design and the sever design are analyzed. A phase velocity taper profile incorporating a positive period followed by a negative period is introduced into the design to improve the efficiency. A Ka-band FWG TWT was developed, which demonstrated the output power up to in 2-GHz bandwidth and electronic efficiency up to .
Autors: Gong, H.;Xu, J.;Tang, T.;Wei, Y.;Gong, Y.;Zhang, C.;Su, X.;Cai, S.;Wu, G.;Feng, J.;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Jan 2014, volume: 42, issue:1, pages: 8 - 12
Publisher: IEEE
 
» A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications
Abstract:
A 10-bit 40-MS/s analog-to-digital converter (ADC) that is suitable for wireless access in vehicular environment applications is introduced. In order to satisfy the severe requirement of a wide range operating temperature under the given constraints, the ADC was simplified by eliminating nonessential building blocks such as reference drivers, a sample-and-hold amplifier (SHA), and level shifters. The proposed internal signal amplification method extends the effective signal range in both multiplying digital-to-analog converter and flash ADC, as well as the error correction range. A new clock generation circuit for a SHA-less pipelined ADC removes the need for a higher frequency external clock. The prototype ADC was fabricated in a 180-nm CMOS process. The ADC core consumes 23.4 mW at 3.3-V/1.8-V supplies. The measured worst differential nonlinearity and integral nonlinearity were LSB and LSB, respectively, at a temperature of . The signal-to-noise-and-distortion ratio stayed above 55 dB in the Nyquist condition in a temperature range of , which is about a 0.5 effective-number-of-bits drop from the room-temperature result.
Autors: Oh, G.-G.;Lee, C.-K.;Ryu, S.-T.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2014, volume: 61, issue:1, pages: 6 - 10
Publisher: IEEE
 
» A 1024 8, 700-ps Time-Gated SPAD Line Sensor for Planetary Surface Exploration With Laser Raman Spectroscopy and LIBS
Abstract:
A 1024 8 time-gated, single-photon avalanche diode line sensor is presented for time-resolved laser Raman spectroscopy and laser-induced breakdown spectroscopy. Two different chip geometries were implemented and characterized. A type-I sensor has a maximum photon detection efficiency of 0.3% and median dark count rate of 80 Hz at 3 V of excess bias. A type-II sensor offers a maximum photon detection efficiency of 19.3% and a median dark count rate of 5.7 kHz at 3 V of excess bias. Both chips have 250-ps temporal resolution and fast gating capability, with a minimum gate width of 1.8 ns for type I and 0.7 ns for type II. Raman spectra were successfully observed from natural minerals, such as calcite and willemite. With the use of subnanosecond gating, background fluorescence was significantly reduced.
Autors: Maruyama, Y.;Blacksberg, J.;Charbon, E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 179 - 189
Publisher: IEEE
 
» A 1024 8, 700-ps Time-Gated SPAD Line Sensor for Planetary Surface Exploration With Laser Raman Spectroscopy and LIBS
Abstract:
A 1024 8 time-gated, single-photon avalanche diode line sensor is presented for time-resolved laser Raman spectroscopy and laser-induced breakdown spectroscopy. Two different chip geometries were implemented and characterized. A type-I sensor has a maximum photon detection efficiency of 0.3% and median dark count rate of 80 Hz at 3 V of excess bias. A type-II sensor offers a maximum photon detection efficiency of 19.3% and a median dark count rate of 5.7 kHz at 3 V of excess bias. Both chips have 250-ps temporal resolution and fast gating capability, with a minimum gate width of 1.8 ns for type I and 0.7 ns for type II. Raman spectra were successfully observed from natural minerals, such as calcite and willemite. With the use of subnanosecond gating, background fluorescence was significantly reduced.
Autors: Maruyama, Y.;Blacksberg, J.;Charbon, E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 179 - 189
Publisher: IEEE
 
» A 130.7- 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology
Abstract:
A 32-Gb ReRAM test chip has been developed in a 24-nm process, with a diode as the selection device and metal oxide as the switching element. The memory array is constructed with cross-point architecture to allow multiple memory layers stacked above the supporting circuitry and minimize the circuit area overhead. Die efficiency is further improved by sharing wordlines and bitlines between adjacent blocks. As the number of sense amplifiers under the memory array is limited, a pipelined array control scheme is adopted to compensate the performance impact while utilizing the fast switching time of ReRAM cells. With the chip current consumption being dominated by the array leakage and sensitive to array bias and operating conditions, a charge pump stage control scheme is introduced to dynamically adapt to the operating conditions for optimal power consumption. Smart Read during sensing and leakage current compensation scheme during programming are applied to the large-block architecture and achieve a chip density that is several orders of magnitude higher than prior ReRAM developments.
Autors: Liu, T.;Yan, T.H.;Scheuerlein, R.;Chen, Y.;Lee, J.K.;Balakrishnan, G.;Yee, G.;Zhang, H.;Yap, A.;Ouyang, J.;Sasaki, T.;Al-Shamma, A.;Chen, C.;Gupta, M.;Hilton, G.;Kathuria, A.;Lai, V.;Matsumoto, M.;Nigam, A.;Pai, A.;Pakhale, J.;Siau, C.H.;Wu, X.;Yin,
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 140 - 153
Publisher: IEEE
 
» A 130.7- 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology
Abstract:
A 32-Gb ReRAM test chip has been developed in a 24-nm process, with a diode as the selection device and metal oxide as the switching element. The memory array is constructed with cross-point architecture to allow multiple memory layers stacked above the supporting circuitry and minimize the circuit area overhead. Die efficiency is further improved by sharing wordlines and bitlines between adjacent blocks. As the number of sense amplifiers under the memory array is limited, a pipelined array control scheme is adopted to compensate the performance impact while utilizing the fast switching time of ReRAM cells. With the chip current consumption being dominated by the array leakage and sensitive to array bias and operating conditions, a charge pump stage control scheme is introduced to dynamically adapt to the operating conditions for optimal power consumption. Smart Read during sensing and leakage current compensation scheme during programming are applied to the large-block architecture and achieve a chip density that is several orders of magnitude higher than prior ReRAM developments.
Autors: Liu, T.;Yan, T.H.;Scheuerlein, R.;Chen, Y.;Lee, J.K.;Balakrishnan, G.;Yee, G.;Zhang, H.;Yap, A.;Ouyang, J.;Sasaki, T.;Al-Shamma, A.;Chen, C.;Gupta, M.;Hilton, G.;Kathuria, A.;Lai, V.;Matsumoto, M.;Nigam, A.;Pai, A.;Pakhale, J.;Siau, C.H.;Wu, X.;Yin,
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 140 - 153
Publisher: IEEE
 
» A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS
Abstract:
A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino-compatible, CD logic predischarges the output to logic “0” and conditionally makes a transition to logic “1” through the critical-path CLK PMOS transistors for an NMOS transistor network. The constant delay (regardless of the fan-in) feature makes it up to faster than a dynamic logic gate during the D-Q mode for a complex logic such as a two-bit binary comparator. The proposed comparator's architecture is divided into two stages, where the first stage adapts a novel tree comparator structure specifically designed for static logic to achieve low-power consumption and the second stage utilizes CD logic to realize high performance without sacrificing the overall energy efficiency. At 1-V supply, the proposed comparator's measured delay is 167 ps, and has an average power and a leakage power of 2.34 mW and 0.06 mW, respectively. At 0.3-pJ iso-energy or 250-ps iso-delay budget, the proposed comparator with CD logic is 20% faster or 17% more energy-efficient compared to a comparator implemented with just the static logic.
Autors: Chuang, P.I-J.;Sachdev, M.;Gaudet, V.C.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2014, volume: 61, issue:1, pages: 160 - 171
Publisher: IEEE
 
» A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications
Abstract:
High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes—a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.
Autors: Tikekar, M.;Huang, C.-T.;Juvekar, C.;Sze, V.;Chandrakasan, A.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 61 - 72
Publisher: IEEE
 
» A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit
Abstract:
This paper presents circuit techniques to reduce both active and standby mode power, especially at room temperature (RT). A bit-line power calculator is used to adaptively set the cell supply voltage in the active mode. A digitally controllable retention circuit regulates in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28-nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25 is reduced by 27% and 85%, respectively.
Autors: Tachibana, F.;Hirabayashi, O.;Takeyama, Y.;Shizuno, M.;Kawasumi, A.;Kushida, K.;Suzuki, A.;Niki, Y.;Sasaki, S.;Yabe, T.;Unekawa, Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 118 - 126
Publisher: IEEE
 
» A 3-D Miniaturized High Selectivity Bandpass Filter in LTCC Technology
Abstract:
Transmission zeros are used to improve the roll-off factors of filters but as a consequence, the out-of-band rejection decreases. In this work, an LTCC filter design is presented which employs a series inductor (implemented as a via hole) to improve the out-of-band rejection by introducing a third transmission zero. The filter, designed for GPS band (1.57 GHz), has one of the smallest reported foot prints ( ) and demonstrates the highest roll off factor (16.7 dB/100 MHz) for this band. With only four LTCC layers, the design is cost effective and thus highly suitable for miniaturized, ultra-thin system-on-package applications.
Autors: Arabi, E.;Lahti, M.;Vaha-Heikkila, T.;Shamim, A.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2014, volume: 24, issue:1, pages: 8 - 10
Publisher: IEEE
 
» A 3.4- W Object-Adaptive CMOS Image Sensor With Embedded Feature Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging
Abstract:
We report a low-power object-adaptive CMOS imager, which suppresses spatial temporal bandwidth. The object-adaptive imager has embedded a feature extraction algorithm for identifying objects of interest. The sensor wakes up triggered by motion sensing and extracts features from the captured image for the detection of object-of-interest (OOI). Full-image capturing operation and image signal transmission are performed only when the interested objects are found, which significantly reduces power consumption at the sensor node. This motion-triggered OOI imaging significantly saves a spatial bandwidth more than 96.5% from the feature output and saves a temporal bandwidth from the motion-triggered wakeup and object adaptive imaging. The sensor consumes low power by employing a reconfigurable differential-pixel architecture with reduced power supply voltage and by implementing the feature extraction algorithm with mixed-signal circuitry in a small area. The chip operates at 0.22 W/frame in motion-sensing mode and at 3.4 W/frame for feature extraction, respectively. The object detection from on-chip feature extraction circuits has demonstrated a 94.5% detection rate for human from a set of 200 sample images.
Autors: Choi, J.;Park, S.;Cho, J.;Yoon, E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 289 - 300
Publisher: IEEE
 
» A 3.4- W Object-Adaptive CMOS Image Sensor With Embedded Feature Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging
Abstract:
We report a low-power object-adaptive CMOS imager, which suppresses spatial temporal bandwidth. The object-adaptive imager has embedded a feature extraction algorithm for identifying objects of interest. The sensor wakes up triggered by motion sensing and extracts features from the captured image for the detection of object-of-interest (OOI). Full-image capturing operation and image signal transmission are performed only when the interested objects are found, which significantly reduces power consumption at the sensor node. This motion-triggered OOI imaging significantly saves a spatial bandwidth more than 96.5% from the feature output and saves a temporal bandwidth from the motion-triggered wakeup and object adaptive imaging. The sensor consumes low power by employing a reconfigurable differential-pixel architecture with reduced power supply voltage and by implementing the feature extraction algorithm with mixed-signal circuitry in a small area. The chip operates at 0.22 W/frame in motion-sensing mode and at 3.4 W/frame for feature extraction, respectively. The object detection from on-chip feature extraction circuits has demonstrated a 94.5% detection rate for human from a set of 200 sample images.
Autors: Choi, J.;Park, S.;Cho, J.;Yoon, E.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 289 - 300
Publisher: IEEE
 
» A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13- CMOS for Nonvolatile Processing in Digital Systems
Abstract:
In order to realize a digital system with no distinction between “on” and “off,” the computational state must be stored in nonvolatile memory elements. If the energy cost and time cost of managing the computational state in nonvolatile memory can be lowered to the microsecond and picojoule-per-bit level, such a system could operate from unreliable harvested energy, never requiring a reboot. This work presents a nonvolatile D-flip-flop (NVDFF) designed in 0.13- CMOS that retains state in ferroelectric capacitors during sporadic power loss. The NVDFF is integrated into an ASIC design flow, and a test-case nonvolatile FIR filter with an accompanying power management unit automatically saves and restores the state based on the status of a one-bit indicator of energy availability. Correct operation has been verified over power-cycle intervals from 4.8 to 1 day. The round-trip save-restore energy is 3.4 pJ per NVDFF. Also presented are statistical measurements across 21 000 NVDFFs to validate the capability of the circuit to achieve the requisite 10-ppm failure rate for embedded system applications.
Autors: Qazi, M.;Amerasekera, A.;Chandrakasan, A.P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 202 - 211
Publisher: IEEE
 
» A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm
Abstract:
The 3.6 GHz SPARC T5 processor is Oracle's next generation CMT SoC processor implemented in TSMC's 28 nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generations number of cores to 16 and L3 cache size to 8 MB while increasing bandwidth by nearly 3×. Power efficiency was improved through features like DVFS, core-pair cycle skipping and SerDes power scaling. The SPARC T5 processor has been designed to fit in systems that can scale from 1 to 8 sockets, or 128 to 1024 threads, in glueless fashion. The diverse system-level bandwidth requirements of up to 5.65 TB/sec in these systems are met by advanced SERDES design that handles up to 30 dB loss in an area and power efficient manner. The different thermal envelopes of these systems are addressed by power management features that span software, system and chip design.
Autors: Hart, J.M.;Cho, H.;Ge, Y.;Gruber, G.;Huang, D.;Hwang, C.;Jian, D.;Johnson, T.;Konstadinidis, G.K.;Krishnaswamy, V.;Kwong, L.;Masleid, R.P.;Mehta, R.;Nawathe, U.;Ramachandran, A.;Sathianathan, H.;Sheng, Y.;Shin, J.L.;Turullols, S.;Qin, Z.;Yen, K.C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 19 - 31
Publisher: IEEE
 
» A 4.2 mm 72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS
Abstract:
This paper presents a direct-conversion DTV tuner for both VHF and UHF bands. The proposed tuner achieves a noise figure of 2.5–3.5 dB at VHF band and 2–3 dB at UHF band while the LNA consumes only 3.5 mW. An external band-pass LC filter is adopted for RF pre-filtering and providing DC conduction path for noise cancelling balun LNA. The system-level co-design of the LNA and pre-selecting filter further help to obtain 33 dB third-order harmonic rejection ratio without using harmonic rejection mixers. A quantization-noise-compensated fractional- frequency synthesizer is implemented, achieving 0.5 integrated phase error (1 kHz to 4 MHz) at 666 MHz, and suppressing out-of-band noise by 20 dB. The proposed PLL injects compensation current into the loop filter during the PFD delay time, which precisely tracks the VCO output frequency. Highly reconfigurable analog baseband with 0.5–4 MHz bandwidth and 6–54 dB gain is integrated. The tuner is implemented in 65 nm CMOS process, occupies an area of 4.2 , and consumes only 72 mW from a 1.2 V voltage supply.
Autors: Chen, L.;Wang, Y.;Wang, C.;Wang, J.;Shi, C.;Weng, X.;Ye, L.;Liu, J.;Liao, H.;Wang, Y.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2014, volume: 61, issue:1, pages: 280 - 292
Publisher: IEEE
 
» A 4.2 mm 72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS
Abstract:
This paper presents a direct-conversion DTV tuner for both VHF and UHF bands. The proposed tuner achieves a noise figure of 2.5–3.5 dB at VHF band and 2–3 dB at UHF band while the LNA consumes only 3.5 mW. An external band-pass LC filter is adopted for RF pre-filtering and providing DC conduction path for noise cancelling balun LNA. The system-level co-design of the LNA and pre-selecting filter further help to obtain 33 dB third-order harmonic rejection ratio without using harmonic rejection mixers. A quantization-noise-compensated fractional- frequency synthesizer is implemented, achieving 0.5 integrated phase error (1 kHz to 4 MHz) at 666 MHz, and suppressing out-of-band noise by 20 dB. The proposed PLL injects compensation current into the loop filter during the PFD delay time, which precisely tracks the VCO output frequency. Highly reconfigurable analog baseband with 0.5–4 MHz bandwidth and 6–54 dB gain is integrated. The tuner is implemented in 65 nm CMOS process, occupies an area of 4.2 , and consumes only 72 mW from a 1.2 V voltage supply.
Autors: Chen, L.;Wang, Y.;Wang, C.;Wang, J.;Shi, C.;Weng, X.;Ye, L.;Liu, J.;Liao, H.;Wang, Y.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2014, volume: 61, issue:1, pages: 280 - 292
Publisher: IEEE
 
» A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter With an AC-/DC-Coupled Equalizer and a Voltage Offset Generator
Abstract:
This paper describes a voltage-mode transmitter with an AC-/DC-coupled equalizer. A dual-loop regulator controls the tap-weight coefficient for the DC-coupled equalizer while maintaining the output matching condition. An AC-coupling technique is employed to enhance the edge rate and reduce the burden of the DC-coupled equalizer. The transmitter also supports the ability to add a DC differential voltage offset into the output signal so that the voltage margin of the link can be measured. The transmitter was fabricated using a 0.13-um CMOS technology. When 240- , 5.2-Gb/s data are sent over 20-inch FR4 channels, the eye of the received data has a voltage margin of 60 mV and a peak-to-peak jitter of 40 ps. The proposed transmitter consumes 5.86 mW from a 1.2-V supply while operating at 5.2 Gb/s.
Autors: Kim, S.;Jeong, Y.;Lee, M.;Kwon, K.-W.;Chun, J.-H.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2014, volume: 61, issue:1, pages: 213 - 225
Publisher: IEEE
 
» A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems
Abstract:
This paper describes an asymmetric 6.4-Gb/s memory interface for a wide range of DIMM configurations for desktop and server applications. The link uses a fly-by quadrature forwarded clock to enable fast startup and power-mode transitions on the DRAM and per-bit timing adjustment on the controller to enable the high-speed signaling. Single-ended low-swing near-ground signaling (NGS) is introduced in order to minimize signaling power. Transmitter and receiver equalization are used on the controller, but not the DRAM, in order to save DRAM complexity and power. Architectural and circuit techniques are presented to address the complex signaling and timing environment encountered in the explored configurations. The implemented link achieves 6.4-Gb/s communication over a 3.5-in FR4 PCB trace with a dual-rank dual-in line memory module with better than 9.1-pJ/bit power efficiency for the entire chip.
Autors: Bucher, M.;Kollipara, R.T.;Su, B.;Gopalakrishnan, L.;Prabhu, K.;Venkatesan, P.K.;Kaviani, K.;Daly, B.;Stonecypher, B.W.F.;Dettloff, W.;Stone, T.;Heaton, F.;Lu, Y.;Madden, C.;Bangalore, S.;Eble, J.C.;Nguyen, N.M.;Luo, L.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 127 - 139
Publisher: IEEE
 
» A 94 GHz, 1.4 dB Insertion Loss Single-Pole Double-Throw Switch Using Reverse-Saturated SiGe HBTs
Abstract:
This work demonstrates two 94 GHz SPDT quarter-wave shunt switches using saturated SiGe HBTs. A new mode of operation, called reverse saturation, using the emitter at the RF output node of the switch, is utilized to take advantage of the higher emitter doping and improved isolation from the substrate. The switches were designed in a 180 nm SiGe BiCMOS technology featuring 90 nm SiGe HBTs (selective emitter shrink) with of 250/300+ GHz. The forward-saturated switch achieves an insertion loss and isolation at 94 GHz of 1.8 dB and 19.3 dB, respectively. The reverse-saturated switch achieves a similar isolation, but reduces the insertion loss to 1.4 dB. This result represents a 30% improvement in insertion loss in comparison to the best CMOS SPDT at 94 GHz.
Autors: Schmid, R.L.;Ulusoy, A.C.;Song, P.;Cressler, J.D.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2014, volume: 24, issue:1, pages: 56 - 58
Publisher: IEEE
 
» A -Band On-Wafer Active Load–Pull System Based on Down-Conversion Techniques
Abstract:
A new -band active load–pull system is presented. It is the first load–pull system to implement a 94 GHz load by means of an active loop exploiting frequency conversion techniques. The active loop configuration demonstrates a number of advantages that overcome the typical limitations of -band passive tuners or conventional active open-loop techniques in a cost-effective way: load reflection coefficients as high as 0.95 in magnitude can be achieved at 94 GHz, thus providing a nearly full coverage of the Smith chart. Possible applications of the setup include technology assessment, large-signal device model verification at sub-terahertz frequencies, and -band monolithic microwave integrated circuit design and characterization. The availability of direct and accurate load–pull measurements at -band should prove an asset in the development of sub-terahertz integrated circuits. First measurements performed on high-performance InP double heterojunction bipolar transistors and GaN high electron-mobility transistors are presented.
Autors: Teppati, V.;Benedickter, H.;Marti, D.;Garelli, M.;Tirelli, S.;Lovblom, R.;Fluckiger, R.;Alexandrova, M.;Ostinelli, O.;Bolognesi, C.R.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2014, volume: 62, issue:1, pages: 148 - 153
Publisher: IEEE
 
» A -Band On-Wafer Active Load–Pull System Based on Down-Conversion Techniques
Abstract:
A new -band active load–pull system is presented. It is the first load–pull system to implement a 94 GHz load by means of an active loop exploiting frequency conversion techniques. The active loop configuration demonstrates a number of advantages that overcome the typical limitations of -band passive tuners or conventional active open-loop techniques in a cost-effective way: load reflection coefficients as high as 0.95 in magnitude can be achieved at 94 GHz, thus providing a nearly full coverage of the Smith chart. Possible applications of the setup include technology assessment, large-signal device model verification at sub-terahertz frequencies, and -band monolithic microwave integrated circuit design and characterization. The availability of direct and accurate load–pull measurements at -band should prove an asset in the development of sub-terahertz integrated circuits. First measurements performed on high-performance InP double heterojunction bipolar transistors and GaN high electron-mobility transistors are presented.
Autors: Teppati, V.;Benedickter, H.;Marti, D.;Garelli, M.;Tirelli, S.;Lovblom, R.;Fluckiger, R.;Alexandrova, M.;Ostinelli, O.;Bolognesi, C.R.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2014, volume: 62, issue:1, pages: 148 - 153
Publisher: IEEE
 
» A Band-Reconfigurable Antenna Based on Directed Dipole
Abstract:
A novel reconfigurable directed dipole antenna operated in a wideband or four narrowband modes is presented. The wideband mode (0.83–2.5 GHz) is based on a folded bowtie-shaped dipole while the four narrowband modes are based on a length-reconfigurable thin dipole. A rectangular cavity is introduced to provide the antenna with well-controlled unidirectional radiation patterns. PIN diodes are used as switches at specific locations for choosing different modes. The design procedure is presented in details which maybe a useful guideline. A fully functional prototype is developed and tested, which exhibits good performance. The unidirectional patterns and frequency selective feature make the antenna potentially suitable for fixed facilities in cognitive radio.
Autors: Ge, L.;Luk, K.-M.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2014, volume: 62, issue:1, pages: 64 - 71
Publisher: IEEE
 
» A Bandgap-Engineered Silicon-Germanium Biristor for Low-Voltage Operation
Abstract:
A bandgap-engineered silicon-germanium biristor for low-voltage operation is investigated through numerical simulations. A reduced latch-up voltage is achieved using germanium as a base, and improved hysteresis is attained by adopting a hetero-bandgap structure which harnesses the silicon-germanium composite at the collector/emitter. The geometric parameters of the base length and base diameter are optimized. The proposed device shows a much lower latch-up voltage than a pure-silicon biristor and larger hysteresis than a pure-germanium biristor. Thus, the proposed bandgap-engineered silicon-germanium biristor is preferable for low-voltage operations.
Autors: Moon, J.-B.;Moon, D.-I.;Choi, Y.-K.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2014, volume: 61, issue:1, pages: 2 - 7
Publisher: IEEE
 
» A Bayesian Model for Crowd Escape Behavior Detection
Abstract:
People naturally escape from a place when unexpected events happen. Based on this observation, efficient detection of crowd escape behavior in surveillance videos is a promising way to perform timely detection of anomalous situations. In this paper, we propose a Bayesian framework for escape detection by directly modeling crowd motion in both the presence and absence of escape events. Specifically, we introduce the concepts of potential destinations and divergent centers to characterize crowd motion in the above two cases respectively, and construct the corresponding class-conditional probability density functions of optical flow. Escape detection is finally performed based on the proposed Bayesian framework. Although only data associated with nonescape behavior are included in the training set, the density functions associated with the case of escape can also be adaptively updated using observed data. In addition, the identified divergent centers indicate possible locations at which the unexpected events occur. The performance of our proposed method is validated in a number of experiments on crowd escape detection in various scenarios.
Autors: Wu, S.;Wong, H.-S.;Yu, Z.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Jan 2014, volume: 24, issue:1, pages: 85 - 98
Publisher: IEEE
 
» A Bi-Phase MEMS Resonator Modulator
Abstract:
The high-electric field piezoelectric properties of a PZT-transduced, two-port, acoustic resonator are utilized to create a binary phase shift modulator. The modulator operates at frequencies below 100 MHz in a length extensional mode. Typical peak modulation voltage levels are 7 V. The design is configured as a subsystem with separate RF and data ports for use in low data rate, battery-powered networks.
Autors: Kaul, R.;Pulskamp, J.S.;Polcawich, R.G.;Bedair, S.S.;Proie, R.M.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2014, volume: 24, issue:1, pages: 41 - 43
Publisher: IEEE
 
» A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection
Abstract:
Design fingerprinting is a means to trace the illegally redistributed intellectual property (IP) by creating a unique IP instance with a different signature for each user. Existing fingerprinting techniques for hardware IP protection focus on lowering the design effort to create a large number of different IP instances without paying much attention on the ease of fingerprint detection upon IP integration. This paper presents the first dynamic fingerprinting technique on sequential circuit IPs to enable both the owner and legal buyers of an IP embedded in a chip to be readily identified in the field. The proposed fingerprint is an oblivious ownership watermark independently endorsed by each user through a blind signature protocol. Thus, the authorship can also be proved through the detection of different user's fingerprints without the need to separately embed an identical IP owner's signature in all fingerprinted instances. The proposed technique is applicable to both application-specific integrated circuit and field-programmable gate array IPs. Our analyses show that the fingerprint is immune to collusion attack and can withstand all perceivable attacks, with a lower probability of removal than state-of-the-art FSM watermarking schemes. The probability of coincidence of a 32-bit fingerprint is in the order of and up to 32-bit fingerprinted instances can be generated for a small design of 100 flip-flops.
Autors: Chang, C.-H.;Zhang, L.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Jan 2014, volume: 33, issue:1, pages: 76 - 89
Publisher: IEEE
 
» A Blind Fine Synchronization Scheme for SC-FDE Systems
Abstract:
This work presents a blind fine synchronization scheme, which estimates and compensates residual carrier-frequency offset (RCFO) and symbol timing offset (STO) , for single-carrier frequency-domain equalization (SC-FDE) systems. Existing fine synchronization schemes for SC-FDE systems rely on time-domain unique words (UW) sequences as reference signals to assure the estimation accuracy, at the cost of decreased system throughput. The proposed technique, named simplified weighted least-square method for single-carrier systems (SWLS-SC), combines the decision feedback structure and SWLS estimator for OFDM systems. Together with specifically derived weighting factors, it has much better estimation accuracy than the well-known linear least-square (LLS) method for SC-FDE systems, and its BER performance can approach that of the ideal synchronization condition. The proposed technique is more effective than existing techniques, in terms of both performance and throughput. Theoretical estimation bounds are also derived to verify the effectiveness of the proposed method.
Autors: Lin, Ying-Tsung;Chen, Sau-Gee;
Appeared in: IEEE Transactions on Communications
Publication date: Jan 2014, volume: 62, issue:1, pages: 293 - 301
Publisher: IEEE
 
» A bottom-up approach to verifiable embedded system information flow security
Abstract:
With the wide deployment of embedded systems and constant increase in their inter-connections, embedded systems tend to be confronted with attacks through security holes that are hard to predict using typical security measures such as access control or data encryption. To eliminate these security holes, embedded security should be accounted for during the design phase from all abstraction levels with effective measures taken to prevent unintended interference between different system components caused by harmful flows of information. This study proposes a bottom-up approach to designing verifiably information flow secure embedded systems. The proposed method enables tight information flow controls by monitoring all flows of information from the level of Boolean gates. It lays a solid foundation to information flow security in the underlying hardware and exposes the ability to prove security properties to all abstraction levels in the entire system stack. With substantial amounts of modifications made to the instruction set architecture, operating system, programming language and input/output architecture, the target system can be designed to be verifiably information flow secure.
Autors: Mu, D.;Hu, W.;Mao, B.;Ma, B.;
Appeared in: IET Information Security
Publication date: Jan 2014, volume: 8, issue:1, pages: 12 - 17
Publisher: IEEE
 
» A Broad-Band Conductively-Loaded Slot Antenna for Pulse Radiation
Abstract:
A slot antenna with a conductive loading profile, which is complementary to the dipole antenna with the Wu-King resistive profile, is derived based on a transmission line model. The drive point impedance of the nonreflecting slot antenna is determined using Babinet's principle. The voltage distribution along the slot arms is shown to be an outward traveling wave with no internal reflection. In addition, the radiated electric field pattern and the efficiency of the nonreflecting slot antenna are discussed. The complementary nature between the Wu-King dipole and nonreflecting slot is numerically verified. The pulse radiation and reception characteristics of the antenna are then demonstrated both numerically and experimentally.
Autors: Kang, W.;Kim, K.;Kim, W.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2014, volume: 62, issue:1, pages: 33 - 39
Publisher: IEEE
 
» A Buoyant Tethered Sphere for Marine Current Estimation
Abstract:
The high cost of acoustic Doppler ocean current meters means few are deployed in marine research studies. To address this problem, we have developed a low-cost robust current velocimeter based on the drag–tilt principle. The instrument tilts in response to current flow, for which the angle and direction of tilt are related to the water velocity. Static analytic approximation shows a sigmoid-type tilt response to increasing current speed. We detail a calibration method that models the relationship using a Gompertz curve. Calibration and field tests conducted near Magnetic Island, Australia, show a speed accuracy of 0.05 m/s for current speeds less than 0.6 m/s, and direction accuracy better than 15 for current speeds greater than 0.15 m/s. This instrument should be especially useful for research projects where numerous or spatially dense measurements of ocean currents are required.
Autors: Marchant, R.;Stevens, T.;Choukroun, S.;Coombes, G.;Santarossa, M.;Whinney, J.;Ridd, P.;
Appeared in: IEEE Journal of Oceanic Engineering
Publication date: Jan 2014, volume: 39, issue:1, pages: 2 - 9
Publisher: IEEE
 
» A Changing Map: Four Decades of Service Restoration at Alabama Power
Abstract:
Restoring service to customers has always been a top priority at the Alabama Power Company during my 45 years there. Although the task is the same, the methods and technologies that can be brought to bear on it have changed and improved dramatically. Technology has helped the company improve its response to system disturbances. Automation technology deployed in the distribution control room, in distribution substations, and at discrete sites along the distribution feeder provides system intelligence regarding the state and condition of the electric distribution system. Automation technology also facilitates the presentation of supervisory control and data acquisition (SCADA) telemetry to the distribution operator. Meanwhile, advances in desktop computing workstations permit the geographical display of distribution circuits in a wide-area view, which improves the visibility of the distribution system for the operator. The big-picture or wide-area view that was once displayed on the paper map board is now presented in the control room on its desktop workstations. Today, application integration is providing the next round of technology improvement in the distribution control room. Advanced applications within an integrated platform are providing techniques to improve the efficiency and reliability of the distribution system. Together, these advanced applications improve service restoration. This article describes the past, present, and future of service restoration technology at Alabama Power.
Autors: Clark, G.;
Appeared in: IEEE Power and Energy Magazine
Publication date: Jan 2014, volume: 12, issue:1, pages: 64 - 69
Publisher: IEEE
 
» A Closed-Form Model for the IEEE 802.3az Network and Power Performance
Abstract:
We propose an analytical model able to accurately estimate both power consumption and network performance indexes of Energy Efficient Ethernet (EEE) links working at the three available speeds under various traffic load patterns and packet size distributions. The model is sufficiently flexible and accurate to consider different traffic parameters; among others, the packet size distribution, the average burst inter-arrival rate, the burst size distribution, etc. With relatively low complexity, since it addresses stationary queue behavior, the analysis allows obtaining the average energy consumption of the link and, unlike previous works, the mean latency time experienced by incoming packets in closed form, without any upper or lower bound approximations. This aspect makes the model suitable to be adopted in optimization frameworks for network design and control purposes. The numerical results of the model are validated against measurements on a real test bench.
Autors: Bolla, Raffaele;Bruschi, Roberto;Carrega, Alessandro;Davoli, Franco;Lago, Paolo;
Appeared in: IEEE Journal on Selected Areas in Communications
Publication date: Jan 2014, volume: 32, issue:1, pages: 16 - 27
Publisher: IEEE
 
» A Compact Optoelectronic Oscillator Based on an Electroabsorption Modulated Laser
Abstract:
A novel method to miniaturize the optoelectronic oscillator (OEO) is proposed and demonstrated by replacing the laser source, intensity modulator, and photodetector with an electroabsorption modulated laser (EML), because the electroabsorption modulator (EAM) in the EML can perform simultaneously photodetection and intensity modulation. A 9.945-GHz microwave signal with a phase noise of at 10 kHz offset is experimentally generated. The dependence of the phase noise on the EAM bias voltage is investigated. The EML-based OEO features low cost, simple structure, and potentially high operational frequency, which can find applications in future communications, radars, navigation, and satellite systems.
Autors: Zhou, P.;Pan, S.;Zhu, D.;Guo, R.;Zhang, F.;Zhao, Y.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2014, volume: 26, issue:1, pages: 86 - 88
Publisher: IEEE
 
» A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration
Abstract:
This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of –243 dB. It also consumes an area of only 0.022 mm² resulting in the best performance-area trade-off system presented up-to-date.
Autors: Musa, A.;Deng, W.;Siriburanon, T.;Miyahara, M.;Okada, K.;Matsuzawa, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 50 - 60
Publisher: IEEE
 
» A Comparative Study of Tunneling FETs Based on Graphene and GNR Heterostructures
Abstract:
In this paper, for the first time device characteristics of field-effect tunneling transistors based on vertical graphene-hBN heterostructure (VTGFET) and vertical graphene nanoribbon (GNR)-hBN heterostructure (VTGNRFET) are theoretically investigated and compared. An atomistic simulation based on the nonequilibrium Green's function (NEGF) formalism is employed. The results indicate that due to the presence of an energy gap in GNRs, the ratio of VTGNRFET can be much larger than that of VTGFET, which renders VTGNRFETs as promising candidates for future electronic applications. Furthermore, it can be inferred from the results that due to smaller density of states and as a result smaller quantum capacitance of GNRs in comparison with that of graphene, better switching and frequency response can be achieved for VTGNRFETs.
Autors: Ghobadi, N.;Pourfath, M.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2014, volume: 61, issue:1, pages: 186 - 192
Publisher: IEEE
 
» A Computational Study on the Electronic Transport Properties of Ultranarrow Disordered Zigzag Graphene Nanoribbons
Abstract:
In this paper, the effect of structural nonidealities on the electronic transport properties of ultranarrow zigzag graphene nanoribbons (ZGNRs) is systemically investigated for the first time, employing the nonorthogonal third nearest neighbor mean-field Hubbard model along with the nonequilibrium Green's function formalism. We have evaluated the influence of line-edge roughness, single atom vacancies, and substrate-induced potential fluctuations on the transport gap, ON-and OFF-state conductances, and the ON/OFF conductance ratio of 12-nm-length ultranarrow ZGNRs. The results reveal that while even moderate amounts of edge roughness lead to a nonuniform suppression of the transmission probability and increase the transport gap, the presence of single atom vacancies tends to decrease the induced transport gap. Furthermore, it is shown that the transport properties of ZGNRs are more robust against potential fluctuations compared with their armchair counterparts.
Autors: Djavid, N.;Khaliji, K.;Tabatabaei, S.M.;Pourfath, M.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2014, volume: 61, issue:1, pages: 23 - 29
Publisher: IEEE
 
» A Concurrent Tri-Band Distributed Power Amplifier With Negative-Resistance Active Notch Using SiGe BiCMOS Process
Abstract:
A new tri-band power amplifier (PA) on a 0.18- m SiGe BiCMOS process, operating concurrently in -, -, and -band, is presented. The concurrent tri-band PA design is based on the distributed amplifier structure with capacitive coupling to enable large device size, while maintaining wide bandwidth, gain cells with the enhanced-gain peaking inductor, and negative-resistance active notch filters for improved tri-band gain response. The concurrent tri-band PA exhibits measured small-signal gain around 15.4, 14.7, and 12.3 dB in the low band (10–19 GHz), midband (23–29 GHz), and high band (33–40 GHz), respectively. In the single-band mode, the PA has maximum output powers of 15, 13.3, and 13.8 dBm at 15, 25, and 35 GHz, respectively. When the PA is operated in dual-band mode, it has maximum output powers of 11.4/8.2 dBm at 15/25 GHz, 13.3/3 dBm at 15/35 GHz, and 8.7/6.7 dBm at 25/35 GHz. In the tri-band mode, it exhibits 8.8/5.4/3.8-dBm maximum output power at 15/25/35 GHz. The concurrent tri-band PA exhibits relatively flat responses in gain and output power across its three frequency bands and good matching up to 40 GHz.
Autors: Kim, K.;Nguyen, C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2014, volume: 62, issue:1, pages: 125 - 136
Publisher: IEEE
 
» A Concurrent Tri-Band Distributed Power Amplifier With Negative-Resistance Active Notch Using SiGe BiCMOS Process
Abstract:
A new tri-band power amplifier (PA) on a 0.18- m SiGe BiCMOS process, operating concurrently in -, -, and -band, is presented. The concurrent tri-band PA design is based on the distributed amplifier structure with capacitive coupling to enable large device size, while maintaining wide bandwidth, gain cells with the enhanced-gain peaking inductor, and negative-resistance active notch filters for improved tri-band gain response. The concurrent tri-band PA exhibits measured small-signal gain around 15.4, 14.7, and 12.3 dB in the low band (10–19 GHz), midband (23–29 GHz), and high band (33–40 GHz), respectively. In the single-band mode, the PA has maximum output powers of 15, 13.3, and 13.8 dBm at 15, 25, and 35 GHz, respectively. When the PA is operated in dual-band mode, it has maximum output powers of 11.4/8.2 dBm at 15/25 GHz, 13.3/3 dBm at 15/35 GHz, and 8.7/6.7 dBm at 25/35 GHz. In the tri-band mode, it exhibits 8.8/5.4/3.8-dBm maximum output power at 15/25/35 GHz. The concurrent tri-band PA exhibits relatively flat responses in gain and output power across its three frequency bands and good matching up to 40 GHz.
Autors: Kim, K.;Nguyen, C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2014, volume: 62, issue:1, pages: 125 - 136
Publisher: IEEE
 
» A Content-Adaptive Distortion–Quantization Model for H.264/AVC and its Applications
Abstract:
Accurately estimating the resultant quality or distortion associated with quantization parameter is very helpful to video encoding. In this research, a content-adaptive distortion–quantization model for H.264/AVC is proposed to predict the distortion level, which is defined as the difference between the original video frame and the decoded one in the sum of squared errors. The proposed model has only one adjustable parameter related to the macroblock content and provides a mapping between and the corresponding distortion before the exact encoding process. Given a targeted frame quality measured in peak signal to noise ratio (PSNR), this model can help to assign a suitable value to each frame. Two applications are then presented, i.e., the single-pass constant frame PSNR coding and the two-pass coding with the additional bitrate or storage constraint, both of which may facilitate such applications of video archiving and editing. The experimental results show that the targeted PSNR of each decoded frame can be achieved effectively by the proposed mechanism.
Autors: Wu, C.-Y.;Su, P.-C.;
Appeared in: IEEE Transactions on Circuits and Systems for Video Technology
Publication date: Jan 2014, volume: 24, issue:1, pages: 113 - 126
Publisher: IEEE
 
» A Contention-Free Parallel Access by Butterfly Networks for Turbo Interleavers
Abstract:
A theoretical foundation for any turbo interleaver to be a contention-free interleaver to access data in parallel by a butterfly network is presented. A contention-free parallel access of multiple memories in parallel plays a crucial role for implementing high speed turbo decoders for high data rate applications. The presented theoretical analysis shows that a butterfly network has a sufficiently rich permutation structure to be a routing network between parallel decoder units and multiple memories. Thus turbo code design is independent of the designing of a contention-free parallel access by butterfly networks. In particular, a turbo interleaver needs not to provide a built-in contention-free parallel access for any parallel access by butterfly networks. We demonstrate how to apply this theory to turbo interleavers widely used in commercial telecommunication standards.
Autors: Nieminen, E.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2014, volume: 60, issue:1, pages: 237 - 251
Publisher: IEEE
 
» A Control-Based Approach to Accurate Nanoindentation Quantification in Broadband Nanomechanical Measurement Using Scanning Probe Microscope
Abstract:
This paper presents a control-based approach to accurately quantify the indentation in broadband nanomechanical property measurements using scanning probe microscope (SPM). Accurate indentation measurement is essential to probe-based material property characterization as the force exerted and the indentation generated are the two most important physical variables measured in the process. Large measurement errors, however, occur when the measurement frequency range becomes large (i.e., broadband). Such errors result from the inability of the conventional method to account for the difference between the SPM -axis piezo actuator displacement and the vertical displacement of the cantilever at its fixed end, and the lateral-vertical coupling-caused cantilever motion when the measurement frequency range increases. A control-based approach is presented to address these limits of the conventional method. The proposed approach is demonstrated through experiments to measure the viscoelastic properties of a Polydimethylsiloxane (PDMS) sample over a broad-frequency range.
Autors: Ren, J.;Zou, Q.;
Appeared in: IEEE Transactions on Nanotechnology
Publication date: Jan 2014, volume: 13, issue:1, pages: 46 - 54
Publisher: IEEE
 
» A cylindrical converging shock tube for shock-interface studies
Abstract:
A shock tube facility for generating a cylindrical converging shock wave is developed in this work. Based on the shock dynamics theory, a specific wall profile is designed for the test section of the shock tube to transfer a planar shock into a cylindrical one. The shock front in the converging part obtained from experiment presents a perfect circular shape, which proves the feasibility and reliability of the method. The time variations of the shock strength obtained from numerical simulation, experiment, and theoretical estimation show the desired converging effect in the shock tube test section. Particular emphasis is then placed on the problem of shock-interface interaction induced by cylindrical converging shock waves. For this purpose, membrane-less gas cylinder is adopted to form the interface between two different fluids while the laser sheet technique to visualize the flow field. The result shows that it is convenient to perform such experiments in this facility.
Autors: Luo, Xisheng;Si, Ting;Yang, Jiming;Zhai, Zhigang;
Appeared in: Review of Scientific Instruments
Publication date: Jan 2014, volume: 85, issue:1, pages: 015107 - 015107-6
Publisher: IEEE
 
» A Detailed Failure Analysis Examination of the Effect of Thermal Cycling on Cu TSV Reliability
Abstract:
In this paper, the reliability of through-silicon via (TSV) daisy chains under thermal cycling conditions was examined. The electrical resistance of TSV daisy chains was found to increase with the number of thermal cycles, due to thermally induced damage leading to the formation and growth of defects. The contributions of each identified damage type to the change in the electrical resistance of the TSV chain were evaluated by electrical modeling. Thermo-mechanical modeling showed a good correlation between the observed damage locations and the simulated stress-concentration regions of the TSV.
Autors: Okoro, C.;Lau, J.W.;Golshany, F.;Hummler, K.;Obeng, Y.S.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2014, volume: 61, issue:1, pages: 15 - 22
Publisher: IEEE
 
» A Deterministic Polynomial-Time Protocol for Synchronizing From Deletions
Abstract:
In this paper, we consider a synchronization problem between nodes and that are connected through a two-way communication channel. Node contains a binary file of length and node contains a binary file that is generated by randomly deleting bits from , by a small deletion rate . The location of deleted bits is not known to either node or node . We offer a deterministic, polynomial-time synchronization scheme between nodes and that needs a total of transmitted bits and reconstructs at node with probability of error that is exponentially low in the size of . Orderwise, the rate of our scheme matches the optimal rate for this channel.
Autors: Tabatabaei Yazdi, S.M.S.;Dolecek, L.;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2014, volume: 60, issue:1, pages: 397 - 409
Publisher: IEEE
 
» A diamond-based scanning probe spin sensor operating at low temperature in ultra-high vacuum
Abstract:
We present the design and performance of an ultra-high vacuum (UHV) low temperature scanning probe microscope employing the nitrogen-vacancy color center in diamond as an ultrasensitive magnetic field sensor. Using this center as an atomic-size scanning probe has enabled imaging of nanoscale magnetic fields and single spins under ambient conditions. In this article we describe an experimental setup to operate this sensor in a cryogenic UHV environment. This will extend the applicability to a variety of molecular systems due to the enhanced target spin lifetimes at low temperature and the controlled sample preparation under UHV conditions. The instrument combines a tuning-fork based atomic force microscope (AFM) with a high numeric aperture confocal microscope and the facilities for application of radio-frequency (RF) fields for spin manipulation. We verify a sample temperature of <50 K even for strong laser and RF excitation and demonstrate magnetic resonance imaging with a magnetic AFM tip.
Autors: Schaefer-Nolte, E.;Reinhard, F.;Ternes, M.;Wrachtrup, J.;Kern, K.;
Appeared in: Review of Scientific Instruments
Publication date: Jan 2014, volume: 85, issue:1, pages: 013701 - 013701-8
Publisher: IEEE
 
» A Dual Circularly Polarized Waveguide Antenna With Bidirectional Radiations of the Same Sense
Abstract:
A dual circularly polarized waveguide antenna with bidirectional radiations of the same sense is proposed in this communication. Bidirectional circular polarization (Bi-CP) of the same sense was obtained by two identical rectangular metal slices installed on one lateral side of the waveguide with an intersection angle of 45 . These two metal slices were horizontally perpendicular to each other and vertically spaced by a quarter guided wavelength. A rat-race coupler was employed to excite the two metal slices with the same amplitude, but with a 0 or 180 phase difference depending on the selection of two inputs. One sense of Bi-CP was realized when the two metal slices were fed in phase and the opposite sense of Bi-CP could be obtained when they were fed out of phase. A prototype for 2.4-GHz WLAN application was tested to verify our design. The measured common bandwidth for 10-dB return loss and 3-dB axial ratio at the two feed ports was 230 MHz (9.6%, 2.29–2.52 GHz) and 210 MHz (8.6%, 2.35–2.56 GHz), respectively. The measured isolation between the two feed ports was better than 30 dB over the whole operating band.
Autors: Zhao, Y.;Zhang, Z.;Wei, K.;Feng, Z.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2014, volume: 62, issue:1, pages: 480 - 484
Publisher: IEEE
 
» A Dual-Frequency Ultralow-Power Efficient 0.5-g Rectenna
Abstract:
The second annual Student Wireless Energy Harvesting (WEH) Design Competition was held during the 2013 IEEE Microwave Theory and Techniques Society (MTT_S) International Microwave Symposium (IMS2013) in Seattle, Washington, United States. This year, the competition parameters were modified from those of last year [1], and a new figure of merit (FoM) was established. The overall goal of the competition was to demonstrate low-mass hardware that can efficiently receive and rectify extremely low-incident power densities at two frequencies, with a fixed dc load. As the radio-frequency (RF) environment gets more saturated with spurious power, designs from this competition will become a feasible way to energize ultralow-powered or low-duty-cycle hard-to-reach sensors. Concepts such as Internet-of-Things, in which small ubiquitous devices and sensors will log data and send it to the cloud, could benefit from wireless energy harvesters. These sensors will not have convenient ways to stay powered unless power harvesting circuits are used for the sensor hardware.
Autors: Scheeler, R.;Korhummel, S.;Popovic, Z.;
Appeared in: IEEE Microwave Magazine
Publication date: Jan 2014, volume: 15, issue:1, pages: 109 - 114
Publisher: IEEE
 
» A Dual-Material Gate Junctionless Transistor With High- Spacer for Enhanced Analog Performance
Abstract:
In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT presents superior transconductance , early voltage , and intrinsic gain compared with SMG DGJLT. The values are further improved for DMG-SP DGJLT, because high- spacer enhances the fringing electric fields through the spacer.
Autors: Baruah, R.K.;Paily, R.P.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2014, volume: 61, issue:1, pages: 123 - 128
Publisher: IEEE
 
» A Dynamic Flow Control Algorithm for LTE-Advanced Relay Networks
Abstract:
Relay technology is a candidate for extending the coverage or enhancing the throughput of next-generation cellular systems. In the downlink of a Long Term Evolution Advanced (LTE-A) relay network, a relay node (RN) normally reserves a small buffer for each user equipment (UE) such that the RN can minimize the number of forwarding packets during UE handover. The small buffer and a mismatch of the data rates between the access link and the relay link may result in buffer overflow for some UE and in buffer underflow for the other UE served by the same RN. This paper presents a simple analytical model to illustrate the buffer-overflow and buffer-underflow problems in the downlink of an LTE-A relay network. A dynamic flow control algorithm (DFCA) is then proposed to minimize the buffer-overflow and buffer-underflow probabilities. The proposed DFCA is designed to minimize the feedback signaling overhead by dynamically adjusting the window size and the feedback frequency based on the relevant measures obtained from individual UE. Simulation results showed that most of the flow control schemes can effectively prevent the buffer-overflow problem. However, only DFCA can provide lower buffer-underflow probabilities and higher throughput for most UEs versus what the other flow control schemes can do.
Autors: Lin, P.-C.;Cheng, R.-G.;Chang, Y.-J.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Jan 2014, volume: 63, issue:1, pages: 334 - 343
Publisher: IEEE
 
» A Dynamic Programming Approach to Estimate the Capacity Value of Energy Storage
Abstract:
We present a method to estimate the capacity value of storage. Our method uses a dynamic program to model the effect of power system outages on the operation and state of charge of storage in subsequent periods. We combine the optimized dispatch from the dynamic program with estimated system loss of load probabilities to compute a probability distribution for the state of charge of storage in each period. This probability distribution can be used as a forced outage rate for storage in standard reliability-based capacity value estimation methods. Our proposed method has the advantage over existing approximations that it explicitly captures the effect of system shortage events on the state of charge of storage in subsequent periods. We also use a numerical case study, based on five utility systems in the U.S., to demonstrate our technique and compare it to existing approximation methods.
Autors: Sioshansi, R.;Madaeni, S.H.;Denholm, P.;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jan 2014, volume: 29, issue:1, pages: 395 - 403
Publisher: IEEE
 
» A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching
Abstract:
This paper presents a dynamic timing control technique to prevent timing errors in a pipeline under variations. Timing errors in a pipeline are prevented by borrowing time from the following stage and resolving the borrowed time by stretching the next clock cycle. This paper analyzes the operating principles of the proposed technique; presents the design of the required circuit components; and demonstrates its operation through fabrication and measurement of a prototype test-chip designed in an 180 nm CMOS process. The measurement results demonstrate that a system employing the dynamic timing control technique can operate in a wider frequency and voltage range.
Autors: Chae, K.;Mukhopadhyay, S.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2014, volume: 61, issue:1, pages: 74 - 83
Publisher: IEEE
 
» A Fast Screening Measurement for TDDB Assessment of Ultra-Thick Inter-Metal Dielectrics
Abstract:
Semiconductor manufacturing economics necessitate the development of novel and innovative techniques that can replace the traditional time consuming reliability methods, i.e., the constant voltage stress time-dependent dielectric breakdown (CVS-TDDB) tests. We show that positive charge trapping is a dominant process when ultra-thick oxides are stressed through the ramped voltage test. Exploiting the physics behind positive charge generation/trapping at high electric fields, a fast measurement technique is proposed that can be used to effectively distinguish the ultra-thick oxides' intrinsic quality at low electric fields. It will be demonstrated, based on experimental data, that our proposed technique can be a suitable replacement for the CVS-TDDB as a quality screening tool.
Autors: Elhami Khorasani, A.;Griswold, M.;Alford, T.L.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2014, volume: 35, issue:1, pages: 117 - 119
Publisher: IEEE
 
» A Fast Screening Measurement for TDDB Assessment of Ultra-Thick Inter-Metal Dielectrics
Abstract:
Semiconductor manufacturing economics necessitate the development of novel and innovative techniques that can replace the traditional time consuming reliability methods, i.e., the constant voltage stress time-dependent dielectric breakdown (CVS-TDDB) tests. We show that positive charge trapping is a dominant process when ultra-thick oxides are stressed through the ramped voltage test. Exploiting the physics behind positive charge generation/trapping at high electric fields, a fast measurement technique is proposed that can be used to effectively distinguish the ultra-thick oxides' intrinsic quality at low electric fields. It will be demonstrated, based on experimental data, that our proposed technique can be a suitable replacement for the CVS-TDDB as a quality screening tool.
Autors: Elhami Khorasani, A.;Griswold, M.;Alford, T.L.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2014, volume: 35, issue:1, pages: 117 - 119
Publisher: IEEE
 
» A fast slewing cryostat for small sample in vacuo electrical/optical testing in the range 30 K–500 K
Abstract:
A cold finger vacuum cryostat is described in which a sapphire heat conducting element is used to achieve very fast slew rates for a small sample stage over a wide temperature range with optimal matching to a closed cycle helium refrigerator head. When the set temperature is reached it is maintained with very high stability (±5 mK). The target applications are associated with semiconductor electrical material characterisation measurements which require temperature scanning, e.g., thermally stimulated current, deep level transient spectroscopy, and applications which require annealing followed by rapid transition to lower temperature for measurement.
Autors: Hawkins, Ian D;
Appeared in: Review of Scientific Instruments
Publication date: Jan 2014, volume: 85, issue:1, pages: 013903 - 013903-5
Publisher: IEEE
 
» A Flexible Method for Multi-Material Decomposition of Dual-Energy CT Images
Abstract:
Pub DtlThe ability of dual-energy computed-tomographic (CT) systems to determine the concentration of constituent materials in a mixture, known as material decomposition, is the basis for many of dual-energy CT's clinical applications. However, the complex composition of tissues and organs in the human body poses a challenge for many material decomposition methods, which assume the presence of only two, or at most three, materials in the mixture. We developed a flexible, model-based method that extends dual-energy CT's core material decomposition capability to handle more complex situations, in which it is necessary to disambiguate among and quantify the concentration of a larger number of materials. The proposed method, named multi-material decomposition (MMD), was used to develop two image analysis algorithms. The first was virtual unenhancement (VUE), which digitally removes the effect of contrast agents from contrast-enhanced dual-energy CT exams. VUE has the ability to reduce patient dose and improve clinical workflow, and can be used in a number of clinical applications such as CT urography and CT angiography. The second algorithm developed was liver-fat quantification (LFQ), which accurately quantifies the fat concentration in the liver from dual-energy CT exams. LFQ can form the basis of a clinical application targeting the diagnosis and treatment of fatty liver disease. Using image data collected from a cohort consisting of 50 patients and from phantoms, the application of MMD to VUE and LFQ yielded quantitatively accurate results when compared against gold standards. Furthermore, consistent results were obtained across all phases of imaging (contrast-free and contrast-enhanced). This is of particular importance since most clinical protocols for abdominal imaging with CT call for multi-phase imaging. We conclude that MMD can successfully form the basis of a number of dual-energy CT image analysis algorithms, and has the potential to improve the clini- al utility of dual-energy CT in disease management.
Autors: Mendonca, P.R.S.;Lamb, P.;Sahani, D.V.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Jan 2014, volume: 33, issue:1, pages: 99 - 116
Publisher: IEEE
 
» A Framework for Compositional Synthesis of Modular Nonblocking Supervisors
Abstract:
This paper describes a framework for compositional supervisor synthesis, which is applicable to all discrete event systems modeled as a set of deterministic automata. Compositional synthesis exploits the modular structure of the input model, and therefore works best for models consisting of a large number of small automata. The state-space explosion is mitigated by the use of abstraction to simplify individual components, and the property of synthesis equivalence guarantees that the final synthesis result is the same as it would have been for the non-abstracted model. The paper describes synthesis equivalent abstractions and shows their use in an algorithm to efficiently compute supervisors. The algorithm has been implemented in the DES software tool Supremica and successfully computes nonblocking modular supervisors, even for systems with more than reachable states, in less than 30 seconds.
Autors: Mohajerani, S.;Malik, R.;Fabian, M.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Jan 2014, volume: 59, issue:1, pages: 150 - 162
Publisher: IEEE
 
» A Fully Differential Charge-Balanced Accelerometer for Electronic Stability Control
Abstract:
An accelerometer for electronic stability control utilizes a two-mass mechanical sensor element to implement a fully-differential signal path, achieving robustness against electromagnetic interference (EMI) without the need for external shielding in the package. The EMI rejection is augmented further with a pseudo-random chopping scheme, which spreads the interference over a wide bandwidth, reducing its in-band portion to the level of the noise floor. The chopping function maintains zero-mean voltage waveforms across the sensor electrodes, which is also beneficial for the long-term offset stability of the device. A charge-balanced capacitance-to-voltage converter provides linear transduction for displacements of the proof-mass up to 70% of the gap and minimizes the residual electrostatic forces. A dual-axis design occupies 1.1 mm in 0.18- m CMOS and consumes 820 A from an internally regulated 1.9-V supply. The system achieves 380 noise floor and 84-dB dynamic range. The offset variation in the automotive temperature range of 40 to 140 C has a range of 11 mg.
Autors: Petkov, V.P.;Balachandran, G.K.;Beintner, J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 262 - 270
Publisher: IEEE
 
» A Fully Digital 8 16 SiPM Array for PET Applications With Per-Pixel TDCs and Real-Time Energy Output
Abstract:
An 8 16 pixel array based on CMOS small-area silicon photomultipliers (mini-SiPMs) detectors for PET applications is reported. Each pixel is 570 610 m in size and contains four digital mini-SiPMs, for a total of 720 SPADs, resulting in a full chip fill-factor of 35.7%. For each gamma detection, the pixel provides the total detected energy and a timestamp, obtained through two 7-b counters and two 12-b 64-ps TDCs. An adder tree overlaid on top of the pixel array sums the sensor total counts at up to 100 Msamples/s, which are then used for detecting the asynchronous gamma events on-chip, while also being output in real-time. Characterization of gamma detection performance with an 3 3 5 mm LYSO scintillator at 20 C is reported, showing a 511-keV gamma energy resolution of 10.9% and a coincidence timing resolution of 399 ps.
Autors: Braga, L.H.C.;Gasparini, L.;Grant, L.;Henderson, R.K.;Massari, N.;Perenzoni, M.;Stoppa, D.;Walker, R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 301 - 314
Publisher: IEEE
 
» A Fully Digital 8 16 SiPM Array for PET Applications With Per-Pixel TDCs and Real-Time Energy Output
Abstract:
An 8 16 pixel array based on CMOS small-area silicon photomultipliers (mini-SiPMs) detectors for PET applications is reported. Each pixel is 570 610 m in size and contains four digital mini-SiPMs, for a total of 720 SPADs, resulting in a full chip fill-factor of 35.7%. For each gamma detection, the pixel provides the total detected energy and a timestamp, obtained through two 7-b counters and two 12-b 64-ps TDCs. An adder tree overlaid on top of the pixel array sums the sensor total counts at up to 100 Msamples/s, which are then used for detecting the asynchronous gamma events on-chip, while also being output in real-time. Characterization of gamma detection performance with an 3 3 5 mm LYSO scintillator at 20 C is reported, showing a 511-keV gamma energy resolution of 10.9% and a coincidence timing resolution of 399 ps.
Autors: Braga, L.H.C.;Gasparini, L.;Grant, L.;Henderson, R.K.;Massari, N.;Perenzoni, M.;Stoppa, D.;Walker, R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2014, volume: 49, issue:1, pages: 301 - 314
Publisher: IEEE
 

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