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Electrical and Electronics Engineering publications abstract of: 01-2012 sorted by title, page: 0
» “Trends” Expert Overview Sessions Revived at ICASSP 2011: Part 3 [In the Spotlight]
Abstract:
This is the third in a series of three columns summarizing the “Trends” expert sessions organized by the Signal Processing Society Technical Committees during ICASSP 2011 in Prague, Czech Republic. Readers have an opportunity to access these Trends session summaries authored by the Technical Committees.
Autors: van der Veen, A.-J.;Principe, J.C.;
Appeared in: IEEE Signal Processing Magazine
Publication date: Jan 2012, volume: 29, issue:1, pages: 184 - 184
Publisher: IEEE
 
» (Si)5-2y(AlP)y alloys assembled on Si(100) from Al-P-Si3 building units
Abstract:
An original class of IV/III-V hybrid (Si)5-2y(AlP)y/Si(100) semiconductors have been produced via tailored interactions of molecular P(SiH3)3 and atomic Al yielding tetrahedral “Al-P-Si3” building blocks. Extensive structural, optical, and vibrational characterization corroborates that these units condense to assemble single-phase, monocrystalline alloys containing 60%-90% Si (y = 0.3-1.0) as nearly defect-free layers lattice-matched to Si. Spectroscopic ellipsometry and density functional theory band structure calculations indicate mild compositional bowing of the band gaps, suggesting that the tuning needed for optoelectronic applications should be feasible.
Autors: Watkins, T.;Jiang, L.;Xu, C.;Chizmeshya, A. V. G.;Smith, D. J.;Menendez, J.;Kouvetakis, J.;
Appeared in: Applied Physics Letters
Publication date: Jan 2012, volume: 100, issue:2, pages: 022101 - 022101-4
Publisher: IEEE
 
» 20 Years Past Weiser: What's Next?
Abstract:
Over the past two decades, the pervasive computing field evolved through roughly three generations of research challenges. Now, the scientific community, in a new research agenda book, articulates next-generation research directions as the quest to attain Weiser's vision continues.
Autors: Ferscha, Alois;
Appeared in: IEEE Pervasive Computing
Publication date: Jan 2012, volume: 11, issue:1, pages: 52 - 61
Publisher: IEEE
 
» 2011 Reviewer appreciation
Abstract:
[No author name available]
Autors: Source: Advanced Powder Technology, Volume 23, Issue 1, January 2012, Pages 129-131
Appeared in: Advanced Powder Technology
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» 2012 BizTech Trends and Guidance
Abstract:
This list of the "2011 top 10 biztech trends" will provide guidance to business and technology executives to help them develop a high-level, long-term approach for exploiting opportunities to help the business grow.
Autors: Costello, Tom;
Appeared in: IT Professional
Publication date: Jan 2012, volume: 14, issue:1, pages: 64 - 63
Publisher: IEEE
 
» 3-D Formal Resolution of Maxwell Equations for the Computation of the No-Load Flux in an Axial Flux Permanent-Magnet Synchronous Machine
Abstract:
This paper presents a 3-D analytical model of an axial flux permanent-magnet synchronous machine, based on formal resolution of Maxwell equations. This method requires much less computation time than conventional 3-D finite elements, and is therefore suitable for optimization purposes. In a first part, the mathematical procedure used to compute the machine no-load flux is described in detail. This method is 3-D, and then takes into account the radial edge effects of the machine, as well as the curvature effects by a resolution in cylindrical coordinates. Moreover, the originality of this method lies in the fact that it is totally analytical. The obtained results are verified using 3-D finite elements, and compared with simpler analytical models of axial flux machines, taken from the literature. This work puts in evidence the advantages of the proposed model. In particular, it is shown that the radial edge effects are important for a correct estimation of the no-load flux. On the contrary, the curvature effects are a second-order phenomenon.
Autors: de la Barriere, O.;Hlioui, S.;Ben Ahmed, H.;Gabsi, M.;LoBue, M.;
Appeared in: IEEE Transactions on Magnetics
Publication date: Jan 2012, volume: 48, issue:1, pages: 128 - 136
Publisher: IEEE
 
» 3-D Vector Electromagnetic Scattering From Arbitrary Random Rough Surfaces Using Stabilized Extended Boundary Condition Method for Remote Sensing of Soil Moisture
Abstract:
We develop the stabilized extended boundary condition method (SEBCM) based on the classical EBCM to solve the 3-D vector electromagnetic scattering problem from arbitrary random rough surfaces. Similar to the classical EBCM, we expand the fields in terms of Floquet modes and match the extended boundary conditions at test surfaces away from the actual rough surface to retrieve the surface currents and therefore the scattered fields. However, to solve long-standing stability problems of the classical EBCM, we introduce a z-coordinate transformation to restrict and control the test surface locations explicitly. We also introduce the concepts of moderated test surface locations and balanced k-charts for further stabilization and optimization of the solutions. The computational efficiency is optimized by judicious submatrix decomposition. The resulting bistatic scattering cross sections are validated by comparing with analytical and numerical solutions. Specifically, the solutions are compared with those from the small perturbation method and small-slope approximation within their validity region, and with those from the method of moments outside the validity domains of analytical solutions. It is shown that SEBCM gives accurate, numerically efficient, full-wave solutions over a large range of surface roughnesses and medium losses, which are far beyond the validity range of analytical methods. These properties are expected to make SEBCM a competitive forward solver for soil moisture retrieval from radar measurements.
Autors: Duan, X.;Moghaddam, M.;
Appeared in: IEEE Transactions on Geoscience and Remote Sensing
Publication date: Jan 2012, volume: 50, issue:1, pages: 87 - 103
Publisher: IEEE
 
» 3-Time-Slot Group-Decodable STBC with Full Rate and Full Diversity
Abstract:
In this paper, we propose a generic method to construct group-decodable space-time block codes (STBC) with arbitrary code dimensions, including odd time slot. Based on the proposed code construction method, 3-time-slot STBC for two transmit antennas with full or even higher code rate can be obtained. The full-rate 3-time-slot STBC obtained can achieve full diversity and symbol-wise decoding complexity. It serves as a solution to the orphan-symbol (3-time-slot) transmit diversity issue raised in 3rd Generation Partnership Project (3GPP) standards.
Autors: Ren, Tian Peng;Yuen, Chau;Guan, Yong Liang;Wang, Kun Hua;
Appeared in: IEEE Communications Letters
Publication date: Jan 2012, volume: 16, issue:1, pages: 86 - 88
Publisher: IEEE
 
» 3.2-9.7 GHz ultra-wideband low-noise amplifier with excellent stop-band rejection
Abstract:
A low-power 3.2-9.7 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent stop-band rejection by 0.18 μm CMOS technology is demonstrated. High stop-band rejection is achieved by using a passive bandpass filter (BP-filter) with three finite transmission zeros (in the input terminal), one of which (ωz1 = 0.9 GHz) is in the low-frequency stop-band and the other two (ωMz3 and ωz5) are in the high-frequency stop-band. In addition, an active notch filter is used in the output terminal to introduce another low-frequency stop-band transmission zero (ωz2) at 2.4 GHz. The LNA consumes 4.68 mW and achieves S11 of -10 to -39.5 dB, S21 of 9.3 + 1.5 dB, and an average NF of 6 dB over the 3.2-9.7 GHz band. The measured stopband rejection is better than 21.6 dB for frequencies DC-2.5 and 11.2-20 GHz.
Autors: Chang, J.-F.;Lin, Y.-S.;
Appeared in: Electronics Letters
Publication date: Jan 2012, volume: 48, issue:1, pages: 44 - 45
Publisher: IEEE
 
» 320-to-40-Gb/s Optical Demultiplexing Using Four-Wave Mixing in a Quantum-Dot SOA
Abstract:
We report, for the first time, the optical demultiplexing of a 320-Gb/s intensity-modulated signal using four-wave mixing in a quantum-dot semiconductor optical amplifier. Error-free operations were successfully achieved for all the 40-Gb/s channels extracted by the optical demultiplexer.
Autors: Matsuura, M.;Gomez-Agis, F.;Calabretta, N.;Raz, O.;Dorren, H. J. S.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2012, volume: 24, issue:2, pages: 101 - 103
Publisher: IEEE
 
» 3D 'atomistic' simulations of dopant induced variability in nanoscale implant free In0.75Ga0.25As MOSFETs
Abstract:

Highlights

? We use quantum-corrected DD simulations to study the variability in IF III-V MOSFETs. ? Quantum corrections (QCs) are introduced through the DG approach. ? We use an atomistic mesh to resolve the exact positions of the random dopants (RDs). ? We have investigated the RD induced variability in the Vt, Ioff, and SS of the device. ? QCs lead to a decrease in the Vt fluctuations when compared to the classical DD.


Autors: A detailed simulation study of the impact of quantum effects on random dopant induced fluctuations in a 15 nm gate length, implant free In0.75Ga0.25As MOSFET is carried out using parallel 3D finite-element drift-diffusion (DD) device simulations and
Appeared in: Solid-State Electronics
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» 3D Nanoporous FeAl-KIT-5 with a cage type pore structure: a highly efficient and stable catalyst for hydroarylation of styrene and arylacetylenes
Abstract:

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Autors: A novel bimetallic nanoporous FeAl-KIT-5 catalyst with a cage type porous structure and a high surface area has been prepared for the hydroarylation of styrene and arylacetylenes to afford 1,1-diarylalkanes and 1,1-diarylalkenes, respectively. The ca
Appeared in: International Journal of Electrical Power & Energy Systems
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» 41 GHz and 10.6 GHz low threshold and low noise InAs/InP quantum dash two-section mode-locked lasers in L band
Abstract:
This paper reports recent results on InAs/InP quantum dash–based, two-section, passively mode-locked lasers pulsing at 41 GHz and 10.6 GHz and emitting at 1.59 μm at 20 °C. The 41-GHz device (1 mm long) starts lasing at 25 mA under uniform injection and the 10.6 GHz (4 mm long) at 71 mA. Their output pulses are significantly chirped. The 41-GHz laser exhibits 7 ps pulses after propagation in 60 m of a single-mode fiber. The 10.6-GHz laser generates one picosecond pulses with 545 m of a single-mode fiber. Its single side-band phase noise does not exceed –80 dBc/Hz at 100 kHz offset, leading to an average timing jitter of 800 fs.
Autors: Dontabactouny, M.;Piron, R.;Klaime, K.;Chevalier, N.;Tavernier, K.;Loualiche, S.;Le Corre, A.;Larsson, D.;Rosenberg, C.;Semenova, E.;Yvind, K.;
Appeared in: Journal of Applied Physics
Publication date: Jan 2012, volume: 111, issue:2, pages: 023102 - 023102-5
Publisher: IEEE
 
» 430 kHz Vertical p-Type Radio Frequency Metal-Base Transistor
Abstract:
This paper reports the radio frequency (RF) and direct current performance of organic metal-base transistors using double emitter hole injection layers. We report on transistors exhibiting a cutoff frequency of 430 kHz at room temperature. Besides the cutoff frequency, other important key parameters for RF transistors are current gain and on /off current ratio, which are 293.46 and 50.5, respectively.
Autors: bin Mohd Yusoff, A. R.;da Silva, W. J.;Song, Y.;Holz, E.;Schulz, D.;Shuib, S. A.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2012, volume: 59, issue:1, pages: 176 - 179
Publisher: IEEE
 
» 444.9 nm semipolar (1122) laser diode grown on an intentionally stress relaxed InGaN waveguiding layer
Abstract:
We demonstrate an electrically injected semipolar (1122) laser diode (LD) grown on an intentionally stress relaxed n-In0.09Ga0.91N waveguiding layer. Detrimental effects of misfit dislocations (MDs) in the proximity of the active region were effectively suppressed by utilizing a p/n-Al0.2Ga0.8N electron/hole blocking layer between the dislocated heterointerfaces and the active region. The threshold current density of the LD was ∼20.3 kA/cm2 with a lasing wavelength of 444.9 nm. This LD demonstrates an alternative approach in semipolar AlInGaN LD waveguide design where the thickness and composition of the waveguiding and/or cladding layers are not limited by the critical thickness for MD formation.
Autors: Shan Hsu, Po;Hardy, Matthew T.;Wu, Feng;Koslow, Ingrid;Young, Erin C.;Romanov, Alexey E.;Fujito, Kenji;Feezell, Daniel F.;DenBaars, Steven P.;Speck, James S.;Nakamura, Shuji;
Appeared in: Applied Physics Letters
Publication date: Jan 2012, volume: 100, issue:2, pages: 021104 - 021104-4
Publisher: IEEE
 
» 5-V Buck Converter Using 3.3-V Standard CMOS Process With Adaptive Power Transistor Driver Increasing Efficiency and Maximum Load Capacity
Abstract:
A high-voltage-tolerant buck converter with a novel adaptive power transistor driver is proposed in this paper. In order to minimize the of the cascode power transistor, the proposed scheme uses optimized and separated driving voltages for bias of the pMOS and nMOS power transistors. This increases not only the conversion efficiency, but also the maximum allowable load current for the transistor driver with small layout size, when compared to the buck converter with the earlier scheme. The measurements show that when the supply voltage is 2.5 V and the load current is 150 mA, the efficiency of the buck converter with the earlier scheme is 82%, whereas the efficiency of the buck converter with the proposed scheme is 92%, showing a maximum improvement of 10%. The designed buck converter uses the 0.35- m-thick gate oxide CMOS process, and at 2.5–5 V of voltage, can supply up to 380 mA of load current. The total chip size is 2.7 .
Autors: Nam, H.;Ahn, Y.;Roh , J.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Jan 2012, volume: 27, issue:1, pages: 463 - 471
Publisher: IEEE
 
» 50-nm Asymmetrically Recessed Metamorphic High-Electron Mobility Transistors With Reduced Source–Drain Spacing: Performance Enhancement and Tradeoffs
Abstract:
Whereas gate-length reduction has served as the major driving force to enhance the performance of GaAs- and InP-based high-electron mobility transistors (HEMTs) over the past three decades, the limitation of this approach begins to emerge. In this paper, we present a systematic evaluation of the impact of greatly reduced source–drain spacing on the performance of 50-nm asymmetrically recessed metamorphic HEMTs (MHEMTs). Extremely high extrinsic transconductance has been achieved over a wide drain bias range starting from as low as 0.1 V by reducing source–drain spacing to 0.5 with a self-aligned (SAL) ohmic process. The measured maximum extrinsic transconductance of 3 S/mm is a new record for all HEMT devices on a GaAs substrate and is equal to the best results reported for InP-based HEMTs. With the use of an asymmetric recess, SAL MHEMTs also demonstrate remarkable improvement in other major figures of merit, including off-state breakdown, on-state breakdown, subthreshold characteristics, ratio, and the voltage gain over the other SAL HEMTs reported so far. However, they still, in a few respects, underperform the conventional devices typically with 2- source–drain spacing. In particular, the on-state breakdown of the SAL devices has been capped at approximately 2 V, even with a very wide asymmetric recess. It appears that the uniqueness of the SAL technology would best fit applications that require low voltage and/or low DC power consumption, which can be fully tapped only when the parasitic capacitance is also properly controlled with, e.g., a high stem gate process.
Autors: Xu, D.;Yang, X.;Seekell, P.;Mt. Pleasant, L. M.;Mohnkern, L.;Chu, K.;Stedman, R. G.;Vera, A.;Isaak, R.;Schlesinger, L. L.;Carnevale, R. A.;Duh, K. H. G.;Smith, P. M.;Chao, P. C.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2012, volume: 59, issue:1, pages: 128 - 138
Publisher: IEEE
 
» 8-QAM+ Periodic Complementary Sequence Sets
Abstract:
This letter presents three methods that can transform ternary complementary sequence sets (CSSs) into 8-QAM+ CSSs. Method 1 yields 8-QAM+ CSSs with sequences of even length. Method 2 works for sequences with an arbitrary period, but results in 8-QAM+ CSSs with a size twice that of the ternary sets. Method 3 transforms ternary CSSs with odd periods into 8-QAM+ CSSs, but with double the period. The resultant 8-QAM+ CSSs can be applied to signal processing, channel estimation, and synchronization.
Autors: Zeng, Fanxin;Zeng, Xiaoping;Zhang, Zhenyu;Xuan, Guixin;
Appeared in: IEEE Communications Letters
Publication date: Jan 2012, volume: 16, issue:1, pages: 83 - 85
Publisher: IEEE
 
» 94 GHz Substrate Integrated Monopulse Antenna Array
Abstract:
A planar W-band monopulse antenna array is designed based on the substrate integrated waveguide (SIW) technology. The sum-difference comparator, 16-way divider and 32 32 slot array antenna are all integrated on a single dielectric substrate in the compact layout through the low-cost PCB process. Such a substrate integrated monopulse array is able to operate over 93 96 GHz with narrow-beam and high-gain. The maximal gain is measured to be 25.8 dBi, while the maximal null-depth is measured to be 43.7 dB. This SIW monopulse antenna not only has advantages of low-cost, light, easy-fabrication, etc., but also has good performance validated by measurements. It presents an excellent candidate for W-band directional-finding systems.
Autors: Cheng, Y. J.;Hong, W.;Wu, K.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2012, volume: 60, issue:1, pages: 121 - 129
Publisher: IEEE
 
» 99 fJ/(bit km) Energy to Data-Distance Ratio at 17 Gb/s Across 1 km of Multimode Optical Fiber With 850-nm Single-Mode VCSELs
Abstract:
We present extremely energy-efficient oxide-confined 850-nm single-mode vertical-cavity surface-emitting lasers (VCSELs) for optical interconnects. Error-free transmission at 17 Gb/s across 1 km of multimode optical fiber is achieved with an ultra-low energy-to-data ratio of 99 fJ/bit, corresponding to a record-low energy-to-data-distance ratio of 99 fJ/(bit km). This performance is achieved without changing any of the driving parameters up to 55 C. To date our VCSELs are the most energy-efficient directly modulated light-sources for data transmission across all distances up to 1 km of multimode optical fiber.
Autors: Moser, P.;Lott, J. A.;Wolf, P.;Larisch, G.;Payusov, A.;Ledentsov, N. N.;Hofmann, W.;Bimberg, D.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2012, volume: 24, issue:1, pages: 19 - 21
Publisher: IEEE
 
» -Norm Computation for Continuous-Time Descriptor Systems Using Structured Matrix Pencils
Abstract:
In this technical note, we discuss an algorithm for the computation of the -norm of transfer functions related to descriptor systems. We show how one can achieve this goal by computing the eigenvalues of certain skew-Hamiltonian/Hamiltonian matrix pencils and analyze arising problems. We also formulate and prove a theoretical result which serves as a basis for testing a transfer function matrix for properness. Finally, we illustrate our results using a descriptor system related to mechanical engineering.
Autors: Benner, P.;Sima, V.;Voigt, M.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Jan 2012, volume: 57, issue:1, pages: 233 - 238
Publisher: IEEE
 
» : Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA
Abstract:
Spatial processing of sparse, irregular, double-precision floating-point computation using a single field-programmable gate array (FPGA) enables up to an order of magnitude speedup (mean speedup) over a conventional microprocessor for the SPICE circuit simulator. We develop a parallel, FPGA-based, heterogeneous architecture customized for accelerating the SPICE simulator to deliver this speedup. To properly parallelize the complete simulator, we decompose SPICE into its three constituent phases—model evaluation, sparse matrix-solve, and iteration control—and customize a spatial architecture for each phase independently. Our heterogeneous FPGA organization mixes very large instruction word, dataflow and streaming architectures into a cohesive, unified design to match the parallel patterns exposed by our programming framework. This FPGA architecture is able to outperform conventional processors due to a combination of factors, including high utilization of statically-scheduled resources, low-overhead dataflow scheduling of fine-grained tasks, and streaming, overlapped processing of the control algorithms. We demonstrate that we can independently accelerate model evaluation by a mean factor of across a range of nonlinear device models and matrix solve by across various benchmark matrices while delivering a mean combined speedup of for the composite design when comparing a Xilinx Virtex-6 LX760 (40 nm) with an Intel Core i7 965 (45 nm). We also estimate mean energy savings of (up to $40.9times$) when comparing a Xilinx Virtex-6 LX760 with an Intel Core i7 965.
Autors: Kapre, N.;DeHon, A.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Jan 2012, volume: 31, issue:1, pages: 9 - 22
Publisher: IEEE
 
» -Ary RFID Tags Splitting With Small Idle Slots
Abstract:
In radio frequency identifications (RFIDs), an idle slot can be interrupted by the reader and takes less time than the other slots. In this case, the widely used binary splitting (BS) protocol is not optimal. -ary splitting ( ) with a carefully selected outperforms BS, because it can take into account smaller duration of the idle slots. In this paper, we provide optimal value of ( ) for varying slot sizes that yields minimum identification time. The proposed scheme is called optimal splitting (OS). We also revise OS to deal with mobile tags and propose the optimal splitting with arrival tags blocking (OS-ATB) protocol. Extensive simulations show that OS and OS-ATB consistently yield better performance than the other splitting and tree-based schemes.
Autors: Guo, H.;Leung, V. C. M.;Bolic, M.;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Jan 2012, volume: 9, issue:1, pages: 177 - 181
Publisher: IEEE
 
» -Connectivity Analysis of One-Dimensional Linear VANETs
Abstract:
In a 1-D linear vehicular ad hoc network (1-DL-VANET), some vehicles may leave the network (e.g., at highway exits), which may make the 1-DL-VANET disconnected. Thus, it is important to analyze the connectivity of the 1-DL-VANET. When removal of any arbitrary nodes from a network does not disconnect the network, the network is said to be -connected. In this paper, we investigate the -connectivity of the 1-DL-VANET. Sufficient and necessary conditions are derived for the 1-DL-VANET to be -connected, and based on this, a method is provided, with the help of matrix decomposition, to obtain expression of the probability of the 1-DL-VANET being -connected. The expectation of the maximum number of tolerable vehicle departures is also derived. Simulation results confirm the accuracy of our analysis and indicate that the expectation of the maximum number of tolerable vehicle departures almost linearly increases with the total number of vehicles.
Autors: Yan, Z.;Jiang, H.;Shen, Z.;Chang, Y.;Huang, L.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Jan 2012, volume: 61, issue:1, pages: 426 - 433
Publisher: IEEE
 
» -Band CMOS Differential and Quadrature Voltage-Controlled Oscillators for Low Phase-Noise and Low-Power Applications
Abstract:
In this paper, modified circuit topologies of a differential voltage-controlled oscillator (VCO) and a quadrature VCO (QVCO) in a standard bulk 90-nm CMOS process are presented for low dc power and low phase-noise applications. By utilizing current-reuse and transformer-feedback techniques, the proposed VCO and QVCO can be operated at reduced dc power consumption while maintaining extraordinary circuit performance in terms of low phase-noise and low amplitude/phase errors. The VCO circuit topology is investigated to obtain the design procedure. The VCO is further applied to the QVCO design with a bottom-series coupling technique. The coupling network between two differential VCOs and device size are properly designed based on our proposed design methodology to achieve low amplitude and phase errors. Moreover, the VCO and the QVCO are fully characterized with amplitude and phase errors via a four-port vector network analyzer. With a dc power of 3 mW, the VCO exhibits a frequency tuning range from 20.3 to 21.3 GHz, a phase noise of 116.4 dBc/Hz at 1-MHz offset, a figure-of-merit (FOM) of 198 dBc/Hz, a phase error of 3.8 , and an amplitude error of 0.9 dB. With a dc power of 6 mW, the QVCO demonstrates a phase noise of 117.4 dBc/Hz, a FOM of 195.6 dBc/Hz, a phase error of 4 , and an amplitude error of 0.6 dB. The proposed VCO and QVCO can be compared with the previously reported state-of-the-art VCOs and QVCOs in silicon-based technologies.
Autors: Chang, H.-Y.;Chiu, Y.-T.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2012, volume: 60, issue:1, pages: 46 - 59
Publisher: IEEE
 
» : Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA
Abstract:
Spatial processing of sparse, irregular, double-precision floating-point computation using a single field-programmable gate array (FPGA) enables up to an order of magnitude speedup (mean speedup) over a conventional microprocessor for the SPICE circuit simulator. We develop a parallel, FPGA-based, heterogeneous architecture customized for accelerating the SPICE simulator to deliver this speedup. To properly parallelize the complete simulator, we decompose SPICE into its three constituent phases—model evaluation, sparse matrix-solve, and iteration control—and customize a spatial architecture for each phase independently. Our heterogeneous FPGA organization mixes very large instruction word, dataflow and streaming architectures into a cohesive, unified design to match the parallel patterns exposed by our programming framework. This FPGA architecture is able to outperform conventional processors due to a combination of factors, including high utilization of statically-scheduled resources, low-overhead dataflow scheduling of fine-grained tasks, and streaming, overlapped processing of the control algorithms. We demonstrate that we can independently accelerate model evaluation by a mean factor of across a range of nonlinear device models and matrix solve by across various benchmark matrices while delivering a mean combined speedup of for the composite design when comparing a Xilinx Virtex-6 LX760 (40 nm) with an Intel Core i7 965 (45 nm). We also estimate mean energy savings of (up to $40.9times$) when comparing a Xilinx Virtex-6 LX760 with an Intel Core i7 965.
Autors: Kapre, N.;DeHon, A.;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Jan 2012, volume: 31, issue:1, pages: 9 - 22
Publisher: IEEE
 
» A 0.013 , 5 , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply
Abstract:
We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel input offset and prevent noise folding while enabling “per-pixel” digitization, alleviating system-level complexity. Implemented in a 65 nm CMOS process, the prototype occupies 0.013 while consuming 5 and achieving 4.9 of input-referred noise in a 10 kHz bandwidth.
Autors: Muller, R.;Gambini, S.;Rabaey, J. M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 232 - 243
Publisher: IEEE
 
» A 0.24-nJ/b Wireless Body-Area-Network Transceiver With Scalable Double-FSK Modulation
Abstract:
An energy-efficient wireless body-area-network (WBAN) transceiver is implemented in 0.18- m CMOS technology with 1-V supply voltage. For the low energy consumption, the body channel communication (BCC) PHY is utilized with the theoretical results of Maxwell's equation analysis behind the BCC. Based on the channel analysis, the resonance matching (RM) and contact impedance sensing (CIS) techniques are proposed to enhance the quality of the body channel. A double-FSK modulation scheme is adopted with high scalability to fulfill the IEEE 802.15.6 Task Group specifications. In addition, a low-power double-FSK transceiver is implemented by five circuit techniques: 1) a reconfigurable LNA with CIS; 2) a current-reuse wideband demodulator; 3) a divider-based local oscillator (LO) generation with duty-cycle correction in the receiver; 4) a reconfigurable driver with RM; and 5) a divider-based digital double-FSK modulator in the transmitter. As a result, fully WBAN compatible receiver and transmitter consume 2.4 and 2 mW, respectively, at a data rate of 10 Mb/s, corresponding to energy consumption of 0.24 nJ per received bit and 0.2 nJ per transmitted bit.
Autors: Bae, J.;Song, K.;Lee, H.;Cho, H.;Yoo, H.-J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 310 - 322
Publisher: IEEE
 
» A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking
Abstract:
A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify functions through micro bumps and test pads have been developed. Block based dual period refresh scheme is applied to reduce self refresh current with minimum chip size burden. Stacking of 2 dies with 7.5 diameter and 40 pitch TSVs has been fabricated and tested, which results in 76% overall package yield without difference in performances between top and bottom die.
Autors: Kim, J.-S.;Oh, C. S.;Lee, H.;Lee, D.;Hwang, H. R.;Hwang, S.;Na, B.;Moon, J.;Kim, J.-G.;Park, H.;Ryu, J.-W.;Park, K.;Kang, S. K.;Kim, S.-Y.;Kim, H.;Bang, J.-M.;Cho, H.;Jang, M.;Han, C.;LeeLee, J.-B.;Choi, J. S.;Jun, Y.-H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 107 - 116
Publisher: IEEE
 
» A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology
Abstract:
A 512 Mbit consumer DDR2 SDRAM that uses self-dynamic voltage scaling (SDVS) and adaptive design techniques is introduced in this paper. With the increase in the significance of process variation, higher performance requirements reduce the allowable design margin in DRAM circuits. However, self-dynamic voltage scaling gives a greater timing margin in the circuitry by changing the internal supply voltage in response to the operating frequency and process skew. By changing the internal supply voltage, the life time of the chip increases by more than 23 times when the supply voltage is lowered by 300 mV. The proposed adaptive design techniques include an adaptive bandwidth delay-locked loop and an adaptive clock gating. The former improves the performance by obtaining a wider valid data window and the latter saves on dynamic power consumption in the clock distribution network. The SDVS method reduces the IDD3P by 9.3% and the adaptive clock gating saves 8.8% of the IDD3N when measured at 200 MHz, 25 The studied consumer DDR2 SDRAM was fabricated using 44 nm standard DRAM process technology. It occupies a 17.7 die area and operates using a 1.8 V power supply.
Autors: Lee, H.-W.;Kim, K.-H.;Choi, Y.-K.;Sohn, J.-H.;Park, N.-K.;Kim, K.-W.;Kim, C.;Choi, Y.-J.;Chung, B.-T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 131 - 140
Publisher: IEEE
 
» A 10-kV Linear Current-Mode Power Amplifier for Capacitive Actuators
Abstract:
High-voltage linear pulse amplifiers with current output are advantageous for driving piezoelectric or electrorheological actuators because the inherent current ripple of switched-mode power converters can be avoided. The new amplifier provides output voltages up to 10 kV with an output current of 200 mA. Low quiescent currents of 0.6 mA minimize static power loss. Nested feedback loops are applied to ensure symmetrical voltage division among cascaded output insulated-gate bipolar transistors (IGBTs) in half-bridge configurations. Optical isolated output stages control the load current. Local current controllers at the power IGBTs enhance linearity and allow for quasi-complementary circuit design without high-voltage small-signal transistors.The symmetrical rise and fall times of 80 are achieved, together with the pulse peak power of more than 1 kW.
Autors: Horn, T.;Melbert, J.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Jan 2012, volume: 61, issue:1, pages: 2 - 8
Publisher: IEEE
 
» A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier
Abstract:
A 100-V ac energy meter based on the system-on- a-film (SoF) concept, in which various devices are integrated on a flexible film, is presented. The system consists of 20-V organic CMOS digital and analog circuits with a floating gate (FG) for process variation compensation, 100-V organic pMOS rectifiers for generating a 50-Hz clock and 20-V dc power, and an organic LED (OLED) bar indicator. The energy meter based on the SoF is flexible and therefore can be installed to monitor each ac outlet simultaneously. The organic devices are printable, and it is expected that they can be formed using a low-cost printing process in the future. The energy meter can measure the accumulated energy of a 100- ac lineup to a full-scale value of 360 Wh when a 500-W target load is monitored. The flexible film is foldable and its total area excluding the ac connector is 200 200 in the unfolded form or 70 70 when folded.
Autors: Ishida, K.;Huang, T.-C.;Honda, K.;Sekitani, T.;Nakajima, H.;Maeda, H.;Takamiya, M.;Someya, T.;Sakurai, T.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 301 - 309
Publisher: IEEE
 
» A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency
Abstract:
The design and implementation of a high-speed voltage-controlled oscillator (VCO) in 65-nm CMOS technology is presented. The proposed VCO oscillates at the secondary resonant pole of its resonator and achieves a frequency enhancement of 84.7% while compared with a conventional cross-coupled VCO. The proposed VCO is also incorporated into a phase-locked loop (PLL) to generate clock signals above 100 GHz. For a 1.2-V supply, the measured tuning range of this VCO is from 103.057 to 104.581 GHz, and the measured phase noise of this VCO is dBc/Hz at 10-MHz offset. The locking range of the PLL is from 103.058 to 104.58 GHz, and its measured in-band phase noise is dBc/Hz at 1-MHz offset. The measured reference spur level of this PLL is less than dBc while consuming 63 mW from a 1.2-V supply.
Autors: Tsai, K.-H.;Liu, S.-I.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2012, volume: 20, issue:1, pages: 80 - 88
Publisher: IEEE
 
» A 151-mm 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology
Abstract:
A 64-Gb MLC (2 bit/cell) NAND flash memory with the highest memory density to date as an MLC flash memory, has been successfully developed. To decrease the chip size, 2-physical-plane configuration with 16 KB wordline-length, a new bit-line hook-up architecture, and a top-metal-congestion-free optimized peripheral circuit floor plan, are introduced. As a result, 151 die size with an excellent 79% cell area efficiency is achieved. Newly introduced precharge detect algorithm and smart precharge algorithm improve program throughput by 10%. 14 MB/s program throughput is obtained, which is comparable or even higher performance than NAND flash memories reported in the previous 30 nm technology generation. The proposed smart precharge algorithm reduces program operation current by 6%, and 25 mA operation current with 16 KB programming is achieved. Moreover, a high-speed asynchronous DDR interface is incorporated and 266 MB/s data transfer is achieved.
Autors: Fukuda, K.;Watanabe, Y.;Makino, E.;Kawakami, K.;Sato, J.;Takagiwa, T.;Kanagawa, N.;Shiga, H.;Tokiwa, N.;Shindo, Y.;Ogawa, T.;Edahiro, T.;Iwai, M.;Nagao, O.;Musha, J.;Minamoto, T.;Furuta, Y.;Yanagidaira, K.;Suzuki, Y.;Nakamura, D.;Hosomura, Y.;Tanaka,
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 75 - 84
Publisher: IEEE
 
» A 17–35 GHz Broadband, High Efficiency PHEMT Power Amplifier Using Synthesized Transformer Matching Technique
Abstract:
This paper presents a 17 GHz to 35 GHz broadband power amplifier (PA) using 0.15- m GaAs pHEMT technology. The synthesized transformer using microstrip line matching technique is proposed in this PA design to enhance the broadband frequency response and minimize the chip size. The design procedures are also presented. A high efficiency broadband PA in commercial 0.15 m GaAs pHEMT process with the best of 22 dBm, of 23.5 dBm, and PAE of 40% are demonstrated to verify the design concepts. This PA has the highest PAE, smallest chip size, and wide fractional bandwidth among the broadband GaAs HEMT PAs from K to Ka band.
Autors: Huang, P.-C.;Tsai, Z.-M.;Lin, K.-Y.;Wang, H.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2012, volume: 60, issue:1, pages: 112 - 119
Publisher: IEEE
 
» A 1 GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
Abstract:
image

Highlights

? We present a 1 GHz DDR2/3 combo SSTL driver. ? The driver achieves all DDR2 and DDR3 operations. ? The driver incorporates all relevant (DDR2/3) JEDEC features. ? Control of slew rate is supported. ? ODT and OCD calibration at either the rails (VDDQ/VSS) or at VDDQ/2 are supported.

Autors:

Graphical abstract

Appeared in: Computers & Electrical Engineering
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» A 28 nm 0.6 V Low Power DSP for Mobile Applications
Abstract:
Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold variation, already a significant issue in today's advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local variation and achieve a reliable design with minimal pessimism.
Autors: Ickes, N.;Gammie, G.;Sinangil, M. E.;Rithe, R.;Gu, J.;Wang, A.;Mair, H.;Datla, S.;Rong, B.;Honnavara-Prasad, S.;Ho, L.;Baldwin, G.;Buss, D.;Chandrakasan, A. P.;Ko, U.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 35 - 46
Publisher: IEEE
 
» A 3- CMOS Glucose Sensor for Wireless Contact-Lens Tear Glucose Monitoring
Abstract:
This paper presents a noninvasive wireless sensor platform for continuous health monitoring. The sensor system integrates a loop antenna, wireless sensor interface chip, and glucose sensor on a polymer substrate. The IC consists of power management, readout circuitry, wireless communication interface, LED driver, and energy storage capacitors in a 0.36- CMOS chip with no external components. The sensitivity of our glucose sensor is 0.18 . The system is wirelessly powered and achieves a measured glucose range of 0.05–1 mM with a sensitivity of 400 Hz/mM while consuming 3 from a regulated 1.2-V supply.
Autors: Liao, Y.-T.;Yao, H.;Lingley, A.;Parviz, B.;Otis, B. P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 335 - 344
Publisher: IEEE
 
» A 3.3 V 6-Bit 100 kS/s Current-Steering Digital-to-Analog Converter Using Organic P-Type Thin-Film Transistors on Glass
Abstract:
A 3.3 V 6-bit binary-weighted current-steering digital-to-converter converter (DAC) using low-voltage organic p-type thin-film transistors (OTFTs) is presented. The converter marks records in speed and compactness owing to an OTFT fabrication process that is based on high-resolution silicon stencil masks. The chip has been fabricated on a glass substrate and consumes an area of . The converter has a maximum update rate of 100 kS/s and a maximum output voltage swing of 2 V. The measured DNL and INL at an update rate of 1 kS/s are 0.69 and 1.16 LSB, respectively. A spurious-free dynamic range (SFDR) of 32 dB has been measured for output sinusoids at 31 Hz (update rate of 1 kS/s) and 3.1 kHz (update rate of 100 kS/s).
Autors: Zaki, T.;Ante, F.;Zschieschang, U.;Butschke, J.;Letzkus, F.;Richter, H.;Klauk, H.;Burghartz, J. N.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 292 - 300
Publisher: IEEE
 
» A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers
Abstract:
An Itanium® processor implemented in 32 nm CMOS with nine layers of Cu contains 3.1 billion transistors. The die measures 18.2 mm by 29.9 mm. The processor has eight multi-threaded cores, a ring based system interface and combined cache on the die is 50 MB. High-speed links allow for peak processor-to-processor bandwidth of up to 128 GB/s and memory bandwidth of up to 45 GB/s.
Autors: Riedlinger, R.;Arnold, R.;Biro , L.;Bowhill, B.;Crop, J.;Duda, K.;Fetzer, E. S.;Franza, O.;Grutkowski, T.;Little, C.;Morganti, C.;Moyer, G.;Munch, A.;Nagarajan, M.;Parks, C.;Poirier, C.;Repasky, B.;Roytman, E.;Singh, T.;Stefaniw, M. W.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 177 - 193
Publisher: IEEE
 
» A 324-Element Vivaldi Antenna Array for Radio Astronomy Instrumentation
Abstract:
This paper presents a 324-element 2-D broadside array for radio astronomy instrumentation which is sensitive to two mutually orthogonal polarizations. The array is composed of cruciform units consisting of a group of four Vivaldi antennas arranged in a cross-shaped structure. The Vivaldi antenna used in this array exhibits a radiation intensity characteristic with a symmetrical main beam of 87.5 at 3 GHz and 44.2 at 6 GHz. The measured maximum side/backlobe level is 10.3 dB below the main beam level. The array can operate at a high frequency of 5.4 GHz without the formation of grating lobes.
Autors: Reid, E. W.;Ortiz-Balbuena, L.;Ghadiri, A.;Moez, K.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Jan 2012, volume: 61, issue:1, pages: 241 - 250
Publisher: IEEE
 
» A 40-Gb/s OFDM PON System Based on 10-GHz EAM and 10-GHz Direct-Detection PIN
Abstract:
This letter demonstrates a 40-Gb/s optical double-sideband (ODSB) orthogonal frequency-division multiplexing passive optical network (OFDM-PON) system using a cost-effective 10-GHz-bandwidth electroabsorption modulator (EAM). By employing a subcarrier-adaptive modulation format and pre-emphasis, we successfully achieve 20-km EAM-based single-mode-fiber (SMF) transmission.
Autors: Chen, H.-Y.;Wei, C. C.;Hsu, D.-Z.;Yuang, M. C.;Chen, J.;Lin, Y.-M.;Tien, P.-L.;Lee, S. S. W.;Lin, S.-H.;Li, W.-Y.;Hsu, C.-H.;Shih, J.-L.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2012, volume: 24, issue:1, pages: 85 - 87
Publisher: IEEE
 
» A 50-Mb/s CMOS QPSK/O-QPSK Transmitter Employing Injection Locking for Direct Modulation
Abstract:
A 50-Mb/s quadrature phase-shift keying (QPSK)/offset quadrature phase-shift keying (O-QPSK) transmitter suitable for biomedical high-quality imaging application is presented. Centered at 915 MHz, the phase modulation is achieved by directly modifying the self-resonant frequency of an LC voltage-controlled oscillator through capacitor bank switching. By eliminating many unnecessary building blocks in the conventional QPSK/O-QPSK transmitter, significant power and area savings are achieved. Implemented in 0.18- CMOS technology, it occupies an active core area of . With 305-MHz injection frequency and consuming 5.6 mW under 1.4-V supply, the transmitter achieves error vector magnitude (EVM) of 11.4%/5.97% for O-QPSK/QPSK modulation while delivering output power of at 50 Mb/s. By lowering the injection frequency to 101.67 MHz, it consumes 5.88 mW under the same supply voltages while delivering an output power of . The transmitter achieves measured EVM of 6.4% at 50 Mb/s under QPSK modulation.
Autors: Diao, S.;Zheng, Y.;Gao, Y.;Cheng, S.-J.;Yuan, X.;Je, M.;Heng, C.-H.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2012, volume: 60, issue:1, pages: 120 - 130
Publisher: IEEE
 
» A 62 mV 0.13 m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic
Abstract:
Supply voltage reduction beyond the minimum energy per operation point is advantageous for supply voltage constrained applications, but is limited by the degradation of on-to-off current ratios with decreasing supply. In this work, we show that the effective on-to-off ratio can be considerably improved by the use of Schmitt Trigger structures, which effectively reduce the leakage from the gate output node and thereby stabilize the output level. A method for applying this concept to general logic is presented. Design rules concerning transistor sizing, gate selection and layout necessary to further minimize the required supply voltage are outlined and applied to the design of a chip implementing 8 8 bit multipliers as test structures. The only custom design step is the creation of the Schmitt Trigger standard-cell library, otherwise a regular digital tool chain is used. The multipliers exhibit full functionality down to supply voltages of 84 mV–62 mV, depending on the area overhead invested. No process or post-silicon tuning like body biasing is used. At the minimum possible supply voltage of 62 mV, a power consumption of 17.9 nW at an operation frequency of 5.2 kHz is measured for an 8 8 bit multiplier.
Autors: Lotze, N.;Manoli, Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 47 - 60
Publisher: IEEE
 
» A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements
Abstract:
A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology. The SRAM features a 0.154 bit-cell, the smallest to date for a 32 nm SOI product. A 0.7 V operation is enabled by three assist features. Stability is improved by a bit-line regulation scheme which reduces charge injection into the bit-cell. Enhancements to the write path include an increase of 40% of bit-line boost voltage. Finally, a bit-cell-tracking delay circuit improves both performance and yield across the process space.
Autors: Pilo, H.;Arsovsi, I.;Batson, K.;Braceras, G.;Gabric, J.;Houle, R.;Lamphier, S.;Radens, C.;Seferagic, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 97 - 106
Publisher: IEEE
 
» A 675 Mbps, 4 4 64-QAM K-Best MIMO Detector in 0.13 CMOS
Abstract:
This paper introduces a novel scalable pipelined VLSI architecture for a 4 4 64-QAM hard-output multiple-input–multiple-output (MIMO) detector based on K-best lattice decoders. The key contribution is a means of expanding the intermediate nodes of the search tree on-demand, rather than exhaustively, along with three types of distributed sorters operating in a pipelined structure. The proposed architecture has a fixed critical path independent of the constellation size, on-demand expansion scheme, efficient distributed sorters, and is scalable to higher number of antennas. Fabricated in 0.13 CMOS, it occupies 0.95 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no BER performance loss. It achieves an SNR-independent throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and long term evolution (LTE) systems. The measurements confirm that this design consumes 3.0 less energy/bit and operates at a significantly higher throughput compared to the best previously published design.
Autors: Shabany, M.;Gulak, P. G.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2012, volume: 20, issue:1, pages: 135 - 147
Publisher: IEEE
 
» A 70-Mb/s 100.5-dBm Sensitivity 65-nm LP MIMO Chipset for WiMAX Portable Router
Abstract:
In this paper, we present a low-power high-performance WiMAX chipset fully compliant with IEEE 802.16e specification corrigendum 1, 2 for mobile broadband access and WiMAX Forum system profile Wave2. The chipset is comprised of a 632.7-mW/24.99- modem/router chip and a 364-mW/11.05- dual-band 2 2 MIMO RF transceiver chip, both developed in 65-nm CMOS process. The proposed chipset is capable of handling a maximum peak WiMAX downlink (DL) throughput of 70 Mbps. Moreover, the chipset can reach up to 100.5-dBm sensitivity in a 10-MHz AWGN channel, which outperforms WiMAX Forum mobile radio conformance test (MRCT) by 9.5 dB. Such high sensitivity is due to the proposed low-noise high-linearity RF transceiver chip, which has 2.5-dB RX noise figure (NF) and 37-dB TX error vector magnitude (EVM), and the applied high-performance baseband signal processing algorithms. Several low-power design techniques—from SW level, firmware/DSP level, to HW module level—have been implemented to enable portable applications. The modem/router chip is highly integrated and has rich features and various interfaces for applications such as router or VoIP phone. Furthermore, this is the only published WiMAX chipset which has been in mass production.
Autors: Liao, S.;Chang, Y.-S.;Wu, C.-H.;Tsai, H.-C.;Chen, H.-H.;Chen, M.;Hsueh, C.-W.;Lin, J.-B.;Juang, D.-K.;Yang, S.-A.;Liu, C.-T.;Lee, T.-P.;Chen, J.-R.;Shih, C.-H.;Hong, B.;Hsu, H.-R.;Wang, C.-Y.;Lin, M.-S.;Tseng, W.-H.;Yang, C.-H.;Lee, L. C.;Jheng, T.-J
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 61 - 74
Publisher: IEEE
 
» A 75 W Real-Time Scalable Body Area Network Controller and a 25 W ExG Sensor IC for Compact Sleep Monitoring Applications
Abstract:
A light-weighted body area network using 3-layer coin-sized fabric patches is proposed for sleep monitoring systems. It consists of two ICs, a network controller (NC) and a sensor node (SN), and also Wearable Band (W-Band) to connect them. The Continuous Data Transmission (CDT) protocol is proposed for low power and real-time scalability by in-order data transmission using W-Band among several sensors. Based on this protocol, Linked List based network Manager (LLM) and Adaptive Dual Mode Controller (ADMC) in NC, and low swing data transmitter (D-TX) and its own back-end circuits are introduced. The LLM and ADMC can adaptively change the network configuration according to the dynamic network variances in real-time ( 500 ms), and D-TX can make low energy data transmitter of 0.33 pJ/b with 20 Mbps data rate for W-Band interface. These two low power ICs, which are implemented in 0.18 CMOS process and operates with 1.5 V supply, consume 75 and 25 , respectively.
Autors: Lee, S.;Yan, L.;Roh, T.;Hong, S.;Yoo, H.-J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 323 - 334
Publisher: IEEE
 
» A battery as big as the grid
Abstract:
Sometime this quar ter, a shovel will sink into the dry desert soil of a Mexicali industrial park, breaking ground for the construction of an unprecedented energystorage facility. Once completed, its batteries will be able to feed a full gigawatt into the grid for 4 to 6 hours.
Autors: Kumagai, J.;
Appeared in: IEEE Spectrum
Publication date: Jan 2012, volume: 49, issue:1, pages: 45 - 46
Publisher: IEEE
 
» A Bayesian estimation for single target tracking based on state mixture models
Abstract:

Highlights

? The measurement likelihood function using all the measurements is derived. ? An analytic Bayesian filter for single target tracking is proposed. ? Under linear Gaussian assumptions on the dynamic and measurement models, a closed-form solution is proposed.


Autors: This paper presents a Bayesian algorithm for single target tracking using state mixture model theory. Compared with the existing approaches, the proposed algorithm aims at deriving the likelihood function of all measurements. Given this, an analytic
Appeared in: Signal Processing
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» A Bayesian Hierarchical Framework for Multitarget Labeling and Correspondence With Ghost Suppression Over Multicamera Surveillance System
Abstract:
In this paper, the main purpose is to locate, label, and correspond multiple targets with the capability of ghost suppression over a multicamera surveillance system. In practice, the challenges come from the unknown target number, the interocclusion among targets, and the ghost effect caused by geometric ambiguity. Instead of directly corresponding objects among different camera views, the proposed framework adopts a fusion-inference strategy. In the fusion stage, we formulate a posterior distribution to indicate the likelihood of having some moving targets at certain ground locations. Based on this distribution, a systematic approach is proposed to construct a rough scene model of the moving targets. In the inference stage, the scene model is inputted into a proposed Bayesian hierarchical detection framework, where the target labeling, target correspondence, and ghost removal are regarded as a unified optimization problem subject to 3-D scene priors, target priors, and foreground detection results. Moreover, some target priors, such as target height, target width, and the labeling results are iteratively refined based on an expectation-maximization (EM) mechanism to further boost system performance. Experiments over real videos verify that the proposed system can systematically determine the target number, efficiently label moving targets, precisely locate their 3-D locations, and effectively tackle the ghost problem.
Autors: Huang, C.-C.;Wang, S.-J.;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Jan 2012, volume: 9, issue:1, pages: 16 - 30
Publisher: IEEE
 
» A Bayesian Theoretic Approach to Multiscale Complex-Phase-Order Representations
Abstract:
This paper explores a Bayesian theoretic approach to constructing multiscale complex-phase-order representations. We formulate the construction of complex-phase-order representations at different structural scales based on the scale-space theory. Linear and nonlinear deterministic approaches are explored, and a Bayesian theoretic approach is introduced for constructing representations in such a way that strong structure localization and noise resilience are achieved. Experiments illustrate its potential for constructing robust multiscale complex-phase-order representations with well-localized structures across all scales under high-noise situations. Illustrative examples of applications of the proposed approach is presented in the form of multimodal image registration and feature extraction.
Autors: Wong, A.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Jan 2012, volume: 21, issue:1, pages: 28 - 40
Publisher: IEEE
 
» A Biasing and Demodulation System for Kilopixel TES Bolometer Arrays
Abstract:
We describe the signal processing logic, firmware, and software for a frequency-domain multiplexed biasing and demodulation system that reads out transition-edge-sensor bolometer arrays for millimeter-wavelength cosmology telescopes. This system replaces a mixed-signal readout back end with a much smaller and more power-efficient system relying on field-programmable gate arrays for control, computation, and signal processing. The new system is sufficiently robust, automated, and power efficient to be flown on stratospheric balloon-borne telescopes and is being developed further for satellite applications.
Autors: Smecher, G.;Aubin, F.;Bissonnette, E.;Dobbs, M.;Hyland, P.;MacDermid, K.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Jan 2012, volume: 61, issue:1, pages: 251 - 260
Publisher: IEEE
 
» A BJT-Based Heterostructure 1T-DRAM for Low-Voltage Operation
Abstract:
We propose a BJT-based floating-body 1T-DRAM cell made of a novel heterostructure suitable to low-power DRAM technology. Based on the numerical simulation, we verify that the proposed structure is capable of reducing the breakdown voltage and single-transistor latch bias in the BJT-based 1T-DRAM, which largely depends on the impact ionization and parasitic BJT through enhancement of the current gain . Moreover, it is discerned that the novel structure with the SiGe structure has advantages of dynamic refresh characteristics due to reduced bit-line disturb compared with the normal Si device.
Autors: Shim, K.-S.;Chung, I.-Y.;Park, Y. J.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2012, volume: 33, issue:1, pages: 14 - 16
Publisher: IEEE
 
» A categorical, improper probability method for combining NDVI and LiDAR elevation information for potential cotton precision agricultural applications
Abstract:

Highlights

? We build a map for statistical analyses and site-specific decisions for cotton. ? We use both the NDVI and LiDAR elevation to obtain the geographical information. ? We combined data with incompatible units of measurement. ? A categorical, improper probability algorithm is described as a solution.


Autors: An algorithm is presented to fuse the Normalized Difference Vegetation Index (NDVI) with Light Detection and Ranging (LiDAR) elevation data to produce a map potentially useful for site-specific management practices in cotton. A bi-variate Gaussian pr
Appeared in: Computers and Electronics in Agriculture
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» A Channel Aware MAC Protocol in an ALOHA Network with Selfish Users
Abstract:
We consider a game theoretic model incorporating channel state information into slotted ALOHA in a fading environment. Each user sets a threshold for her channel gain and sends a packet only when the channel gain is higher than the threshold at a given slot. This threshold is decided to maximize the net benefit of a user, utility minus power consumption. The asymptotic behaviors of the total throughput at a symmetric Nash equilibrium point are studied for fading and non-fading environments in a homogeneous system. It is shown that the total throughput in a fading environment increases as the number of users increases, while the total throughput in the simple classical slotted ALOHA decreases when users are sensitive enough to power consumption. Convergence to the symmetric Nash equilibrium is also studied.
Autors: Jin, Youngmi;Kesidis, George;Jang, Ju Wook;
Appeared in: IEEE Journal on Selected Areas in Communications
Publication date: Jan 2012, volume: 30, issue:1, pages: 128 - 137
Publisher: IEEE
 
» A charge-pump and comparator based power-efficient pipelined ADC technique
Abstract:
A charge-pump and comparator based technique is presented for power-efficient pipelined analog-to-digital conversion. The technique takes advantage of a passive charge pump to implement the core function of residue voltage amplification and exploits a comparator-controlled charging circuit to buffer the residue voltage to the next stage. Unlike the conventional buffer circuit using source followers, no voltage headroom is sacrificed in this voltage buffering scheme. The comparator overshoot due to comparator delay is minimized by a self-cancellation scheme. The proposed pipelined ADC technique uses only capacitors, comparators and current sources with digital calibration to achieve low power consumption. Designed and fabricated in a 0.18 ?m CMOS technology, a proof-of-concept ADC has measured 39.1 dB SNDR (6.2-bit ENOB) at 25 MS/s while consuming 3.5 mW from a 1.8 V supply.
Autors: Xian Tang, Chi-Tung Ko, Kong-Pang Pun
Appeared in: Microelectronics Journal
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» A Classification Technique for Recloser-Fuse Coordination in Distribution Systems With Distributed Generation
Abstract:
In this paper, a novel approach is presented to study the impact of distributed-generation penetration on recloser-fuse coordination. The main core of this approach is based on an assessment process using a classification technique to classify the recloser-fuse coordination status at fault conditions to either coordination holds or coordination lost. Accordingly, the distribution system operator can take the proper decision. Then, two complementary actions are recommended in the proposed approach as a solution to decrease the number of cases where coordination is lost. The first one is to search for the best DG locations, where such locations are characterized by the minimum number of cases classified as coordination lost. The second one is based on changing the recloser setting in such a way to minimize the cases where coordination is lost. This new approach has been implemented on the IEEE 37-node test feeder using MATLAB-based developed software and the obtained results are presented and discussed.
Autors: Naiem, A. F.;Hegazy, Y.;Abdelaziz, A. Y.;Elsharkawy, M. A.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Jan 2012, volume: 27, issue:1, pages: 176 - 185
Publisher: IEEE
 
» A closed-loop approach for improving the wellness of low-income elders at home using game consoles
Abstract:
As life expectancy in the industrialized world increases, so does the number of elders with chronic health conditions such as diabetes and congestive heart failure who require complex self-management routines. We present a motivational exercise gaming system whose goal is to increase the activity of elders with complex chronic conditions. Our gaming system, initially deployed unattended, showed discouraging results. Our second attempt addresses these shortcomings by coupling the gaming console with an application for presenting exercise results to remote clinicians and caregivers, and a smartphone- based application for collecting feedback and issuing alerts. HealthOS, a platform for developing healthcare applications, integrates all components of the applications.
Autors: Lim, J.H.;Zhan, A.;Ko, J.;Terzis, A.;Szanton, S.;Gitlin, L.;
Appeared in: IEEE Communications Magazine
Publication date: Jan 2012, volume: 50, issue:1, pages: 44 - 51
Publisher: IEEE
 
» A CMOS-compatible temperature sensor based on the gaseous thermal conduction dependent on temperature
Abstract:

Highlights

? We propose a temperature sensor with the gas as the sensing component. ? The sensor consists of the tungsten microhotplate as the heating component. ? The sensor has a good response to the temperature from -20 °C to 70 °C. ? The sensor can immerge in the pipeline to measure the temperature.


Autors: There are many different types of temperature sensors, including thermal resistor, thermocouple, thermal diode, etc. All the operational principles of them are based on the fact that some property of the sensor material is temperature-related. Based
Appeared in: Sensors and Actuators A: Physical
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» A Coarse-to-Fine Subpixel Registration Method to Recover Local Perspective Deformation in the Application of Image Super-Resolution
Abstract:
In this paper, a coarse-to-fine framework is proposed to register accurately the local regions of interest (ROIs) of images with independent perspective motions by estimating their deformation parameters. A coarse registration approach based on control points (CPs) is presented to obtain the initial perspective parameters. This approach exploits two constraints to solve the problem with a very limited number of CPs. One is named the point–point–line topology constraint, and the other is named the color and intensity distribution of segment constraint. Both of the constraints describe the consistency between the reference and sensed images. To obtain a finer registration, we have converted the perspective deformation into affine deformations in local image patches so that affine refinements can be used readily. Then, the local affine parameters that have been refined are utilized to recover precise perspective parameters of a ROI. Moreover, the location and dimension selections of local image patches are discussed by mathematical demonstrations to avoid the aperture effect. Experiments on simulated data and real-world sequences demonstrate the accuracy and the robustness of the proposed method. The experimental results of image super-resolution are also provided, which show a possible practical application of our method.
Autors: Zhou, F.;Yang, W.;Liao, Q.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Jan 2012, volume: 21, issue:1, pages: 53 - 66
Publisher: IEEE
 
» A Compact Hepta-Band Loop-Inverted F Reconfigurable Antenna for Mobile Phone
Abstract:
A folded loop-inverted F reconfigurable antenna for mobile phone applications is designed and the obtained results are discussed in this communication. It is shown that loop antenna mode and an inverted F antenna (IFA) mode are controlled by only one p-i-n diodes with simple bias circuit. The impedance can be matched by adopting a matching bridge for both the loop and IFA modes. In a compact volume of 60 5 5 mm , the proposed antenna operates in hepta-band, including GSM850, GSM900, GPS, DCS, PCS, UMTS and WLAN, with the return loss lower than 6 dB. A prototype of the proposed antenna is fabricated, measured, and obtained results including return loss, efficiency and gain, are presented.
Autors: Li, Y.;Zhang, Z.;Zheng, J.;Feng, Z.;Iskander, M. F.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2012, volume: 60, issue:1, pages: 389 - 392
Publisher: IEEE
 
» A comparative analysis of performance improvement schemes for cache memories
Abstract:
image

Highlights

? Cache memories are accessed non-uniformly causing significantly more conflicts on a few cache lines. ? Changing how caches are addressed and relocating addresses to less used cache lines improve performance. ? We show side-by-side comparison of several different techniques. ? The performance gained by these techniques are application dependent. ? Caches for multicore systems with multiple addressing schemes result in better cache performance.

Autors:

Graphical abstract

Caches for multicore systems with multiple addressing schemes resul
Appeared in: Computers & Electrical Engineering
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» A Comparative Study on Two Types of Automated Container Terminal Systems
Abstract:
This paper introduces a new type of automated container terminal system, which utilizes multistory frame bridges and rail-mounted trolleys to transport containers between the quay and the yard. For this new design concept, this paper makes an explorative study to identify the challenges and opportunity for it to be applied in transshipment hubs. We compare the transport efficiency and stacking capacity between this new system and the widely used AGV-based system. Several analytical models and performance measures are proposed for the quantitative comparisons between these two ACT systems.
Autors: Zhen, L.;Lee, L. H.;Chew, E. P.;Chang, D.-F.;Xu, Z.-X.;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Jan 2012, volume: 9, issue:1, pages: 56 - 69
Publisher: IEEE
 
» A Comparison of Four Robust Control Schemes for Field-Weakening Operation of Induction Motors
Abstract:
Four sensorless control schemes for the operation of induction motors in the field-weakening region are compared and assessed in terms of performance and complexity. These four control schemes fully utilize the maximum available voltage and current and can produce the maximum possible torque in the entire field-weakening region. For comparison, the four control schemes are implemented on the same experimental platform, i.e., the same DSP board, power inverter, and motor drive. In this way, it is possible to assess not only the performance of each solution, but also its requirements in terms of computational time, tuning complexity, parameter knowledge, and stability of operation.
Autors: Mengoni, M.;Zarri, L.;Tani, A.;Serra, G.;Casadei, D.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Jan 2012, volume: 27, issue:1, pages: 307 - 320
Publisher: IEEE
 
» A comprehensive study on the leakage current mechanisms of Pt/SrTiO3/Pt capacitor
Abstract:
The leakage current characteristics of SrTiO3 MIM capacitors, fabricated using atomic layer deposition, are investigated. The characteristics are highly sensitive to the polarity and magnitude of applied voltage bias, punctuated by sharp increases at high field. The characteristics are also asymmetric with bias and the negative to positive current crossover point always occurs at a negative voltage bias. In this work, a model comprising thermionic field emission and tunneling phenomena is proposed to explain the dependence of leakage current upon the device parameters quantitatively.
Autors: Mojarad, Shahin A.;Kwa, Kelvin S. K.;Goss, Jonathan P.;Zhou, Zhiyong;Ponon, Nikhil K.;Appleby, Daniel J. R.;Al-Hamadany, Raied A. S.;ONeill, Anthony;
Appeared in: Journal of Applied Physics
Publication date: Jan 2012, volume: 111, issue:1, pages: 014503 - 014503-6
Publisher: IEEE
 
» A constraint sampling approach for multi-stage robust optimization
Abstract:
We propose a tractable approximation scheme for convex (not necessarily linear) multi-stage robust optimization problems. We approximate the adaptive decisions by finite linear combinations of prescribed basis functions and demonstrate how one can optimize over these decision rules at low computational cost through constraint randomization. We obtain a-priori probabilistic guarantees on the feasibility properties of the optimal decision rule by applying existing constraint sampling techniques to the semi-infinite problem arising from the decision rule approximation. We demonstrate that for a suitable choice of basis functions, the approximation converges as the size of the basis and the number of sampled constraints tend to infinity. The approach yields an algorithm parameterized in the basis size, the probability of constraint violation and the confidence that this probability will not be exceeded. These three parameters serve to tune the trade-off between optimality and feasibility of the decision rules and the computational cost of the algorithm. We assess the convergence and scalability properties of our approach in the context of two inventory management problems.
Autors: Phebe Vayanos, Daniel Kuhn, Berç Rustem
Appeared in: Automatica
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» A contactless methodology of picking up micro-particles from rigid surfaces by acoustic radiation force
Abstract:
Controlled movement and pick up of small object from a rigid surface is a primary challenge in many applications. In this paper, a contactless methodology of picking up micro-particles within deionized water from rigid surfaces by acoustic radiation force is presented. In order to achieve this, an acoustic radiation force was generated by 1.75 MHz transducers. A custom built setup facilitates the optimization of the sound field by varying the parameters such as sound source size and source position. The three-dimensional pressure distributions are measured and its relative sound field is also characterized accordingly. The standing wave field has been formed and it is mainly composed of two obliquely incident plane waves and their reflectors. We demonstrated the gripping and positioning of silica beads, SiO2, and aluminum micro-particles of 100 μm to 500 μm in size with this method using acoustic radiation force. The acoustic radiation force generated is well controlled, contactless, and in the tens of nano-Newton range which allowed us to manipulate relative big micro objects such as MEMS components as well as moving objects such as living cells. The proposed method provided an alternative form of contactless operating environment with scalable dimensions suitable for the manipulating of small objects. This permits high-throughput processing and reduction in time required for MEMS assembling, cell biomechanics, and biotechnology applications.
Autors: Jia, Kun;Yang, Keji;Fan, Zongwei;Ju, Bing-Feng;
Appeared in: Review of Scientific Instruments
Publication date: Jan 2012, volume: 83, issue:1, pages: 014902 - 014902-11
Publisher: IEEE
 
» A controller design based on a functionalfilter for descriptor systems: The time and frequency domain cases
Abstract:
In this paper, we investigate the time and frequency domain designs of a controller based on a functional filter for both continuous-time and discrete-time multivariable descriptor systems. The order of this controller is equal to the dimension of the state to be estimated, and the control gain is designed usingtechniques. The time procedure is based on the unbiasedness of the estimation error using a Sylvester equation; then a new method for avoiding the derivative of the disturbance vector in the observation error dynamics is proposed. This problem is solved by means of linear matrix inequalities (LMIs). The frequency domain procedure design is derived from time domain results, where we propose some suitable matrix fraction descriptions (MFDs) and, most importantly, the factorization approach permits us to give a polynomial parameterization of the functionalfilter-based controller.
Autors: Montassar Ezzine, Harouna Souley Ali, Mohamed Darouach, Hassani Messaoud
Appeared in: Automatica
Publication date: Jan 2012
Publisher: Elsevier B.V.
 
» A Convex Optimization Approach to Synthesizing Bounded Complexity Filters
Abstract:
We consider the worst-case estimation problem in the presence of unknown but bounded noise. Contrary to stochastic approaches, the goal here is to confine the estimation error within a bounded set. Previous work dealing with the problem has shown that the complexity of estimators based upon the idea of constructing the state consistency set (e.g., the set of all states consistent with the a priori information and experimental data) cannot be bounded a priori, and can, in principle, continuously increase with time. To avoid this difficulty we propose a class of bounded complexity filters, based upon the idea of confining —length error sequences (rather than states) to hyperrectangles. The main result of the technical note shows that this can be accomplished by using linear time invariant filters of order no larger than . Further, synthesizing these filters reduces to a combination of convex optimization and line search.
Autors: Blanchini, F.;Sznaier, M.;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Jan 2012, volume: 57, issue:1, pages: 216 - 221
Publisher: IEEE
 
» A Critique of Geoengineering
Abstract:
Interest in “geoengineering” technologies has increased significantly over the past few years because of concern about global climate change coupled with a growing recognition of the inadequacies of the Kyoto Protocol and the ongoing climate change negotiating process.
Autors: Allenby, B.;
Appeared in: IEEE Potentials
Publication date: Jan 2012, volume: 31, issue:1, pages: 22 - 26
Publisher: IEEE
 
» A Cyber–Physical Systems Approach to Data Center Modeling and Control for Energy Efficiency
Abstract:
This paper presents data centers from a cyber–physical system (CPS) perspective. Current methods for controlling information technology (IT) and cooling technology (CT) in data centers are classified according to the degree to which they take into account both cyber and physical considerations. To evaluate the potential impact of coordinated CPS strategies at the data center level, we introduce a control-oriented model that represents the data center as two coupled networks: a computational network representing the cyber dynamics and a thermal network representing the physical dynamics. These networks are coupled through the influence of the IT on both networks: servers affect both the quality of service (QoS) delivered by the computational network and the generation of heat in the thermal network. Using this model, three control strategies are evaluated with respect to their energy efficiency and computational performance: a baseline strategy that ignores CPS considerations, an uncoordinated strategy that manages the IT and CT independently, and a coordinated strategy that manages the IT and CT together to achieve optimal performance with respect to both QoS and energy efficiency. Simulation results show that the benefits to be realized from coordinating the control of IT and CT depend on the distribution and heterogeneity of the computational and cooling resources throughout the data center. A new cyber–physical index (CPI) is introduced as a measure of this combined distribution of cyber and physical effects in a given data center. We illustrate how the CPI indicates the potential impact of using coordinated CPS control strategies.
Autors: Parolini, L.;Sinopoli, B.;Krogh, B. H.;Wang, Z.;
Appeared in: Proceedings of the IEEE
Publication date: Jan 2012, volume: 100, issue:1, pages: 254 - 268
Publisher: IEEE
 
» A Darlington-Enhanced CMOS Oscillator Architecture
Abstract:
A fully differential CMOS oscillator using Darlington composite pMOS transistors is presented. The composite transistor structure increases gain of the negative-Gm stage for a reliable startup and improves device reliability due to use of high-voltage transistors. To achieve good phase noise available with large voltages and the speed of small active devices in a modern CMOS process, a higher (2.8 V) power supply requiring a combination of low- and high-voltage transistors is used. In addition, the oscillator uses negative feedback to reduce amplitude variation due to -tank loading. Circuit functionality is confirmed with a test circuit fabricated in a standard 130-nm CMOS process. The oscillator reaches a phase noise better than 121.2 dBc/Hz at 1-MHz offset across a tuning range of 3015 to 5298 MHz while consuming a less than 10.6-mA current from a 2.8-V power supply.
Autors: Lehtonen, T. A.;Ruippo, P.;Keitaanniemi, T.;Tchamov, N. T.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2012, volume: 59, issue:1, pages: 11 - 15
Publisher: IEEE
 
» A Direct Algorithm for Nonorthogonal Approximate Joint Diagonalization
Abstract:
While a pair of matrices can almost always be exactly and simultaneously diagonalized by a generalized eigendecomposition, no exact solution exists in the case of a set with more than two matrices. This problem, termed approximate joint diagonalization (AJD), is instrumental in blind signal processing. When the set of matrices to be jointly diagonalized includes at least linearly independent matrices, we propose a suboptimal but closed-form solution for AJD in the direct least-squares sense. The corresponding non-iterative algorithm is given the acronym (DIagonalization using Equivalent Matrices). Extensive numerical simulations show that is both fast and accurate compared to the state-of-the-art iterative AJD algorithms.
Autors: Chabriel, G.;Barrere, J.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Jan 2012, volume: 60, issue:1, pages: 39 - 47
Publisher: IEEE
 
» A Direct Approach to Optimal Feeder Routing for Radial Distribution System
Abstract:
Much of the research has been focused on developing the optimization techniques, varying from classical to nontraditional soft computing techniques, to solve the distribution system planning problem. Most of the methods preserve the distinctions and niceties, but dependent on complex search algorithm with a lot of convergence related issues that require more time to reach a firm conclusion at planning stage. This paper proposes a simple direct solution that significantly reduces the inherent difficulties of finding the solution and ensures optimum solution at the same time. Moreover, the concept of principle of optimality is effectively used to make the proposed technique more computationally efficient and useful. The effectiveness of the developed planning technique has been verified with different test cases.
Autors: Samui, A.;Singh, S.;Ghose, T.;Samantaray, S. R.;
Appeared in: IEEE Transactions on Power Delivery
Publication date: Jan 2012, volume: 27, issue:1, pages: 253 - 260
Publisher: IEEE
 
» A Dual Purpose Principal and Minor Subspace Gradient Flow
Abstract:
The dual purpose principal and minor subspace gradient flow can be used to track principal subspace (PS) and if altered simply by the sign, it can also serve as a minor subspace (MS) trackor. This is of practical significance in the implementations of algorithms. In this paper, a unified information criterion is proposed and a dual purpose principal and minor subspace gradient flow is derived based on the information criterion. In this dual purpose gradient flow, the weight matrix length is self-stabilizing, i.e., moving towards unit length in each learning step. The energy function associated with the dual purpose gradient flow for tracking PS and MS is given, and it exhibits a unique global minimum attained if and only if its state matrices span the PS or MS of the autocorrelation matrix of a vector data stream. The other stationary points of its energy function are (unstable) saddle points. The proposed dual purpose gradient flow can efficiently track an orthonormal basis of the PS or MS, which is illustrated through simulation experiments.
Autors: Kong, X.;Hu, C.;Han, C.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Jan 2012, volume: 60, issue:1, pages: 197 - 210
Publisher: IEEE
 
» A dual-channel, focusing x-ray spectrograph with uniform dispersion for Z pinch plasmas measurement
Abstract:
A dual-channel, focusing x-ray spectrograph with uniform dispersion (i.e., the linear dispersion of this spectrograph is a constant) is described for measuring the x-ray spectra emission from the hot, dense Al Z pinch plasmas. The spectrograph uses double uniform-dispersed crystals (e.g., a Quartz 1010 crystal and a Mica 002 crystal) as dispersion elements and a double-film box as detector to achieve the simultaneous recording of the time integrated spectrum covering a wide spectral range of ∼5–9 Å. Since this spectrograph disperse the x-rays on the detector plane with uniform spacing for every wavelength, it needs not the calibration of the wavelength with spatial coordinate, thereby own the advantages of easiness and veracity for spectra identification. The design of this spectrograph and the example of experiment on the “Yang” accelerator are presented.
Autors: Yang, Qingguo;Li, Zeren;Chen, Guanhua;Ye, Yan;Huang, Xianbin;Cai, Hongchun;Li, Jing;Xiao, Shali;
Appeared in: Review of Scientific Instruments
Publication date: Jan 2012, volume: 83, issue:1, pages: 013106 - 013106-6
Publisher: IEEE
 
» A Dual-Feedforward Carrier-Modulated Second-Order Class-D Amplifier With Improved THD
Abstract:
The advancement of power MOSFET fabrication technology has aided the reduction of power stage errors in class-D amplifiers (amps). This reduction reveals intrinsic distortion, which is a key performance limiter in modern pulsewidth-modulation (PWM)-based class-D amps. In this brief, a dual-feedforward carrier modulation topology is proposed to reduce the intrinsic harmonic distortion of a second-order loop filter class-D amp. The proposed design achieves a total harmonic distortion of less than 0.01% for input frequency up to 6 kHz, and it has an idle carrier frequency of 310 kHz. Such low carrier frequency is particularly important in high-power devices as it guarantees low switching loss. Moreover, the carrier frequency varies in a narrow range in the presence of an input signal and helps to suppress the audible intermodulation distortion in multichannel applications. The prototype circuit is implemented and tested on a printed circuit board using discrete components.
Autors: Yu, J.;Tan, M. T.;Goh, W. L.;Cox, S. M.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2012, volume: 59, issue:1, pages: 35 - 39
Publisher: IEEE
 
» A Dual-Mode CMOS RF Power Amplifier With Integrated Tunable Matching Network
Abstract:
A dual-mode CMOS power amplifier (PA) with an integrated tunable matching network is presented. A switched capacitor is fully analyzed to implement a tunable matching network in terms of power-handling capability, tuning ratio, quality factor, and linearity. Based on the presented consideration, a 3.3-V 2.4-GHz fully integrated CMOS dual-mode PA is implemented in a 0.18- m CMOS process. The PA has two power modes, high-power and low-power (LP), and each mode is optimally matched by the tunable matching network. The LP mode enables more than 50% dc current reduction from 0- to 10-dBm power range. The improved efficiency in this study is approximately twice that of other multimode CMOS PAs reported thus far.
Autors: Yoon, Y.;Kim, J.;Kim, H.;An, K. H.;Lee, O.;Lee, C.-H.;Kenney, J. S.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2012, volume: 60, issue:1, pages: 77 - 88
Publisher: IEEE
 
» A Fast Loss and Temperature Simulation Method for Power Converters, Part I: Electrothermal Modeling and Validation
Abstract:
Simulation of power converters has traditionally been carried out using simplified models to shorten simulation time. This will compromise the accuracy of the results. A proposed fast simulation method for simulating converter losses and device temperatures over long mission profiles (load cycles) is described in this paper. It utilizes accurate physics-based models for the device losses, and is validated with experimentally obtained results.
Autors: Bryant, A.;Parker-Allotey, N.-A.;Hamilton, D.;Swan, I.;Mawby , P.;Ueta, T.;Nishijima, T.;Hamada, K.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Jan 2012, volume: 27, issue:1, pages: 248 - 257
Publisher: IEEE
 
» A field study of aging in paper-oil insulation systems
Abstract:
The paper used to insulate the windings of power transformers is mostly made from wood pulp, a cellulosic material. Over decades the paper is slowly attacked by water, oxygen, oil acids, and high temperatures and eventually degrades to the point where it is no longer an effective insulator. The transformer is then likely to fail. Power utilities need to know when a transformer is nearing the end of its useful life in order to plan its replacement. However, a problem with monitoring the condition of the paper within a transformer is that it may be difficult to obtain a sample to test. Furthermore, a particular sample may not accurately reflect the overall paper condition. A power transformer operating in Australia failed in 2010. Thus we had the opportunity to study the paper condition at various points within the transformer and evaluate the validity of the current understanding of paper aging. In this article we discuss the mechanisms of cellulose degradation, and the associated equations, and apply them to the paper insulation in the failed transformer.
Autors: Lelekakis, N.;Guo, W.;Martin, D.;Wijaya, J.;Susa, D.;
Appeared in: IEEE Electrical Insulation Magazine
Publication date: Jan 2012, volume: 28, issue:1, pages: 12 - 19
Publisher: IEEE
 
» A Filter Bank and a Self-Tuning Adaptive Filter for the Harmonic and Interharmonic Estimation in Power Signals
Abstract:
We present a method that combines a filter bank (FB) system with adaptive filtering to estimate parameters describing the harmonics and the interharmonics present in power signals. The proposed method decomposes the input power signal using an FB system that is a modular binary tree structure with the fundamental FBs arranged successively in each stage. The fundamental FB is designed to separate the odd and even harmonics to reduce spectral leakage. An adaptive filter is used to improve the accuracy of parameter estimation for each decomposed harmonic. Parameters describing the interharmonic components are estimated from the error signal of the adaptive filter, which is self-tuning. The estimation of the amplitude and frequency of each of the harmonic and interharmonic components is done recursively. Computer simulations were performed on synthesized signals to assess the performance of the method.
Autors: Sohn, S.-W.;Lim, Y.-B.;Yun, J.-J.;Choi, H.;Bae, H.-D.;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Jan 2012, volume: 61, issue:1, pages: 64 - 73
Publisher: IEEE
 
» A flat transistor comeback?
Abstract:
After years of doping, straining, shrinking, and tweaking, engineers seem to have exhausted all their strategies for improving the planar complementary metal-oxide semiconductor (CMOS) transistors at the heart of today??s computer processors. Producers of cutting-edge chips are now resorting to new structures?? building up in three dimensions or constructing transistors in ultrathin layers of silicon??to ensure that devices keep shrinking and that Moore's Law keeps going just a bit longer.
Autors: Courtland, R.;
Appeared in: IEEE Spectrum
Publication date: Jan 2012, volume: 49, issue:1, pages: 18 - 21
Publisher: IEEE
 
» A Flexible Approach to Improving System Reliability with Virtual Lockstep
Abstract:
There is an increasing need for fault tolerance capabilities in logic devices brought about by the scaling of transistors to ever smaller geometries. This paper presents a hypervisor-based replication approach that can be applied to commodity hardware to allow for virtually lockstepped execution. It offers many of the benefits of hardware-based lockstep while being cheaper and easier to implement and more flexible in the configurations supported. A novel form of processor state fingerprinting is also presented, which can significantly reduce the fault detection latency. This further improves reliability by triggering rollback recovery before errors are recorded to a checkpoint. The mechanisms are validated using a full prototype and the benchmarks considered indicate an average performance overhead of approximately 14 percent with the possibility for significant optimization. Finally, a unique method of using virtual lockstep for fault injection testing is presented and used to show that significant detection latency reduction is achievable by comparing only a small amount of data across replicas.
Autors: Jeffery, Casey M.;Figueiredo, Renato J. O.;
Appeared in: IEEE Transactions on Dependable and Secure Computing
Publication date: Jan 2012, volume: 9, issue:1, pages: 2 - 15
Publisher: IEEE
 
» A Flexible Approach to Multisession Trust Negotiations
Abstract:
Trust Negotiation has shown to be a successful, policy-driven approach for automated trust establishment, through the release of digital credentials. Current real applications require new flexible approaches to trust negotiations, especially in light of the widespread use of mobile devices. In this paper, we present a multisession dependable approach to trust negotiations. The proposed framework supports voluntary and unpredicted interruptions, enabling the negotiating parties to complete the negotiation despite temporary unavailability of resources. Our protocols address issues related to validity, temporary loss of data, and extended unavailability of one of the two negotiators. A peer is able to suspend an ongoing negotiation and resume it with another (authenticated) peer. Negotiation portions and intermediate states can be safely and privately passed among peers, to guarantee the stability needed to continue suspended negotiations. We present a detailed analysis showing that our protocols have several key properties, including validity, correctness, and minimality. Also, we show how our negotiation protocol can withstand the most significant attacks. As by our complexity analysis, the introduction of the suspension and recovery procedures, and mobile negotiations does not significantly increase the complexity of ordinary negotiations. Our protocols require a constant number of messages whose size linearly depend on the portion of trust negotiation that has been carried before the suspensions.
Autors: Squicciarini, Anna;Bertino, Elisa;Trombetta, Alberto;Braghin, Stefano;
Appeared in: IEEE Transactions on Dependable and Secure Computing
Publication date: Jan 2012, volume: 9, issue:1, pages: 16 - 29
Publisher: IEEE
 
» A flexible Bloch mode method for computing complex band structures and impedances of two-dimensional photonic crystals
Abstract:
We present a flexible method that can calculate Bloch modes, complex band structures, and impedances of two-dimensional photonic crystals from scattering data produced by widely available numerical tools. The method generalizes previous work which relied on specialized multipole and finite element method (FEM) techniques underpinning transfer matrix methods. We describe the numerical technique for mode extraction, and apply it to calculate a complex band structure and to design two photonic crystal antireflection coatings. We do this for frequencies at which other methods fail, but which nevertheless are of significant practical interest.
Autors: Lawrence, Felix J.;Botten, Lindsay C.;Dossou, Kokou B.;McPhedran, R. C.;Martijn de Sterke, C.;
Appeared in: Journal of Applied Physics
Publication date: Jan 2012, volume: 111, issue:1, pages: 013105 - 013105-8
Publisher: IEEE
 
» A Framework for Learning Comprehensible Theories in XML Document Classification
Abstract:
XML has become the universal data format for a wide variety of information systems. The large number of XML documents existing on the web and in other information storage systems makes classification an important task. As a typical type of semistructured data, XML documents have both structures and contents. Traditional text learning techniques are not very suitable for XML document classification as structures are not considered. This paper presents a novel complete framework for XML document classification. We first present a knowledge representation method for XML documents which is based on a typed higher order logic formalism. With this representation method, an XML document is represented as a higher order logic term where both its contents and structures are captured. We then present a decision-tree learning algorithm driven by precision/recall breakeven point (PRDT) for the XML classification problem which can produce comprehensible theories. Finally, a semi-supervised learning algorithm is given which is based on the PRDT algorithm and the cotraining framework. Experimental results demonstrate that our framework is able to achieve good performance in both supervised and semi-supervised learning with the bonus of producing comprehensible learning theories.
Autors: Wu, Jemma;
Appeared in: IEEE Transactions on Knowledge and Data Engineering
Publication date: Jan 2012, volume: 24, issue:1, pages: 1 - 14
Publisher: IEEE
 
» A Framework for Routing Performance Analysis in Delay Tolerant Networks with Application to Noncooperative Networks
Abstract:
In this paper, we present a framework for analyzing routing performance in delay tolerant networks (DTNs). Differently from previous work, our framework is aimed at characterizing the exact distribution of relevant performance metrics, which is a substantial improvement over existing studies characterizing either the expected value of the metric, or an asymptotic approximation of the actual distribution. In particular, the considered performance metrics are packet delivery delay, and communication cost, expressed as number of copies of a packet circulating in the network at the time of delivery. Our proposed framework is based on a characterization of the routing process as a stochastic coloring process and can be applied to model performance of most stateless delay tolerant routing protocols, such as epidemic, two-hops, and spray and wait. After introducing the framework, we present examples of its application to derive the packet delivery delay and communication cost distribution of two such protocols, namely epidemic and two-hops routing. Characterizing packet delivery delay and communication cost distribution is important to investigate fundamental properties of delay tolerant networks. As an example, we show how packet delivery delay distribution can be used to estimate how epidemic routing performance changes in presence of different degrees of node cooperation within the network. More specifically, we consider fully cooperative, noncooperative, and probabilistic cooperative scenarios, and derive nearly exact expressions of the packet delivery rate (PDR) under these scenarios based on our proposed framework. The comparison of the obtained packet delivery rate estimation in the various cooperation scenarios suggests that even a modest level of node cooperation (probabilistic cooperation with a low probability of cooperation) is sufficient to achieve 2-fold performance improvement with respect to the most pessimistic scenario in which all potential forwarders dr- - op packets.
Autors: Resta, Giovanni;Santi, Paolo;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Jan 2012, volume: 23, issue:1, pages: 2 - 10
Publisher: IEEE
 
» A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor
Abstract:
This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of integration. The paper describes the chip floor plan, the power delivery network, energy conservation techniques, the clock generation and distribution, the on-die thermal sensors, and a novel debug port.
Autors: Yuffe, M.;Mehalel, M.;Knoll, E.;Shor, J.;Kurts, T.;Altshuler, E.;Fayneh, E.;Luria, K.;Zelikson, M.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 194 - 205
Publisher: IEEE
 
» A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS
Abstract:
On-chip DC-DC converters have the potential to offer fine-grain power management in modern chip-multiprocessors. This paper presents a fully integrated 3-level DC-DC converter, a hybrid of buck and switched-capacitor converters, implemented in 130 nm CMOS technology. The 3-level converter enables smaller inductors (1 nH) than a buck, while generating a wide range of output voltages compared to a 1/2 mode switched-capacitor converter. The test-chip prototype delivers up to 0.85 A load current while generating output voltages from 0.4 to 1.4 V from a 2.4 V input supply. It achieves 77% peak efficiency at power density of 0.1 W/mm and 63% efficiency at maximum power density of 0.3 W/mm . The converter scales output voltage from 0.4 V to 1.4 V (or vice-versa) within 20 ns at a constant 450 mA load current. A shunt regulator reduces peak-to-peak voltage noise from 0.27 V to 0.19 V under pseudo-randomly fluctuating load currents. Using simulations across a wide range of design parameters, the paper compares conversion efficiencies of the 3-level, buck and switched-capacitor converters.
Autors: Kim, W.;Brooks, D.;Wei, G.-Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2012, volume: 47, issue:1, pages: 206 - 219
Publisher: IEEE
 

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