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Electrical and Electronics Engineering publications abstract of: 01-2011 sorted by title, page: 0
» $F^2$Dock: Fast Fourier Protein-Protein Docking
Abstract:
The functions of proteins are often realized through their mutual interactions. Determining a relative transformation for a pair of proteins and their conformations which form a stable complex, reproducible in nature, is known as docking. It is an important step in drug design, structure determination, and understanding function and structure relationships. In this paper, we extend our nonuniform fast Fourier transform-based docking algorithm to include an adaptive search phase (both translational and rotational) and thereby speed up its execution. We have also implemented a multithreaded version of the adaptive docking algorithm for even faster execution on multicore machines. We call this protein-protein docking code F2Dock (F2 = Fast Fourier). We have calibrated F2Dock based on an extensive experimental study on a list of benchmark complexes and conclude that F2Dock works very well in practice. Though all docking results reported in this paper use shape complementarity and Coulombic-potential-based scores only, F2Dock is structured to incorporate Lennard-Jones potential and reranking docking solutions based on desolvation energy .
Autors: Bajaj, C.L.;Chowdhury, R.;Siddahanavalli, V.;
Appeared in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Publication date: Jan 2011, volume: 8, issue:1, pages: 45 - 58
Publisher: IEEE
 
» “Vector Cross-Product Direction-Finding” With an Electromagnetic Vector-Sensor of Six Orthogonally Oriented But Spatially Noncollocating Dipoles/Loops
Abstract:
Direction-finding capability has recently been advanced by synergies between the customary approach of inter ferometry and the new approach of “vector cross product” based Poynting-vector estimator. The latter approach measures the incident electromagnetic wavefield for each of its six electromagnetic components, all at one point in space, to allow a vector cross-product between the measured electric-field vector and the measured magnetic-field vector. This would lead to the estimation of each incident source's Poynting-vector, which (after proper norm-normalization) would then reveal the corresponding Cartesian direction-cosines, and thus the azimuth-elevation arrival angles. Such a “vector cross product” algorithm has been predicated on the measurement of all six electromagnetic components at one same spatial location. This physically requires an electromagnetic vector-sensor, i.e., three identical but orthogonally oriented electrically short dipoles, plus three identical but orthogonally oriented magnetically small loops—all spatially collocated in a point-like geometry. Such a complicated “vector-antenna” would require exceptionally effective electromagnetic isolation among its six component-antennas. To minimize mutual coupling across these collocated antennas, considerable antennas-complexity and hardware cost could be required. Instead, this paper shows how to apply the “vector cross-product” direction-of-arrival estimator, even if the three dipoles and the three loops are located separately (instead of collocating in a point-like geometry). This new scheme has great practical value, in reducing mutual coupling, in simplifying the antennas hardware, and in sparsely extending the spatial aperture to refine the direction-finding accuracy by orders of magnitude.
Autors: Wong, K. T.;Yuan, X.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Jan 2011, volume: 59, issue:1, pages: 160 - 171
Publisher: IEEE
 
» 'COMSOC 2020' in the converged communications era [The President's Page]
Abstract:
A year has passed since I wrote my first President's Column, bringing me half way through my presidential term. Looking back a year ago, I recollect the view of the road ahead was hazy, obscured by the global economic downturn, but now our society¿s outlook is much brighter.
Autors: Lee, B.G.;
Appeared in: IEEE Communications Magazine
Publication date: Jan 2011, volume: 49, issue:1, pages: 6 - 13
Publisher: IEEE
 
» 0.5-6 ghz low-voltage low-power mixer using a modified cascode topology in 0.18 μm cmos technology
Abstract:
A broadband low-voltage low-power down-conversion mixer using a 0.18 μm standard CMOS process is presented. The proposed mixer uses a modified cascode topology with a bulk-injection technique to achieve lowvoltage and low-power performance. The mixer features a maximum conversion gain of 6 dB at a radio frequency (RF) of 2.4 GHz, a single-sideband (SSB) noise figure of 15.2 dB, and an input third-order intercept point (IIP3) of 0 dBm. Moreover, the chip area of the mixer core is only 0.15 ?? 0.23 mm2. The measured 3 dB RF bandwidth is from 0.5 to 6 GHz with an intermediate frequency (IF) of 100 MHz. The optimum DC supply voltage (VDD) can be scaled down to 0.7 V with a drain current within 0.4 mA. The supply voltage and DC power of this circuit can be compatible with an advanced 90 or 65 nm CMOS technology.
Autors: Liang, K.-H.;Chang, H.-Y.;
Appeared in: IET Microwaves, Antennas & Propagation
Publication date: Jan 2011, volume: 5, issue:2, pages: 167 - 174
Publisher: IEEE
 
» 1.3- m In(Ga)As Quantum-Dot VCSELs Fabricated by Dielectric-Free Approach With Surface-Relief Process
Abstract:
We present the 1.3- m In(Ga)As quantum-dot (QD) vertical-cavity surface-emitting lasers (VCSELs) fabricated by the dielectric-free (DF) approach with the surface-relief (SR) process. Compared with the conventional dielectric-dependent (DD) method, the lower differential resistance and improved output power have been achieved by the DF approach. With the same oxide aperture area, the differential resistance is reduced by 36.47% and output power is improved by 78.32% under continuous-wave operation; it is up to 3.42 mW under pulsed operation with oxide aperture diameter 15 m. The surface-relief technique is also applied, for the first time, in 1.3- m QD VCSELs, and it effectively enhances the emission of the fundamental mode. The characteristic of small signal modulation response is also analyzed.Pub _bookmark Command="[Quick Mark]"
Autors: Xu, D. W.;Yoon, S. F.;Ding, Y.;Tong, C. Z.;Fan, W. J.;Zhao, L. J.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2011, volume: 23, issue:2, pages: 91 - 93
Publisher: IEEE
 
» 1.52 μm electroluminescence from GaAs-based quantum dot bilayers
Abstract:
InGaAs strain reducing layers (SRLs) are applied to InAs bilayer quantum dots (QDs) grown by molecular beam epitaxy on GaAs substrates. By control of the QD size and density and the composition of the SRLs, peak ground state electroluminescence of up to 1.52 /sp mu/m is demonstrated from devices incorporating five QD bilayers, without the need for a metamorphic buffer layer.
Autors: Majid, M.A.;Childs, D.T.D.;Shahid, H.;Airey, R.;Kennedy, K.;Hogg, R.A.;Clarke, E.;Spencer, P.;Murray, R.;
Appeared in: Electronics Letters
Publication date: Jan 2011, volume: 47, issue:1, pages: 44 - 46
Publisher: IEEE
 
» 10-GHz Mode-Locked Extended Cavity Laser Integrated With Surface-Etched DBR Fabricated by Quantum-Well Intermixing
Abstract:
The 10-GHz passively mode-locked AlGaInAs/InP 1.55- m extended cavity lasers integrated with optimized surface-etched distributed Bragg mirrors have been fabricated. A quantum-well intermixing process was used to provide low-absorption loss gratings with accurate wavelength control. The lasers produce 2.99-ps sech -pulses with a time-bandwidth product (TBP) of 0.51.
Autors: Hou, L.;Haji, M.;Dylewicz, R.;Qiu, B.;Bryce, A. C.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2011, volume: 23, issue:2, pages: 82 - 84
Publisher: IEEE
 
» 150 GHz Complementary Anti-Parallel Diode Frequency Tripler in 130 nm CMOS
Abstract:
The first complementary anti-parallel Schottky diode frequency tripler in CMOS is demonstrated. The tripler exhibits minimum conversion loss, maximum output power at 150 GHz, and 3 db output frequency range of .
Autors: Shim, D.;Mao, C.;Sankaran, S.;O, K. K.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2011, volume: 21, issue:1, pages: 43 - 45
Publisher: IEEE
 
» 2.4 GHz antenna array using vector modulatorbased active phase shifters for beamforming
Abstract:
This study presents the analysis and the experimental results of a 2.4 GHz antenna array using vector modulators working as active phase shifters for beamforming. With the use of such an active phase shifter, a continuously controlled 3608 phase shifting range can be achieved leading to an efficient beamforming architecture. To show the robustness of this system, a theoretical analysis is first performed in order to quantify the impact of vector modulators I/Q mismatch on the obtained gains and phase shifts. In the same way, the impact of the vector modulators noisy command voltages is also quantified by system simulations. The experimental results of the 2.4 GHz vector modulators show a maximum relative gain error close to 2.5% and an absolute phase error less than 38. The measured 1 dB output compression point is 26 dBm. Measurements of the prototype including an array of four 'patch' antennas controlled by the vector modulators were also performed in an anechoic chamber. The results show good agreement between measured and theoretical radiation patterns.
Autors: Hutu, F.;Cordeau, D.;Paillot, J.-M.;
Appeared in: IET Microwaves, Antennas & Propagation
Publication date: Jan 2011, volume: 5, issue:2, pages: 245 - 254
Publisher: IEEE
 
» 2011 begins with raft of e-border initiatives
Abstract:
Border authorities worldwide moved ahead with biometrics-based initiatives at the close of 2010.
Autors: [No author name available]
Appeared in: Biometric Technology Today
Publication date: Jan 2011
Publisher: Elsevier B.V.
 
» 2011 Editorial—A Tribute and a Challenge
Abstract:
Autors: Jensen, m. A.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2011, volume: 59, issue:1, pages: 2 - 3
Publisher: IEEE
 
» 24-GOPS 4.5- Digital Cellular Neural Network for Rapid Visual Attention in an Object-Recognition SoC
Abstract:
This paper presents the Visual Attention Engine (VAE), which is a digital cellular neural network (CNN) that executes the VA algorithm to speed up object-recognition. The proposed time-multiplexed processing element (TMPE) CNN topology achieves high performance and small area by integrating 4800 (80 60) cells and 120 PEs. Pipelined operation of the PEs and single-cycle global shift capability of the cells result in a high PE utilization ratio of 93%. The cells are implemented by 6T static random access memory-based register files and dynamic shift registers to enable a small area of 4.5 . The bus connections between PEs and cells are optimized to minimize power consumption. The VAE is integrated within an object-recognition system-on-chip (SoC) fabricated in the 0.13- complementary metal-oxide—semiconductor process. It achieves 24 GOPS peak performance and 22 GOPS sustained performance at 200 MHz enabling one CNN iteration on an 80 60 pixel image to be completed in just 4.3 . With VA enabled using the VAE, the workload of the object-recognition SoC is significantly reduced, resulting in 83% higher frame rate while consuming 45% less energy per frame without degradation of recognition accuracy.
Autors: Lee, S.;Kim, M.;Kim, K.;Kim, J.-Y.;Yoo, H.-J.;
Appeared in: IEEE Transactions on Neural Networks
Publication date: Jan 2011, volume: 22, issue:1, pages: 64 - 73
Publisher: IEEE
 
» 3D Displays without Glasses: Coming to a Screen near You
Abstract:
The most common 3D displays require users to wear special glasses, which has limited the technology's popularity. Now, researchers and vendors are working on glasses-free 3D displays.
Autors: Lawton, George;
Appeared in: Computer
Publication date: Jan 2011, volume: 44, issue:1, pages: 17 - 19
Publisher: IEEE
 
» 65 nm CMOS receiver with 4.2 dB NF and 66 dB gain for 60 GHz applications
Abstract:
A direct conversion receiver for 60 GHz applications is fabricated in 65 nm CMOS. It consists of three low-noise amplifier gain stages, an RF mixer, a lowpass filter and a three-stage programmable gain amplifier. An overall minimum noise figure (NF) of 4.2 dB and maximum gain of 66 dB is achieved by the receiver occupying a core area of 0.26 mm2 while drawing 36 mA of current from a 1 V supply.
Autors: Wang, N.Y.;Wu, H.;Liu, J.Y.C.;Chang, M.-C.F.;
Appeared in: Electronics Letters
Publication date: Jan 2011, volume: 47, issue:1, pages: 15 - 17
Publisher: IEEE
 
» : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation
Abstract:
This paper presents a novel approach to extending the life of current-based test techniques for the detection and diagnosis of bridging defects. Called (Complementary ), this approach combines a modified test pattern generation with a simple post-processing of measurements (namely additions and subtractions) such that the resulting measurement combination equals zero. Consequently, eliminates the main current variance sources: wafer-to-wafer, IC-to-IC and vector-to-vector variations; the only remaining source is the measurement variance. The modified test pattern generation is based on the innovative concept of transient-fault test pattern decomposition and the use of layout information to target realistic bridging defect sites. Verification based on logic simulation confirms that the combination of the resulting subset of fault-free measurements is equal to 0. Using this promising new technique, bridging defect detection capability can be improved by orders of magnitude. Simulation results also show that this improved detection capability may be necessary even for low-power devices.
Autors: Thibeault, C.;Hariri, Y.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2011, volume: 19, issue:1, pages: 130 - 141
Publisher: IEEE
 
» Sensing for IGBT Protection in NPC Three Level Converters—Causes For Spurious Trippings and Their Elimination
Abstract:
Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the sense fault signals of the inner devices of the leg.
Autors: Jain, A. K.;Ranganathan, V. T.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Jan 2011, volume: 26, issue:1, pages: 298 - 307
Publisher: IEEE
 
» -Segments-Based Geometric Modeling of VLS Scan Lines
Abstract:
A novel -segments-based 2-D geometric modeling schematic is proposed for characterizing the scan lines of vehicle-based laser scanning (VLS) with just a few geometric primitives. VLS has been developing quickly as a new research focus recently, but the relevant data processing techniques lag behind the system establishment due to the associated huge standwise point clouds collected in a real 3-D sense. To solve this issue, the often-assumed sampling mode based on scan lines suggests an alternative frame for exploring new efficient methodologies in diverse applications. As we know, principal segments can reflect the morphological signatures of the scatter-point-represented objects, and besides, profiles comprised by various open and close outlines can be geometrically modeled by line segments and ellipses, respectively. By combining these two merits, the -segments-based geometric modeling algorithm can be constructed, which segments and fits the center-clustered points, e.g., in crowns, into ellipses and the line-arranged points, e.g., on walls, into line segments. Eventually, the experiments based on real VLS data primarily validate this new algorithm.
Autors: Lin, Y.;Hyyppa, J.;
Appeared in: IEEE Geoscience and Remote Sensing Letters
Publication date: Jan 2011, volume: 8, issue:1, pages: 93 - 97
Publisher: IEEE
 
» -NN Regression to Improve Statistical Feature Extraction for Texture Retrieval
Abstract:
This correspondence presents an iterative method based upon -nearest neighbors ( -NN) regression to improve the performance of statistical feature extraction for texture image retrieval. The idea exploits the fact that an ideal feature extraction system would extract similar signatures from images characterized by the same texture and different signatures from dissimilar textures. Under the assumption that conventional statistical feature extraction contributes to sufficiently good retrieval performance, the signatures of retrieved textures are used to update the signature of the query image using the -NN regression algorithm. Extensive experiments show significant improvements with respect to retrieval performance in comparison to conventional statistical feature extraction.
Autors: Khelifi, F.;Jiang, J.;
Appeared in: IEEE Transactions on Image Processing
Publication date: Jan 2011, volume: 20, issue:1, pages: 293 - 298
Publisher: IEEE
 
» Sensing for IGBT Protection in NPC Three Level Converters—Causes For Spurious Trippings and Their Elimination
Abstract:
Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., VCE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false VCE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false VCE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the VCE sense fault signals of the inner devices of the leg.
Autors: Jain, A.K.;Ranganathan, V.T.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Jan 2011, volume: 26, issue:1, pages: 298 - 307
Publisher: IEEE
 
» A 0.18- Dual-Gate CMOS Device Modeling and Applications for RF Cascode Circuits
Abstract:
A merged-diffusion dual-gate CMOS device model is presented in this paper. The proposed large-signal model consists of two intrinsic BSIM3v3 nonlinear models and parasitic components. The parasitic elements, including the substrate networks, the distributed resistances, and the inductances, are extracted from the measured -parameters. In order to verify the model accuracy, a cascode configuration with the proposed dual-gate device is employed in a low-noise amplifier. The dual-gate model is also evaluated with power sweep and load–pull measurements. In addition, a doubly balanced dual-gate mixer is successfully demonstrated using the proposed model. The measured results agree with the simulated results using the proposed device model for both linear and nonlinear applications. The advanced large-signal dual-gate CMOS model can be further used as an RF sub-circuit cell for simplifying the design procedure.
Autors: Chang, H.-Y.;Liang, K.-H.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2011, volume: 59, issue:1, pages: 116 - 124
Publisher: IEEE
 
» A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel ADC Architecture
Abstract:
This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma ADC architecture. The use of a second-order ADC improves the conversion speed while reducing the random noise (RN) level as well. The ADC employing an inverter-based modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25- m and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13- m CMOS process. Measurement results show a RN of 2.4 and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 nJ.
Autors: Chae, Y.;Cheon, J.;Lim, S.;Kwon, M.;Yoo, K.;Jung, W.;Lee, D.-H.;Ham, S.;Han, G.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 236 - 247
Publisher: IEEE
 
» A 2.4 GHz Quadrature-Input Programmable Fractional Frequency Divider
Abstract:
A 2.4 GHz quadrature-input programmable frequency divider with step size of 0.5 is demonstrated in a standard 0.35 CMOS process. Fractional division is realized by phase switching between the cross-coupled divide-by-4 injection-locked frequency divider outputs. The proposed circuit exhibits an operation frequency range from 2.24 to 2.70 GHz and consumes less than 5.13 mW with a 1.5 V supply.
Autors: Chang, K. F.;Cheng, K.-K. M.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2011, volume: 21, issue:1, pages: 34 - 36
Publisher: IEEE
 
» A 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS
Abstract:
Scaled CMOS proves to be suitable for the design of transceiver ICs at micro- and millimeter-waves. The effort is presently toward compact and low-power solutions in view of integrating several transceivers on the same chip enabling phased array systems. In this paper we present a 24 GHz receiver, based on a subharmonic direct conversion architecture, designed in a 65 nm node. The local oscillator takes advantage of the half frequency operation proving significantly lower power consumption when compared to conventional solutions running at received frequency. Stacked switches for subharmonic down-conversion are passive to save voltage room, current driven and loaded by a transresistance amplifier. Optimum biasing of the switches allows maximizing linearity while saving power in the baseband. The integrated LNA matching network is the bottleneck toward low sensitivities. The LNA design trades-off power consumption, gain and sensitivity. Detailed insights into implementation issues, critical in a single-ended topology where both forward and return signal paths have to be supported, are provided. The chip consumes 78 mW and occupies 1.4 mm of active area. Experiments show: 30.5 dB gain, 6.7 dB NF, dBm IIP3.
Autors: Mazzanti, A.;Sosio, M.;Repossi, M.;Svelto, F.;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2011, volume: 58, issue:1, pages: 88 - 97
Publisher: IEEE
 
» A 3.9 mW 25-Electrode Reconfigured Sensor for Wearable Cardiac Monitoring System
Abstract:
A low power highly sensitive Thoracic Impedance Variance (TIV) and Electrocardiogram (ECG) monitoring SoC is designed and implemented into a poultice-like plaster sensor for wearable cardiac monitoring. 0.1 TIV detection is possible with a sensitivity of 3.17 and . This is achieved with the help of a high quality ( }, \{30}$" style="Vertical-Align:0px" border=0> ) balanced sinusoidal current source and low noise reconfigurable readout electronics. A cm-range 13.56 MHz fabric inductor coupling is adopted to start/stop the SoC remotely. Moreover, a 5% duty-cycled Body Channel Communication (BCC) is exploited for 0.2 nJ/b 1 Mbps energy efficient external data communication. The proposed SoC occupies 5 mm 5 mm including pads in a standard 0.18 1P6M CMOS technology. It dissipates a peak power of 3.9 mW when operating in body channel receiver mode, and consumes 2.4 mW when operating in TIV and ECG detection mode. The SoC is integrated on a 15 cm 15 cm fabric circuit board together with a flexible battery to form a compact wearable sensor. With 25 adhesive screen-printed fabric electrodes, detection of TIV and ECG at 16 different sites of the heart is possible, allowing optimal detection sites to be configur- - ed to accommodate different user dependencies.
Autors: Yan, L.;Bae, J.;Lee, S.;Roh, T.;Song, K.;Yoo, H.-J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 353 - 364
Publisher: IEEE
 
» A 30 W Analog Signal Processor ASIC for Portable Biopotential Signal Monitoring
Abstract:
This paper presents the design and implementation of an analog signal processor (ASP) ASIC for portable ECG monitoring systems. The ASP ASIC performs four major functionalities: 1) ECG signal extraction with high resolution, 2) ECG signal feature extraction, 3) adaptive sampling ADC for the compression of ECG signals, 4) continuous-time electrode-tissue impedance monitoring for signal integrity monitoring. These functionalities enable the development of wireless ECG monitoring systems that have significantly lower power consumption yet that are more capable than their predecessors. The ASP has been implemented in 0.5 CMOS process and consumes 30 from a 2 V supply. The noise density of the ECG readout channel is 85 and the CMRR is better that 105 dB. The adaptive sampling ADC is capable of compressing the ECG data by a factor of 7 and the heterodyne chopper readout extracts the features of the ECG signals. Combination of these two features leads to a factor 4 reduction in the power consumption of a wireless ECG monitoring system. Furthermore, the proposed continuous-time impedance monitoring circuit enables the monitoring of the signal integrity.
Autors: Yazicioglu, R. F.;Kim, S.;Torfs, T.;Kim, H.;Van Hoof, C.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 209 - 223
Publisher: IEEE
 
» A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation
Abstract:
SRAM bitcell design margin continues to shrink due to random and systematic process variation in scaled technologies and conventional SRAM faces a challenge in realizing the power and density benefits of technology scaling. Smart and adaptive assist circuits can improve design margins while satisfying SRAM power and performance requirements in scaled technologies. This paper introduces an adaptive, dynamic SRAM word-line under-drive (ADWLUD) scheme that uses a bitcell-based sensor to dynamically optimize the strength of WLUD for each die. The ADWLUD sensor enables 130 mV reduction in SRAM Vccmin while increasing frequency yield by 9% over conventional SRAM without WLUD. The sensor area overhead is limited to 0.02% and power overhead is 2% for a 3.4 Mb SRAM array.
Autors: Kolar, P.;Karl, E.;Bhattacharya, U.;Hamzaoglu, F.;Nho, H.;Ng, Y.-G.;Wang, Y.;Zhang, K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 76 - 84
Publisher: IEEE
 
» A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS
Abstract:
Novel program and read schemes are presented to break barriers in scaling of NAND flash memory such as threshold voltage endurance from floating gate interference, and charge loss tolerance. To enhance threshold voltage endurance and charge loss tolerance, we introduced three schemes; MSB Re-PGM scheme, Moving Read scheme and Adaptive Code Selection scheme. Using the MSB Re-PGM scheme, threshold voltage distribution width is improved about 200 mV. The PGM throughput is enhanced from 1500 to 1250 . With the Moving Read scheme about half order of UBER is improved with 10 bit ECC. Also, Adaptive Code Selection scheme are used to decrease a current consumption. There is 5.5% current reduction. With these techniques, 32-Gb MLC NAND flash memory has been fabricated using a 32 nm CMOS process technology. Its program throughput reaches 13.0 MB/s at a multi-plane program operation with cache operation keeping a desirable threshold voltage distribution.
Autors: Lee, C.;Lee, S.-K.;Ahn, S.;Lee, J.;Park, W.;Cho, Y.;Jang, C.;Yang, C.;Chung, S.;Yun, I.-S.;Joo, B.;Jeong, B.;Kim, J.;Kwon, J.;Jin, H.;Noh, Y.;Ha, J.;Sung, M.;Choi, D.;Kim, S.;Choi, J.;Jeon, T.;Park, H.;Yang, J.-S.;Koh, Y.-H.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 97 - 106
Publisher: IEEE
 
» A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition
Abstract:
A heterogeneous many-core object recognition processor is proposed to realize robust and efficient object recognition on real-time video of cluttered scenes. Unlike previous approaches that simply aimed for high GOPS/W, we aim to achieve high Effective GOPS/W, or EGOPS/W, which only counts operations carried out on meaningful regions of an input image. This is achieved by the Unified Visual Attention Model (UVAM) which confines complex Scale Invariant Feature Transform (SIFT) feature extraction to meaningful object regions while rejecting meaningless background regions. The Intelligent Inference Engine (IIE), a mixed-mode neuro-fuzzy inference system, performs the top-down familiarity attention of the UVAM which guides attention toward pre-learned objects. Weight perturbation-based learning of the IIE ensures high attention precision through online adaptation. The SIFT recognition is accelerated by an optimized array of 4 20-way SIMD Vector Processing Elements, 32 MIMD Scalar Processing Elements, and 1 Feature Matching Processor. When processing 30 fps 640 480 video, the 50 mm object recognition processor implemented in a 0.13 m process achieves 246 EGOPS/W, which is 46% higher than the previous work. The average power consumption is only 345 mW.
Autors: Lee, S.;Oh, J.;Park, J.;Kwon, J.;Kim, M.;Yoo, H.-J.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 42 - 51
Publisher: IEEE
 
» A 38/114 GHz Switched-Mode and Synchronous Lock Standing Wave Oscillator
Abstract:
This letter presents a 38/114 GHz switched-mode standing wave oscillator (SWO) capable of synchronous locking. Triple output frequency can be excited by digital control of different mode operations. The experimental prototype was fabricated using a low leakage 65 nm 1P9M triple-well CMOS technology. Incorporating a synchronous lock scheme, the measured phase noise from a 38 GHz carrier before and after the phase locked at 1 MHz offset are 102 dBc/Hz and 120 dBc/Hz, respectively. For the mode 1 operation at 38 GHz and mode 3 operation at 114 GHz, the experimental prototype consumes 4 and 20 mA, respectively, under a 1.2 V biasing voltage and with a chip size of .
Autors: Lu, T.-Y.;Chen, W.-Z.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2011, volume: 21, issue:1, pages: 40 - 42
Publisher: IEEE
 
» A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology
Abstract:
A 4 Mb embedded phase change memory macro has been developed in a 90 nm 6-ML CMOS technology. The storage element has been integrated using 3 additional masks with respect to process baseline. The cell selector is implemented by a standard LV nMOS device, achieving a cell size of 0.29 m . A dual-voltage row decoder and a double-path column decoder are introduced, enabling a completely low voltage read operation. A 20b-parallelism write scheme is embedded in the digital controller in order to maximize throughput. In alternative, a power-saving low-parallelism write algorithm can be employed. The macro features a 1.2 V 12 ns read access time and a write throughput of 1 MB/s. Set and reset current distributions showing a good read window are presented and robust reliability results are demonstrated.
Autors: De Sandre, G.;Bettini, L.;Pirola, A.;Marmonier, L.;Pasotti, M.;Borghi, M.;Mattavelli, P.;Zuliani, P.;Scotti, L.;Mastracchio, G.;Bedeschi, F.;Gastaldi, R.;Bez, R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 52 - 63
Publisher: IEEE
 
» A 40 nm 16-Core 128-Thread SPARC SoC Processor
Abstract:
This fourth generation UltraSPARC T3 SoC processor implements sixteen 8-threaded SPARC cores to double on-chip thread count and throughput performance over its previous generation. It enhances glueless scalability to enable up to 512 threads in a 4-way system. A 16-Bank 6 MB L2 Cache, a 512 GB/s hierarchical crossbar and a 312-lane SerDes I/O of 2.4 Tb/s support the bandwidth required by the large number of threads. This SoC processor integrates the memory controller, PCIE 2.0, 10 Gb Ethernet ports, and required cache coherency support in multi-chip configurations. Multiple clock and power domains are used to optimize performance and power for the SoC components. Extensive power management features, from architecture to circuit techniques, optimize both active and idle power. The 377 die includes 1 billion transistors in a flip-chip ceramic package with 2117 pins. The chip is fabricated in TSMC's 40 nm high-performance process with 11 Cu metals and four transistor types.
Autors: Shin, J. L.;Huang, D.;Petrick, B.;Hwang, C.;Tam, K. W.;Smith, A.;Pham, H.;Li, H.;Johnson, T.;Schumacher, F.;Leon, A. S.;Strong, A.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 131 - 144
Publisher: IEEE
 
» A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM
Abstract:
In this paper we introduce a 14-core application processor for multimedia mobile applications, implemented in 40 nm, with a 222 mW H.264 full high-definition (full-HD) video engine, a 124 mW 40 M-polygons/s 3D/2D graphics engine, and a video/audio multiprocessor for various Codecs and image processing. The application processor has 25 power domains to achieve coarse-grain power gating for adjusting to the required performance of wide range of multimedia applications. The simple on-chip power switch circuits perform less than 1 switching while reducing rush current. Furthermore, the Stacked Chip SoC (SCS) technology enables rewiring to the DRAM chip during assembly/packaging phase using a wire with 10 minimum pitch on Re-Distribution Layer (RDL) using electroplating. The peak memory bandwidth is 10.6 GB/s with an x512b SCS-DRAM interface, and the power consumption of this interface is 3.9 mW at 2.4 GB/s workload.
Autors: Kikuchi, Y.;Takahashi, M.;Maeda, T.;Fukuda, M.;Koshio, Y.;Hara, H.;Arakida, H.;Yamamoto, H.;Hagiwara, Y.;Fujita, T.;Watanabe, M.;Ezawa, H.;Shimazawa, T.;Ohara, Y.;Miyamori, T.;Hamada, M.;Takahashi, M.;Oowaki, Y.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 32 - 41
Publisher: IEEE
 
» A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
Abstract:
A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency guardbands for dynamic parameter variations to improve throughput and energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds error-detection sequential (EDS) circuits in critical paths to detect late timing transitions. In addition to reducing the guardbands for dynamic variations, the embedded EDS design can exploit path-activation rates to operate the microprocessor faster than infrequently-activated critical paths. The second error-detection design offers a less-intrusive approach for dynamic timing-error detection by placing a tunable replica circuit (TRC) per pipeline stage to monitor worst-case delays. Although the TRCs require a delay guardband to ensure the TRC delay is always slower than critical-path delays, the TRC design captures most of the benefits from the embedded EDS design with less implementation overhead. Furthermore, while core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage measurements. Both error-detection designs interface with error-recovery techniques, enabling the detection and correction of timing errors from fast-changing variations such as high-frequency droops.
Autors: Bowman, K. A.;Tschanz, J. W.;Lu, S.-L. L.;Aseron, P. A.;Khellah, M. M.;Raychowdhury, A.;Geuskens, B. M.;Tokunaga, C.;Wilkerson, C. B.;Karnik, T.;De, V. K.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 194 - 208
Publisher: IEEE
 
» A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache
Abstract:
A 1.35 ns random access and 1.7 ns-random-cycle SOI embedded-DRAM macro has been developed for the POWER7™ high-performance microprocessor. The macro employs a 6 transistor micro sense-amplifier architecture with extended precharge scheme to enhance the sensing margin for product quality. The detailed study shows a 67% bit-line power reduction with only 1.7% area overhead, while improving a read zero margin by more than 500ps. The array voltage window is improved by the programmable BL voltage generator, allowing the embedded DRAM to operate reliably without constraining of the microprocessor voltage supply windows. The 2.5nm gate oxide transistor cell with deep-trench capacitor is accessed by the 1.7 V wordline high voltage (VPP) with V WL low voltage (VWL), and both are generated internally within the microprocessor. This results in a 32 MB on-chip L3 on-chip-cache for 8 cores in a 567 mm POWER7™ die.
Autors: Barth, J.;Plass, D.;Nelson, E.;Hwang, C.;Fredeman, G.;Sperling, M.;Mathews, A.;Kirihata, T.;Reohr, W. R.;Nair, K.;Cao, N.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 64 - 75
Publisher: IEEE
 
» A 470- 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme
Abstract:
This paper presents a digitally controlled injection-locked multimodulus frequency divider (ILMFD) based on a ring-oscillator using inverter chains for a small area and low power consumption. In the proposed ILMFD, division ratios of 2, 3, 4, 5 and 6 are achieved by using a programmable delay line that changes the self-oscillation frequency of the ring-oscillator. The locking range of the proposed ILMFD is improved by employing a dual-input injection scheme, which unlike previous multiinput injection schemes, does not require distinct phase inputs. A prototype chip implemented in a 0.13- CMOS process has an area of and operates at 5 GHz while consuming 470 from 1.2 V supply, where 350 is dissipated in the core of the ILMFD. The proposed divider is the first reported multimodulus ILFD with digitally controlled division ratios and an in-phase dual-input injection scheme.
Autors: Lee, J.;Park, S.;Cho, S.;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2011, volume: 19, issue:1, pages: 61 - 70
Publisher: IEEE
 
» A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
Abstract:
This paper describes a multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 6 4 2D-mesh network-on-chip architecture. Located at each mesh node is a five-port virtual cut-through packet-switched router shared between two IA-32 cores. Core-to-core communication uses message passing while exploiting 384 KB of on-die shared memory. Fine grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1 V supply, the cores operate at 1 GHz while the 2D-mesh operates at 2 GHz. As performance and voltage scales, the processor dissipates between 25 W and 125 W. The processor is implemented in 45 nm Hi-K CMOS and has 1.3 billion transistors.
Autors: Howard, J.;Dighe, S.;Vangal, S. R.;Ruhl, G.;Borkar, N.;Jain, S.;Erraguntla, V.;Konow, M.;Riepen, M.;Gries, M.;Droege, G.;Lund-Larsen, T.;Steibl, S.;Borkar, S.;De, V. K.;Van Der Wijngaart, R.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 173 - 183
Publisher: IEEE
 
» A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS
Abstract:
An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2 V down to 0.57 V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global bitline scheme. Finally, a data retention voltage sensor has been developed to predict the mismatch-limited minimum standby voltage without corrupting the contents of the memory.
Autors: Qazi, M.;Stawiasz, K.;Chang, L.;Chandrakasan, A. P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 85 - 96
Publisher: IEEE
 
» A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
Abstract:
This paper describes a 1 Gbit GDDR5 SDRAM with enhanced bank access flexibility for efficient data transfer in 7 Gb/s per pin IO bandwidth. The enhanced flexibility is achieved by elimination of bank group restriction and reduction of bank to bank active time to 2.5 ns. The effectiveness of these key features is verified by system model simulation including memory and its controller. To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller. This GDDR5 SDRAM was fabricated in 50 nm standard DRAM process in 61.6 die area and operates with 1.5 V power supply.
Autors: Oh, T.-Y.;Sohn, Y.-S.;Bae, S.-J.;Park, M.-S.;Lim, J.-H.;Cho, Y.-K.;Kim, D.-H.;Kim, D.-M.;Kim, H.-R.;Kim, H.-J.;Kim, J.-H.;Kim, J.-K.;Kim, Y.-S.;Kim, B.-C.;Kwak, S.-H.;Lee, J.-H.;Lee, J.-Y.;Shin, C.-H.;Yang, Y.;Cho, B.-S.;Bang, S.-Y.;Yang, H.-J.;Choi,
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 107 - 118
Publisher: IEEE
 
» A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current Pre-Amplifier for High Frequency Lateral MEMS Oscillators
Abstract:
This paper reports on the design and characterization of a high-gain tunable transimpedance amplifier (TIA) suitable for gigahertz oscillators that use high- lateral micromechanical resonators with large motional resistance and large shunt parasitic capacitance. The TIA consists of a low-power broadband current pre-amplifier combined with a current-to-voltage conversion stage to boost the input current before delivering it to feedback voltage amplifiers. Using this approach, the TIA achieves a constant gain of 76 dB-Ohm up to 1.7 GHz when connected to a 2 pF load at the input and output with an input-referred noise below 10 in the 100 MHz to 1 GHz range. The TIA is fabricated in a 1P6M 0.18 CMOS process and consumes 7.2 mW. To demonstrate its performance in high frequency lateral micromechanical oscillator applications, the TIA is wirebonded to a 724 MHz high-motional resistance ( , , ) and a 1.006 GHz high-parasitic ( , , AlN-on-Silicon resonator. The 724 MHz and 1.006 GHz oscillators achieve phase-nois- - e better than and @ 1 kHz offset, respectively, with a floor around . The 1.006 GHz oscillator achieves the highest reported figure of merit (FoM) among lateral piezoelectric micromechanical oscillators and meets the phase-noise requirements for most 2G and 3G cellular standards including GSM 900 MHz, GSM 1800 MHz, and HSDPA.
Autors: Lavasani, H. M.;Pan, W.;Harrington, B.;Abdolvand, R.;Ayazi, F.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 224 - 235
Publisher: IEEE
 
» A Barankin-Type Bound on Direction Estimation Using Acoustic Sensor Arrays
Abstract:
We derive a Barankin-type bound (BTB) on the mean-square error (MSE) in estimating the directions of arrival (DOAs) of far-field sources using acoustic sensor arrays. We consider narrowband and wideband deterministic source signals, and scalar or vector sensors. Our results provide an approximation to the threshold of the signal-to-noise ratio (SNR) below which the performance of the maximum likelihood estimation (MLE) degrades rapidly. For narrowband DOA estimation using uniform linear vector-sensor arrays, we show that this threshold increases with the distance between the sensors. As a result, for medium SNR values the performance does not necessarily improve with this distance.
Autors: Li, T.;Tabrikian, J.;Nehorai, A.;
Appeared in: IEEE Transactions on Signal Processing
Publication date: Jan 2011, volume: 59, issue:1, pages: 431 - 435
Publisher: IEEE
 
» A Battery-Less Thermoelectric Energy Harvesting Interface Circuit With 35 mV Startup Voltage
Abstract:
A battery-less thermoelectric energy harvesting interface circuit to extract electrical energy from human body heat is implemented in a 0.35 CMOS process. A mechanically assisted startup circuit enables operation of the system from input voltages as low as 35 mV. An efficient control circuit that performs maximal transfer of the extracted energy to a storage capacitor and regulates the output voltage at 1.8 V is presented.
Autors: Ramadass, Y. K.;Chandrakasan, A. P.;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2011, volume: 46, issue:1, pages: 333 - 341
Publisher: IEEE
 
» A Brain-Deformation Framework Based on a Linear Elastic Model and Evaluation Using Clinical Data
Abstract:
In image-guided neurosurgery, brain tissue displacement and deformation during neurosurgical procedures are a major source of error. In this paper, we implement and evaluate a linear-elastic-model-based framework for correction of brain shift using clinical data from five brain tumor patients. The framework uses a linear elastic model to simulate brain-shift behavior. The model is driven by cortical surface deformations, which are tracked using a surface-tracking algorithm combined with a laser-range scanner. The framework performance was evaluated using displacements of anatomical landmarks, tumor contours and self-defined evaluation parameters. The results show that tumor deformations predicted by the present framework agreed well with the ones observed intraoperatively, especially in the parts of the larger deformations. On average, a brain shift of 3.9 mm and a tumor margin shift of 4.2 mm were corrected to 1.2 and 1.3 mm, respectively. The entire correction process was performed in less than 5 min. The data from this study suggest that the technique is a suitable candidate for intraoperative brain-deformation correction.
Autors: Zhang, C.;Wang, M.;Song, Z.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Jan 2011, volume: 58, issue:1, pages: 191 - 199
Publisher: IEEE
 
» A Broadband -Strip Fed Printed Microstrip Antenna
Abstract:
A broadband -strip fed printed microstrip antenna is presented. The strip loaded slotted broadband microstrip antenna is fed by an -strip feed line to achieve impedance matching for the higher order modes of the patch antenna in addition to the existing resonances. The antenna offers 74% bandwidth when printed on a substrate of dielectric constant 4.2 and has an overall dimension of 42 55 3.2 . The simulated and experimental reflection characteristics of the antenna with and without the -feed along with radiation patterns, input impedance variations, gain and efficiency of the final antenna are presented and discussed. The time domain transient analysis indicates a minimum dispersion to the transmitted pulse.
Autors: Sarin, V. P.;Nishamol, M. S.;Tony, D.;Aanandan, C. K.;Mohanan, P.;Vasudevan, K.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2011, volume: 59, issue:1, pages: 281 - 284
Publisher: IEEE
 
» A Broadband -Strip Fed Printed Microstrip Antenna
Abstract:
A broadband <;i>;L<;/i>; -strip fed printed microstrip antenna is presented. The strip loaded slotted broadband microstrip antenna is fed by an L-strip feed line to achieve impedance matching for the higher order modes of the patch antenna in addition to the existing resonances. The antenna offers 74% bandwidth when printed on a substrate of dielectric constant 4.2 and has an overall dimension of 42 × 55 × 3.2 mm3. The simulated and experimental reflection characteristics of the antenna with and without the L-feed along with radiation patterns, input impedance variations, gain and efficiency of the final antenna are presented and discussed. The time domain transient analysis indicates a minimum dispersion to the transmitted pulse.
Autors: Sarin, V.P.;Nishamol, M.S.;Tony, D.;Aanandan, C.K.;Mohanan, P.;Vasudevan, K.;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2011, volume: 59, issue:1, pages: 281 - 284
Publisher: IEEE
 
» A broadband spectroscopy method for ultrasonic wave velocity measurement under high pressure
Abstract:
A broadband spectroscopy method is proposed to measure the ultrasonic wave phase velocity of Z-cut quartz under high pressure up to 4.7 GPa. The sample is in a hydrostatic circumstance under high pressure, and we can get longitudinal wave and shear wave signals simultaneously in our work. By fast Fourier transform of received signals, the spectrum and phase of the received signals could be obtained. After unwrapping the phase of the received signals, the travel time of ultrasonic wave in the sample could be obtained, and the ultrasonic wave phase velocity could also be resolved after data processing. The elastic constant of measurement under high pressure is also compared with previous studies. This broadband spectroscopy method is a valid method to get ultrasonic wave travel parameters, and it could be applied for elasticity study of materials under high pressure.
Autors: Wang, Zhigang;Liu, Yonggang;Song, Wei;Bi, Yan;Xie, Hongsen;
Appeared in: Review of Scientific Instruments
Publication date: Jan 2011, volume: 82, issue:1, pages: 014501 - 014501-5
Publisher: IEEE
 
» A Calibration Method for RF and Microwave Noise Sources
Abstract:
Uncertainties in noise-figure and noise-parameter measurements depend to a large degree on the accuracy with which noise sources are calibrated. In some cases, the uncertainties are similar to measured quantities. This paper discusses a method for calibration of RF and microwave noise sources against a reference noise source. This method takes into account noise parameters of the receiver used for noise power measurements and includes temperature corrections to account for both drifts in the ambient temperature and heat transfer between the receiver and noise sources. Experimental results demonstrate the feasibility of the proposed method. As estimated with a Monte Carlo analysis, a uncertainty of 0.046 dB for a 5-dB excess-noise-ratio (ENR) noise source is obtained with the proposed method. This uncertainty is approximately one third of ENR uncertainties reported for commercial noise sources.
Autors: Belostotski, L.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2011, volume: 59, issue:1, pages: 178 - 187
Publisher: IEEE
 
» A Capacitive Tactile Sensor Array for Surface Texture Discrimination
Abstract:
This paper presents a silicon MEMS based capacitive sensing array, which has the ability to resolve forces in the sub mN range, provides directional response to applied loading and has the ability to differentiate between surface textures. Texture recognition is achieved by scanning surfaces over the sensing array and assessing the frequency spectrum of the sensor outputs.
Autors: H.B., Muhammad , C., Recchiuto , C.M., Oddo , L., Beccai , C.J., Anthony , ...
Appeared in: Microelectronic Engineering
Publication date: Jan 2011
Publisher: Elsevier B.V.
 
» A Class-F Power Amplifier With CMRC
Abstract:
This letter presents a novel harmonic control circuit (HCC) for class-F power amplifiers (PAs). A compact microstrip resonant cell (CMRC) is inserted between the transistor and the output fundamental matching network. Third harmonic open circuit condition and size reduction are achieved simultaneously. This scheme provides a straightforward and simple approach to design HCC. A class-F PA is designed and fabricated for demonstration. The measured maximum power-added efficiency (PAE) is 74% with 10 dB power gain near the 1 dB compression point.
Autors: Chen, S.;Xue, Q.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2011, volume: 21, issue:1, pages: 31 - 33
Publisher: IEEE
 
» A Classification Tree Approach for Cardiac Ischemia Detection Using Spatiotemporal Information From Three Standard ECG Leads
Abstract:
The accurate noninvasive diagnosis of cardiac ischemia remains a great challenge. To this end, the ECG is the main source of information, and personal health systems may now embed intelligence for enabling any citizen to self-record an ECG anywhere at any time. Our objective is to find a decision-support approach that makes best use of these resources. A new classification tree based on conditions combinations competition (T-3C) is proposed for building a multibranch tree of combined decision rules, and its performance is compared to usual methods based either on discriminant analysis or on classification trees. Moreover, we assessed with these methods, the diagnosis content for ischemia detection of the spatiotemporal ECG information that can be retrieved either from the standard 12-lead ECG or from only the three orthogonal leads subset (I, II, and V2), easy to set-up in self-care. The diagnostic accuracy of 14 decision-making strategies was compared for ischemia detection induced by angioplasty on a test set from a study population of 90 patients. The best performance is obtained with the T-3C algorithm on three-lead ECG, reaching 98% of sensitivity and of specificity, thus exceeding 23% of the diagnostic accuracy of the recommended and currently used standard ECG criteria.
Autors: Fayn, J.;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Jan 2011, volume: 58, issue:1, pages: 95 - 102
Publisher: IEEE
 
» A Closed-Form Formula for Dispersion Characteristics of Fundamental SIW Mode
Abstract:
An accurate closed-form formula is derived from an analytical method to calculate dispersion properties of the substrate integrated waveguide (SIW). The derived equation which is a function of geometrical parameters is used to accurately estimate the cutoff frequency of the dominant mode at a low leakage condition. The unit cell of an SIW can be considered as two consecutive rectangular waveguide sections with the specific difference in their widths. The propagation constant is extracted by applying the Floquet theorem to the overall transmission matrix of the single unit cell. The proposed formula agrees well with numerical solutions as well as reported empirical equations in a wide range of structure parameters.
Autors: Salehi, M.;Mehrshahi, E.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2011, volume: 21, issue:1, pages: 4 - 6
Publisher: IEEE
 
» A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero
Abstract:
A digital random return-to-zero technique is presented to improve the dynamic performance of current-steering digital-to-analog converters (DACs). To demonstrate the proposed technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90-nm CMOS technology. The DAC achieves a spurious-free dynamic range better than 60 dB for a sine-wave input up to 460 MHz and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.
Autors: Tseng, W.-H.;Wu, J.-T.;Chu, Y.-C.;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2011, volume: 58, issue:1, pages: 1 - 5
Publisher: IEEE
 
» A CMOS-MEMS Thermopile With Low Thermal Conductance and a Near-Perfect Emissivity in the 8–14- Wavelength Range
Abstract:
A CMOS-MEMS polysilicon/metal thermopile with low thermal conductance and a high emissivity in 8–14 is presented in this letter. Instead of a traditional aluminum layer with a high thermal conductivity, a titanium film was compatibly introduced to the CMOS process to highly decrease the solid conductance and enhance the responsivity of the infrared sensor. In addition, the solid conductance was further reduced by adopting the design of line-shaped etching windows to isolate heat flow. Furthermore, a gold-black film was evaporated and patterned in situ as the absorber of the sensor to achieve an almost total absorption of received infrared. The responsivity of the poly/Ti thermopile may be about 6.9 times greater than that of the fully standard CMOS poly/Al thermopile without the line-shaped windows and the gold-black coating.
Autors: Chen, C.-N.;Huang, W.-C.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2011, volume: 32, issue:1, pages: 96 - 98
Publisher: IEEE
 
» A Common Electromagnetic Framework for Carbon Nanotubes and Solid Nanowires—Spatially Dispersive Conductivity, Generalized Ohm's Law, Distributed Impedance, and Transmission Line Model
Abstract:
General equations are presented for the spatially dispersive conductivity, distributed impedance, Ohm's law relation, and transmission line model of both carbon nanotubes (CNTs) and solid material nanowires. It is shown that spatial dispersion results in an intrinsic (material-dependent) transmission-line capacitance. Spatial dispersion is numerically unimportant in metal nanowires, but leads to a shift in propagation constant of a few percent for CNTs and semiconducting nanowires. Theoretically, spatial dispersion is important for both nanowires and nanotubes, and is necessary to preserve the inductance–capacitance–velocity relation , where is kinetic inductance, is intrinsic capacitance, and is electron Fermi velocity. It is shown that in order to obtain the correct intrinsic capacitance, it is necessary to use a charge-conserving form of the relaxation-time approximation to Boltzmann's equation. Numerical results for the propagation constant of various nanowires and CNTs are presented. The general formulation developed here allows one to compute, and directly compare and contrast, properties of CNTs and solid nanowires.
Autors: Hanson, G. W.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2011, volume: 59, issue:1, pages: 9 - 20
Publisher: IEEE
 
» A Compact Model for Dual-Gate One-Dimensional FET: Application to Carbon-Nanotube FETs
Abstract:
A compact model for dual-gate (DG) carbon-nanotube field-effect transistors (FETs) (CNTFETs) is presented. This compact model includes the most significant mechanisms present in DG CNTFETs such as the Schottky barrier at the metal–nanotube interface, charge and electrostatic modeling, the band-to-band tunneling effect, and quasi-ballistic transport through the Landauer equation. Also, the structure of our DG CNTFET model and its associated equations are versatile and can be used to model different kinds of 1-D ballistic DG FETs, such as graphene-nanoribbon-based devices. Furthermore, this compact model is compared with measurements from two different technologies. Finally, a simple ring oscillator circuit has been simulated using ten identical devices.
Autors: Fregonese, S.;Maneux, C.;Zimmer, T.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2011, volume: 58, issue:1, pages: 206 - 215
Publisher: IEEE
 
» A Compact Variable-Temperature Broadband Series-Resistor Calibration
Abstract:
We present a broadband on-wafer calibration from 45 MHz to 40 GHz for variable temperature measurements, which requires three standards: a thru, reflect, and series resistor. At room temperature, the maximum error of this technique, compared to a benchmark nine-standard multiline thru-reflect-line (TRL) method, is comparable to the repeatability of the benchmark calibration. The series-resistor standard is modeled as a lumped-element -network, which is described by four frequency-independent parameters. We show that the model is stable over three weeks, and compare the calibration to the multiline TRL method as a function of time. The approach is then demonstrated at variable temperature, where the model parameters are extracted at 300 K and at variable temperatures down to 20 K, in order to determine their temperature dependence. The resulting technique, valid over the temperature range from 300 to 20 K, reduced the total footprint of the calibration standards by a factor of 17 and the measurement time by a factor of 3.
Autors: Orloff, N. D.;Mateu, J.;Lewandowski, A.;Rocas, E.;King, J.;Gu, D.;Lu, X.;Collado, C.;Takeuchi, I.;Booth, J. C.;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jan 2011, volume: 59, issue:1, pages: 188 - 195
Publisher: IEEE
 
» A Compact Wideband Ring Coupler Utilizing a Pair of Transitions for Phase Inversion
Abstract:
A new wideband ring coupler utilizing a pair of ultra-wideband planar transitions is introduced in this letter. The two types of transitions (in-phase and inverted phase transitions) are coplanar waveguide-to-parallel stripline transitions, and very similarly structured except for the phase inversion part. The area of the proposed ring coupler is only 41.4% of the conventional ring coupler. The measured bandwidth of the implemented ring coupler with more than 10 dB return loss is 92.5% with the port excitation, and 81.3% with the port excitation. Also, due to good matched properties of the transitions, the ring coupler shows less than 0.7 dB amplitude mismatch, less than 4 phase difference, and more than 30 dB isolation over the operating frequencies.
Autors: Kim, Y.-G.;Song, S.-Y.;Kim, K. W.;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2011, volume: 21, issue:1, pages: 25 - 27
Publisher: IEEE
 
» A Comparative Analysis of Fuel Economy and Emissions Between a Conventional HEV and the UTS PHEV
Abstract:
Unlike conventional hybrid electric vehicles (HEVs), the novel powertrain configuration of the University of Technology, Sydney (UTS) plug-in HEV (PHEV) contains only one electric machine, which functions as either an electric motor or a generator in different time intervals specified by a special energy management strategy (EMS). This paper presents a comparative analysis of the fuel economy and the greenhouse gas (GHG) emissions between a conventional HEV and the UTS PHEV, which includes vehicle modeling, EMS development, and a simulation model of the conventional HEV, which is embedded in the advanced vehicle simulator, and the UTS PHEV simulation code. The fuel economy and the emissions, such as hydrocarbon, carbon monoxide, and nitrogen oxides, are computed, analyzed, and compared for the two standard drive cycles, i.e., 1) the high-speed highway drive cycle and 2) the low-speed city drive cycle, proposed by the U.S. Environmental Protection Agency and their combination.
Autors: Salisa, A. R.;Zhang, N.;Zhu, J. G.;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Jan 2011, volume: 60, issue:1, pages: 44 - 54
Publisher: IEEE
 
» A Comparative Analysis of Krylov Solvers for Three-Dimensional Simulations of Borehole Sensors
Abstract:
We perform a comparative analysis of three Krylov subspace methods, viz., the restarted generalized minimum residual (RGMRES), the conjugate gradient squared (CGS), and the stabilized biconjugate gradient (Bi-CGSTAB), for solving large non-Hermitian sparse linear systems arising from the 3-D finite-volume modeling of electromagnetic borehole sensors in complex earth formations. Incomplete LU factorization and symmetric successive overrelaxation preconditioning strategies are used to speed up the convergence rate. We compare these algorithms in terms of accuracy, convergence rate, and overall CPU time. Results show that CGS has a highly irregular convergence behavior, whereas RGMRES and Bi-CGSTAB provide similar numerical accuracy. However, the convergence rate and CPU time of the latter depend on the borehole sensor geometry and on the type of preconditioner adopted.
Autors: Novo, M. S.;da Silva, L. C.;Teixeira, F. L.;
Appeared in: IEEE Geoscience and Remote Sensing Letters
Publication date: Jan 2011, volume: 8, issue:1, pages: 98 - 102
Publisher: IEEE
 
» A Comparative Study of Multicell Amplifiers for AC-Power-Source Applications
Abstract:
AC test power sources are essential for testing electric equipment that is ac-mains connected. Typically, linear power amplifiers (LPAs) are mainly employed as ac test sources because of their high fidelity and excellent dynamic behavior. However, these LPAs have very high losses in their output stages, which make the systems bulky and expensive due to the large heatsinks that are required. In recent years, two approaches have attracted popular interest to improve the efficiency of ac power sources. These are hybrid operation, i.e., combination of linear and switch mode, and multilevel switch-mode inverters. In this paper, three types of multilevel power amplifiers, based on hybrid or switching technology, are presented, namely: hybrid multicell amplifier (H-MCA), amplitude-modulated (AM) + pulsewidth-modulated (PWM) MCA (AP-MCA), and PWM MCA (P-MCA). For each of these topologies, the operating principle and control scheme are introduced. Finally, a 1-kVA laboratory prototype, which can realize all the three topologies, is built, and the measured performance based on this universal prototype are compared.
Autors: Gong, G.;Hassler, D.;Kolar, J. W.;
Appeared in: IEEE Transactions on Power Electronics
Publication date: Jan 2011, volume: 26, issue:1, pages: 149 - 164
Publisher: IEEE
 
» A comparative study of TiN and TiC: Oxidation resistance and retention of xenon at high temperature and under degraded vacuum
Abstract:
Dense TiN and TiC samples were prepared by hot pressing using micrometric powders. Xenon species (simulating rare gas fission products) were then implanted into the ceramics. The samples were annealed for 1 h at 1500 °C under several degraded vacuums with PO2 varying from 10-6 to 2×10-4 mbars. The oxidation resistance of the samples and their retention properties with respect to preimplanted xenon species were analyzed using scanning electron microscopy, grazing incidence x-ray diffraction, Rutherford backscattering spectrometry, and nuclear backscattering spectrometry. Results indicate that TiC is resistant to oxidation and does not release xenon for PO2≤6×10-6 mbars. When PO2 increases, geometric oxide crystallites appear at the surface depending on the orientation and size of TiC grains. These oxide phases are Ti2O3, Ti3O5, and TiO2. Apparition of oxide crystallites is associated with the beginning of xenon release. TiC surface is completely covered by the oxide phases at PO2=2×10-4 mbars up to a depth of 3 μm and the xenon is then completely released. For TiN samples, the results show a progressive apparition of oxide crystallites (Ti3O5 mainly) at the surface when PO2 increases. The presence of the oxide crystallites is also directly correlated with xenon release, the more oxide crystallites are growing the more xenon is released. TiN surface is completely covered by an oxide layer at PO2=2×10-4 mbars up to 1 μm. A correlation between the initial fine microstructure of TiN and the properties of the growing layer is suggested.
Autors: Gavarini, S.;Bes, R.;Millard-Pinard, N.;Cardinal, S.;Peaucelle, C.;Perrat-Mabilon, A.;Garnier, V.;Gaillard, C.;
Appeared in: Journal of Applied Physics
Publication date: Jan 2011, volume: 109, issue:1, pages: 014906 - 014906-9
Publisher: IEEE
 
» A computational tool to assist the analysis of the transformer behavior related to lightning
Abstract:
This paper proposes the application of computational intelligence techniques to assist complex problems concerning lightning in transformers. In order to estimate the currents related to lightning in a transformer, a neural tool is presented. ATP has generated the training vectors. The input variables used in Artificial Neural Networks (ANN) were the wave front time, the wave tail time, the voltage variation rate and the output variable is the maximum current in the secondary of the transformer. These parameters can define the behavior and severity of lightning. Based on these concepts and from the results obtained, it can be verified that...
Autors: André N., de Souza , Maria G., Zago , Osvaldo R., Saavedra , Caio C., Oba Ramos , Kleber, Ferraz
Appeared in: International Journal of Electrical Power & Energy Systems
Publication date: Jan 2011
Publisher: Elsevier B.V.
 
» A Computer Assisted Method for Nuclear Cataract Grading From Slit-Lamp Images Using Ranking
Abstract:
In clinical diagnosis, a grade indicating the severity of nuclear cataract is often manually assigned by a trained ophthalmologist to a patient after comparing the lens' opacity severity in his/her slit-lamp images with a set of standard photos. This grading scheme is often subjective and time-consuming. In this paper, a novel computer-aided diagnosis method via ranking is proposed to facilitate nuclear cataract grading following conventional clinical decision-making process. The grade of nuclear cataract in a slit-lamp image is predicted using its neighboring labeled images in a ranked image list, which is achieved using a learned ranking function. This ranking function is learned via direct optimization on a newly proposed approximation to a ranking evaluation measure. Our proposed method has been evaluated by a large dataset composed of 1000 different cases, which are collected from an ongoing clinical population-based study. Both experimental results and comparison with several existing methods demonstrate the benefit of grading via ranking by our proposed method.
Autors: Huang, W.;Chan, K. L.;Li, H.;Lim, J. H.;Liu, J.;Wong, T. Y.;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Jan 2011, volume: 30, issue:1, pages: 94 - 107
Publisher: IEEE
 
» A context-aware service architecture for the integration of body sensor networks and social networks through the IP multimedia subsystem
Abstract:
In this article a new context-aware architecture is proposed for the integration of body sensor networks and social networks through the IP Multimedia Subsystem. Its motivating application scenarios are described. The benefits and main research challenges for an efficient communication using the proposed architecture are outlined.
Autors: Domingo, M.C.;
Appeared in: IEEE Communications Magazine
Publication date: Jan 2011, volume: 49, issue:1, pages: 102 - 108
Publisher: IEEE
 
» A Cost-Effective WDM-PON Using a Multiple Section Fabry–Pérot Laser Diode
Abstract:
We demonstrated a wavelength-division-multiplexing passive optical network using a multiple section Fabry–Pérot laser diode without a seed light. The electrical envelope tuning of the laser enables color-free operation at 1.25 Gb/s with 100-GHz channel spacing. The mode partition noise is mitigated by shifting the signal spectrum.Pub _bookmark Command="[Quick Mark]"
Autors: Mun, S.-G.;Cho, H.-S.;Lee, C.-H.;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2011, volume: 23, issue:1, pages: 3 - 5
Publisher: IEEE
 
» A Current-Transient Methodology for Trap Analysis for GaN High Electron Mobility Transistors
Abstract:
Trapping is one of the most deleterious effects that limit performance and reliability in GaN HEMTs. In this paper, we present a methodology to study trapping characteristics in GaN HEMTs that is based on current-transient measurements. Its uniqueness is that it is amenable to integration with electrical stress experiments in long-term reliability studies. We present the details of the measurement and analysis procedures. With this method, we have investigated the trapping and detrapping dynamics of GaN HEMTs. In particular, we examined layer location, energy level, and trapping/detrapping time constants of dominant traps. We have identified several traps inside the AlGaN barrier layer or at the surface close to the gate edge and in the GaN buffer.
Autors: Joh, J.;del Alamo, J. A.;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2011, volume: 58, issue:1, pages: 132 - 140
Publisher: IEEE
 
» A Degenerately Doped Bipolar Junction Transistor
Abstract:
An InGaAs bipolar junction transistor having degenerately doped base and emitter layers is reported. The high emitter efficiency is attributed to the asymmetry between the density of states of the conduction and valence bands. A high-frequency transistor having base and emitter metals simultaneously deposited on the emitter layer is demonstrated. The base contact backward diode resistance was 125 .
Autors: Yalon, E.;Elias, D. C.;Gavrilov, A.;Cohen, S.;Halevy, R.;Ritter, D.;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2011, volume: 32, issue:1, pages: 21 - 23
Publisher: IEEE
 
» A Digital Gigapixel Large-Format Tile-Scan Camera
Abstract:
Emerging applications in virtual museums, cultural-heritage projects, and digital art preservation require high-quality, high-resolution imaging of objects with fine structure, shape, and texture. Large-format digital photography can provide such imaging. However, such photography presents unique challenges, particularly sensor-lens mismatch and extended depth of field. A new digital tile-scan large-format camera can acquire high-quality, high-resolution images of static scenes. It employs unique calibration techniques and a novel but simple algorithm for focal-stack processing of very large images with significant magnification variations. The camera automatically collects a set of overlapping focal stacks and processes them into a single high-resolution and extended-depth-of-field image.
Autors: Ben-Ezra, Moshe;
Appeared in: IEEE Computer Graphics and Applications
Publication date: Jan 2011, volume: 31, issue:1, pages: 49 - 61
Publisher: IEEE
 
» A digital watermarking scheme based on singular value decomposition and tiny genetic algorithm
Abstract:
A robust digital image watermarking scheme based on singular value decomposition (SVD) and a tiny genetic algorithm (Tiny-GA) is proposed in this paper. Previous works have shown that both one-way and non-symmetric properties of SVD make it desirable for watermarking techniques. The produced singular values are very stable and vary very little under various image processing operations or attacks. In the proposed scheme, the singular values of a cover image are modified by multiple scale factors to embed the watermark image. Since the values of scale factors determine the watermark strength; therefore, we use the Tiny-GA to search the proper...
Autors: Chih-Chin, Lai
Appeared in: Digital Signal Processing
Publication date: Jan 2011
Publisher: Elsevier B.V.
 

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