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Electrical and Electronics Engineering publications abstract of: 01-2017 sorted by title, page: 0

» $mathsf{REboost}$ : Improving Throughput in Wireless Networks Using Redundancy Elimination
Abstract:
Traffic redundancy elimination (RE) is an attractive approach to improve the throughput in bandwidth-limited networks. While previous studies show that the RE is useful for improving the throughput in such networks, we observed that the RE would not be an effective solution in wireless networks. We found the TCP congestion control cannot take advantage of the RE, without knowing how the underlying RE system manipulates each TCP packet. In this letter, we present a novel technique called REboost to enable the TCP layer to be aware of the underlying RE system and improve the throughput. Our evaluation with a prototype shows that REboost significantly improves the throughput compared with the previous RE systems.
Autors: Kilho Lee;Daehyeok Kim;Insik Shin;
Appeared in: IEEE Communications Letters
Publication date: Jan 2017, volume: 21, issue:1, pages: 160 - 163
Publisher: IEEE
 
» $Q$ Bounds for Planar and Ellipsoidal Antennas
Abstract:
The procedure for numerically deriving equivalent circuits for the six lowest-order modes of arbitrarily shaped, electrically small antennas is reviewed. Element values and the effective radius are tabulated for thin prisms, spheroids, and ellipsoids with a wide range of aspect ratios. A self-consistency test for the elements is defined and applied. These circuits allow calculation of the internal and external electric and magnetic reactive energies and thus establish lower bounds for Q of antennas with these shapes as a function of their electrical radius, ka. Electromagnetic simulations on a family of meander dipoles and a planar loop provide Q values that are compared with the bounds over a range of ka up to one.
Autors: Herbert L. Thal;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2017, volume: 65, issue:1, pages: 353 - 358
Publisher: IEEE
 
» $W$ -Band Traveling Wave Tube Amplifier Based on Planar Slow Wave Structure
Abstract:
A novel planar slow wave structure (SWS) for traveling wave tube (TWT) is proposed. The major advantage of the planar architecture is its easy realization with respect to the typical 3-D SWSs. The particle in cell simulations of the TWT show an achievable gain up to 36.4 dB and a maximum output power of 17.4 W for an operating frequency of 92 GHz. The planar structure can be realized using the standard photolithographic techniques, which improve the reproducibility and performance.
Autors: G. Ulisse;V. Krozer;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2017, volume: 38, issue:1, pages: 126 - 129
Publisher: IEEE
 
» “Driving”-Stress-Induced Degradation in Polycrystalline Silicon Thin-Film Transistors and Its Suppression by a Bridged-Grain Structure
Abstract:
In this letter, degradation of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under “driving” stress is characterized and analyzed for the first time. Dynamic hot carrier (HC) effect, related to pulse falling time, dominates device degradation. To suppress such “driving”-stress-induced dynamic HC degradation, a bridged-grain (BG) structure is applied to the active channel of poly-Si TFTs. Due to the lateral electric field reduction at source/drain junctions, “driving”-stress-induced dynamic HC degradation is significantly improved by the BG structure. Incorporated with transient simulations, the degradation mechanism is elucidated.
Autors: Meng Zhang;Wei Zhou;Rongsheng Chen;Man Wong;Hoi-Sing Kwok;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2017, volume: 38, issue:1, pages: 52 - 55
Publisher: IEEE
 
» 2.25- $mu$ m Avalanche Photodiodes Using Metamorphic Absorber and Lattice-Matched Multiplier on InP
Abstract:
A separated absorption and multiplication aval-anche photodiode for light detection to wavelengths as long as is reported. Photons were absorbed in a metamorphic In0.75Ga0.25As layer, while the photo-generated electrons were injected into a lattice-matched In0.52Al0.48As multiplier on InP. A responsivity gain of 2.7 was attained at 2 at 250 K and increased to 20 at 77 K. A primary dark current of A/cm2 at −15 V was measured at 77 K, which is dominated by dislocation defect-assisted tunneling with activation energies between 0.1 and 0.2 eV. This letter demonstrates the potentiality of extending spectral range of avalanche photodiodes in metamorphic device architecture.
Autors: Y. J. Ma;Y. G. Zhang;Y. Gu;X. Y. Chen;Y. H. Shi;W. Y. Ji;S. P. Xi;B. Du;H. J. Tang;Y. F. Li;J. X. Fang;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2017, volume: 29, issue:1, pages: 55 - 58
Publisher: IEEE
 
» 2016 MTT-S Awards [Awards]
Abstract:
Presents the recipients of various MTTS society awards.
Autors: Charlie Jackson;
Appeared in: IEEE Microwave Magazine
Publication date: Jan 2017, volume: 18, issue:1, pages: 114 - 131
Publisher: IEEE
 
» 2017: The New Computer Society
Abstract:
Ensuring the continued success of our members is the driving force behind recent and future changes to the Society's lineup of products and services. As we grow and adapt to global changes, we look to the ideas and energy of our new and renewing members to help us meet the needs of the profession and the communities we serve.
Autors: Jean-Luc Gaudiot;
Appeared in: Computer
Publication date: Jan 2017, volume: 50, issue:1, pages: 5 - 7
Publisher: IEEE
 
» 256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers
Abstract:
A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology is presented. Several vertical scale-down effects such as deteriorated WL loading and variations are discussed. To enhance performance, reverse read scheme and variable-pulse scheme are presented to cope with nonuniform WL characteristics. For improved performance, dual state machine architecture is proposed to achieve optimal timing for BL and WL, respectively. Also, to maintain robust IO driver strength against PVT variations, an embedded ZQ calibration technique with temperature compensation is introduced. The chip, fabricated in a third generation of V-NAND technology, achieved a density of 2.6 Gb/mm2 with 53.2 MB/s of program throughput.
Autors: Dongku Kang;Woopyo Jeong;Chulbum Kim;Doo-Hyun Kim;Yong Sung Cho;Kyung-Tae Kang;Jinho Ryu;Kyung-Min Kang;SungYeon Lee;Wandong Kim;Hanjun Lee;Jaedoeg Yu;Nayoung Choi;Dong-Su Jang;Cheon An Lee;Young-Sun Min;Moo-Sung Kim;An-Soo Park;Jae-Ick Son;In-Mo Kim
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 210 - 217
Publisher: IEEE
 
» 3-D Mechanically Tunable Square Slot FSS
Abstract:
We introduce an innovative 3-D mechanically tunable frequency selective surface (FSS), which is inspired by the classical flat square slot FSS. The proposal improves the performance of classical 2-D FSS designs, and it also represents a novel method of achieving mechanical frequency tuning, despite other 3-D designs that consist of a collection of stacked 3-D layers exist. In our proposal, the rotation of an inner element provides tuning capability to the squared cell structure, consisting of metallic grids with a movable inner element. An aluminum prototype was built, which can be tuned from 2.4 to 4 GHz, and also compared its measured performance and numerical simulations. Some characteristics of the proposed structure are the rejection level at main polarization, up to 20 dB, and the maximum frequency sweep of approximately 50% of the fundamental frequency. The prototype showed a stable frequency response for angles of incidence up to 45°. Since results are in good agreement with simulations, we provide parametric equations to design 3-D structures at desired frequencies.
Autors: David Ferreira;Iñigo Cuiñas;Rafael F. S. Caldeirinha;Telmo R. Fernandes;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2017, volume: 65, issue:1, pages: 242 - 250
Publisher: IEEE
 
» 3-D Memristor Crossbars for Analog and Neuromorphic Computing Applications
Abstract:
We report a monolithically integrated 3-D metal-oxide memristor crossbar circuit suitable for analog, and in particular, neuromorphic computing applications. The demonstrated crossbar is based on Pt/Al2O3/TiO2–x/TiN/Pt memristors and consists of a stack of two passive crossbars with shared middle electrodes. The fabrication process has a low, less than 175 °C, temperature budget and includes a planarization step performed before the deposition of the second crossbar layer. These features greatly improve yield and uniformity of the crosspoint devices and allows for utilizing such a fabrication process for integration with CMOS circuits as well as for stacking of multiple crossbar layers. Furthermore, the integrated crosspoint memristors are optimized for analog computing applications allowing successful forming and switching of all 200 devices in the demonstrated crossbar circuit, and, most importantly, precise tuning of the devices’ conductance values within the dynamic range of operation. We believe that the demonstrated work is an important milestone toward the implementation of analog artificial neural networks, specifically, those based on 3-D CMOL circuits.
Autors: Gina C. Adam;Brian D. Hoskins;Mirko Prezioso;Farnood Merrikh-Bayat;Bhaswar Chakrabarti;Dmitri B. Strukov;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2017, volume: 64, issue:1, pages: 312 - 318
Publisher: IEEE
 
» 3-D Numerical Simulation on Plasma Immersion Ion Implantation Batch Treating Process of Bearing Balls
Abstract:
In the plasma immersion ion implantation (PIII) process, since the dose distribution is affected by the sheath around the sample to be treated, controlling the sheath expanding process is very important for obtaining a good dose uniformity. In this paper, a 3-D particle-in-cell (PIC) model was established to study the sheath expanding process around balls of the bearing in a PIII batch treating process respectively. Using the finite difference method, the spatial distributions of the normalized potential and ion density in the simulation region were calculated by solving Poisson’s Equation, Newton’s motion equations and the Boltzmann assumption for the electrons. The influences of the magnitude and pulse width of the implantation voltage applied as well as the plasma density on the sheath conformability were studied. The simulation results show that the sheath conformability around the balls in batch treating process is worse than that in a single process due to the sheath overlap of neighbor bearing components. The bad conformability of the sheath would lead to a bad distribution of the incident dose on the surface of bearing balls. In order to guarantee the conformability of the sheath around the bearing balls, a small pulse width, enough display distance as well as proper implantation voltage and plasma density should be promised in the PIII batch treating process.
Autors: Yonghao Yu;Langping Wang;Xiaofeng Wang;Yang Lu;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Jan 2017, volume: 45, issue:1, pages: 39 - 42
Publisher: IEEE
 
» 3-D Position Location in Ad Hoc Networks: A Manhattanized Space
Abstract:
Position location information (PLI) has become a crucial requirement for the provision of multiple location-based services in cellular and wireless ad hoc networks. As sensor networks and Internet of Things scenarios proliferate, 3-D position location becomes more relevant as a solution enabler for location-based services and applications. Nevertheless, PLI acquisition techniques in 3-D ad hoc and sensor networks present several challenges. For instance, conventional triangulation algorithms may not be applicable as a direct line of sight between concerned nodes and fixed references cannot be guaranteed. In this letter, a PLI acquisition algorithm suitable for 3-D ad hoc environments is proposed based on space discretization. Feasibility of the algorithm is examined through analysis and simulation. Algorithm improvements are also proposed.
Autors: Rafaela Villalpando-Hernández;David Muñoz-Rodríguez;Cesar Vargas-Rosales;Luis Rizo-Dominguez;
Appeared in: IEEE Communications Letters
Publication date: Jan 2017, volume: 21, issue:1, pages: 124 - 127
Publisher: IEEE
 
» 3-D-Printed 96 GHz Bull’s-Eye Antenna With Off-Axis Beaming
Abstract:
Reducing the profile, footprint and weight of antennas embarked on aircrafts, drones or satellites has been a long pursued objective. Here we tackle this issue by developing a millimeter-wave 96 GHz elliptical Bull’s-Eye antenna with off-axis radiation at 16.5° that has been fabricated by low cost 3-D printing stereolithography, followed by metal coating. The theoretical basis for optimum off-axis operations is explained. Measurement results show an overall good agreement with simulations, displaying a gain of 17 dB and a 3.5° beamwidth (E-plane) at the operational frequency. The off-axis beaming enlarges the potential applicability of this technology with respect to the broadside beam solution.
Autors: Unai Beaskoetxea;Stefano Maci;Miguel Navarro-Cía;Miguel Beruete;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2017, volume: 65, issue:1, pages: 17 - 25
Publisher: IEEE
 
» 3D Statistical Shape Models Incorporating Landmark-Wise Random Regression Forests for Omni-Directional Landmark Detection
Abstract:
3D Statistical Shape Models (3D-SSM) are widely used for medical image segmentation. However, during segmentation, they typically perform a very limited unidirectional search for suitable landmark positions in the image, relying on weak learners or use-case specific appearance models that solely take local image information into account. As a consequence, segmentation errors arise, and results in general depend on the accuracy of a previous model initialization. Furthermore, these methods become subject to a tedious and use-case dependent parameter tuning in order to obtain optimized results. To overcome these limitations, we propose an extension of 3D-SSM by landmark-wise random regression forests that perform an enhanced omni-directional search for landmark positions, thereby taking rich non-local image information into account. In addition, we provide a long distance model fitting based on a multi-scale approach, that allows an accurate and reproducible segmentation even from distant image positions, thus enabling an application without model initialization. Finally, translation of the proposed method to different organs is straightforward and requires no adaptation of the training process. In segmentation experiments on 45 clinical CT volumes, the proposed omni-directional search significantly increased accuracy and displayed great precision regardless of model initialization. Furthermore, for liver, spleen and kidney segmentation in a competitive multi-organ labeling challenge on publicly available data, the proposed method achieved similar or better results than the state of the art. Finally, liver segmentation results were obtained that successfully compete with specialized state-of-the-art methods from the well-known liver segmentation challenge SLIVER.
Autors: Tobias Norajitra;Klaus H. Maier-Hein;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Jan 2017, volume: 36, issue:1, pages: 155 - 168
Publisher: IEEE
 
» 3D-DXA: Assessing the Femoral Shape, the Trabecular Macrostructure and the Cortex in 3D from DXA images
Abstract:
The 3D distribution of the cortical and trabecular bone mass in the proximal femur is a critical component in determining fracture resistance that is not taken into account in clinical routine Dual-energy X-ray Absorptiometry (DXA) examination. In this paper, a statistical shape and appearance model together with a 3D-2D registration approach are used to model the femoral shape and bone density distribution in 3D from an anteroposterior DXA projection. A model-based algorithm is subsequently used to segment the cortex and build a 3D map of the cortical thickness and density. Measurements characterising the geometry and density distribution were computed for various regions of interest in both cortical and trabecular compartments. Models and measurements provided by the “3D-DXA” software algorithm were evaluated using a database of 157 study subjects, by comparing 3D-DXA analyses (using DXA scanners from three manufacturers) with measurements performed by Quantitative Computed Tomography (QCT). The mean point-to-surface distance between 3D-DXA and QCT femoral shapes was 0.93 mm. The mean absolute error between cortical thickness and density estimates measured by 3D-DXA and QCT was 0.33 mm and 72 mg/cm3. Correlation coefficients (R) between the 3D-DXA and QCT measurements were 0.86, 0.93, and 0.95 for the volumetric bone mineral density at the trabecular, cortical, and integral compartments respectively, and 0.91 for the mean cortical thickness. 3D-DXA provides a detailed analysis of the proximal femur, including a separate assessment of the cortical layer and trabecular macrostructure, which could potentially improve osteoporosis management while maintaining DXA as the standard routine modality.
Autors: Ludovic Humbert;Yves Martelli;Roger Fonollà;Martin Steghöfer;Silvana Di Gregorio;Jorge Malouf;Jordi Romera;Luis Miguel Del Río Barquero;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Jan 2017, volume: 36, issue:1, pages: 27 - 39
Publisher: IEEE
 
» 4-D Flow Control in Porous Scaffolds: Toward a Next Generation of Bioreactors
Abstract:
Tissue engineering (TE) approaches that involve seeding cells into predetermined tissue scaffolds ignore the complex environment where the material properties are spatially inhomogeneous and evolve over time. We present a new approach for controlling mechanical forces inside bioreactors, which enables spatiotemporal control of flow fields in real time. Our adaptive approach offers the flexibility of dialing-in arbitrary shear stress distributions and adjusting flow field patterns in a scaffold over time in response to cell growth without needing to alter scaffold structure. This is achieved with a multi-inlet bioreactor and a control algorithm with learning capabilities to dynamically solve the inverse problem of computing the inlet pressure distribution required over the multiple inlets to obtain a target flow field. The new method constitutes a new platform for studies of cellular responses to mechanical forces in complex environments and opens potentially transformative possibilities for TE.
Autors: Khalid Youssef;Nanette N. Jarenwattananon;Brian J. Archer;Julia Mack;M. Luisa Iruela-Arispe;Louis-S. Bouchard;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Jan 2017, volume: 64, issue:1, pages: 61 - 69
Publisher: IEEE
 
» 40 GSample/s All-Optical Analog to Digital Conversion With Resolution Degradation Prevention
Abstract:
In this letter, we report the experimental demonstration of a 40 GSample/s all-optical analog to digital converter (ADC). The proposed all-optical ADC consists of optical quantization and coding processes based on intensity-to-wavelength conversion by soliton self-frequency shift with an optical sampling process using an ultrastable optical pulse train. A 5-GHz sinusoidal analog input signal was successfully converted to a digitized output signal in real time with no degradation of resolution. (High sampling rate operation may lead to resolution degradation due to the reduction of pulse peak power and the narrowing of the interval between adjacent pulses.) To evaluate system performance, we estimated the effective number of bits from the experimental results as 3.79 b.
Autors: Tomotaka Nagashima;Makoto Hasegawa;Tsuyoshi Konishi;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2017, volume: 29, issue:1, pages: 74 - 77
Publisher: IEEE
 
» 5.6 Mb/mm $^{2}$ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology
Abstract:
Multiported high-performance on-die memories occupy significantly more die area than a comparable single-port memory. Among various multiport memory topologies, the 1-read (R), 1-write (W) 8-transistor (T) Static Random Access Memory (SRAM) with a decoupled read port allows separate optimization of the read and write ports when organized without interleaved logical columns. This enables a lower minimum operating voltage () compared with other dual-port SRAMs that require ports optimized for read stability and write operations. However, the 1R1W 8T SRAM often employs large signal, hierarchical bitline sensing to achieve high performance due to the nondifferential read bitline. This large-signal read architecture necessitates frequently placed local bitline sensing circuits, degrading the array bit density. In this paper, we present two sense amplifier (SA) techniques for small-signal pseudo-differential sensing to facilitate 256 bits per bitline achieving an 8T SRAM array density of 5.6 Mb/mm in 14 nm FinFET CMOS. The first design employs a charge sharing SA scheme to generate a reference voltage () by leveraging the capacitance of otherwise unused metal tracks over the bitcell column. The second design utilizes an asymmetric SA in which the read bitline precharged to in the unselected sector acts as a reference voltage and the active bitline side is intentionally upsized to skew the SA. High volume measurement results demonstrate 560 mV at 400 MHz/−10 °C and reaches 2.21- GHz at 1 V supply.
Autors: Jaydeep P. Kulkarni;John Keane;Kyung-Hoae Koo;Satyanand Nalam;Zheng Guo;Eric Karl;Kevin Zhang;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 229 - 239
Publisher: IEEE
 
» 60-GHz LTCC Differential-Fed Patch Antenna Array With High Gain by Using Soft-Surface Structures
Abstract:
This paper presents a 60-GHz differential -fed patch antenna array using low-temperature cofired ceramic (LTCC) process. Wideband patch with L-shaped feeding scheme is adopted as antenna element, while differential substrate integrated waveguide feeding network with low insertion loss is applied for the integration of antenna array. The differential-fed structure improves the symmetry of radiation patterns and reduces the cross-polarization level significantly. To further suppress the surface wave and improve the gain of the antenna array, one kind of soft surface structure is proposed. The equivalent circuit model of the soft surface is developed for calculating its dispersion diagram and analyzing stopband characteristics. The simulated results indicate that the antenna gain enhancement can be up to 2 dB because of the proposed soft surface. For demonstration, one prototype using LTCC process is fabricated and measured. The measured 10-dB impedance bandwidth of the antenna array is 11.7%. The measured antenna peak gain of 18.62 dBi at 61.5 GHz and symmetrical radiation patterns with a low cross polarization of −25 dB across the whole operating frequency are achieved.
Autors: Huayan Jin;Wenquan Che;Kuo-Sheng Chin;Guangxu Shen;Wanchen Yang;Quan Xue;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2017, volume: 65, issue:1, pages: 206 - 216
Publisher: IEEE
 
» 7.28-W, High-Energy, Conductively Cooled, Q-Switched Tm,Ho:YLF Laser
Abstract:
A diode-side-pumped laser oscillator with a Tm,Ho:YLF rod conductively cooled to −80 °C was developed. A Q-switched pulse energy of 104 mJ was achieved at a pulse repetition frequency of 70 Hz, corresponding to an average output power of 7.28 W. In addition, the maximum Q-switched pulse energy of 125 mJ was obtained at 50 Hz. Even at the maximum output level, the beam quality factor was measured to be 1.5. To the best of our knowledge, this is the highest average output power reported for a 100-mJ-class Q-switched 2- laser oscillator using a conductively cooled laser head.
Autors: Atsushi Sato;Makoto Aoki;Shoken Ishii;Ryouhei Otsuka;Kohei Mizutani;Satoshi Ochiai;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2017, volume: 29, issue:1, pages: 134 - 137
Publisher: IEEE
 
» A $4 times 4 times 2$ Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links
Abstract:
Future many cores, either for high performance computing or for embedded applications, are facing the power wall, and cannot be scaled up using only the reduction of technology nodes; 3D integration, using through silicon via (TSV) as an advanced packaging technology, allows further system integration, while reducing the power dissipation devoted to system-level communication. In this paper, we present a 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic. The 3DNOC circuit targets a Telecom long-term evolution application; it is composed of two die layers, fabricated in 65 nm technology using TSV middle aspect ratio 1:8, and integrates ESD protection, a 3D design-for-test, and a fault tolerant scheme. The 3D links achieve 0.66 pJ/b energy consumption and 326 Mb/s data rate per pin for the parallel link. Thin die effect is demonstrated by thermal analysis and measurements, as well as the dynamic self-adaptation of the 3D link performances with 3D thermal conditions. Finally, the scalability of the 3DNOC circuit, in terms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eight die layers.
Autors: Pascal Vivet;Yvain Thonnart;Romain Lemaire;Cristiano Santos;Edith Beigné;Christian Bernard;Florian Darve;Didier Lattard;Ivan Miro-Panadès;Denis Dutoit;Fabien Clermidy;S. Cheramy;Abbas Sheibanyrad;Frédéric Pétrot;Eri
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 33 - 49
Publisher: IEEE
 
» A $K$ -Band High Efficiency High Power Monolithic GaAs Power Oscillator Using Class-E Network
Abstract:
This letter presents design of a K-band high power high efficiency monolithic GaAs power oscillators using class-E load network with finite dc-feed inductance. To further extend the operation frequency up to millimeter-wave band with high efficiency, the core transistor is operated in the saturated region with overdriven condition to obtain the bifurcated current waveform. The proposed power oscillator is fabricated using a 0.15- GaAs pseudomorphic high-electron mobility transistor process, and it features a tuning range from 23.5 to 24.5 GHz, a peak efficiency of 19%, a maximum output power of 21 dBm, and a phase noise of −106.3 dBc/Hz at 1-MHz offset.
Autors: Hong-Yeh Chang;Chi-Hsien Lin;Yu-Cheng Liu;Wen-Ping Li;Yu-Chi Wang;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2017, volume: 27, issue:1, pages: 55 - 57
Publisher: IEEE
 
» A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction
Abstract:
Closed-loop neuromodulation is an essential function in future neural implants for delivering efficient and effective therapy. However, a closed-loop system requires the neural-recording front-end to handle large stimulation artifacts—a feature not supported by most state-of-the-art designs. In this paper, we present a neural-recording front-end that has an input range of ±50 mV and can be used in closed-loop systems. The proposed front-end avoids the saturation due to stimulation artifacts by employing a voltage-controlled oscillator (VCO) to directly convert the input signal into the frequency domain. The VCO nonlinearity is corrected using area-efficient foreground polynomial correction. Implemented in a 40-nm CMOS process, the design occupies 0.135 mm with an analog power of 3 and a digital switching power of 4 . It achieves ten times higher linear input range than prior art, and 79-dB spurious-free dynamic range at peak input, with an input-referred noise of 5.2 across the local-field-potential band of 1–200 Hz. With on-chip subhertz high-pass filters realized by duty-cycled resistors, the front-end also eliminates the need of off-chip dc-blocking capacitors.
Autors: Wenlong Jiang;Vahagn Hokhikyan;Hariprasad Chandrakumar;Vaibhav Karkare;Dejan Marković;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 173 - 184
Publisher: IEEE
 
» A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS
Abstract:
Modern multicore processors employ multiple phase-locked loops (PLLs) to operate individual cores at a power-optimal frequency. This paper presents techniques to implement such PLLs in a small area. The area occupied by classical charge-pump-based analog PLLs is mostly due to the large loop filter capacitor needed to implement the integral control portion of type-II response. Digital PLLs (DPLL) can eliminate the capacitor by implementing the integral control in digital domain but their jitter performance is degraded by the quantization error introduced by DPLL building blocks such as a time-to-digital converter (TDC). We seek to combine the advantages of analog (no quantization error) and digital (small area) PLLs by implementing the integral control using time-based techniques. To this end, a ring oscillator-based integrator (ROI) is used to implement the integral control. ROI integrates its input and generates an output in the form of a pulse-width modulated (PWM) signal. While the ROI does not introduce quantization error, controlling the voltage controlled oscillator with the PWM signal introduces undesirable spurious tones. We propose to use a pseudo-differential ROI to mitigate these tones and achieve good jitter performance. Fabricated in 65 nm CMOS LP process, the prototype PLL occupies an active area of only 0.0021 mm2 and operates across a supply voltage range of 0.6 V to 1.2 V providing 0.4–2.6 GHz output frequencies. At 2.2 GHz output frequency, the PLL consumes 1.82 mW at 1 V supply voltage, and achieves 3.73 psrms integrated jitter. This translates to an FoMJ of −226.0 dB, which compares favorably with state-of-the-art designs while occupying the smallest reported active area.
Autors: Junheng Zhu;Romesh Kumar Nandwana;Guanghua Shu;Ahmed Elkholy;Seong Joong Kim;Pavan Kumar Hanumolu;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 8 - 20
Publisher: IEEE
 
» A 0.5–9.5-GHz, 1.2- $mu text{s}$ Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling
Abstract:
A phase-locked loop (PLL) architecture is proposed for improved efficiency of power and thermal management techniques in system-on-chips (SoCs). PLL architecture introduces two techniques: a dual-stage phase-acquisition loop filter that enables fast lock time of 1.2 without any frequency overshoots and a nonlinear DCO that enables a wide frequency range of 0.5–9.5 GHz and a low period jitter of ±1.25%UI p-p with a single wideband tuning. With this proposed PLL architecture, SoC can continue its operation without any interruption caused by frequency overshoots during power and thermal management techniques like dynamic core-count scaling and dynamic voltage frequency scaling. The PLL achieves 0.45 ps rms period jitter at 3.25 GHz in fractional-N mode operation, while consuming a total power of 7.1 mW.
Autors: Fazil Ahmad;Greg Unruh;Amrutha Iyer;Pin-En Su;Sherif Abdalla;Bo Shen;Mark Chambers;Ichiro Fujimori;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 21 - 32
Publisher: IEEE
 
» A 0.6-V, 0.015-mm2, Time-Based ECG Readout for Ambulatory Applications in 40-nm CMOS
Abstract:
A scalable time-based analog front end in 40-nm CMOS is presented for ECG readout for ambulatory applications. The main challenge addressed is achieving a large dynamic range readout (necessary to handle large signals during motion) in a power and area-efficient manner at low voltage supplies while also tackling the challenges of increase in flicker noise and gate-leakage current. Demonstrated results show a significant improvement in ac-dynamic range without compromising on area (0.015 mm) and power consumption (). This paper will be relevant toward developing low-cost, low-power sensor system-on-chips required for wearable biomedical applications.
Autors: Rachit Mohan;Samira Zaliasl;Georges G. E. Gielen;Chris Van Hoof;Refet Firat Yazicioglu;Nick Van Helleputte;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 298 - 308
Publisher: IEEE
 
» A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution
Abstract:
A 1.2 V 20 nm 307 GB/s high-bandwidth memory (HBM) DRAM is presented to satisfy a high-bandwidth requirement of high-performance computing application. The HBM is composed of buffer die and multiple core dies, and each core die has 8 Gb DRAM cell array with additional 1 Gb ECC array. At-speed wafer level, a u-bump IO test scheme and an adaptive refresh scheme considering temperature distribution are proposed to guarantee test coverage and stable operation in a power-efficient manner.
Autors: Kyomin Sohn;Won-Joo Yun;Reum Oh;Chi-Sung Oh;Seong-Young Seo;Min-Sang Park;Dong-Hak Shin;Won-Chang Jung;Sang-Hoon Shin;Je-Min Ryu;Hye-Seung Yu;Jae-Hun Jung;Hyunui Lee;Seok-Yong Kang;Young-Soo Sohn;Jung-Hwan Choi;Yong-Cheol Bae;Seong-Jin Jang;Gyoyoung
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 250 - 260
Publisher: IEEE
 
» A 1.2-V Self-Reconfigurable Recursive Mixer With Improved IF Linearity in 130-nm CMOS
Abstract:
A 1.2-V self-reconfigurable recursive mixer structure with improved intermediate frequency (IF) linearity and signal isolation is proposed. For a traditional recursive mixer that reuses the gm stage to amplify both the input radio frequency (RF) and downconverted IF signal, signal isolation and linearity are limited by the signal-reusing structure. In this brief, the self-reconfigurable gm stage is designed to provide open-loop conversion for the input RF signal and acts as a negative-feedback voltage amplifier for the downconverted IF signal. The RF and IF signal paths are also split by the filtering networks and the feedback branches within the gm stage. Thus, IF linearity, loop stability, and signal isolation are all guaranteed. The proposed mixer was designed and fabricated in a Taiwan Semiconductor Manufacturing Company 130-nm complementary metal–oxide–semiconductor process and occupied a die area of 0.48 mm2. The mixer operates in the frequency band from 2 to 3 GHz with the conversion gain of around 33 dB. The measured input-referred third-order intercept point and the double-sideband noise figure are −16 dBm and 11 dB, respectively, at 2.4-GHz input frequency. The power consumption is 2.5 mW under 1.2-V supply voltage.
Autors: Chao Chen;Jianhui Wu;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2017, volume: 64, issue:1, pages: 36 - 40
Publisher: IEEE
 
» A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique
Abstract:
A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need for a decision feedback equalizer. In order to increase the data sampling margin, the PLL bandwidth is optimized depending on the system noises, which reduces the clock jitter by up to 55.1%. The crosstalk-induced jitter (CIJ) reduction technique suppresses the DQs jitter by employing the suggested training sequence for the GDDR5 interface. Pre- and de-emphasis are merged in one auxiliary driver. This chip operates at 10 Gbits/s/pin and exhibits a data eye opening of 0.78 UI with the CIJ reduction technique. The power consumptions of the TX and RX are 8.28 and 5.5 pJ/b/channel, respectively.
Autors: Junyoung Song;Hyun-Woo Lee;Sewook Hwang;Chulwoo Kim;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2017, volume: 25, issue:1, pages: 344 - 353
Publisher: IEEE
 
» A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization
Abstract:
Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040 6T SRAM bitcell is designed for high density (HD), and 0.049 for high performance (HP). The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage () and assist overheads. The dual-transient wordline scheme is proposed to improve the by 47.5 mV for the 128 Mb 6T-HP SRAM. The suppressed bitline scheme with negative bitline improves the by 135 mV for the 128 Mb 6T-HD SRAM. The FOM of PPA gain evaluates the optimum SRAM assist for the different bitcells based on the applications.
Autors: Taejoong Song;Woojin Rim;Sunghyun Park;Yongho Kim;Giyong Yang;Hoonki Kim;Sanghoon Baek;Jonghoon Jung;Bongjae Kwon;Sungwee Cho;Hyuntaek Jung;Yongjae Choo;Jaeseung Choi;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 240 - 249
Publisher: IEEE
 
» A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations
Abstract:
A 10-bit 500-MS/s partial-interleaving pipelined successive approximation register (SAR) analog-to-digital converter (ADC) architecture is presented that implements a full-speed 2-bit/cycle SAR at the front end with interleaved residue MDACs and SAR ADCs at the back end. This architecture achieves high speed, while preventing the interleaving spurs. In addition, the design considerations and calibration techniques for gain and offset are also introduced. A histogram stage gain error (HSGE) calibration is implemented to correct the conversion nonlinearities in the digital domain. Measurement results on a 65-nm CMOS prototype show an signal-to-noise distortion ratio (SNDR) of 55.9 dB at dc input and a figure of merit (FoM) of 32 fJ/conversion step at 1.2 V supply.
Autors: Yan Zhu;Chi-Hang Chan;Seng Pan U;Rui Paulo Martins;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2017, volume: 25, issue:1, pages: 354 - 363
Publisher: IEEE
 
» A 10-GS/s 4-Bit Single-Core Digital-to-Analog Converter for Cognitive Ultrawidebands
Abstract:
This brief delineates the design and realization of a 10-GS/s 4-bit digital-to-analog converter (DAC) for the cognitive ultrawideband (CUWB), an emerging solution for low interference and efficient spectrum utilization in communication networks. The DAC serves as the data converter for the adaptive waveform transmitter therein, largely to reduce its power dissipation and hardware complexity. For reasons of low power dissipation and low-cost CUWB application, the resolution of the DAC is 4 bits, its realization is in standard 65-nm CMOS, and the architecture is a single core. The binary current-steering DAC includes critical building blocks such as current sources and a novel deglitcher circuit. The current sources are designed for small area with high linearity based on our derived relationship between current-source output resistance and linearity parameters [integral nonlinearity (INL) and spurious-free dynamic range (SFDR)]. The deglitcher design includes high-speed source followers as high-speed low voltage swing buffers to improve the linearity by decreasing the output glitch energy. The DAC embodies an in situ hardware efficient (small integrated-circuit area and reduced input/output pinout) tester that generates 4 10-Gb/s test-data pattern to facilitate functional verification. The designed DAC achieves ≤ 0.16-least significant bit INL/differential nonlinearity and > 23-dBc SFDR over the Nyquist bandwidth up to 4.53 GHz, and features the most competitive figures-of-merit of all similar DACs reported to date.
Autors: F. N. U. Juanda;Wei Shu;Joseph S. Chang;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2017, volume: 64, issue:1, pages: 16 - 20
Publisher: IEEE
 
» A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard
Abstract:
It is getting mandatory to comply with ISO26262 in the recent automotive development. The implementation of safety mechanism to detect faults is one of the keys in ISO26262. The fault prediction will make the automotive system more reliable. The SoC in this paper introduces two features: hardware built-in self-test (BIST) for safety mechanism supporting automotive safety integrity level (ASIL) B and killer-droop monitor for fault prediction. In addition, time slicing is introduced to the testing with hardware BIST during runtime so that each test session can be shorter than the required interrupt response time in the application. The killer-droop monitor can predict the voltage droop and stop the clock supply for a certain period of time to mitigate the droop for preventing delay faults on the SoC. The monitor samples the voltage based on time-to-digital converter at CPU operation clock and predicts the voltage from the history of sampled voltage. With that prediction feature, the minimum operation voltage can be improved by 50 mV at 2.02 GHz CPU operation, and the maximum frequency can be improved by 140 MHz under 0.82 V power supply in 16 nm process.
Autors: Shinichi Shibahara;Chikafumi Takahashi;Kazuki Fukuoka;Yuko Kitaji;Takahiro Irita;Hirotaka Hara;Yasuhisa Shimazaki;Jun Matsushima;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 77 - 88
Publisher: IEEE
 
» A 2.3-mW 11-cm Range Bootstrapped and Correlated-Double-Sampling Three-Dimensional Touch Sensing Circuit for Mobile Devices
Abstract:
This brief discusses an oscillator-based capacitive 3-D touch-sensing circuit for mobile devices. The proposed 3-D touch sensor uses correlated double sampling to achieve a high sensing resolution in the Z-direction and employs bootstrapping circuitry to reduce the mobile screen's interchannel-coupling effects. Additionally, to reduce chip area and assembly, the sensing oscillator is implemented with inverter-based active resonators instead of using either on- or off-chip inductors. The prototyped 3-D touch sensor is fabricated using 65-nm CMOS process technology and consumes an area of 2 mm2, with a 2.3-mW power consumption from a 1-V power supply. Measured together with a 3.4′′ HTC standard mobile screen, the sensor achieves an 11-cm Z-direction sensing range with a 1-cm resolution, demonstrating the potential implementation of 3-D finger position sensing in a mobile device.
Autors: Li Du;Yan Zhang;Chun-Chen Liu;Adrian Tang;Frank Hsiao;Mau-Chung Frank Chang;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2017, volume: 64, issue:1, pages: 96 - 100
Publisher: IEEE
 
» A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
Abstract:
A high-resolution time-to-digital converter (TDC) implemented with field programmable gate array (FPGA) based on delay wrapping and averaging is presented. The fundamental idea is to pass a single clock through a series of delay elements to generate multiple reference clocks with different phases for input time quantization. Due to periodicity, those phases will be equivalently wrapped within one reference clock period to achieve the required fine resolution. In practice, a hybrid delay matrix is created to significantly reduce the required number of delay cells. Multiple TDC cores are constructed for parallel measurements and then exquisite routing control and averaging are applied to smooth out the large quantization errors caused by the inhomogeneity of the TDC delay lines for both linearity and single-shot precision enhancement. To reduce the impact of temperature sensitivity, a cancellation circuit is created to substantially reduce the offset and confine the output difference within 2 LSB for the same input interval over the full operation temperature range of FPGA. With such a fine resolution of 2.5 ps, the integral nonlinearity is measured to be from merely −2.98 to 3.23 LSB and the corresponding rms resolution is 4.99–6.72 ps. The proposed TDC is tested to be fully functional over 0 °C–50 °C ambient temperature range with extremely low resolution variation. Its performance is even superior to many full-custom-designed TDCs.
Autors: Poki Chen;Ya-Yun Hsiao;Yi-Su Chung;Wei Xiang Tsai;Jhih-Min Lin;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2017, volume: 25, issue:1, pages: 114 - 124
Publisher: IEEE
 
» A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor
Abstract:
This paper proposes a coarse-fine dual-loop architecture for the digital low drop-out (LDO) regulators with fast transient response and more than 200-mA load capacity. In the proposed scheme, the output voltage is coregulated by two loops, namely, the coarse loop and the fine loop. The coarse loop adopts a fast current-mirror flash analog to digital converter and supplies high output current to enhance the transient performance, while the fine loop delivers low output current and helps reduce the voltage ripples and improve the regulation accuracies. Besides, a digital controller is implemented to prevent contentions between the two loops. Fabricated in a 28-nm Samsung CMOS process, the proposed digital LDO achieves maximum load up to 200 mA when the input and the output voltages are 1.1 and 0.9 V, respectively, with a chip area of 0.021 mm2. The measured output voltage drop of around 120 mV is observed for a load step of 180 mA.
Autors: Yong-Jin Lee;Wanyuan Qu;Shashank Singh;Dae-Yong Kim;Kwang-Ho Kim;Sang-Ho Kim;Jae-Jin Park;Gyu-Hyeong Cho;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 64 - 76
Publisher: IEEE
 
» A 220-mV Power-on-Reset Based Self-Starter With 2-nW Quiescent Power for Thermoelectric Energy Harvesting Systems
Abstract:
Miniaturized thin-film thermoelectric generators (TEGs) are emerging energy harvesting sources suitable for wearable and implantable applications. However, these sources usually exhibit large internal equivalent series resistance (ESR) that leads to low energy conversion efficiency and self-startup failures at ultra-low voltages. This paper presents a highly efficient boost converter with a novel Power-on-Reset (PoR) based self-startup circuit for systems harvesting the micro-scale thermal energy. The proposed circuit generates a train of pulses to kick start the self-startup through an internal feedback loop formed by the ESR of TEG, an auxiliary boost converter and a PoR circuit. The self-startup circuit is automatically disabled after the startup operation with a quiescent power consumption of 2 nW. A boost converter test chip with the proposed self-starter was fabricated in 65-nm CMOS technology node. It achieved a self-startup TEG voltage of 220 mV and a peak conversion efficiency of 76%. The minimum input voltage to sustain the boost operation is as low as 85 mV after the startup.
Autors: Abhik Das;Yuan Gao;Tony Tae-Hyoung Kim;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2017, volume: 64, issue:1, pages: 217 - 226
Publisher: IEEE
 
» A 24 GHz High Frequency-Sweep Linearity FMCW Signal Generator with Floating-Shield Distributed Metal Capacitor Bank
Abstract:
A 24 GHz FMCW generator based on ADPLL was implemented in this work. Two-point modulation technology was used to achieve high sweep linearity. Meanwhile, a floating shield distributed metal capacitor bank was proposed to provide high frequency-sweep linearity DCO. By using these technologies, the FMCW generator’s frequency error can be controlled as small as 60 kHzrms when 180 MHz frequency was swept in 1.3 ms. High speed part of the FMCW generator was fabricated in 65 nm CMOS technology and the low speed digital part was implemented on FPGA. Power consumption of the chip excluding IO buffers is 29 mW.
Autors: Jianfei Xu;Na Yan;Sichen Yu;Lei Ma;Dashan Pan;Xiaoyang Zeng;Hao Min;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2017, volume: 27, issue:1, pages: 52 - 54
Publisher: IEEE
 
» A 3-D Active Contour Method for Automated Segmentation of the Left Ventricle From Magnetic Resonance Images
Abstract:
Objective: This study's objective is to develop and validate a fast automated 3-D segmentation method for cardiac magnetic resonance imaging (MRI). The segmentation algorithm automatically reconstructs cardiac MRI DICOM data into a 3-D model (i.e., direct volumetric segmentation), without relying on prior statistical knowledge. Methods: A novel 3-D active contour method was employed to detect the left ventricular cavity in 33 subjects with heterogeneous heart diseases from the York University database. Papillary muscles were identified and added to the chamber using a convex hull of the left ventricle and interpolation. The myocardium was then segmented using a similar 3-D segmentation method according to anatomic information. A multistage approach was taken to determine the method's efficacy. Results: Our method demonstrated a significant improvement in segmentation performance when compared to manual segmentation and other automated methods. Conclusion and Significance: A true 3-D reconstruction technique without the need for training datasets or any user-driven segmentation has been developed. In this method, a novel combination of internal and external energy terms for active contour was utilized that exploits histogram matching for improving the segmentation performance. This method takes advantage of full volumetric imaging, does not rely on prior statistical knowledge, and employs a convex-hull interpolation to include the papillary muscles.
Autors: Mahdi Hajiaghayi;Elliott M. Groves;Hamid Jafarkhani;Arash Kheradvar;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Jan 2017, volume: 64, issue:1, pages: 134 - 144
Publisher: IEEE
 
» A 4.7-Gb/s Reconfigurable CMOS Imaging Optical Receiver Utilizing Adaptive Spectrum Balancing Equalizer
Abstract:
This paper presents a fully integrated imaging receiver for high data rate wireless optical communication. A matrix of Spatially Modulated Light detectors (SML), each with 730-MHz bandwidth followed by on-chip switches are integrated to allow the detection of photodiodes (PDs) in Line of Sight (LOS) with the transmitter. The imaging optical receiver employs a novel adaptive equalizer that uses spectrum reshaping to equalize the low bandwidth of the SML PD and partially compensate for the variable capacitance seen by the transimpedance amplifier resulting from dynamic LOS variations. Implemented in 130-nm CMOS technology, the chip provides an optical sensitivity of -3.5 dBm for nm modulated light with 4.7-Gb/s random data at , and -4.4 dBm at 4.5 Gb/s with , using one activated PD. For the case when all nine PDs are activated, corresponding to 11.5 pF total PDs capacitance at the input of the transimpedance amplifier, measurement results show a sensitivity of -5 dBm for 2-Gb/s data at . The total power consumption including the differential output buffer is 97 mW from a single 1.5-V supply while providing 750-mV peak to peak output voltage over the differential resistance of the measurement equipment. The total die area including bond pads is .
Autors: Behrooz Nakhkoob;Mona Mostafa Hella;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2017, volume: 64, issue:1, pages: 182 - 194
Publisher: IEEE
 
» A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
Abstract:
This brief presents a novel 4096-point radix-4 memory-based fast Fourier transform (FFT). The proposed architecture follows a conflict-free strategy that only requires a total memory of size and a few additional multiplexers. The control is also simple, as it is generated directly from the bits of a counter. Apart from the low complexity, the FFT has been implemented on a Virtex-5 field programmable gate array (FPGA) using DSP slices. The goal has been to reduce the use of distributed logic, which is scarce in the target FPGA. With this purpose, most of the hardware has been implemented in DSP48E. As a result, the proposed FPGA is efficient in terms of hardware resources, as is shown by the experimental results.
Autors: Mario Garrido;Miguel Ángel Sánchez;María Luisa López-Vallejo;Jesús Grajal;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2017, volume: 25, issue:1, pages: 375 - 379
Publisher: IEEE
 
» A 5-bit 300–900-MS/s 0.8–1.2-V Supply Voltage ADC With Background Self-Calibration
Abstract:
Low-power, high-speed, and low-resolution analog-to-digital converters (ADCs) are mandatory for a wide range of modern applications. In this brief, a background-calibrated low-power 5-bit comparator-based binary-search ADC is presented. The ADC, which was implemented in a 130-nm complementary metal–oxide–semiconductor process, can compensate for process–voltage–temperature variations on-the-fly and offers state-of-the-art figure of merit (FoM) for the set of specifications. Multiple track-and-hold working in time interleaving are employed to enable increased conversion speed at low power consumption, whereas the comparator stages operate in amplifierless pipelining. As the comparators present a significant offset spread due to process variations, the thresholds are concurrently calibrated with the conversion using a reference digital-to-analog converter. The ADC operates with supply voltages ranging from 0.8 to 1.2 V. When supplied with 0.8 V, the ADC performs up to 300 MS/s and presents 28.13 dB, 235 , and 39.4 fJ/conversion step of signal-to-noise-and-distortion ratio (SNDR), power consumption, and FoM, respectively. With 1.2 V of supply, the ADC performs up to 900 MS/s and presents 27.83 dB of SNDR, 1.54 mW of power consumption, and 82.5 fJ/conversion step of FoM.
Autors: Fábio Rabuske;Taimur Rabuske;Jorge Fernandes;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2017, volume: 64, issue:1, pages: 1 - 5
Publisher: IEEE
 
» A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network
Abstract:
A digital clock and data recovery (CDR) is presented, which employs a low supply sensitivity scheme for a digitally controlled oscillator (DCO). A coupling network comprising capacitors, resistors, and coupling buffers enhances the supply variation immunity of the DCO and mitigates the jitter performance degradation. A supply variation-dependent bias generator produces the corresponding bias voltage to alleviate the supply variation with minimal area and power penalty. The proposed scheme improves 29.3 ps of peak-to-peak jitter and 11.5 dB of spur level, at 6 and 5 MHz 50 mVpp sinusoidal supply noise tone, respectively. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER for PRBS 31 and consumes 15.4 mW. The CDR occupies an active die area of 0.075 mm2.
Autors: Taeho Lee;Yong-Hun Kim;Lee-Sup Kim;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2017, volume: 25, issue:1, pages: 380 - 384
Publisher: IEEE
 
» A 502-GOPS and 0.984-mW Dual-Mode Intelligent ADAS SoC With Real-Time Semiglobal Matching and Intention Prediction for Smart Automotive Black Box System
Abstract:
The advanced driver assistance system (ADAS) for adaptive cruise control and collision avoidance is strongly dependent upon the robust image recognition technology such as lane detection, vehicle/pedestrian detection, and traffic sign recognition. However, the conventional ADAS cannot realize more advanced collision evasion in real environments due to the absence of intelligent vehicle/pedestrian behavior analysis. Moreover, accurate distance estimation is essential in ADAS applications and semiglobal matching (SGM) is most widely adopted for high accuracy, but its system-on-chip (SoC) implementation is difficult due to the massive external memory bandwidth. In this paper, an ADAS SoC with behavior analysis with Artificial Intelligence functions and hardware implementation of SGM is proposed. The proposed SoC has dual-mode operations of high-performance operation for intelligent ADAS with real-time SGM in D-Mode (d-mode) and ultralow-power operation for black box system in parking-mode. It features: 1) task-level pipelined SGM processor to reduce external memory bandwidth by 85.8%; 2) region-of-interest generation processor to reduce 86.2% of computation; 3) mixed-mode intention prediction engine for dual-mode intelligence; and 4) dynamic voltage and frequency scaling control to save 36.2% of power in d-mode. The proposed ADAS processor achieves 862 GOPS/W energy efficiency and 31.4-GOPS/mm2 area efficiency, which are 1.53 and 1.75 improvements than the state of the art, with 30 frames/s throughput under 720p stereo inputs.
Autors: Kyuho Jason Lee;Kyeongryeol Bong;Changhyeon Kim;Jaeeun Jang;Kyoung-Rog Lee;Jihee Lee;Gyeonghoon Kim;Hoi-Jun Yoo;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 139 - 150
Publisher: IEEE
 
» A 64 $times$ 64-Pixels Digital Silicon Photomultiplier Direct TOF Sensor With 100-MPhotons/s/pixel Background Rejection and Imaging/Altimeter Mode With 0.14% Precision Up To 6 km for Spacecraft Navigation and Landing
Abstract:
This paper describes a 6464-pixel 3-D imager based on single-photon avalanche diodes (SPADs) for long-range applications, such as spacecraft navigation and landing. Each 60- pixel includes eight SPADs combined as a digital silicon photomultiplier, a triggering logic for photons temporal correlation, a 250-ps 16-b time-to-digital converter, and an intensity counter, with an overall 26.5% fill factor. The sensor provides time-of-flight and intensity information even with a background intensity up to 100 MPhotons/s/pixel. The sensor can work in imaging (short range, 3-D image) and altimeter (long range, single point) modes, achieving up to 300-m and 6-km maximum distance with <0.2-m and <0.5-m precision, respectively, consuming less than 100 mW.
Autors: Matteo Perenzoni;Daniele Perenzoni;David Stoppa;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 151 - 160
Publisher: IEEE
 
» A 650 V Super-Junction MOSFET With Novel Hexagonal Structure for Superior Static Performance and High BV Resilience to Charge Imbalance: A TCAD Simulation Study
Abstract:
A superjunction MOSFET (SJ-MOSFET) with a new fully close-packed hexagonal pattern for its superjunction (SJ) region is proposed. According to TCAD simulation, the proposed device can accommodate highly doped n-pillars with no significant degradation of its blocking voltage (BV), where its conventional counterpart, a SJ-MOSFET with a stripe-patterned SJ region is incapable of. In comparison with the conventional device, the proposed device shows dramatic reduction of ON-resistance down by 41% while keeping its BV of 650 V. The proposed device also shows superior BV resilience to charge imbalance than the conventional device.
Autors: Jaehoon Park;Jong-Ho Lee;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2017, volume: 38, issue:1, pages: 111 - 114
Publisher: IEEE
 
» A Bandpass Sampling Receiver for Wide-Bandwidth, Spectrally-Sparse Waveforms for High-Accuracy Range Measurements
Abstract:
Measuring range to millimeter accuracy using microwave wireless systems is challenging due to the need for wide-bandwidth waveforms. This work presents a Sparse Ranging Receiver (SpaRR) that utilizes spectrally-sparse waveforms and bandpass sampling to achieve high range accuracy measurements without the need for expensive wideband digitizers. The accuracy of a ranging system varies inversely with the RMS bandwidth of the waveform, and the optimal ranging waveform is one that concentrates its frequency content at the edges of its bandwidth. The SpaRR utilizes widely separate two-tone waveforms from L to X band to achieve high range accuracy with a low-speed digitizer. The theory, architecture, and signal processing associated with the SpaRR are presented, and measurements are shown demonstrating accuracies on the order of for tone separations on the order of 2 GHz.
Autors: Thomas M. Comberiate;Robert L. Schmid;Jason E. Hodkin;Matthew D. Sharp;Jeffrey A. Nanzer;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2017, volume: 27, issue:1, pages: 88 - 90
Publisher: IEEE
 
» A Bayesian Method for Localization by Multistatic Active Sonar
Abstract:
The question of localizing a target with multistatic active sonar is reexamined from the perspective of finding a peak in a probability distribution function. The probability distribution function is constructed using straightforward Bayesian principles. Both a position estimate and a covariance matrix can be found, provided that an implementation of a numerical algorithm for finding a local maximum is available. The localization method developed herein can account for transmitter and receiver location errors, sound-speed errors, time errors, and bearing errors. A Monte Carlo test is conducted to compare the accuracy of the proposed method to that of a more conventional method used as a baseline. In each iteration, a transmitter, several receivers, and a target are positioned randomly within a square region, and the target is localized by both methods. The proposed method is generally more accurate than the baseline method, within the range of parameters considered here. The degree of improvement over the baseline is greater with a larger region area, with a larger bearing measurement error, and with a smaller time-of-arrival measurement error, and slightly greater with a larger number of receivers.
Autors: Daniel J. Peters;
Appeared in: IEEE Journal of Oceanic Engineering
Publication date: Jan 2017, volume: 42, issue:1, pages: 135 - 142
Publisher: IEEE
 
» A Bayesian Nonparametric Model for Disease Subtyping: Application to Emphysema Phenotypes
Abstract:
We introduce a novel Bayesian nonparametric model that uses the concept of disease trajectories for disease subtype identification. Although our model is general, we demonstrate that by treating fractions of tissue patterns derived from medical images as compositional data, our model can be applied to study distinct progression trends between population subgroups. Specifically, we apply our algorithm to quantitative emphysema measurements obtained from chest CT scans in the COPDGene Study and show several distinct progression patterns. As emphysema is one of the major components of chronic obstructive pulmonary disease (COPD), the third leading cause of death in the United States [1], an improved definition of emphysema and COPD subtypes is of great interest. We investigate several models with our algorithm, and show that one with , (a measure of cigarette exposure), and as predictors gives the best compromise between estimated predictive performance and model complexity. This model identified nine subtypes which showed significant associations to seven single nucleotide polymorphisms (SNPs) known to associate with COPD. Additionally, this model gives better predictive accuracy than multiple, multivariate ordinary least squares regression as demonstrated in a five-fold cross validation analysis. We view our subtyping algorithm as a contribution that can be applied to bridge the gap between CT-level assessment of tissue composition to population-level analysis of compositional trends that vary between disease subtypes.
Autors: James C. Ross;Peter J. Castaldi;Michael H. Cho;Junxiang Chen;Yale Chang;Jennifer G. Dy;Edwin K. Silverman;George R. Washko;Raúl San José Estépar;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Jan 2017, volume: 36, issue:1, pages: 343 - 354
Publisher: IEEE
 
» A Better Balun? Done The Design of a 4:1 Wideband Balun Using a Parallel-Connected Transmission-Line Balun
Abstract:
This article presents a 4:1 wide-band balun that won the student design competition for wide-band baluns held during the 2016 IEEE Microwave Theory and Techniques Society (MTT-S) International Microwave Symposium (IMS2016) in San Francisco, California. For this contest, sponsored by Technical Committee MTT-17, participants were required to implement and evaluate their own baluns, with the winning entry achieving the widest bandwidth while satisfying the conditions of the competition rules during measurements at IMS2016. Some of the conditions were revised for this year's competition compared with previous competitions as follows.
Autors: Hansik Oh;Wooseok Lee;Hwiseob Lee;Hyungmo Koo;Sungjae Oh;Keum Choel Hwang;Kang-Yoon Lee;Cheon-seok Park;Youngoo Yang;
Appeared in: IEEE Microwave Magazine
Publication date: Jan 2017, volume: 18, issue:1, pages: 85 - 90
Publisher: IEEE
 
» A Bias-Bounded Digital True Random Number Generator Architecture
Abstract:
Bias phenomenon has been a ubiquitous problem in the designs of digital True Random Number Generator (TRNG). Circuit performance can be improved with some auxiliary modules such as analog circuits and post-processing components, which usually involve the compromising of cost, compatibility, throughput, and security as well. In some cases only sub-optimal designs can be achieved. In this paper, by utilizing the diverse timing characteristics of different initial states, a staged-running Self-timed Ring (STR) architecture, which is able to suppress the degree of bias, is proposed. The proposed architecture is compared with some conventional free-running architectures using a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) platform for a throughput of 100 Mbps. With the increase of the ring size, the bias degree of the newly proposed structure is within a negligible level of less than 1%; whereas those of the conventional architectures can exceed 10%. Statistical tests were also conducted and the results show that the quality of randomness rises as the complexity in initial-state mapping and the ring nodes of the proposed structure increases. The test passes the National Institute of Standards and Technology (NIST) test suite with high p-values.
Autors: Yao Liu;Ray C. C. Cheung;Hei Wong;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2017, volume: 64, issue:1, pages: 133 - 144
Publisher: IEEE
 
» A Charge-Plasma-Based Dielectric-Modulated Junctionless TFET for Biosensor Label-Free Detection
Abstract:
To reduce the fabrication complexity and cost of the nanoscale devices, a charge-plasma concept is introduced for the first time to implement a dielectric-modulated junctionless tunnel field-effect transistor (DM-JLTFET) for biosensor label-free detection. The formation of p+ source and n+ drain regions in DM-JLTFET is done by the deposition of platinum (work function = 5.93 eV) and hafnium (work function = 3.9 eV) materials, respectively, over the silicon body. Furthermore, a nanogap cavity embedded within the gate dielectric is created by etching the portion of gate oxide layer toward the source end for sensing biomolecules. For this, the sensing capability of DM-JLTFET has been investigated in terms of variation in dielectric constant, charge density, length, and thickness of the cavity at different bias conditions. Finally, a comparative study between DM-JLTFET and MOSFET biosensor is investigated. The implementation of proposed device and all the simulations have been performed by using ATLAS device simulator.
Autors: Deepika Singh;Sunil Pandey;Kaushal Nigam;Dheeraj Sharma;Dharmendra Singh Yadav;Pravin Kondekar;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jan 2017, volume: 64, issue:1, pages: 271 - 278
Publisher: IEEE
 
» A Class of 1-Bit Multi-Step Look-Ahead $Sigma $ - $Delta $ Modulators
Abstract:
Digital Multi-Step Look-Ahead (MSLA) 1-bit - modulators are introduced. They improve upon the stability and noise shaping characteristics of conventional 1-bit - modulators by minimizing quantization error metrics of the current and future output samples. The mathematical model of the proposed MSLA modulators is analyzed. It is shown that the MSLA modulators are equivalent to a system of conventional - modulators in parallel, but with a common multi-input 1-bit quantizer instead of a typical one. The properties of this multi-input quantizer are studied and the transfer functions of the MSLA modulators are derived. Simulation results are presented demonstrating the advantages of the MSLA modulators over conventional 1-bit - ones in a number of applications. A parametric hardware architecture of the MSLA modulators is presented offering an adjustable trade-off between performance and hardware complexity based on the number of look-ahead steps. Finally, a FPGA implementation of a MSLA modulator is presented along with simulation results.
Autors: Charis Basetas;Thanasis Orfanos;Paul P. Sotiriadis;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2017, volume: 64, issue:1, pages: 24 - 37
Publisher: IEEE
 
» A Class of Non-Linearly Solvable Networks
Abstract:
For each positive composite integer , a network is constructed, which is solvable over an alphabet of size but is not solvable over any smaller alphabet. These networks have no linear solutions over any module alphabets and are not asymptotically linearly solvable over any finite-field alphabets. The networks’ capacities are all shown to equal one, and their linear capacities are all shown to be bounded away from one for all finite-field alphabets. In addition, if is a non-power-of-prime composite number, then such a network is not solvable over any prime-power-size alphabet.
Autors: Joseph Connelly;Kenneth Zeger;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2017, volume: 63, issue:1, pages: 201 - 229
Publisher: IEEE
 
» A Clustering Approach to Learning Sparsely Used Overcomplete Dictionaries
Abstract:
We consider the problem of learning overcomplete dictionaries in the context of sparse coding, where each sample selects a sparse subset of dictionary elements. Our main result is a strategy to approximately recover the unknown dictionary using an efficient algorithm. Our algorithm is a clustering-style procedure, where each cluster is used to estimate a dictionary element. The resulting solution can often be further cleaned up to obtain a high accuracy estimate, and we provide one simple scenario where -regularized regression can be used for such a second stage.
Autors: Alekh Agarwal;Animashree Anandkumar;Praneeth Netrapalli;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2017, volume: 63, issue:1, pages: 575 - 592
Publisher: IEEE
 
» A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array
Abstract:
In the paper, a CMOS pixel has been proposed for imaging arrays with massively parallel image acquisition and simultaneous compensation of dark signal nonuniformity (DSNU) as well as photoresponse nonuniformity (PRNU). In our solution the pixel contains all necessary functional blocks: a photosensor and an analog-to-digital converter (ADC) with built-in correlated double sampling (CDS) integrated together. It is implemented in standard CMOS technology. The size of the pixel with 9-bit resolution is . Measurements of the pixel array confirm functionality of the proposed solution. CDS reduces dark FPN from 12 LSB (3%) to 0.8 LSB (0.2%) and light FPN from 14 LSB (3.7%) to 7 LSB (1.8%). Further reduction of the light FPN (to ~1 LSB) was achieved by compensating PRNU using massively parallel innovative digital multiplication which features good resolution (1/511), does not disturb CDS executed at the same time, and can be implemented within a small pixel area.
Autors: M. Kłosowski;W. Jendernalik;J. Jakusz;G. Blakiewicz;S. Szczepański;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2017, volume: 64, issue:1, pages: 38 - 49
Publisher: IEEE
 
» A Colorimetric CMOS-Based Platform for Rapid Total Serum Cholesterol Quantification
Abstract:
Elevated cholesterol levels are associated with a greater risk of developing cardiovascular disease and other illnesses, making it a prime candidate for detection on a disposable biosensor for rapid point of care diagnostics. One of the methods to quantify cholesterol levels in human blood serum uses an optically mediated enzyme assay and a bench top spectrophotometer. The bulkiness and power hungry nature of the equipment limits its usage to laboratories. Here, we present a new disposable sensing platform that is based on a complementary metal oxide semiconductor process for total cholesterol quantification in pure blood serum. The platform that we implemented comprises readily mass-manufacturable components that exploit the colorimetric changes of cholesterol oxidase and cholesterol esterase reactions. We have shown that our quantification results are comparable to that obtained by a bench top spectrophotometer. Using the implemented device, we have measured cholesterol concentration in human blood serum as low as 29 with a limit of detection at 13 , which is approximately 400 times lower than average physiological range, implying that our device also has the potential to be used for applications that require greater sensitivity.
Autors: Mohammed A. Al-Rawhani;Boon Chong Cheah;Alasdair Iain Macdonald;Christopher Martin;Chunxiao Hu;James Beeley;Luiz Carlos Gouveia;James P. Grant;Gordon Campbell;Michael P. Barrett;David R. S. Cumming;
Appeared in: IEEE Sensors Journal
Publication date: Jan 2017, volume: 17, issue:2, pages: 240 - 247
Publisher: IEEE
 
» A Compact 60W X-Band GaN HEMT Power Amplifier MMIC
Abstract:
The design and performance of a compact X-band power amplifier MMIC utilizing Nanjing Electronic Devices Institute’s (NEDI’s) gallium nitride (GaN) high electron mobility transistor (HEMT) technology is presented. The MMIC operates in pulse conditions with typical pulse width of sec and 10% duty cycle. An output power of 47.5 dBm to 48.7 dBm with over 20 dB power gain and a power added efficiency (PAE) of 40% to 45% over the band of 8-12 GHz under a drain voltage of 28 V have been achieved. The chip size is mm2 and the amplifier delivers an output power density up to 5.57 W/mm2 over the chip area and up to 6.43 W/mm over the active periphery of the power stage. The thermal resistance is 1.7 °C/W measured in CW mode.
Autors: Hong-Qi Tao;Wei Hong;Bin Zhang;Xu-Ming Yu;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2017, volume: 27, issue:1, pages: 73 - 75
Publisher: IEEE
 
» A Compact Dual-Circularly Polarized Cavity-Backed Ring-Slot Antenna
Abstract:
A low profile dual-circularly polarized printed ring-slot antenna with a small footprint, which radiates above an open cavity loaded with an artificial magnetic conducting reflector, is presented. The feed network consists of two T-shaped capacitive feed structures connected to a miniaturized hybrid branch-line coupler. Experimental results for a final antenna design (with a size of ) show a 4% isolation bandwidth between the two ports of the dual-circularly polarized antenna and a maximum gain of approximately 6.8 dBic. Good front-to-back ratios and low cross-polarization were achieved. These very compact and low profile antennas are suitable for 2.4 GHz wireless local area network (WLAN) communication systems.
Autors: Riaan Ferreira;Johan Joubert;Johann W. Odendaal;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2017, volume: 65, issue:1, pages: 364 - 368
Publisher: IEEE
 
» A Comparative Study of the Very Early Age Cement Hydration Monitoring Using Compressive and Shear Mode Smart Aggregates
Abstract:
The load-bearing capacity of concrete is highly influenced by the initial cement hydration process, especially in its very early age (0–48 h). Due to the rapid and intense chemical reactions between the cement and the water in the very early hydration process, it is still a challenge to monitor the cement hydration process in real time. In this paper, we investigated a stress wave-based active sensing method to monitor the cement hydration process using piezoceramic-based transducers, called smart aggregates. Using different types of the embedded piezoceramic patches, including and modes, smart aggregates can function as both the compressive and shear wave transmitters and receivers. In each mode of the smart aggregate, the active sensing approach that uses a pair of smart aggregates, one as a wave transmitter and the other one as a wave receiver, was employed. A comparative study was conducted to investigate the performance of monitoring the very early age cement hydration process by using compressive wave (P-wave) and shear wave (S-wave). A frequency domain analysis of the received signal was performed during the very early age cement hydration process. Experimental results reveal the differences of the received signal strength, valid monitoring period, and the effective frequency range by using both P-wave and S-wave.
Autors: Qingzhao Kong;Gangbing Song;
Appeared in: IEEE Sensors Journal
Publication date: Jan 2017, volume: 17, issue:2, pages: 256 - 260
Publisher: IEEE
 
» A Computational Model of the Electric Field Distribution due to Regional Personalized or Nonpersonalized Electrodes to Select Transcranial Electric Stimulation Target
Abstract:
Objective: A procedure to personalize the electrode to stimulate specific cortical regions by transcranial electric stimulations has been recently proposed. This study aims to assess the distribution of the electric field (E) induced by tES via the personalized (RePE) and the nonpersonalized (ReNPE) electrode. Methods: We used two anatomical models on which we shaped and placed the RePE, based on brain anatomy, and the ReNPE to target the bilateral primary motor (M1) or somatosensory cortex (S1) with the reference on the occipital area in both cases. The effect of shifts of the ReNPE position has been also evaluated. Results: The RePE induced higher E peak and median values than the ReNPE along the bilateral primary motor sensory cortices, up to their lateral regions, on a great percentage of volume of these cortices along all their extent. The shift of the ReNPE electrode toward the inion still induced higher E peak and median values than the ReNPE not shifted, but less than the RePE, mainly in the central region and, in a lower percentage of volume, in the lateral regions of these cortices. Conclusion: The E distributions induced for both targets (M1 and S1) by the RePE are different from the ones due to the ReNPE, along the whole extent of the bilateral primary sensorimotor cortices. The shift in the ReNPE positioning can modify the E distributions mainly in the more central region of these cortices. Significance: These results strengthen the suitability of personalized electrodes in targeting extended cortical regions.
Autors: Marta Parazzini;Serena Fiocchi;Andrea Cancelli;Carlo Cottone;Ilaria Liorni;Paolo Ravazzani;Franca Tecchio;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Jan 2017, volume: 64, issue:1, pages: 184 - 195
Publisher: IEEE
 
» A Construction of Linear Codes Over ${mathbb {F}}_{2^t}$ From Boolean Functions
Abstract:
In this paper, we present a construction of linear codes over from Boolean functions, which is a generalization of Ding’s method. Based on this construction, we give two classes of linear codes and over from a Boolean function , where and is some subfield of . The complete weight enumerator of can be easily determined from the Walsh spectrum of , while the weight distribution of the code can also be easily settled. Particularly, the number of nonzero weights of and is the same as the number of distinct Walsh values of . As applications of this construction, we show several series of linear codes over with two or three weights by using bent, semibent, monomial and quadratic Boolean function .
Autors: Can Xiang;Keqin Feng;Chunming Tang;
Appeared in: IEEE Transactions on Information Theory
Publication date: Jan 2017, volume: 63, issue:1, pages: 169 - 176
Publisher: IEEE
 
» A Coordinate Control Strategy for Circulating Current Suppression in Multiparalleled Three-Phase Inverters
Abstract:
This paper addresses the zero-sequence circulating current control in the multiparalleled three-phase voltage-source inverters. The model of the zero-sequence circulating current in the N-paralleled inverters is derived. It is shown that the circulating current is not only susceptible to the mismatches of circuit parameters, but it is also influenced by the interactions of circulating current controllers used by other paralleled inverters. To eliminate these adverse effects on the circulating current control loop, a coordinate control strategy for the N-paralleled inverter is proposed based on the zero-vector feedforward method with the space-vector pulse width modulation. Moreover, a virtual inverter method is introduced to facilitate the implementation of the proposed controller, which decouples the interactions of circulating current controllers in the paralleled inverters. Finally, experimental results obtained from three-paralleled, grid-connected inverters validate the effectiveness of theoretical analysis and proposed approach. An effective mitigation of the circulating current is demonstrated for the paralleled inverters under the unequal operating conditions.
Autors: Xueguang Zhang;Tianyi Wang;Xiongfei Wang;Gaolin Wang;Zhe Chen;Dianguo Xu;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jan 2017, volume: 64, issue:1, pages: 838 - 847
Publisher: IEEE
 
» A Data-Driven Approach to Improve Wind Dispatchability
Abstract:
Wind power has been treated as a non-dispatchable resource until recent development of active wind dispatch strategies in several electricity markets. In markets such as ISO New England, a dispatch range for each wind farm is determined based on security analysis. Wind power will be fully absorbed unless it is out of the ranges. This approach, though aiming at improving wind utilization with system security considered, relies solely on wind power forecasting, which could be inaccurate by nature, and might result in unnecessary wind curtailment. In our work, we recognize the discrepancy between wind power forecast and the actual wind power dispatched and develop a data-driven approach to better capture the uncertainties in wind power dispatch. The computational experiments demonstrate that the dispatch ranges determined by our data-driven approach can dispatch more wind without endangering the system security and that solution is also efficient.
Autors: Feng Qiu;Zhigang Li;Jianhui Wang;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jan 2017, volume: 32, issue:1, pages: 421 - 429
Publisher: IEEE
 
» A Data-Driven Learning Approach for Nonlinear Process Monitoring Based on Available Sensing Measurements
Abstract:
A data-driven learning approach is proposed to monitor nonlinear processes based only on the available sensing measurements in this paper. To achieve this aim, locally weighted projection regression (LWPR) is used to establish the model of the underlying nonlinear process with local linear models, in which the modified principal component analysis (MPCA) could be further applied for process monitoring. Moreover, the normalized weighted mean of all the proposed test statistics is employed to detect the possible abnormalities. A detailed discussion is made on principal-component-analysis-based approaches as well as on the reason of selecting MPCA under LWPR framework. The Tennessee Eastman process is first employed to demonstrate the superiority of MPCA. A numerical simulation example and an industrial benchmark of an autosuspension system are finally utilized to validate the effectiveness of the proposed scheme.
Autors: Shen Yin;Chengming Yang;Jingxin Zhang;Yuchen Jiang;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jan 2017, volume: 64, issue:1, pages: 643 - 653
Publisher: IEEE
 
» A Direct Method for the Estimation of Sediment Sound Speed With a Horizontal Array in Shallow Water
Abstract:
In this paper, a fast approach for estimating sediment sound speed in a shallow-water environment is developed. Under certain assumptions, this algorithm recovers the seabed sound-speed profile using pressure field measurements at low frequencies. The geometry of the problem involves measuring the pressure at horizontally placed hydrophones in the water column. The Deift–Trubowitz integral equation is then solved. This work introduces two methods for this task. The first is a modified Born approximation that builds upon a standard first-order approximation; the second is based on interpolating the integrand. It is shown with synthetic data that these methods work well with successful sound-speed estimation and identification of sharp discontinuities in sound speed. Although the methods are stable and effective with noise-free data, problems arise when noise contaminates the acoustic field. Regularization approaches, reducing the disruptive effect of singular points and smoothing a measured reflection coefficient, are developed to remedy this problem, leading to improved results in noisy environments. In addition to providing sound-speed estimates, the method also computes sediment thickness. This feature is of particular interest, since it makes the method suitable as a preprocessing step providing useful information to other inversion methods. Sensitivity analyses demonstrate that some assumptions required for the approach implementation are not restrictive.
Autors: Tao Lin;Zoi-Heleni Michalopoulou;
Appeared in: IEEE Journal of Oceanic Engineering
Publication date: Jan 2017, volume: 42, issue:1, pages: 208 - 218
Publisher: IEEE
 
» A Discriminatively Trained Fully Connected Conditional Random Field Model for Blood Vessel Segmentation in Fundus Images
Abstract:
Goal: In this work, we present an extensive description and evaluation of our method for blood vessel segmentation in fundus images based on a discriminatively trained fully connected conditional random field model. Methods: Standard segmentation priors such as a Potts model or total variation usually fail when dealing with thin and elongated structures. We overcome this difficulty by using a conditional random field model with more expressive potentials, taking advantage of recent results enabling inference of fully connected models almost in real time. Parameters of the method are learned automatically using a structured output support vector machine, a supervised technique widely used for structured prediction in a number of machine learning applications. Results: Our method, trained with state of the art features, is evaluated both quantitatively and qualitatively on four publicly available datasets: DRIVE, STARE, CHASEDB1, and HRF. Additionally, a quantitative comparison with respect to other strategies is included. Conclusion: The experimental results show that this approach outperforms other techniques when evaluated in terms of sensitivity, F1-score, G-mean, and Matthews correlation coefficient. Additionally, it was observed that the fully connected model is able to better distinguish the desired structures than the local neighborhood-based approach. Significance: Results suggest that this method is suitable for the task of segmenting elongated structures, a feature that can be exploited to contribute with other medical and biological applications.
Autors: José Ignacio Orlando;Elena Prokofyeva;Matthew B. Blaschko;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Jan 2017, volume: 64, issue:1, pages: 16 - 27
Publisher: IEEE
 
» A Distributed Networked Approach for Fault Detection of Large-Scale Systems
Abstract:
Networked systems present some key new challenges in the development of fault-diagnosis architectures. This paper proposes a novel distributed networked fault detection methodology for large-scale interconnected systems. The proposed formulation incorporates a synchronization methodology with a filtering approach in order to reduce the effect of measurement noise and time delays on the fault detection performance. The proposed approach allows the monitoring of multirate systems, where asynchronous and delayed measurements are available. This is achieved through the development of a virtual sensor scheme with a model-based resynchronization algorithm and a delay compensation strategy for distributed fault-diagnostic units. The monitoring architecture exploits an adaptive approximator with learning capabilities for handling uncertainties in the interconnection dynamics. A consensus-based estimator with time-varying weights is introduced, for improving fault detectability in the case of variables shared among more than one subsystem. Furthermore, time-varying threshold functions are designed to prevent false-positive alarms. Analytical fault detectability sufficient conditions are derived, and extensive simulation results are presented to illustrate the effectiveness of the distributed fault detection technique.
Autors: Francesca Boem;Riccardo M. G. Ferrari;Christodoulos Keliris;Thomas Parisini;Marios M. Polycarpou;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Jan 2017, volume: 62, issue:1, pages: 18 - 33
Publisher: IEEE
 
» A Distributionally Robust Linear Receiver Design for Multi-Access Space-Time Block Coded MIMO Systems
Abstract:
A receiver design problem for multi-access space-time block coded multiple-input multiple-output systems is considered. To hedge the mismatch between the true and the estimated channel state information (CSI), several robust receivers have been developed in the past decades. Among these receivers, the Gaussian robust receiver has been shown to be superior in performance. This receiver is designed based on the assumption that the CSI mismatch has Gaussian distribution. However, in real-world applications, the assumption of Guassianity might not hold. Motivated by this fact, a more general distributionally robust receiver is proposed in this paper, where only the mean and the variance of the CSI mismatch distribution are required in the receiver design. A tractable semi-definite programming (SDP) reformulation of the robust receiver design is developed. To suppress the self-interferences, a more advanced distributionally robust receiver is proposed. A tight convex approximation is given and the corresponding tractable SDP reformulation is developed. Moreover, for the sake of easy implementation, we present a simplified distributionally robust receiver. Simulations results are provided to show the effectiveness of our design by comparing with some existing well-known receivers.
Autors: Bin Li;Yue Rong;Jie Sun;Kok Lay Teo;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Jan 2017, volume: 16, issue:1, pages: 464 - 474
Publisher: IEEE
 
» A Distributionally Robust Optimization Model for Unit Commitment Considering Uncertain Wind Power Generation
Abstract:
This paper proposes a distributionally robust optimization model for solving unit commitment (UC) problems considering volatile wind power generation. The uncertainty of wind power is captured by an ambiguity set that defines a family of wind power distributions, and the expected total cost under the worst-case distribution is minimized. Compared with stochastic programming, this method may have less dependence on the data of exact probability distributions. It should also outperform the conventional robust optimization methods because some distribution information can be incorporated into the ambiguity sets to generate less conservative results. In this paper, the UC model is formulated based on the typical two-stage framework, where the UC decisions are determined in a here-and-now manner, and the economic dispatch decisions are assumed to be wait-and-see, made after the observation of wind power outcomes. For computational tractability, the wait-and-see decisions are addressed by linear decision rule approximation, assuming that the economic dispatch decisions affinely depend on uncertain parameters as well as auxiliary random variables introduced to describe distributional characteristics of wind power generation. It is shown in case studies that this decision rule model tends to provide a tight approximation to the original two-stage problem, and the performance of UC solutions may be greatly improved by incorporating information on wind power distributions into the robust model.
Autors: Peng Xiong;Panida Jirutitijaroen;Chanan Singh;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jan 2017, volume: 32, issue:1, pages: 39 - 49
Publisher: IEEE
 
» A Domain Specific Approach to High Performance Heterogeneous Computing
Abstract:
Users of heterogeneous computing systems face two problems: first, in understanding the trade-off relationships between the observable characteristics of their applications, such as latency and quality of the result, and second, how to exploit knowledge of these characteristics to allocate work to distributed computing platforms efficiently. A domain specific approach addresses both of these problems. By considering a subset of operations or functions, models of the observable characteristics or domain metrics may be formulated in advance, and populated at run-time for task instances. These metric models can then be used to express the allocation of work as a constrained integer program. These claims are illustrated using the domain of derivatives pricing in computational finance, with the domain metrics of workload latency and pricing accuracy. For a large, varied workload of 128 Black-Scholes and Heston model-based option pricing tasks, running upon a diverse array of 16 Multicore CPUs, GPUs and FPGAs platforms, predictions made by models of both the makespan and accuracy are generally within 10 percent of the run-time performance. When these models are used as inputs to machine learning and MILP-based workload allocation approaches, a latency improvement of up to 24 and 270 times over the heuristic approach is seen.
Autors: Gordon Inggs;David B. Thomas;Wayne Luk;
Appeared in: IEEE Transactions on Parallel and Distributed Systems
Publication date: Jan 2017, volume: 28, issue:1, pages: 2 - 15
Publisher: IEEE
 
» A Dopingless FET With Metal–Insulator–Semiconductor Contacts
Abstract:
By adopting the charge-plasma concept, dopingless FETs with metal-semiconductor and metal–insulator–semiconductor (MIS) contacts in parallel at the source/drain (SD) have been studied in this letter. Currents are found to flow mainly through the MIS contacts for a given SD metal workfunction when the insulator thickness is thin enough. In order to avoid the possible penalty caused by Fermi level pinning, the dopingless FET with only SD MIS contacts has been proposed as well. The impacts of insulator material parameters, such as bandgap, electron affinity, dielectric constant, and physical thickness, on the electrical characteristics of the dopingless FET have been investigated systematically. Based on numerical simulations, this letter provides a general guideline with physical insights for designing dopingless FETs with high-permittivity insulator at the SD MIS contacts.
Autors: Kuo-Hsing Kao;Liang-Yu Chen;
Appeared in: IEEE Electron Device Letters
Publication date: Jan 2017, volume: 38, issue:1, pages: 5 - 8
Publisher: IEEE
 
» A Dual-Band Feed Network for Series-Fed Antenna Arrays Using Extended Composite Right/Left-Handed Transmission Lines
Abstract:
In this paper, extended composite right/left-handed (E-CRLH) structures are studied to design multiband microwave devices. As an example, a three-way series power divider (SPD) is designed. The overall effects of the E-CRLH structures, as the feeding networks of the antenna arrays, on the antenna arrays main-beam variations are investigated. We also design and implement two antenna arrays with elements and the same interelement distances each fed by a distinct three-way SPD. The radiation patterns of the antennas are examined. Simulation and measurement results demonstrate that the desired main-beam squinting of the antenna array could be obtained by engineering the parameters of the feeding network instead of adjusting the interelement distances.
Autors: Mohammad Bemani;Saeid Nikmehr;Mahdi Fozi;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2017, volume: 65, issue:1, pages: 178 - 189
Publisher: IEEE
 
» A Dual-Buck–Boost AC/DC Converter for DC Nanogrid With Three Terminal Outputs
Abstract:
Due to the widely used dc characterized loads and more distributed power generation sources, the dc nanogrid becomes more and more popular, and it is seen as an alternative to the ac grid. For safety considerations, the dc nanogrid should provide reliable grounding for the residential loads such as the low-voltage ac power system. There are three typical grounding configurations for a dc nanogrid: the united grounding, the unidirectional grounding, and the virtual isolated grounding. Each grounding configuration has its own specifications to ac/dc converters. In this paper, a dual-buck–boost ac/dc converter for use in the united-grounding-configuration-based dc nanogrid with three terminal outputs is proposed. The working principle of this converter is presented in detail through analyzing the equivalent circuits. Experiments are carried out to verify the theoretical analysis.
Autors: Weimin Wu;Houqing Wang;Yuan Liu;Min Huang;Frede Blaabjerg;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jan 2017, volume: 64, issue:1, pages: 295 - 299
Publisher: IEEE
 
» A Dynamic Model and Control Method for a Two-Axis Inertially Stabilized Platform
Abstract:
To realize high-performance control for a two-axis inertially stabilized platform (ISP), a nonlinear dynamic model based on the geographic coordinate and a compound control method based on the back-stepping sliding mode control and adaptive radial basis function neural network (RBFNN) are proposed. Compared with the traditional dynamic model based on the inertial coordinate, the nonlinear dynamic model based on the geographic coordinate constructs the direct relationship among the control inputs and criteria of the ISP. Moreover, the back-stepping sliding mode control method is proposed to handle the system nonlinearity, parameter variations, and disturbances. Furthermore, the adaptive RBFNN is constructed and optimized to estimate the upper bound of the residual error on line to reduce the chatting phenomenon. The asymptotic stability of the proposed control method has been proven by the Lyapunov stability theory. The effectiveness of the proposed method is validated by a series of simulations and flight tests.
Autors: Fei Dong;Xusheng Lei;Wusheng Chou;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jan 2017, volume: 64, issue:1, pages: 432 - 439
Publisher: IEEE
 
» A Dynamic-Bayesian-Network-Based Fault Diagnosis Methodology Considering Transient and Intermittent Faults
Abstract:
Transient fault (TF) and intermittent fault (IF) of complex electronic systems are difficult to diagnose. As the performance of electronic products degrades over time, the results of fault diagnosis could be different at different times for the given identical fault symptoms. A dynamic Bayesian network (DBN)-based fault diagnosis methodology in the presence of TF and IF for electronic systems is proposed. DBNs are used to model the dynamic degradation process of electronic products, and Markov chains are used to model the transition relationships of four states, i.e., no fault, TF, IF, and permanent fault. Our fault diagnosis methodology can identify the faulty components and distinguish the fault types. Four fault diagnosis cases of the Genius modular redundancy control system are investigated to demonstrate the application of this methodology.
Autors: Baoping Cai;Yu Liu;Min Xie;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Jan 2017, volume: 14, issue:1, pages: 276 - 285
Publisher: IEEE
 
» A Dynamics Perspective of Pursuit-Evasion: Capturing and Escaping When the Pursuer Runs Faster Than the Agile Evader
Abstract:
Pursuit-evasion is fascinating in both nature and artificial world. Typically, a pursuer runs faster than its targeted evader while with less agile maneuverability. Naturally, there is a wonder that how an evader escapes from a faster pursuer or how faster a pursuer is able to capture an agile evader? This is not yet answered from the dynamics (i.e., Lagrangian or Newtonian) perspective. In this paper, we first provide a concise dynamics formulation from a bio-inspired perspective, in which the evader's escape strategy consists of two simplest possible yet efficient ingredients integrated as an organic whole, i.e., the suddenly turning-left or turning-right propelling maneuver, together with the early alert condition for starting and maintaining this maneuver. Then, we characterize the dynamic properties of the system at two different levels: 1) the maneuvers and non-trivial escape of the evader, at the level of individual runs of the system; and further 2) the non-trivial escape zones, the sharp phase-transitions and the phase-transition lines of the gaming outcome, at the level of the running results with respect to different ranges of the system parameters. The results are consistent with natural observations and may disclose some clues of natural laws, as well as imply applications in competition of autonomous mobile robots.
Autors: Wei Li;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Jan 2017, volume: 62, issue:1, pages: 451 - 457
Publisher: IEEE
 
» A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy
Abstract:
With fabrication technology reaching nanolevels, systems are becoming more prone to manufacturing defects with higher susceptibility to soft errors. This paper is focused on designing combinational circuits for soft error tolerance with minimal area overhead. The idea is based on analyzing random pattern testability of faults in a circuit and protecting sensitive transistors, whose soft error detection probability is relatively high, until desired circuit reliability is achieved or a given area overhead constraint is met. Transistors are protected based on duplicating and sizing a subset of transistors necessary for providing the protection. In addition to that, a novel gate-level reliability evaluation technique is proposed that provides similar results to reliability evaluation at the transistor level (using SPICE) with the orders of magnitude reduction in CPU time. LGSynth’91 benchmark circuits are used to evaluate the proposed algorithm. Simulation results show that the proposed algorithm achieves better reliability than other transistor sizing-based techniques and the triple modular redundancy technique with significantly lower area overhead for 130-nm process technology at a ground level.
Autors: Ahmad T. Sheikh;Aiman H. El-Maleh;Muhammad E. S. Elrabaa;Sadiq M. Sait;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jan 2017, volume: 25, issue:1, pages: 224 - 237
Publisher: IEEE
 
» A Ferrite LTCC-Based Monolithic SIW Phased Antenna Array
Abstract:
In this paper, we present a novel configuration for realizing monolithic substrate integrated waveguide (SIW)-based phased antenna arrays using Ferrite low-temperature cofired ceramic (LTCC) technology. Unlike the current common schemes for realizing SIW phased arrays that rely on surface-mount component (p-i-n diodes, etc.) for controlling the phase of the individual antenna elements, here the phase is tuned by biasing of the ferrite filling of the SIW. This approach eliminates the need for mounting of any additional RF components and enables seamless monolithic integration of phase shifters and antennas in SIW technology. As a proof of concept, a two-element slotted SIW-based phased array is designed, fabricated, and measured. The prototype exhibits a gain of 4.9 dBi at 13.2 GHz and a maximum -plane beam-scanning of ±28° using external windings for biasing the phase shifters. Moreover, the array can achieve a maximum beam-scanning of ±19° when biased with small windings that are embedded in the package. This demonstration marks the first time a fully monolithic SIW-based phased array is realized in Ferrite LTCC technology and paves the way for future larger size implementations.
Autors: Ahmed Nafe;Farhan A. Ghaffar;Muhammad Fahad Farooqui;Atif Shamim;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2017, volume: 65, issue:1, pages: 196 - 205
Publisher: IEEE
 
» A Forward-Wave Oscillator Based on Folded-Waveguide Slow-Wave Structure
Abstract:
A new concept of oscillator based on a folded waveguide slow-wave structure (FWG SWS) is studied. The resonant cavity of the oscillator is formed by a section of FWG SWS, a length-adjustable waveguide, and a waveguide loaded by multilayer dielectric. The beam is synchronized with the forward wave on the SWS. If an FWG traveling-wave amplifier (TWA) is driven by this oscillator, there is a possibility that the amplifier and the oscillator share the same design and the same art of manufacturing and power supplier. A forward-wave oscillator based on a design of a TWA in 2-mm band is calculated by both a 1-D nonlinear code and particle-in-cell (PIC) simulation. From both the code and the simulation results, when the oscillator is 30-pitch long, the operation voltage 22000 V and the start current is 3 mA at 138 GHz. When the oscillator is 22-pitch long, operation current 15 mA, and operation voltage 22400 V, simulation result shows that the output power is 58.32 W, and the efficiency is 17.26% at 133.2GHz. When both the voltage and length of the length-adjustable waveguide are tuned, the oscillator can operate within all the first dispersion band of the SWS. If only voltage is tuned, the oscillator can oscillate at several discrete frequencies.
Autors: Hairong Yin;Jin Xu;Lingna Yue;Yubin Gong;Yanyu Wei;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Jan 2017, volume: 45, issue:1, pages: 24 - 29
Publisher: IEEE
 
» A Fresh Look for IEEE Industry Applications Magazine [From the Editor's Desk]
Abstract:
Presents the introductory editorial for this issue of the publication.
Autors: Lanny Floyd;
Appeared in: IEEE Industry Applications Magazine
Publication date: Jan 2017, volume: 23, issue:1, pages: 3 - 3
Publisher: IEEE
 
» A Full-Bridge Submodule-Based Modular Unipolar/Bipolar High-Voltage Pulse Generator With Sequential Charging of Capacitors
Abstract:
Repetitive high pulsed electric field (PEF) is an effective method to kill microorganisms and bacteria in water treatment applications. The PEF can be generated by applying high-power electromagnetic pulse across the sample to be treated. There are two main types of high-voltage pulse generators, namely, unipolar and bipolar. In this paper, a full-bridge submodule-based modular high-voltage pulse generator, having the ability to generate unipolar and bipolar high-voltage pulses with different shapes from a relatively low-voltage input dc supply, is proposed. In the proposed configuration, relatively low-voltage insulated gate bipolar transistors (IGBTs) are required to generate the high-voltage bipolar pulses. A thyristor rated at the level of the pulsed output voltage is required in the proposed configuration to bypass the load during the charging process of capacitors. In the proposed approach, a thyristor is used instead of the self-commutated high-voltage switch (e.g., series-connected IGBTs), as thyristors are available with high-voltage ratings and possess inherent reverse voltage blocking capability. A detailed illustration of the proposed configuration and its operational concept are introduced in this paper. Simulation and experimental results are presented to validate the proposed approach.
Autors: Ahmed A. Elserougi;Ibrahim Abdelsalam;Ahmed M. Massoud;Shehab Ahmed;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Jan 2017, volume: 45, issue:1, pages: 91 - 99
Publisher: IEEE
 
» A Galvanically Isolated DC–DC Converter Based on Current-Reuse Hybrid-Coupled Oscillators
Abstract:
This brief presents a fully integrated dc–dc converter consisting of only two CMOS chips, which are a power oscillator with an integrated transformer and a full-bridge rectifier. A thick inter-metal oxide layer guarantees a galvanic isolation rating as high as 5 kV. A current-reuse hybrid-coupled oscillator is proposed, which is based on a three-winding tapped isolation transformer and improves both output power and silicon area occupation with respect to previous works. The converter is operated at 5-V power supply and is able to deliver up to 300-mW dc power at 10-V output voltage while exhibiting a power density and a power efficiency of 36 mW/mm2 and 24%, respectively.
Autors: Nunzio Greco;Nunzio Spina;Vincenzo Fiore;Egidio Ragonese;Giuseppe Palmisano;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2017, volume: 64, issue:1, pages: 56 - 60
Publisher: IEEE
 
» A Handheld High-Sensitivity Micro-NMR CMOS Platform With B-Field Stabilization for Multi-Type Biological/Chemical Assays
Abstract:
We report a micro-nuclear magnetic resonance (NMR) system compatible with multi-type biological/chemical lab-on-a-chip assays. Unified in a handheld scale (dimension: cm, weight: 1.4 kg), the system is capable to detect <100 pM of Enterococcus faecalis derived DNA from a sample. The key components are a portable magnet (0.46 T, 1.25 kg) for nucleus magnetization, a system PCB for I/O interface, an FPGA for system control, a current driver for trimming the magnetic (B) field, and a silicon chip fabricated in CMOS. The latter, integrated with a current-mode vertical Hall sensor and a low-noise readout circuit, facilitates closed-loop B-field stabilization (2 mT 0.15 mT), which otherwise fluctuates with temperature or sample displacement. Together with a dynamic-B-field transceiver with a planar coil for micro-NMR assay and thermal control, the system demonstrates: 1) selective biological target pinpointing; 2) protein state analysis; and 3) solvent-polymer dynamics, suitable for healthcare, food and colloidal applications, respectively. Compared to a commercial NMR-assay product (Bruker mq-20), this platform greatly reduces the sample consumption (), hardware volume (), and weight ().
Autors: Ka-Meng Lei;Hadi Heidari;Pui-In Mak;Man-Kay Law;Franco Maloberti;Rui P. Martins;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 284 - 297
Publisher: IEEE
 
» A High Efficiency and Low Distortion 6 W GaN MMIC Doherty Amplifier for 7 GHz Radio Links
Abstract:
This contribution presents a novel design methodology for Gallium Nitride (GaN) Monolithic Microwave Integrated Circuit (MMIC) Doherty Power Amplifiers (DPAs). The proposed solution allows to mitigate the relevant phase distortion (AM/PM) and gain penalty, typically registered in GaN DPAs, without worsening other key features such as back-off efficiency and amplitude distortion (AM/AM). To this purpose, a non-linear driver stage is introduced in both Carrier and Peaking branches, with the aim to provide a chip-level phase distortion compensation mechanism. The idea is to almost zeroing the overall phase distortion by achieving, in the driver stage, an opposite AM/PM behaviour with respect to the one of the final stage. The theoretical formulation is verified presenting the design and experimental characterization of a GaN MMIC DPA for 7 GHz radio links. The chip has been developed in a commercial GaN power process, resulting in a mm2 chip area. The realized DPA shows 38 dBm of saturated output power, 16 dB of gain, and less than 3° of phase distortion, with a power added efficiency higher than 41% in 6 dB of output power back off.
Autors: Rocco Giofré;Paolo Colantonio;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2017, volume: 27, issue:1, pages: 70 - 72
Publisher: IEEE
 
» A High-speed In Situ Measuring Method for Inner Dimension Inspection
Abstract:
Inner dimensional measurement techniques are difficult to improve because of the tight working space and complex inside measuring environment. In this paper, a high-speed, in situ measuring method is proposed for inner dimension by using revolved double laser beams. First, two laser beams with the inclined angle of 180° are used to construct the measuring line. The relative position between two laser beams is then calibrated before measurement. Second, the two laser beams are revolved consecutively to get collections of data samples during the measurement. The data samples contain the information concerning the geometrical features of measured workpiece. Finally, by fitting the measured data, inner dimensions can be extracted from the statistical characteristic of measured workpiece. The proposed approach is validated by using a developed measuring head installed on the spindle of a numerical control machine. Inner diameter and planar spacing measurements are taken as examples to showcase the efficacy and efficiency of the method proposed.
Autors: Xingqiang Li;Zhong Wang;Luhua Fu;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Jan 2017, volume: 66, issue:1, pages: 104 - 112
Publisher: IEEE
 
» A Highly Efficient Power Amplifier at 5.8 GHz Using Independent Harmonic Control
Abstract:
An optimal design of a highly efficient power amplifier (PA) is described using independent fundamental and second harmonic impedance control technique. In fabrication of a power amplifier, a tuning method is indispensable because the simulation models of the device and capacitor have some difference with the actual value. To achieve a high drain efficiency, the fundamental and harmonic impedances need to be accurately optimized. However, as the operating frequency is increased, the matching circuit becomes sensitive and it is difficult to realize the accurate optimum matching. To solve the problem, the matching circuit of the PA adopts the independent harmonic control circuit using the characteristic of a quarter-wavelength microstrip line. A power amplifier with the concept is designed and implemented using a Cree GaN HEMT CGH40035 at 5.8 GHz. The peak output power, drain efficiency and gain are 47.2 dBm, 70.2%, and 10.2 dB.
Autors: Yunsik Park;Donggyu Minn;Seokhyeon Kim;Junghwan Moon;Bumman Kim;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2017, volume: 27, issue:1, pages: 76 - 78
Publisher: IEEE
 
» A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency
Abstract:
This brief presents a hybrid design of a configurable logic block (CLB) composed of look-up tables (LUTs) and universal logic gates (ULGs). A ULG is designed to realize holistic efficiency compared with the corresponding LUT. Previous designs with ULGs are either based on pure ULG or LUT-ULG complementary architecture, which incur a longer delay or double the area compared to the LUT-based design. In contrast, we propose a hybrid CLB that contains a mixture of LUTs and ULGs to address the generality problem as well as to achieve the holistic benefits including the area, performance, and power. To exploit the advantage of ULGs thoroughly while not causing negative side effects, the ratio of LUTs and ULGs in one CLB is explored by experiments. Experimental results show that, compared to pure LUT design, our proposed architecture design can save up to 17.1% logic power as well as 11.2% delay improvement and 10.4% logic area reduction. Compared to the state-of-the-art design, our proposed design has 3.8% improvement in power delay product and 17.1% improvement in area cost.
Autors: Tao Luo;Hao Liang;Wei Zhang;Bingsheng He;Douglas Maskell;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jan 2017, volume: 64, issue:1, pages: 71 - 75
Publisher: IEEE
 
» A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations
Abstract:
Dynamic flip-flop conversion (DFFC) is a time borrowing method for improving the performance of digital circuits. Existing types of DFFC [11], [12] suffer from successive critical and critical feedback paths that are frequently seen in digital circuits. Moreover, they are unable to increase the performance of the designs with short sequential depth. In this paper, we introduce a hybrid technique which utilizes DFFC together with a dynamic clock stretching mechanism. Our technique is able to mitigate the problems of successive critical and critical feedback path structures even in the presence of process variations. The results show that our hybrid technique is able to increase the performance of some ITC'99 and ISCAS'89 benchmarks by 24.4% on average while DFFC Type C increases the performance only by 8.4% on average. Furthermore, we have shown that our hybrid technique is able to tolerate process variations, 18% power supply variation, and 100 °C temperature variations, 27.3%, 16.4%, and 13.3% better than the state-of-the-art methods on average, respectively.
Autors: Mehrnaz Ahmadi;Bijan Alizadeh;Behjat Forouzandeh;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jan 2017, volume: 64, issue:1, pages: 100 - 110
Publisher: IEEE
 
» A Laplacian-Based Approach for Finding Near Globally Optimal Solutions to OPF Problems
Abstract:
A semidefinite programming (SDP) relaxation globally solves many optimal power flow (OPF) problems. For other OPF problems where the SDP relaxation only provides a lower bound on the objective value rather than the globally optimal decision variables, recent literature has proposed a penalization approach to find feasible points that are often nearly globally optimal. A disadvantage of this penalization approach is the need to specify penalty parameters. This paper presents an alternative approach that algorithmically determines a penalization appropriate for many OPF problems. The proposed approach constrains the generation cost to be close to the lower bound from the SDP relaxation. The objective function is specified using iteratively determined weights for a Laplacian matrix. This approach yields feasible points to the OPF problem that are guaranteed to have objective values near the global optimum due to the constraint on generation cost. The proposed approach is demonstrated on both small OPF problems and a variety of large test cases representing portions of European power systems.
Autors: Daniel K. Molzahn;Cédric Josz;Ian A. Hiskens;Patrick Panciatici;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jan 2017, volume: 32, issue:1, pages: 305 - 315
Publisher: IEEE
 
» A Liquid Level Sensor Based on a Race-Track Helical Plastic Optical Fiber
Abstract:
A multi-point liquid level sensor was proposed in this letter, which is based on a plastic optical fiber with a race-track helical structure. The principle of liquid sensing is based on higher modes leak out and regenerate repeatedly in the bend and straight sections, respectively. Therefore, propagation loss was introduced in the bend sections of the fiber submerged under the liquid. The liquid level shift can be detected by observing alterations in the propagation loss changes. The sensor features compactness and independence from the refractive index of the liquid. The level measurement resolution is flexible and expected to reach the same order of magnitude as the diameter.
Autors: Ning Jing;Chuanxin Teng;Jie Zheng;Guanjun Wang;Yuanyuan Chen;Zhibin Wang;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jan 2017, volume: 29, issue:1, pages: 158 - 160
Publisher: IEEE
 
» A Look at What's New: Reviewing the Second Edition of API 547
Abstract:
This article will review many of the changes in the second edition of the American Petroleum Institute (API) 547 specification, General-Purpose Form-Wound Squirrel Cage Induction Motors-185 kW (250 hp) Through 2,240 kW (3,000 hp) [1]. The first edition of this standard [2] was released in 2005 to provide a set of requirements for general-purpose motors based on the key criteria of API Standard 541, fourth edition, applicable to 375-kW (500-hp) and larger motors [3]. The scope of API 547 is limited to a range of motor sizes and configurations that fit a majority of general-purpose severe duty applications that are common in petrochemical applications. API 541 has recently been updated to its fifth edition [4], and the second edition of API 547 has followed suit with revisions to the scope and criteria, various clarifications, data sheet changes, and an expanded data sheet guide.
Autors: Tim Rahill;Barry Wood;Mark Chisholm;Joel Ocmand;
Appeared in: IEEE Industry Applications Magazine
Publication date: Jan 2017, volume: 23, issue:1, pages: 70 - 80
Publisher: IEEE
 
» A Low Complexity Sensing Algorithm for Wideband Sparse Spectra
Abstract:
Compressed sensing-based wideband spectrum sensing approaches have gotten much attention owning to their advantage of relieving the pressure on high signal acquisition costs. Most of these approaches need to recover the signal or power spectrum, which require high computational complexity. This letter proposes a novel wideband sensing algorithm with no recovery (NoR) of spectral, where the location of occupied subband is identified via a maximum inner product method, thus reducing computational complexity significantly. Compared with the existing spectral recovery algorithms, NoR algorithm maintains an excellent sensing performance with several orders of magnitude lower computational complexity.
Autors: Shiyu Ren;Zhimin Zeng;Caili Guo;Xuekang Sun;
Appeared in: IEEE Communications Letters
Publication date: Jan 2017, volume: 21, issue:1, pages: 92 - 95
Publisher: IEEE
 
» A Low Complexity Sub-Optimal Approach to Dynamic Spectrum Allocation for White Space Devices With Heterogeneous Bandwidth Requirements
Abstract:
This letter considers the decision-making method of dynamic spectrum allocation by a spectrum manager in a centralized white space cognitive radio communication network with various available frequency fragments and heterogeneous bandwidth requests. To achieve low complexity practical solution to this problem, we propose a hybrid sub-optimal dynamic programming-based algorithm. The performance of the proposed solution is compared with the optimal one and other alternative solutions. The numeric results show that the proposed solution achieves spectrum efficiency close to the optimal one and the complexity is considerably reduced to as compared with that of the optimal solution .
Autors: Zhong Huang;Yugang Ma;Yueyue Li;Guangjun Wen;
Appeared in: IEEE Communications Letters
Publication date: Jan 2017, volume: 21, issue:1, pages: 188 - 191
Publisher: IEEE
 
» A Low Power Inductorless Wideband LNA With Gm Enhancement and Noise Cancellation
Abstract:
This letter presents the design of an inductorless low power differential low-noise amplifier (LNA) in 65 nm Low Power (LP) CMOS technology for multi-standard radio applications between 100MHz and 4.3 GHz. Based on the combination of common-gate (CG) and common-source (CS) with shunt feedback (SFB) topologies, the LNA utilizes a cross-coupled push-pull structure to realize boosting and partial noise cancelling under low power consumption. A cascode transistor is used to alleviate the Miller effect and also constructs a current steering structure to increase the bandwidth and gain. These techniques result in a good overall performance tradeoff after sizing and biasing optimization under the power constraint. A prototype has been implemented and it exhibits a voltage gain of 21.2 dB, an NF of 2.8-4 dB over the frequency range of 100 MHz to 4.3 GHz. It consumes 2 mW from 1.2 V supply and occupies an active area of 0.05 mm2.
Autors: Zhijian Pan;Chuan Qin;Zuochang Ye;Yan Wang;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2017, volume: 27, issue:1, pages: 58 - 60
Publisher: IEEE
 
» A Low Profile Dual-Polarized Wideband Omnidirectional Antenna Based on AMC Reflector
Abstract:
A low-profile dual-polarized wideband omnidirectional antenna with artificial magnetic conductor (AMC) reflector is proposed. The proposed antenna is operated in the long term evolution band (1.7–2.7 GHz), and has a compact size of 200 mm mm 30.6 mm (about height at 2.7 GHz). The antenna structure consists of a horizontally polarized circular loop antenna, a vertically polarized low-profile monopole antenna, and an AMC reflector. By carefully designing the reflection characteristics of the AMC reflector, the profile height of the proposed antenna is significantly reduced as compared with those of antennas backed by conventional perfect electric conductor (PEC) ground planes. Simulated and measured results show that the proposed antenna is able to achieve over 45% impedance bandwidth (VSWR <1.8) with stable radiation patterns in the band of 1.7–2.7 GHz. Owing to the attractive wide bandwidth, low-profile configuration, and ease of fabrication, the proposed antenna is suitable for microbase station systems, especially for indoor ceiling antenna networking applications.
Autors: Jianlin Wu;Shiwen Yang;Yikai Chen;Shiwei Qu;Zaiping Nie;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2017, volume: 65, issue:1, pages: 368 - 374
Publisher: IEEE
 
» A Low-Storage Discontinuous Galerkin Time-Domain Method
Abstract:
In this letter, a discontinuous Galerkin time-domain (DGTD) method with a low memory scheme for the solution of Maxwell’s equations has been proposed. By expressing curl vector basis functions in terms of barycentric coordinates, the matrices in the DGTD method including mass and flux matrices can be rewritten into the summation of a few universal matrices. With the use of the proposed scheme, the computer memory storage requirement of the DGTD method is greatly reduced with the increases of the order of spatial basis functions and the number of meshing elements, albeit a slightly increase of computational time. Numerical results including the slotted waveguide and Vivaldi antenna array are given to illustrate good computational performance.
Autors: Cheng-Yi Tian;Yan Shi;Chang-Hong Liang;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jan 2017, volume: 27, issue:1, pages: 1 - 3
Publisher: IEEE
 
» A Meander Line UHF RFID Reader Antenna for Near-field Applications
Abstract:
A novel ultrahigh frequency radio frequency identification reader antenna based on electromagnetic coupling between two open-ended microstrip (MS) meander lines for near-field applications is investigated in this paper. The corresponding currents flowing along the two MS meander lines are reversed in phase with approximately identical amplitudes. Meander-line units are introduced to achieve a uniform distribution of strong magnetic and electric fields. The performance of an antenna prototype comprised of six pairs of meander lines is analyzed. The proposed antenna simultaneously exhibits a uniform magnetic field distribution with a reading region of 480 mm mm mm and a uniform linear electric field distribution with a reading region of 480 mm mm mm. The proposed antenna exhibits a low far-field gain, and has a bandwidth from 914 to 929 MHz. Both simulated and measured results have shown a good performance of the antenna.
Autors: Yuan Yao;Caixia Cui;Junsheng Yu;Xiaodong Chen;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jan 2017, volume: 65, issue:1, pages: 82 - 91
Publisher: IEEE
 
» A MEMS-Assisted Temperature Sensor With 20- $mu text{K}$ Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2
Abstract:
This paper presents a dual-microelectromechanical system (MEMS) resonator-based temperature sensor. In this sensor, the readout circuit estimates the temperature by measuring the frequency ratio of the two clocks generated by separate resonators with different temperature coefficients. The circuit is realized in a 0.18- CMOS process and achieves a resolution of 20 over a bandwidth of 100 Hz while consuming 19 mW of power, leading to a resolution FOM of 0.04 pJK2. It enables us to implement a MEMS-based programmable oscillator with an Allan deviation of <1 over 1 s averaging time, and a frequency stability of <±0.1 parts per million in the temperature range from −45 °C to 105 °C. Such oscillators are key building blocks in telecom, datacom, and precision timekeeping applications.
Autors: Meisam Heidarpour Roshan;Samira Zaliasl;Kimo Joo;Kamran Souri;Rajkumar Palwai;Lijun Will Chen;Amanpreet Singh;Sudhakar Pamarti;Nicholas J. Miller;Joseph C. Doll;Carl Arft;Sassan Tabatabaei;Carl Sechen;Aaron Partridge;Vinod Menon;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jan 2017, volume: 52, issue:1, pages: 185 - 197
Publisher: IEEE
 
» A Method for Optimizing the Base Position of Mobile Painting Manipulators
Abstract:
This paper presents an algorithm to optimize the base position of a mobile manipulator to meet the requirements of local painting tasks. Considering the physical limits and singularity of the manipulator, the feasible base positions are first discretely calculated with the given poses of the end effector by inverse kinematics. Then, the joint-level performance criteria are proposed with respect to the requirements of the painting process. The weight coefficients are also determined by the critic method to balance the contribution of every criterion. Thus, the globally near-optimal base position is selected by sorting all feasible positions according to the evaluation criteria. The experimental results show that the planning result is well executed and has an acceptable computation time, thus demonstrating that the algorithm is both practical and effective compared with previous methods.
Autors: Shunan Ren;Ying Xie;Xiangdong Yang;Jing Xu;Guolei Wang;Ken Chen;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Jan 2017, volume: 14, issue:1, pages: 370 - 375
Publisher: IEEE
 

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