Electrical and Electronics Engineering publications abstract of: 07-2017 sorted by title, page: 0

» $2\times\text{VDD}$ 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation
Abstract:
A output buffer for 40-nm complementary metal–oxide–semiconductor technology nodes is proposed in this investigation featured with a slew rate (SR) auto-adjusted by process, voltage, temperature, and leakage (PVTL) detection and, particularly, the leakage compensation mechanism. The output driving current is boosted by turning on extra charging paths and discharging paths when the SR is detected to be dropping. With the proposed PVTL detection and leakage compensation circuit, the SR is improved with 11.0% and 67.4% by on-silicon measurement results given different VDDIO values (1.8/0.9 V) and temperatures (from 0 °C to 100 °C), respectively. The data rate is 250/500 MHz for VDDIO at 1.8/0.9 V, respectively.
Autors: Chua-Chin Wang;Zong-You Hou;Kai-Wei Ruan;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jul 2017, volume: 64, issue:7, pages: 812 - 816
Publisher: IEEE
 
» $H_\infty $ Relay Tracking Control of Multiagent Systems With the Assistance of a Voronoi Diagram
Abstract:
This brief is devoted to investigating the relay tracking control problem of a group of agents in a monitoring region. In order to solve such a problem, we partition the monitoring region into several “tracking zones” based on a Voronoi diagram. Then, we propose a novel impulsive model to describe this relay tracking problem, and define the performance for this model. A relay tracking control protocol, which can guarantee the desired performance, is designed based on the solution of a set of matrix inequalities. The effectiveness of the proposed relay tracking control algorithm is illustrated by numerical simulations.
Autors: Sheng-Li Du;Weiguo Xia;Xi-Ming Sun;Wei Wang;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jul 2017, volume: 64, issue:7, pages: 802 - 806
Publisher: IEEE
 
» $L_1$-Stochastic Stability and $L_1$-Gain Performance of Positive Markov Jump Linear Systems With Time-Delays: Necessary and Sufficient Conditions
Abstract:
This paper is concerned with -stochastic stability and -gain performance analysis of a continuous-time positive Markov jump linear system with a time-delay. By constructing a novel linear co-positive stochastic Lyapunov functional based on the positivity of the system, and characterizing the system equation of the mathematical expectation of the markovianized states, some necessary and sufficient delay-dependent conditions for -stochastic stability and -gain performance are presented in terms of linear programming. A numerical example is provided for showing the effectiveness of the obtained conditions, especially for exploring and revealing both the negative effect and the positive effect of the time-delay on stochastic stability of the positive Markov jump linear system with a time-delay.
Autors: Shuqian Zhu;Qing-Long Han;Chenghui Zhang;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Jul 2017, volume: 62, issue:7, pages: 3634 - 3639
Publisher: IEEE
 
» $\epsilon$-Nash Equilibria for Partially Observed LQG Mean Field Games With a Major Player
Abstract:
Huang (2010) and Nguyen and Huang (2012) solved the linear quadratic mean field systems and control problem in the case where there is a major agent (i.e. non-asymptotically vanishing as the population size goes to infinity) together with a population of minor agents (i.e. individually asymptotically negligible). The new feature in this case is that the mean field becomes stochastic and then, by minor agent state extension, the existence of -Nash equilibria together with the individual agents' control laws that yield the equilibria may be established. This paper presents results initially announced by Caines and Kizilkale (2013, 2014) where it is shown that if the major agent's state is partially observed by the minor agents, and if the major agent completely observes its own state, all agents can recursively generate estimates (in general individually distinct) of the major agent's state and the mean field, and thence generate feedback controls yielding -Nash equilibria.
Autors: Peter E. Caines;Arman C. Kizilkale;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Jul 2017, volume: 62, issue:7, pages: 3225 - 3234
Publisher: IEEE
 
» “Leaky Dielectric” Model for the Suppression of Dynamic $R_{\mathrm{ON}}$ in Carbon-Doped AlGaN/GaN HEMTs
Abstract:
GaN-on-Si power switching transistors that use carbon-doped epitaxy are highly vulnerable to dynamic dispersion, leading to reduced switching efficiency. In this paper, we identify the causes of this dispersion using substrate bias ramps to isolate the leakage paths and trapping locations in the epitaxy and simulation to identify their impact on the device characteristics. It is shown that leakage can occur both vertically and laterally, and we suggest that this is associated not only with bulk transport, but also with extended defects as well as hole gases at heterojunctions. For exactly the same epitaxial design, it is shown using a “leaky dielectric” model that depending on the leakage paths, dynamic dispersion can vary between insignificant and infinite. An optimum leakage configuration is identified to minimize dispersion requiring a resistivity which increases with depth in the buffer stack. It is demonstrated that leakage through the undoped GaN channel is required over the entire gate to drain gap, and not just under the contacts, in order to fully suppress dispersion.
Autors: Michael J. Uren;Serge Karboyan;Indranil Chatterjee;Alexander Pooth;Peter Moens;Abhishek Banerjee;Martin Kuball;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jul 2017, volume: 64, issue:7, pages: 2826 - 2834
Publisher: IEEE
 
» 0.9-V Class-AB Miller OTA in 0.35- $\mu \text{m}$ CMOS With Threshold-Lowered Non-Tailed Differential Pair
Abstract:
This paper presents a CMOS operational transconductance amplifier (OTA), suitable for sub-1-V supply applications, whose (input) common-mode voltage can be set to (/2 thanks to two combined techniques applied to the differential pair, namely, threshold voltage lowering and elimination of the tail current generator. Both techniques are implemented through a single common-mode feedback loop, which embeds the shared bulk terminal of the pair. In contrast to other low-voltage approaches employing bulk driving, the proposed OTA is driven from the gate terminals and exploits only MOS transistors in strong inversion. Therefore, effective values of dc gain, gain bandwidth, and noise are found, suitable for high-accuracy switched-capacitor applications. Using a standard 0.35- technology with nominal MOS transistors threshold around 0.7 V, a 0.9-V OTA with 0.45-V analog ground was designed and successfully tested. The measured gain and unity gain frequency were 65 dB and 1 MHz with phase margin of 60° for a capacitive load of 10 pF.
Autors: Alfio Dario Grasso;Salvatore Pennisi;Giuseppe Scotti;Alessandro Trifiletti;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jul 2017, volume: 64, issue:7, pages: 1740 - 1747
Publisher: IEEE
 
» 1-bit Observation for Direct-Learning-Based Digital Predistortion of RF Power Amplifiers
Abstract:
In this paper, we propose a low-cost data-acquisition approach for model extraction of digital predistortion (DPD) of RF power amplifiers. The proposed approach utilizes only 1-bit-resolution analog-to-digital converters (ADCs) in the observation path to digitize the error signal between the input and output signals. The DPD coefficients are then estimated based on the direct learning architecture using the measured signs of the error signal. The proposed solution is proved feasible in theory, and the experimental results show that the proposed algorithm achieves the performance equivalent to that using the conventional method. Replacing high-resolution ADCs with 1-bit comparators in the feedback path can dramatically reduce the power consumption and cost of the DPD system. The 1-bit solution also makes DPD become practically implementable in future broadband systems since it is relatively straightforward to achieve an ultrahigh sampling speed in data conversion using only simple comparators.
Autors: Haoyu Wang;Gang Li;Chongbin Zhou;Wei Tao;Falin Liu;Anding Zhu;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jul 2017, volume: 65, issue:7, pages: 2465 - 2475
Publisher: IEEE
 
» 100-Gb/s Transmission Over a 2520-km Integrated MCF System Using Cladding-Pumped Amplifiers
Abstract:
A 10.5-Tb/s optical transmission ( Gb/s QPSK channels per core) over 2520 km of multicore fiber is achieved using an integrated multicore transmission link consisting of directly spliced multicore components, such as fan-in/fan-out fiber couplers, a 60-km trench-assisted seven-core hexagonal fiber and cladding-pumped erbium-ytterbium-doped fiber amplifiers.
Autors: Carlos Castro;Saurabh Jain;Erik De Man;Yongmin Jung;John Hayes;Stefano Calabrò;Klaus Pulverer;Marc Bohn;Shaif-ul Alam;David John Richardson;Katsuhiro Takenaga;Takayuki Mizuno;Yutaka Miyamoto;Toshio Morioka;Werner Rosenkranz;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jul 2017, volume: 29, issue:14, pages: 1187 - 1190
Publisher: IEEE
 
» 16 × 1 Packaged MUX/DEMUX for Flexible-Grid Optical Networks
Abstract:
A comprehensive experimental study on the performance of a packaged flexible-grid compliant 16 × 1 packaged MUX/DEMUX device is presented. The device relies on a bandwidth and wavelength selective filtering element array integrated on an SOI platform, equipped with on-chip polarization multiplexing functionality. Multilateral operating credentials are demonstrated through the evaluation of the device in 2 × 1 MUX, 1 × 2 DEMUX and PolMUX configurations scenarios under realistic data traffic conditions, thus confirming its suitability for next-generation flexible-grid optical networks.
Autors: Nikolaos Iliadis;Giannis Kanakis;Nikolaos Argyris;Goerg Goetz;Alberto Dede;Dimitrios Kalavrouziotis;Giannis Poulopoulos;Jens Bolten;Ioannis Lazarou;Thorsten Wahlbrink;Anna Lena Giesecke;Antonello Vannucci;Dimitrios Apostolopoulos;Hercules Avramopoulo
Appeared in: Journal of Lightwave Technology
Publication date: Jul 2017, volume: 35, issue:14, pages: 3050 - 3059
Publisher: IEEE
 
» 20-Mb/s GFSK Modulator Based on 3.6-GHz Hybrid PLL With 3-b DCO Nonlinearity Calibration and Independent Delay Mismatch Control
Abstract:
A hybrid two-point modulator which mitigates the nonlinearity problem of a digitally controlled oscillator (DCO) and provides a fine delay mismatch calibration is proposed for high data rate applications. A DCO with a separate high-pass modulation path in which only 3 b are used for a capacitor array is designed for flexible gain partition and simple nonlinearity calibration. A nonuniform multilevel quantizer and a finite-impulse response filter are employed to improve modulation quality and reduce quantization noise for high data rate. In the low-pass modulation, a fractional- divider based on a phase rotator and an additional high-frequency modulator enables fine delay time control between two modulation paths. Delay mismatch calibration circuit based on a time-to-digital converter is designed to calculate the optimum delay time automatically. A prototype 3.6-GHz two-point modulator is implemented in 65-nm CMOS. The modulator performs 20-Mb/s GFSK with the error vector magnitude performance of 3.7%, consuming 10.6 mW from a 1-V supply.
Autors: Xiaoyong Li;Sitao Lv;Woogeun Rhee;Wen Jia;Zhihua Wang;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jul 2017, volume: 65, issue:7, pages: 2387 - 2398
Publisher: IEEE
 
» 200 kJ Pulsed Power System for Pulsed Plasma Device
Abstract:
A 200 kJ pulsed power system (PPS) has been built up to drive pulsed plasma devices. This PPS consists of two 100 kJ capacitor bank modules, each comprising of five capacitors of each , a discharge switch, and a pulse-shaping unit. When both the banks are charged simultaneously to −15 kV using full charging technique, it delivers a peak current 100 kA at the load (damping resistor and pulse-shaping inductor). Later on, a plasma system will be attached at the load which will also have an inductive and resistive effect. A fiber-optic triggering unit controls both the modules and there exists a flexibility of sometimes operating a single module only, besides there are provisions for further up gradation of the PPS to a targeted 600 kJ. Prior to this development, PSpice simulation was carried out to estimate the parameters of the circuit components to achieve the required wave pulse with precision. Using these parameters, a design of the PPS was made keeping into account about the critical issues involved and the ratings of the components, some of which were fabricated in house. This paper basically includes the criticality surrounding the operation of a high-energy long-pulse PPS under negative operating voltage.
Autors: Suramoni Borthakur;Nayan Talukdar;Nirod Kumar Neog;Tridip Kumar Borthakur;Rajesh Kumar;Rishi Verma;Anurag Shyam;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Jul 2017, volume: 45, issue:7, pages: 1769 - 1775
Publisher: IEEE
 
» 200 V Enhancement-Mode p-GaN HEMTs Fabricated on 200 mm GaN-on-SOI With Trench Isolation for Monolithic Integration
Abstract:
Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate. In this letter, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer. By well-controlled epitaxy and device fabrication, high-performance 200 V enhancement-mode (e-mode) p-GaN high electron mobility transistors with a gate width of 36 mm are achieved. This letter demonstrates that by using GaN-on-SOI in combination with trench isolation, it is very promising to monolithically integrate GaN power systems on the same wafer to reduce the parasitic inductance and die size.
Autors: Xiangdong Li;Marleen Van Hove;Ming Zhao;Karen Geens;Vesa-Pekka Lempinen;Jaakko Sormunen;Guido Groeseneken;Stefaan Decoutere;
Appeared in: IEEE Electron Device Letters
Publication date: Jul 2017, volume: 38, issue:7, pages: 918 - 921
Publisher: IEEE
 
» 200-Gbps DFT-S OFDM Using DD-MZM-Based Twin-SSB With a MIMO-Volterra Equalizer
Abstract:
We experimentally demonstrate 208-Gb/s/ discrete Fourier transform spread orthogonal frequency division multiplexing (DFT-S OFDM) transmission over a 40-km standard single-mode fiber without chromatic dispersion compensation using a low-cost direct-detection architecture based on the dual-driver Mach–Zehnder modulator (MZM). One twin-single sideband (SSB) signal is generated by driving the upper and lower arms of a dual-driver MZM with a real signal and its respective Hilbert pair. A MIMO-Volterra equalizer is proposed to mitigate the interference and nonlinearity penalty of the twin-SSB signal. Using the Twin-SSB without the MIMO algorithm can only reach 165 Gb/s/, and applying a conventional SSB can only achieve 164 Gb/s/ with a bit error ratio less than . However, we achieve a 240-Gb/s/ twin-SSB DFT-S OFDM signal in the back-to-back (BTB) case using the twin-SSB signal and MIMO-Volterra Equalization method, which implies that double spectral efficiency and more than 45% data rate improvement are obtained.
Autors: Jianyang Shi;Yingjun Zhou;Yuming Xu;Junwen Zhang;Jianjun Yu;Nan Chi;
Appeared in: IEEE Photonics Technology Letters
Publication date: Jul 2017, volume: 29, issue:14, pages: 1183 - 1186
Publisher: IEEE
 
» 3-D Focused Microwave Hyperthermia for Breast Cancer Treatment With Experimental Validation
Abstract:
A 3-D focusing technique for noninvasive microwave hyperthermia treatment for breast cancer is presented and experimentally validated. The 3-D focusing is conducted to find the optimum excitations (phases and amplitudes) of a 3-D antenna array surrounding the breast using particle swarm optimization. The focusing approach aims at producing the required temperature (42 °C) at a tumor anywhere in the breast without causing hot spots in healthy tissue. Based on the modeling, a microwave system, which includes a 4.2-GHz source, power amplifier, two-stage power dividers, and phase shifters in addition to 24-element antenna array, was designed, built, and tested. The test was performed on the challenging scenario of a very dense breast phantom having 1-cm3 tumor embedded in glands. The experiments were conducted on a 3-D printed phantom that has realistic dielectric and thermal properties. The breast phantom was irradiated for one hour while the temperature distribution was recorded by thermal imager at different time intervals. The results confirmed the capability of the proposed 3-D focusing technique and experimental system in using 65-W microwave power to elevate the temperature at tumor to more than 42 °C while keeping healthy tissue safe at 36 °C without any hot spots.
Autors: Phong Thanh Nguyen;Amin M. Abbosh;Stuart Crozier;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jul 2017, volume: 65, issue:7, pages: 3489 - 3500
Publisher: IEEE
 
» 3-D Implementation of Transformation Optics Using a Tetrahedron-Based Meshing Technique and Homogeneous Materials
Abstract:
A tetrahedron meshing and transforming method for 3-D implementation of transformation optics is proposed and verified for a few waveguide components. The method is applicable to a wide range of electromagnetic problems. An important feature of the proposed method is that the transformed medium will be piecewise homogeneous and free of any singularities. In this method, the region under transformation is divided into a few tetrahedrons, both in the physical and virtual domains. Each tetrahedron of the physical domain transforms to a tetrahedron in the virtual domain. The material properties of each tetrahedron are then calculated using the Jacobean matrix of the transformation. Since the elements of the Jacobean matrix are constant, the and tensors are finite and homogeneous in each tetrahedron. The method is verified for several rectangular waveguide coupler examples. Features of the and tensors of the discussed examples are described. For instance, it is shown that the material properties may reduce to 2-D material types, or material anisotropy may reduce, under certain conditions.
Autors: Mohammad-Rahim Kazemzadeh;Abbas Alighanbari;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jul 2017, volume: 65, issue:7, pages: 3549 - 3559
Publisher: IEEE
 
» 3-D MIMO Parametric Stochastic Channel Model for Urban Macrocell Scenario
Abstract:
For the design, performance evaluation, and optimization of potential 3-D multiple input and multiple output (3-D MIMO) algorithms, an accurate stochastic channel model is indispensable. Simultaneously, it is desirable for the new 3-D MIMO channel model to be a further expansion of already well developed 2-D MIMO channel models to allow easy implementation and facilitate possible generation partnership project standardization. This paper first shows our recent outfield channel measurement campaigns in urban macrocell scenarios with a planar antenna array and a crown-shaped antenna array installed on the base station and the user sides, respectively. A comprehensive methodology from the statistical analysis perspective to characterize the 3-D MIMO channel, particularly, in the elevation domain, is then elaborated upon. The framework of the new approach coincides with mainstream parametric stochastic models. Moreover, it is observed that, by recalculating the statistics of the large scale parameters as well as their cross-correlation matrix to rectify existent non-positive definite problem, adding distance dependent elevation angular spread and introducing a mixture of Von Mises Fisher distributions to describe the interdependence between azimuth and elevation, the accuracy of current standardized 3-D channel models can be improved upon. Finally, numerical results verify the validity of our proposal.
Autors: Yang Zhang;Lihua Pang;Guangliang Ren;Fengkui Gong;Xiao Liang;Jianwu Dou;Jiandong Li;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Jul 2017, volume: 16, issue:7, pages: 4246 - 4260
Publisher: IEEE
 
» 3-D Sidewall Interconnect Formation Climbing Over Self-Assembled KGDs for Large-Area Heterogeneous Integration
Abstract:
Massively parallel chip assembly based on multi-interposer block concept is demonstrated for large-area heterogeneous system integration. The chips are aligned in parallel by liquid surface tension and assembled on the Si interposers through oxide-oxide bonding at room temperature without thermocompression. 3-D Cu sidewall interconnects (the width is approximately ) climbing over 100--thick self-assembled chips are formed with a spin-on thick photoresist by electroplating. In addition, 3-D Cu interconnects with a width of nearly are successfully formed across polyimide slopes formed on the sidewall of self-assembled chips. The electrical properties of the 3-D sidewall interconnects are characterized by the daisy chains, resistance distribution, and characteristic fluctuation of CMOS fabricated on the self-assembled chips.
Autors: Takafumi Fukushima;Akihiro Noriki;Jichoel Bea;Mariappan Murugesan;Hisashi Kino;Koji Kiyoyama;Kang-Wook Lee;Tetsu Tanaka;Mitsumasa Koyanagi;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jul 2017, volume: 64, issue:7, pages: 2912 - 2918
Publisher: IEEE
 
» 3D MIMO Outdoor-to-Indoor Propagation Channel Measurement
Abstract:
The 3-D multiple-input multiple-output (3-D MIMO) systems have received great interest recently because of the spatial diversity advantage and capability for full-dimensional beamforming, making them promising candidates for practical realization of massive MIMO. In this paper, we present a low-cost test equipment (channel sounder) and post-processing algorithms suitable for investigating the 3-D MIMO channels as well as the results from a measurement campaign for obtaining elevation and azimuth characteristics in an outdoor-to-indoor (O2I) environment. Due to limitations in available antenna switches, our channel sounder consists of a hybrid switched/virtual cylindrical array with effectively 480 antenna elements at the base station. The virtual setup increased the overall MIMO measurement duration, thereby introducing phase drift errors in the measurements. Using reference antenna measurements, we estimate and correct for the phase errors during post-processing. We provide the elevation and azimuth angular spreads for the measurements done in an urban macro-cellular and urban micro-cellular environments, and study their dependence on the user equipment (UE) height. Based on the measurements done with UE placed on different floors, we study the feasibility of separating users in the elevation domain. The measured channel impulse responses are also used to study the channel hardening aspects of the massive MIMO and the optimality of the maximum ratio combining receiver.
Autors: Vinod Kristem;Seun Sangodoyin;C. Umit Bas;Martin Käske;Juho Lee;Christian Schneider;Gerd Sommerkorn;Charlie Jianzhong Zhang;R. S. Thomä;Andreas F. Molisch;
Appeared in: IEEE Transactions on Wireless Communications
Publication date: Jul 2017, volume: 16, issue:7, pages: 4600 - 4613
Publisher: IEEE
 
» A 0.065-mm2 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB
Abstract:
A 0.065-mm2 single-channel calibration-free 12-b analog-to-digital converter (ADC) sampling at 600 MS/s in 28-nm ultrathin body bias fully depleted silicon on insulator (FD-SOI) is presented. The selected hybrid architecture, incorporating pipelined and asynchronous successive approximation register ADC, demonstrates advantages and suitability of different design techniques utilizing forward body bias (FBB) capability of FD-SOI. Using an FBB voltage range of 0–1.8 V has enabled an signal-to-noise plus distortion ratio (SNDR) improvement of more than 9 dB. An integrated body bias generator ensures the required voltages for FBB. This paper demonstrates 61.5-dB and 60.7-dB SNDR at low and Nyquist input frequency, respectively, at 600-MS/s sampling frequency. The Walden FoM of 37.2 fJ/conv-step and Schreier FoM of 162.5 dB at 600 MS/s are achieved in Nyquist conditions. Speed robustness of the architecture has been demonstrated by achieving 57-dB SNDR at 800MS/s, >50-dB SNDR up to 950 MS/s, and 58.5-dB SNDR till 500-MHz input frequency at 600 MS/s.
Autors: Ashish Kumar;Chandrajit Debnath;Pratap Narayan Singh;Vivek Bhatia;Shivani Chaudhary;Vigyan Jain;Stephane Le Tual;Rakesh Malik;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jul 2017, volume: 52, issue:7, pages: 1927 - 1939
Publisher: IEEE
 
» A 0.5–16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET
Abstract:
This paper presents a flexible-reach 0.5–16.3 Gb/s serial transceiver which is integrated into a field-programmable gate array (FPGA) and fabricated in 16-nm FinFET CMOS. The transceiver is fully adaptive to cover the FPGA requirement to support a multitude of combinations of data-rates and standards such as 10 G-KR, PCIe Gen3/4, and SFP+ across a wide range of channel loss profiles. High-performance techniques employed include a fully adaptive continuous-time linear equalizer, automatic gain control, an 11-tap decision feedback equalizer, wideband LC phase-locked loops, and a high-tracking-bandwidth clock and data recovery loop with low latency. Low-power techniques such as half-rate clocking, active inductors and data-rate programmability are employed to meet stringent power budgets at the different rates. At 16.3 Gb/s, the receiver has a jitter tolerance of >0.3UI at 100 MHz. The transceiver achieves a bit error rate < 10e − 15 with up to 28-dB loss at Nyquist. It consumes 219 mW/channel at 16.3 Gb/s. The design has robust performance across process, voltage, and temperature, and the architecture allows for a high degree of tuning to handle different system environments in deployment.
Autors: Marc Erett;James Hudner;Declan Carey;Ronan Casey;Kevin Geary;Kay Hearne;Pedro Neto;Thomas Mallard;Vikas Sooden;Mark Smyth;Yohan Frans;Jay Im;Parag Upadhyaya;Wenfeng Zhang;Winson Lin;Bruce Xu;Ken Chang;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jul 2017, volume: 52, issue:7, pages: 1783 - 1797
Publisher: IEEE
 
» A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
Abstract:
This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high- metal-gate (HMG) CMOS technology with macro area of . Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25°.
Autors: Shang-Lin Wu;Kuang-Yu Li;Po-Tsang Huang;Wei Hwang;Ming-Hsien Tu;Sheng-Chi Lung;Wei-Sheng Peng;Huan-Shun Huang;Kuen-Di Lee;Yung-Shin Kao;Ching-Te Chuang;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jul 2017, volume: 64, issue:7, pages: 1791 - 1802
Publisher: IEEE
 
» A 0.71-pJ/b ON-OFF Keying $K$ -Band Oscillator Using an InP-Based Resonant Tunneling Diode
Abstract:
This letter presents the high-data rate performance of a 7-Gb/s resonant tunneling diode (RTD)-based on-off keying (OOK) oscillator core with a heterojunction bipolar transistor (HBT) switch design. It is found that the integrated HBT switch improves the data rate of the RTD OOK oscillator IC by minimizing the RC delay time in the previous direct driving oscillator design. The fabricated OOK oscillator IC shows an energy efficiency of 0.71-pJ/b which is the best value reported to date to the authors’ knowledge in a related frequency range.
Autors: Jaehong Park;Jooseok Lee;Kiwon Lee;Kyounghoon Yang;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jul 2017, volume: 27, issue:7, pages: 660 - 662
Publisher: IEEE
 
» A 10-GHz Delay Line Frequency Discriminator and PD/CP-Based CMOS Phase Noise Measurement Circuit
Abstract:
This paper presents a delay line frequency discriminator and phase detector/charge pump (PD/CP)-based phase noise measurement (PNM) circuit with wide bandwidth, great sensitivity, and reliable on-chip integration. A delay-locked loop is integrated to automatically align the PD input phases, and a dc offset cancellation circuit is embedded to overcome the circuit mismatches. This PNM demonstrates −61/−81 dBc single tone sensitivity and −110.35/−138.60 dBc/Hz phase noise sensitivity at 100 kHz/1 MHz-offset, respectively, for a 10-GHz clock. The PNM errors are 0.35/1.12 dB at 100 kHz/1 MHz, respectively, compared with the signal analyzer’s (Agilent N9030A) PNM results. The PNM bandwidth is 110 MHz. This proof-of-concept design is fabricated in a 65-nm CMOS technology with the chip area of 1.5 mm mm. The circuit consumes 97.7 mW of power.
Autors: Shilei Hao;Tongning Hu;Qun Jane Gu;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jul 2017, volume: 65, issue:7, pages: 2361 - 2372
Publisher: IEEE
 
» A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC
Abstract:
This paper presents a 12b 180 MS/s 0.068 mm2 time-interleaved pipelined-SAR analog-to-digital conver-ter (ADC) with gain and offset calibrations fully embedded on-chip. The proposed binary-search gain calibration (BSGC) technique corrects the inter-stage gain error caused by the open-loop residue amplifier. The BSGC, fully integrated into the second-stage SAR ADC, contributes to a compact area. We improve the noise performance by implementing a merged-residue-DAC operation in the first-stage ADC. Also, we propose a dual-phase bootstrap technique to improve the sampling linearity in the partial interleaving architecture. The measurement results of the ADC prototype in 65 nm CMOS demonstrate the effectiveness of the proposed calibration through the enhancement of the signal to noise-and-distortion ratio from 51.5 to 60.9 dB at a Nyquist input, leading to a FoM@Nyq of 36.7 fJ/conversion-step.
Autors: Jianyu Zhong;Yan Zhu;Chi-Hang Chan;Sai-Weng Sin;Seng-Pan U;Rui Paulo Martins;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jul 2017, volume: 64, issue:7, pages: 1684 - 1695
Publisher: IEEE
 
» A 174.3-dB FoM VCO-Based CT $\Delta \Sigma $ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS
Abstract:
This paper presents a high dynamic range (DR) power-efficient voltage-controlled oscillator (VCO)-based continuous-time modulator. It introduces a robust and low-power fully-digital phase extended quantizer that doubles the VCO quantizer resolution compared to a conventional XOR-based phase detector. A tri-level resistor digital-to-analog converter is also introduced as complementary to the new quantizer, enabling high DR while creating a dynamic power saving mechanism for the proposed design. Fabricated in 130-nm CMOS, the analog-to-digital converter achieved peak Schreier Figure-of-Merit (FoM) of 174.3 dB with a high DR of 89 dB over 0.4-MHz BW, consuming only 1 mW under 1.2-V power supply. It also reaches a peak Walden FoM of 59 fJ/conv with 74.7-dB signal-to-noise-and-distortion ratio over 2-MHz BW.
Autors: Shaolan Li;Abhishek Mukherjee;Nan Sun;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jul 2017, volume: 52, issue:7, pages: 1940 - 1952
Publisher: IEEE
 
» A 2–11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI
Abstract:
Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase rotators (PRs) are key blocks to align the phase of the local clock to the transitions of the incoming data and to sample the eye in the optimal position. Small phase step and high linearity are paramount in preserving the horizontal time margin, tightened by the reduced symbol duration at 25 Gb/s and beyond. Interpolation of /4-spaced signals is a viable means of improving linearity at high resolution, provided multi-phase signals with low phase error are available. An injection-locked ring oscillator (ILRO) with a mixed analog and digital calibration loop is proposed for high accuracy multi-phase generation over a wide frequency range and against large voltage and temperature variations. A phase detector (PD) based on two passive mixers measures the quadrature error and continuously tunes the oscillator to achieve low phase error. Concurrently, a window comparator monitors the PD output and drives digital coarse calibration in background. Two test chips have been fabricated in 28-nm CMOS fully depleted silicon on insulator technology. The stand-alone ILRO demonstrates 0.2–11.7 GHz frequency range with better than 1.5° quadrature phase error over ±20% supply and −40 °C to +120 °C temperature variations. Power consumption is scalable from 3 to 15 mW. When the ILRO drives the 7-bit PR, it demonstrates differential and integral non-linearity within 0.5 and 1.1 LSB, respectively, across the 2–11 GHz frequency range with 18.6-mW maximum power dissipation. Measured performances compare favorably against the state of the art and meet the requir- ments of >25 Gb/s multi-standard I/O RXs.
Autors: Enrico Monaco;Gabriele Anzalone;Guido Albasini;Simone Erba;Matteo Bassi;Andrea Mazzanti;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jul 2017, volume: 52, issue:7, pages: 1739 - 1752
Publisher: IEEE
 
» A 220–275 GHz Direct-Conversion Receiver in 130-nm SiGe:C BiCMOS Technology
Abstract:
This letter presents a wideband 240-GHz direct-conversion receiver manufactured in a 130-nm SiGe:C BiCMOS technology with /500 GHz. A mixer-first receiver is implemented, with a new dc offset cancellation loop architecture to compensate for the mixer dc offsets and biasing purposes. A transimpedance amplifier is utilized as a load for the mixer, optimized with the dc offset cancellation loop to maximize the bandwidth. A local oscillator (LO) chain that multiplies by 8 a 30-GHz input signal drives the mixer. The proposed receiver achieves the widest 3-dB bandwidth among the published works of 55 GHz, with a conversion gain of 13 dB. The measured average single-sideband noise figure is 18 dB. It dissipates 500 mW, while occupying 1.25 mm2, requiring LO input signal of only −10 dBm.
Autors: M. H. Eissa;A. Awny;M. Ko;K. Schmalz;M. Elkhouly;A. Malignaggi;A. C. Ulusoy;D. Kissinger;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jul 2017, volume: 27, issue:7, pages: 675 - 677
Publisher: IEEE
 
» A 220-GHz Compact Equivalent Circuit Model of CMOS Transistors
Abstract:
This study presents a physical-based RF equivalent circuit model for CMOS transistors. To increase the model accuracy and extend the effective frequency band, the interconnection effects between the input–output pad and the gate–drain of the transistor are described by using a second-order distributed parameter transmission line equivalent circuit network. Both the extrinsic and intrinsic parameters in the model are extracted from the multibias scattering parameters. Based on the proposed model, the S-parameters are calculated and compared with the experimental results. The comparison shows that using second-order distributed parameter transmission line model can improve the phase accuracy of the model remarkably. The proposed model achieves a high accuracy up to 220 GHz.
Autors: Yunqiu Wu;Yanan Hao;Jun Liu;Kai Kang;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jul 2017, volume: 27, issue:7, pages: 651 - 653
Publisher: IEEE
 
» A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS
Abstract:
Thanks to the high flexibility in matching the channel frequency response and the compatibility with simple adaptation techniques, Finite Impulse Response (FIR) filters enhance the equalization performances of high-speed wireline receivers. This paper presents a 25-Gb/s FIR equalizer in 28-nm CMOS. The impact of filter noise and distortion, crucial aspects for an analog implementation, is discussed. A thorough system analysis, aimed at deriving the specifications for circuits design, suggests four taps, with a tap-to-tap delay in the range 0.5–1 UI, as optimal compromise among complexity (hence power dissipation) and equalization performances. To keep high SNR, a new all-pass stage is proposed to realize a delay line suitable for high-speed operation while being able to accommodate large input signal amplitude. Measurements are shown at 25 Gb/s for both Non Return to Zero (NRZ) and Pulse Amplitude Modulation (PAM)-4 signals. With a core power dissipation of 25 mW from 1-V supply, the proposed FIR filter recovers 20- and 9-dB channel loss for NRZ and PAM-4, respectively, with horizontal eye openings of 50% and 30%. Compared with the previously reported FIR filters for wireline links at comparable speed, the proposed realization achieves excellent equalization performance with the best power efficiency of 1 mW/Gb/s.
Autors: Fabrizio Loi;Enrico Mammei;Simone Erba;Matteo Bassi;Andrea Mazzanti;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jul 2017, volume: 64, issue:7, pages: 1903 - 1913
Publisher: IEEE
 
» A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise
Abstract:
This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital phase-locked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC). The TDC employs a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizing an error-feedback topology. Such an error-feedback unit of a first-order -TDC can be cascaded as a multi-stage noise shaping configuration to achieve higher-order noise-shaping and, thereby, low in-band phase noise (PN) of the ADPLL. A digitally controlled oscillator with a transformer and a pair of cross-coupled NMOS amplifiers exploits magnetic and capacitive coupling to achieve nearly an octave frequency coverage, i.e., 1.73–3.38 GHz (after a 2 division). Fabricated in 40-nm CMOS, the ADPLL achieves better than −110-dBc/Hz in-band PN and occupies an active area of 0.5 mm2. With a 50-MHz reference clock, a 2-GHz output RF clock, and a loop bandwidth of 800 kHz, this prototype achieves 420-fs jitter, integrated from 1-kHz to 30-MHz offset, while drawing 10.7 mW.
Autors: Ying Wu;Mina Shahmohammadi;Yue Chen;Ping Lu;Robert Bogdan Staszewski;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jul 2017, volume: 52, issue:7, pages: 1885 - 1903
Publisher: IEEE
 
» A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS
Abstract:
This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type bootstrapped sampling switches minimize the interchannel crosstalk among top-plate sampling SAR channels and the signal-dependent leakage current during SAR conversion cycles. The power efficiency of this ADC is significantly improved by many design techniques. The merged capacitor switching algorithm leads to high switching efficiency and a smaller area. The modified reference voltage scheme optimizes input common-mode voltage of the comparators. The optimal subradix-2 capacitive DAC results in low-power reference buffers and higher conversion speed. This ADC achieves 49-dB SNR, 52-dB THD, and 42-dB SNDR up to Nyquist frequency at 5 GS/s, consumes 76 mW from 1 V supply, and occupies 0.57 mm in 28 nm CMOS technology. The implemented architecture also demonstrates high scalability to advanced CMOS technology nodes and has even higher power efficiency potential.
Autors: Jie Fang;Shankar Thirunakkarasu;Xuefeng Yu;Fabian Silva-Rivas;Chaoming Zhang;Frank Singor;Jacob Abraham;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jul 2017, volume: 64, issue:7, pages: 1673 - 1683
Publisher: IEEE
 
» A 58-ppm/°C 40-nW BGR at Supply From 0.5 V for Energy Harvesting IoT Devices
Abstract:
This brief presents a 40-nW 0.5-V supply voltage and 0.24-V output reference for an energy harvester. The emitter–base voltage of a PNP transistor is divided by the presented switch capacitor circuit to obtain the low output reference. The resistorless proportional-to-absolute-temperature circuit and the low-voltage high-power-supply-rejection-ratio current source are used to improve the accuracy and line regulation performance of the reference. The proposed bandgap reference is implemented in a 0.18- standard complementary metal–oxide–semiconductor process and has a total area of 0.058 mm2. Test results show that the minimum supply voltage is 0.5 V due to the clock bootstrap and doubler. The line regulation is about 1.1 mV/V in the supply voltage range of 0.5–0.9 V. With 3-bit trimming, the temperature coefficient of 58 ppm/°C in the range of −25 °C–85 °C and the accuracy of 0.9% can be achieved.
Autors: Junchao Mu;Lianxi Liu;Zhangming Zhu;Yintang Yang;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jul 2017, volume: 64, issue:7, pages: 752 - 756
Publisher: IEEE
 
» A 63-dB DR 22.5-MHz 21.5-dBm IIP3 Fourth-Order FLFB Analog Filter
Abstract:
In this paper, a fourth-order continuous-time follow-the-leader-feedback (FLFB) low-pass (LP) filter is presented. The outstanding FLFB noise behavior is exploited to minimize power consumption. This is achieved by means of customized implementation solutions based on combination of Active-RC/Active--RC cells. The 0.18- CMOS prototype performs 22.5-MHz −3 dB LP frequency response. Large linearity and dynamic range were achieved resulting in 21.5-dBm in-band (iB) IIP3 and 87- input referred iB integrated noise. The SNR for a −40 dB HD3 is 63 dB. The overall power consumption is 12.6 mW (i.e., 7 mA from a 1.8-V supply). The efficiency of the proposed technique is demonstrated by the achieved figure-of-merit (150.8 dB , which favourably compares to the state-of-the-art active-RC analog filters.
Autors: Marcello De Matteis;Alessandra Pipino;Federica Resta;Alessandro Pezzotta;Stefano D’Amico;Andrea Baschirotto;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jul 2017, volume: 52, issue:7, pages: 1977 - 1986
Publisher: IEEE
 
» A 65-nm CMOS Wideband TDD Front-End With Integrated T/R Switching via PA Re-Use
Abstract:
Time-division duplex (TDD) systems rely on off-chip transmit/receive (T/R) switches to isolate the RX from the high-output power of the TX, while existing on-chip T/R switching solutions are narrow-band or high loss. This paper presents a wideband integrated T/R switching technique that eliminates the conventional, lossy series T/R switch from the signal path. The system reconfigures the PA as an LNA during the receive mode, and utilizes only DC mode control switches to enable TDD co-existence. To demonstrate this technique, a polar transmitter that can be re-purposed into a common-gate LNA is implemented in 65-nm CMOS. With an integrated front-end balun transformer, the transmitter achieves 20-dBm peak output power with 32.7% peak drain efficiency. In the receive mode, the PA is reconfigured into a wideband 3.4–5.4-GHz LNA achieving −6.7-dBm P1dB, and 5.1-dB noise figure.
Autors: Xiao Xiao;Amanda Pratt;Bonjern Yang;Angie Wang;Ali M. Niknejad;Elad Alon;Borivoje Nikolić;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jul 2017, volume: 52, issue:7, pages: 1768 - 1782
Publisher: IEEE
 
» A 7-MHz Integrated Peak-Current-Mode Buck Regulator With a Charge-Recycling Technique
Abstract:
A 7-MHz integrated peak-current-mode buck regulator with a charge-recycling technique and a fast response current-sensing circuit is proposed. The proposed charge-recycling technique contributes to the improvement of the light load efficiency by up to 1.7% for the proposed buck regulator. Moreover, the proposed buck regulator achieves a fast response time of less than 10 ns with a fast response current-sensing circuit. Applying the proposed charge-recycling technique and the current-sensing circuit, the peak-current-mode buck regulator for the mobile application is realized with an operating frequency of 7 MHz, an output voltage of 0.8 V, a maximum load current of 500 mA, and a peak efficiency of over 77%.
Autors: Jung-Woo Ha;Byung-Ha Park;Jung-Hoon Chun;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jul 2017, volume: 64, issue:7, pages: 797 - 801
Publisher: IEEE
 
» A 82-nW Chaotic Map True Random Number Generator Based on a Sub-Ranging SAR ADC
Abstract:
An ultra-low power true random number generator (TRNG) based on a sub-ranging SAR analog-to-digital converter (ADC) is proposed. The proposed TRNG is composed of a coarse-SAR ADC with a low-power adaptive-reset comparator and a low-power dynamic amplifier. The coarse-ADC part is shared with a sub-ranging SAR ADC for area reduction. The shared coarse-ADC not only plays the role of discrete-time chaotic circuit but also reduces the overall SAR ADC energy consumption by selectively activating the fine-SAR ADC. Also, the proposed dynamic residue amplifier consumes only 48 nW and the adaptive-reset comparator generates a chaotic map with only 6-nW consumption. The proposed TRNG core occupies 0.0045 mm2 in 0.18- CMOS technology and consumes 82 nW at 270-kbps throughput with 0.6-V supply. It successfully passes all of National Institute of Standards and Technology (NIST) tests, and it achieves the state-of-the-art figure-of-merit of 0.3 pJ/bit.
Autors: Minseo Kim;Unsoo Ha;Kyuho Jason Lee;Yongsu Lee;Hoi-Jun Yoo;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jul 2017, volume: 52, issue:7, pages: 1953 - 1965
Publisher: IEEE
 
» A Band-Notched Absorber Designed With High Notch-Band-Edge Selectivity
Abstract:
In this paper, a band-notched absorber with high notch-band-edge selectivity is proposed and investigated. It is formed by introducing a narrower and full reflectance band into a wider absorption band. For each absorbing unit cell, two independently magnetic and electric resonances with adjacent resonant frequencies are employed to develop the narrower and full reflectance band, while a dipole-shaped metal strip with a resister printed on one side of the supporting substrate and a ground plane is used to realize the wider absorption band. By retrieving relative equivalent circuits of each cell, the performance of the proposed absorber can be qualitatively analyzed. Simply through tuning the frequencies of the independently magnetic and electric resonances, the performance of the notched band can be adjusted with high notch-band-edge selectivity. A sample of an absorber with the notched band frequency from 8.2 to 9.8 GHz, good absorption band from 4.8 to 8.0 GHz and 10.2 to 16 GHz has been designed, fabricated, and measured. Good agreement among circuit analysis, simulation results, and measurement results is finally obtained.
Autors: Peng Mei;Xian Qi Lin;Jia Wei Yu;Peng Cheng Zhang;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jul 2017, volume: 65, issue:7, pages: 3560 - 3567
Publisher: IEEE
 
» A Bandit Approach to Price-Aware Energy Management in Cellular Networks
Abstract:
We introduce a reinforcement learning algorithm inspired by the combinatorial multi-armed bandit problem to minimize the time-averaged energy cost at individual base stations (BSs), powered by various energy markets and local renewable energy sources, over a finite-time horizon. The algorithm sustains traffic demands by enabling sparse beamforming to schedule dynamic user-to-BS allocation and proactive energy provisioning at BSs to make ahead-of-time price-aware energy management decisions. Simulation results indicate a superior performance of the proposed algorithm in reducing the overall energy cost, as compared with recently proposed cooperative energy management designs.
Autors: Xinruo Zhang;Mohammad Reza Nakhai;Wan Nur Suryani Firuz Wan Ariffin;
Appeared in: IEEE Communications Letters
Publication date: Jul 2017, volume: 21, issue:7, pages: 1609 - 1612
Publisher: IEEE
 
» A Bayesian Approach for Parameter Estimation With Uncertainty for Dynamic Power Systems
Abstract:
We address the problem of estimating the uncertainty in the solution of power grid inverse problems within the framework of Bayesian inference. We investigate two approaches, an adjoint-based method and a stochastic spectral method. These methods are used to estimate the maximum a posteriori point of the parameters and their variance, which quantifies their uncertainty. Within this framework, we estimate several parameters of the dynamic power system, such as generator inertias, which are not quantifiable in steady-state models. We illustrate the performance of these approaches on a 9-bus power grid example and analyze the dependence on measurement frequency, estimation horizon, perturbation size, and measurement noise. We assess the computational efficiency, and discuss the expected performance when these methods are applied to large systems.
Autors: Noémi Petra;Cosmin G. Petra;Zheng Zhang;Emil M. Constantinescu;Mihai Anitescu;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jul 2017, volume: 32, issue:4, pages: 2735 - 2743
Publisher: IEEE
 
» A Black-Box Identification Method for Automated Discrete-Event Systems
Abstract:
This paper deals with the identification of discrete-event manufacturing systems that are automated using a programmable logic controller (PLC). The behavior of the closed-loop system (PLC and Plant) is observed during its operation and is represented by a single long sequence of observed input/output (I/O) signals vectors. The proposed method follows a black-box and passive identification approach that allows addressing large and complex industrial DES and yields compact and expressive interpreted Petri net (IPN) models. It consists of two complementary stages; the first one obtains, from the I/O sequence, the reactive part of the model composed by observable places and transitions. The I/O sequence is also mapped into a sequence of the created transitions, from which the second stage builds the non observable part of the model including places that ensure the reproduction of the observed input output sequence. This method, based on polynomial-time algorithms on the size of the input data, has been implemented as a software tool that generates and draws the IPN model; it has been tested with input/output sequences obtained from real systems in operation. The tool is described and its application is illustrated through a case study.
Autors: Ana Paula Estrada-Vargas;Ernesto López-Mellado;Jean-Jacques Lesage;
Appeared in: IEEE Transactions on Automation Science and Engineering
Publication date: Jul 2017, volume: 14, issue:3, pages: 1321 - 1336
Publisher: IEEE
 
» A Cavity-Backed Annular Slot Antenna With High Efficiency for Smartwatches With Metallic Housing
Abstract:
A cavity-backed annular slot antenna designed for the use in smartwatches in the 2.4-GHz Wi-Fi band is proposed. The cavity is metallic and has a cylindrical shape with a volume of mm3. An annular slot is cut along the edge of the top surface (as the smartwatch screen) of the cavity. The circumference of the annular slot is about , making the design small enough for the smartwatch applications. The resonant modes, current distribution, and transverse mode of the cavity-backed annular slot antenna are studied using simulations and the results are used to design a smartwatch antenna. The proposed smartwatch is studied in free space, on a computer hand model, and on a phantom hand using simulations and measurements. Measured results show that the antenna has an efficiency of 57%–66% on a phantom hand. To study the antenna in a more realistic environment, the electronic components inside the smartwatch are modeled as a metallic block. For health risk concerns related to exposure to an electromagnetic radiation, the specific absorption rate for the smartwatch in the wrist-worn and next-to-mouth conditions is also studied using simulations.
Autors: Di Wu;S. W. Cheung;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jul 2017, volume: 65, issue:7, pages: 3756 - 3761
Publisher: IEEE
 
» A Charge-Redistribution Phase-Domain ADC Using an IQ-Assisted Binary-Search Algorithm
Abstract:
Phase-domain Analog-to-Digital Converters (Ph-ADCs) have been considered for power-efficient implementa-tion of body-area network transceivers employing phase demodulation. Conventional implementations of the Ph-ADCs, which work based on a full-flash zero-crossing algorithm, use linear resistive/current combiners to determine the thermometer digital code of the signal phase. These architectures suffer from high-accuracy requirements, high-circuit complexity, and high-power consumption. Therefore, in this paper, a new IQ-assisted binary-search algorithm is proposed for implementing the Ph-ADC. The proposed Ph-ADC architecture avoids employing the power-hungry linear combiner. Moreover, for an -bit Ph-ADC, the proposed algorithm requires only comparisons, whereas the conventional full-flash counterpart demands comparisons. Based on the proposed architecture, two different 5-bit charge-redistribution Ph-ADC s are designed and one of them is fabricated in a standard 0.18- CMOS technology. The prototype achieves an ENOB of 4.85 bits at 1 MS/s, while dissipating from a 1.2-V supply.
Autors: Leila Rajabi;Mehdi Saberi;Yao Liu;Reza Lotfi;Wouter A. Serdijn;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jul 2017, volume: 64, issue:7, pages: 1696 - 1705
Publisher: IEEE
 
» A Circuit Particle-in-Cell Coupled Simulation of a Magnetically Insulated Transmission Line System
Abstract:
We have developed a circuit particle-in-cell (PIC) coupled model for simulating a pulsed power system, based on a circuit algorithm of a pulsed power supply and a PIC simulation for a magnetically insulated transmission line (MITL) system. The coupled algorithm comprises an external circuit algorithm based on BERTHA and a coupled algorithm for the PIC and circuit interface based on the Mur absorbing boundary condition. In this paper, a simple coaxial MITL with a single linear transformer driver (LTD) was simulated to validate the coupled model compared with PSPICE and BERTHA simulations. The numerical results show that the circuit–PIC coupled model achieved almost the same outputs on the load. The coupled model was then applied to an MITL system driven by ten LTD cavities. The simulation results and experimental results were in agreement, which confirms that the circuit–PIC coupled model could provide a reference for the structural design of experimental apparatuses.
Autors: Hongguang Wang;Min Peng;Wei Luo;Yong-Dong Li;Chun-Liang Liu;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Jul 2017, volume: 45, issue:7, pages: 1762 - 1768
Publisher: IEEE
 
» A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop
Abstract:
In this paper, a closed-form expression for estimating the minimum operating voltage () of D flip-flops (FFs) is proposed. is defined as the minimum supply voltage at which the FFs are functional without errors. The proposed expression indicates that of FFs is a linear function of the square root of logarithm of the number of FFs, and its slope depends on the within-die variation of the threshold voltage () and its intercept depends on the balance between nMOS and pMOS, which is mainly due to the die-to-die variation. The proposed expression of is validated by the simulation results as well as the silicon measurements. Finally, we discuss the dependence of on the device parameters.
Autors: Hiroshi Fuketa;Shin-ichi O’uchi;Takashi Matsukawa;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jul 2017, volume: 25, issue:7, pages: 2007 - 2016
Publisher: IEEE
 
» A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
Abstract:
A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25- bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage () and the zero-bias drain current () of the proposed n-JFET device can be modified by adjusting the P+ separation () in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of – and –.
Autors: Karuna Nidhi;Ming-Dou Ker;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jul 2017, volume: 64, issue:7, pages: 2812 - 2819
Publisher: IEEE
 
» A Coastline Detection Method in Polarimetric SAR Images Mixing the Region-Based and Edge-Based Active Contour Models
Abstract:
This paper proposes a coastline detection method for polarimetric synthetic aperture radar (SAR) images based on region-based and edge-based active contour models. It can be used to detect coastline accurately and fast. In this method, the region-based and edge-based active contour models are effectively combined by an important property of the likelihood ratio edge detector in polarimetric SAR images, which is proved by theory. Using low-resolution image obtained by multilook processing, we detect accurate and continued coarse coastlines by a region-based level set method. The property of the likelihood ratio edge detector of polarimetric SAR images along the coastline region is then analyzed. The coarse detection result is finally refined using a fast snake active contour model based on the edge property. Polarimetric SAR data acquired by RADARSAT-2 over a Singapore region and TerraSAR-X over a Berkeley region are both used to test the proposed algorithm. The experimental results show that the coastline is fast and accurately detected in different initial scales. The proposed method greatly reduces the data processing time compared with the coastline detection method based on a single scale.
Autors: Chun Liu;Yingying Xiao;Jian Yang;
Appeared in: IEEE Transactions on Geoscience and Remote Sensing
Publication date: Jul 2017, volume: 55, issue:7, pages: 3735 - 3747
Publisher: IEEE
 
» A Collision-Tolerant-Based Anti-Collision Algorithm for Large Scale RFID System
Abstract:
Tag identification is an important issue in an RFID system. Most existing anti-collision algorithms solely focus on reducing collision probability while suffering from vast idle slots. This letter proposes a collision-tolerant dynamic-framed slotted Aloha (CE-DFSA) algorithm, which attempts to identify multiple tags in a slot to reduce the total identification time in the process of identification. In CE-DFSA, tags are allocated with orthogonal Walsh sequence so that multiple tags can be identified in a time slot without spreading the spectrum. Simulation results show that the proposed algorithm considerably accelerates the tag identification process with improved efficiency compared with existing anti-collision algorithms.
Autors: Jian Su;Zhengguo Sheng;Liangbo Xie;
Appeared in: IEEE Communications Letters
Publication date: Jul 2017, volume: 21, issue:7, pages: 1517 - 1520
Publisher: IEEE
 
» A Collocated 3-D HIE-FDTD Scheme With PML
Abstract:
This letter proposes a novel hybrid implicit-explicit finite-difference time-domain method with collocation in the direction of implicitization. In this direction, the method features increased accuracy, the reason being twofold: 1) the applied combination of interpolations and differentiations preserves second-order accuracy upon nonuniform discretization and 2) material boundaries are more accurately approximated by the grid. The method’s stability and accuracy are verified by a microstrip line example. An appropriate PML is included.
Autors: A. Van Londersele;D. De Zutter;D. Vande Ginste;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jul 2017, volume: 27, issue:7, pages: 609 - 611
Publisher: IEEE
 
» A Combined Voxel and Particle Filter-Based Approach for Fast Obstacle Detection and Tracking in Automotive Applications
Abstract:
In this paper, a new method for real-time detection, motion estimation, and tracking of generic obstacles using just a 3-D point cloud and odometry information as input is presented. In this approach, a simplification of the world is done using voxels, supported by a particle filter-based 3-D object segmentation and a motion estimation scheme. That combination of techniques leverages a fast and reliable object detection, providing also motion speed and direction information. Four detailed studies have been performed in order to assess the suitability of the method, two of them related to the parameterization of the method and its input point cloud. Another one compares the tracking and detection results with other state-of-the-art methods. Last tests are intended for the characterization of the execution times required. Results are encouraging, with a high detection rate, low error rate, and real-time capable computing performance. In the attached video, it is possible to observe the behavior of the method, both using a stereovision and a light-detection and ranging generated point clouds as an input.
Autors: Néstor Morales;Jonay Toledo;Leopoldo Acosta;Javier Sánchez-Medina;
Appeared in: IEEE Transactions on Intelligent Transportation Systems
Publication date: Jul 2017, volume: 18, issue:7, pages: 1824 - 1834
Publisher: IEEE
 
» A Common Information Model Oriented Graph Database Framework for Power Systems
Abstract:
Common Information Model (CIM) is widely adopted by many utilities since it offers interoperability through standard information models. Storing, processing, retrieving, and providing concurrent access of the large power network models to the various power system applications in CIM framework are the current challenges faced by utility operators. As the power network models resemble largely connected-data sets, the design of CIM oriented database has to support high-speed data retrieval of the connected-data and efficient storage for processing. The graph database is gaining wide acceptance for storing and processing of largely connected-data for various applications. This paper presents a design of CIM oriented graph database (CIMGDB) for storing and processing the largely connected-data of power system applications. Three significant advantages of the CIMGDB are efficient data retrieval and storage, agility to adapt dynamic changes in CIM profile, and greater flexibility of modeling CIM unified modeling language (UML) in GDB. The CIMGDB does not need a predefined database schema. Therefore, the CIM semantics needs to be added to the artifacts of GDB for every instance of CIM objects storage. A CIM based object-graph mapping methodology is proposed to automate the process. An integration of CIMGDB and power system applications is discussed by an implementation architecture. The data-intensive network topology processing (NTP) is implemented, and demonstrated for six IEEE test networks and one practical 400 kV Maharashtra network. Results such as computation time of executing network topology processing evaluate the performance of the CIMGDB.
Autors: Gelli Ravikumar;Shrikrishna A. Khaparde;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jul 2017, volume: 32, issue:4, pages: 2560 - 2569
Publisher: IEEE
 
» A Compact 0.9-/2.6-GHz Dual-Band RF Energy Harvester Using SiP Technique
Abstract:
A compact dual-band radio frequency (RF) energy harvester (EH) composed of matching networks, bandpass and band-stop filters (BPF/BSF), and rectifiers, using a system-in-package technique is proposed in this letter. The matching networks and BPF/BSF are realized on a low-loss integrated-passive-device (IPD) carrier while the rectifiers are implemented in a 0.18- CMOS technology. The CMOS chip is flipped and bonded onto the IPD carrier through low-loss gold bumps. The proposed BPF/BSF can provide zeros and poles to pass and stop signals, respectively, allowing dual-band operation. Moreover, high-Q IPD passive components are employed to design the matching networks and the filters. This not only gives a compact solution but higher impedance transformation ratio between the source resistance and the rectifier input impedance also becomes feasible, which provides higher voltage gain to greatly enhance the RF-to-dc conversion efficiency. The proposed RF EH can give measured output voltage of 1.35 and 1 V with RF-to-dc conversion efficiency of 12.6% and 7% at 0.93 and 2.63 GHz, respectively, as the input power is −15.4 dBm and the load resistance is 500 . The EH only occupies an area of 11.6 mm2.
Autors: Chun-Hsing Li;Ming-Che Yu;Hsien-Jia Lin;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jul 2017, volume: 27, issue:7, pages: 666 - 668
Publisher: IEEE
 
» A Compact Balanced-to-Balanced Filtering Gysel Power Divider Using $\lambda _{g}$ /2 Resonators and Short-Stub-Loaded Resonator
Abstract:
In this letter, a compact balanced-to-balanced filtering power divider (FPD) is presented. It is composed of three half-wavelength resonators and a short-stub-loaded resonator (SSLR). Due to the intrinsic resonance characteristic of the half-wavelength resonator, the bandpass response and power dividing function for differential-mode signal are realized and the suppression for common-mode signal is also achieved. The SSLR is utilized as an extra isolation resonator to achieve high isolation between two output ports. A resister is also needed to load on the SSLR for adjusting its loaded quality factor . For the demonstration of the design method, an FPD operating at 2.405 GHz has been fabricated and measured. The measured results validate the design method.
Autors: Ming Luo;Xin Xu;Xiao-Hong Tang;Yong-Hong Zhang;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Jul 2017, volume: 27, issue:7, pages: 645 - 647
Publisher: IEEE
 
» A Compact Mach–Zehnder Interferometer Using Composite Plasmonic Waveguide for Ethanol Vapor Sensing
Abstract:
The finite element method (FEM) has attracted a considerable interest in the past few decades for the analysis of a wide range of dielectric waveguides. This method can handle isotropic and anisotropic material properties and arbitrary-shaped complex dielectric discontinuities more efficiently and accurately than any other methods. A modified H-field based full-vectorial finite element method is used for a rigorous analysis of a composite plasmonic waveguide as an efficient ethanol vapor sensor where a porous ZnO (P-ZnO) layer is used as low index material in between high index silicon and silver metal layer. Enhanced field confined into low index slot is utilized for ethanol vapor sensing which has many potential applications in chemical industries. It is reported here that a high waveguide sensitivity over 0.7 per RIU could be realized with our proposed design depending on the porosity of the ZnO layer. For accurate detection of refractometric changes, a compact Mach–Zehnder interferometer is designed where maximum phase sensitivities of 0.30, 0.34, 0.38, and 0.40 are shown to be achieved for 50% volume fraction of ethanol into porous ZnO layer with porosity, P = 30%, 40%, 50%, and 60%, respectively. The complete investigation has been carried out at the well-known telecommunication wavelength 1550 nm and with our in-house, accurate full-vectorial FEM code.
Autors: Souvik Ghosh;B. M. A. Rahman;
Appeared in: Journal of Lightwave Technology
Publication date: Jul 2017, volume: 35, issue:14, pages: 3003 - 3011
Publisher: IEEE
 
» A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers
Abstract:
This paper presents a low-power 9-bit compiled successive-approximation register (SAR) analog-to-digital converter (ADC) for Bluetooth low energy receivers. The ADC is compiled from a SPICE netlist, a technology rule file, and an object definition file into a design rule check and layout versus schematic clean layout and schematic in 28-nm FDSOI. The compiled SAR ADC reduces the design time necessary to port to a new technology, and to demonstrate technology porting the same SAR ADC architecture is compiled in 28-nm FDSOI with Input/Output (IO) transistors. This paper also includes a comparator clock generation loop that uses the bottom plate of the capacitive digital-to-analog converter. The proposed compiled core transistor SAR ADC achieves the state-of-the-art Figure of Merit (FoM) of 2.7 fJ/conv.step at 2 MS/s, and 3.5 fJ/conv.step at 20 MS/s with an area of 0.00312 mm2.
Autors: Carsten Wulff;Trond Ytterdal;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jul 2017, volume: 52, issue:7, pages: 1915 - 1926
Publisher: IEEE
 
» A Comprehensive Bottom-Tracking Method for Sidescan Sonar Image Influenced by Complicated Measuring Environment
Abstract:
The estimations of water column depth and the towfish altitude and the measurements of the target's location and shape all depend on the accuracy and reliability of bottom tracking of a sidescan sonar (SSS) waterfall image. Traditionally, the threshold method has often been adopted, but it is difficult to achieve an ideal bottom-tracking result due to contamination of the water column image in complicated measuring environments such as suspended solids and strong absorption sediments. Besides, it is also time consuming and easy to be influenced by operators' experience because the threshold values used need to be set segmentally. To track the bottom accurately and efficiently, first, this paper studies the threshold method, the last peak method, the assumption of seabed continuous variation, and the symmetry assumption. Then, a comprehensive bottom-tracking method is proposed. To validate the proposed method, an SSS experiment was conducted in the Bohai Sea of China. The bottom tracking for the SSS images was carried out automatically by the developed software. Comparing the port and starboard towfish altitudes tracked for all SSS images, the proposed method achieves 0.19 m of the standard deviation referenced to water depth at the points of measurement. Furthermore, taking the integration of the sounding data, the tidal level, and the towfish depth as reference, the proposed method obtains 0.17 m of the standard deviation. These parameters show that the proposed method has high accuracy in bottom tracking. Finally, this method is further discussed in the applications, and the results show that it has better performance than the traditional threshold method where the SSS waterfall image is influenced under complicated measurement environment. A shortcoming induced by the SSS - maging mechanism is also found that this method may be invalid when high seabed targets lie at two sides of towfish nadir, which can be solved by increasing the towfish altitude.
Autors: Jianhu Zhao;Xiao Wang;Hongmei Zhang;Aixue Wang;
Appeared in: IEEE Journal of Oceanic Engineering
Publication date: Jul 2017, volume: 42, issue:3, pages: 619 - 631
Publisher: IEEE
 
» A Comprehensive Methodology to Assess Tropospheric Fade Affecting Earth–Space Communication Systems
Abstract:
ATMospheric simulator for PROPagation applications (ATM PROP), a comprehensive methodology to assess tropospheric effects affecting high-frequency earth–space communication systems, is presented. The model takes advantage of physically based approaches aimed at synthesizing high-resolution (1 km km horizontal, 100-m vertical) 3-D fields of rain, clouds, and water vapor (dimension: 200 km km horizontal, 20-km vertical), which are all merged so as to maintain their mutual correlation. This, in turn, enables a more realistic combination of the attenuation due to single constituents, if compared to the statistical approach currently recommended by the ITU-R. The accuracy of ATM PROP in predicting tropospheric effects on earth–space systems is initially validated against the large propagation data set collected at the experimental station of Spino d’Adda, Italy, during the ITALSAT propagation campaign. The preliminary results obtained suggest that ATM PROP can be used to predict, with a reasonable level of complexity and limited coarse-resolution Numerical Weather Prediction-derived inputs, the tropospheric fade affecting complex communication systems (e.g., site diversity schemes), especially those involving low elevation links (e.g., low earth orbit or geostationary orbit at high latitude), for which the spatial distribution of the relevant tropospheric constituents needs to be taken in due account.
Autors: Lorenzo Luini;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jul 2017, volume: 65, issue:7, pages: 3654 - 3663
Publisher: IEEE
 
» A Convex Approach to Near-Optimal Beamforming Designs for Two-User MISO Fading Interference Channels
Abstract:
Based on a convex approach with side-information, we propose transmit beamforming designs for two-user multiple-input single-output fading interference channels. Main contribution of this paper is to provide a novel methodology for solving a non-convex optimization problem efficiently based on the effective side-information. Consequently, the proposed scheme exhibits near-optimal average sum-rate performance under single user detection with Gaussian inputs, which is validated through numerical results. As a by-product, we show that the proposed scheme requires almost no parameter optimization on the average over multiple coding blocks.
Autors: Sang Won Choi;Juyeop Kim;
Appeared in: IEEE Transactions on Communications
Publication date: Jul 2017, volume: 65, issue:7, pages: 3110 - 3122
Publisher: IEEE
 
» A Correction Method for DVL Measurement Errors by Attitude Dynamics
Abstract:
Due to the random wave motions as well as the vehicle’s movement pattern changes, the attitude dynamics (including heading, pitch, and roll motions) of the vehicle induced degrades the accuracy of doppler velocity log (DVL), which is a key element in deciding the precision of strapdown inertial navigation system (SINS)/DVL integrated navigation system. In this paper, the effects of heading, pitch and roll dynamics are first analyzed separately. Then, the general error model for DVL measurement errors caused by attitude dynamics is established. In the modeling process, the changes of angular position and angular rate between the DVL signal transmission and reception instant are considered. Subsequently, by utilizing the established error model, a correction method based on the real-time attitude information from SINS/DVL system is presented. Finally, the performance of the proposed method is examined through numerical simulations in which typical scenarios with a series of attitude dynamics are used. Simulation results show that the errors can be effectively corrected by using the correction method. This contributes to an improved positioning accuracy of SINS/DVL navigation.
Autors: Peijia Liu;Bo Wang;Zhihong Deng;Mengyin Fu;
Appeared in: IEEE Sensors Journal
Publication date: Jul 2017, volume: 17, issue:14, pages: 4628 - 4638
Publisher: IEEE
 
» A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs
Abstract:
Regular and redundant through-silicon via (TSV) interconnects are used in fault tolerance techniques of 3-D IC. However, the fabrication process of TSVs results in defects that reduce the yield and reliability of TSVs. On the other hand, each TSV is associated with a significant amount of on-chip area overhead. Therefore, unlike the state-of-the-art fault tolerance architectures, here we propose the time division multiplexing access (TDMA)-based fault tolerance technique without using any redundant TSVs, which reduces the area overhead and enhances the yield. In the proposed technique, by means of TDMA, we reroute the signal through defect-free TSV. Subsequently, an architecture based on the proposed technique has been designed, evaluated, and validated on logic-on-logic 3-D IWLS’05 benchmark circuits using 130-nm technology node. The proposed technique is found to reduce the area overhead by 28.70%-40.60%, compared to the state-of-the-art architectures and results in a yield of 98.9%–99.8%.
Autors: Raviteja P. Reddy;Amit Acharyya;Saqib Khursheed;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Jul 2017, volume: 25, issue:7, pages: 2071 - 2080
Publisher: IEEE
 
» A Dataset and a Technique for Generalized Nuclear Segmentation for Computational Pathology
Abstract:
Nuclear segmentation in digital microscopic tissue images can enable extraction of high-quality features for nuclear morphometrics and other analysis in computational pathology. Conventional image processing techniques, such as Otsu thresholding and watershed segmentation, do not work effectively on challenging cases, such as chromatin-sparse and crowded nuclei. In contrast, machine learning-based segmentation can generalize across various nuclear appearances. However, training machine learning algorithms requires data sets of images, in which a vast number of nuclei have been annotated. Publicly accessible and annotated data sets, along with widely agreed upon metrics to compare techniques, have catalyzed tremendous innovation and progress on other image classification problems, particularly in object recognition. Inspired by their success, we introduce a large publicly accessible data set of hematoxylin and eosin (H&E)-stained tissue images with more than 21000 painstakingly annotated nuclear boundaries, whose quality was validated by a medical doctor. Because our data set is taken from multiple hospitals and includes a diversity of nuclear appearances from several patients, disease states, and organs, techniques trained on it are likely to generalize well and work right out-of-the-box on other H&E-stained images. We also propose a new metric to evaluate nuclear segmentation results that penalizes object- and pixel-level errors in a unified manner, unlike previous metrics that penalize only one type of error. We also propose a segmentation technique based on deep learning that lays a special emphasis on identifying the nuclear boundaries, including those between the touching or overlapping nuclei, and works well on a diverse set of test images.
Autors: Neeraj Kumar;Ruchika Verma;Sanuj Sharma;Surabhi Bhargava;Abhishek Vahadane;Amit Sethi;
Appeared in: IEEE Transactions on Medical Imaging
Publication date: Jul 2017, volume: 36, issue:7, pages: 1550 - 1560
Publisher: IEEE
 
» A Decentralized Dynamic Power Sharing Strategy for Hybrid Energy Storage System in Autonomous DC Microgrid
Abstract:
Power allocation is a major concern in hybrid energy storage system. This paper proposes an extended droop control (EDC) strategy to achieve dynamic current sharing autonomously during sudden load change and resource variations. The proposed method consists of a virtual resistance droop controller and a virtual capacitance droop controller for energy storages with complementary characteristics, such as battery and supercapacitor (SC). By using this method, battery provides consistent power and SC only compensates high-frequency fluctuations without the involvement of conventionally used centralized controllers. To implement the proposed EDC method, a detailed design procedure is proposed to achieve the control objectives of stable operation, voltage regulation, and dynamic current sharing. System dynamic model and relevant impedances are derived and detailed frequency domain analysis is performed. Moreover, the system level stability analysis is investigated and system expansion with the proposed method is illustrated. Both simulations and experiments are conducted to validate the effectiveness of the proposed control strategy and analytical results.
Autors: Qianwen Xu;Xiaolei Hu;Peng Wang;Jianfang Xiao;Pengfei Tu;Changyun Wen;Meng Yeong Lee;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jul 2017, volume: 64, issue:7, pages: 5930 - 5941
Publisher: IEEE
 
» A Deep Denoising Autoencoder Approach to Improving the Intelligibility of Vocoded Speech in Cochlear Implant Simulation
Abstract:
Objective: In a cochlear implant (CI) speech processor, noise reduction (NR) is a critical component for enabling CI users to attain improved speech perception under noisy conditions. Identifying an effective NR approach has long been a key topic in CI research. Method: Recently, a deep denoising autoencoder (DDAE) based NR approach was proposed and shown to be effective in restoring clean speech from noisy observations. It was also shown that DDAE could provide better performance than several existing NR methods in standardized objective evaluations. Following this success with normal speech, this paper further investigated the performance of DDAE-based NR to improve the intelligibility of envelope-based vocoded speech, which simulates speech signal processing in existing CI devices. Results: We compared the performance of speech intelligibility between DDAE-based NR and conventional single-microphone NR approaches using the noise vocoder simulation. The results of both objective evaluations and listening test showed that, under the conditions of nonstationary noise distortion, DDAE-based NR yielded higher intelligibility scores than conventional NR approaches. Conclusion and significance: This study confirmed that DDAE-based NR could potentially be integrated into a CI processor to provide more benefits to CI users under noisy conditions.
Autors: Ying-Hui Lai;Fei Chen;Syu-Siang Wang;Xugang Lu;Yu Tsao;Chin-Hui Lee;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Jul 2017, volume: 64, issue:7, pages: 1568 - 1578
Publisher: IEEE
 
» A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring
Abstract:
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of optimization techniques, seeking the best tradeoff to reach the maximum energy efficiency. Effective adaptation strategies depend critically on the monitoring method as an incorrect assessment of the system’s state will result in poor decision making. Yet it is indeed a fundamental issue: how to get a precise estimation of the system’s state, and especially in a cost-effective way? We address this question for the self-observation of the power consumption. We develop a method that combines several data mining algorithms to monitor the toggling activity on a few relevant signals selected at the register transfer-level. Our approach is based on a generic flow that is able to produce a power model for any register transfer level (RTL) circuit on any technology. This contribution is evaluated on a system on chip RTL model implemented on an field-programmable gate array technology. The experiments demonstrate that the proposed method achieves the accuracy of analog power sensors (error lower than 1%) at a finer granularity and in a cost-effective way.
Autors: Mohamad Najem;Pascal Benoit;Mohamad El Ahmad;Gilles Sassatelli;Lionel Torres;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Jul 2017, volume: 36, issue:7, pages: 1153 - 1166
Publisher: IEEE
 
» A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs
Abstract:
Ultra-low voltage operation is key to achieving energy-efficient operation for microcontroller (MCU) systems. Variation resiliency, high speed operation, and short design time are the most important challenges for these systems. This paper overcomes these challenges in a new design strategy that enables standard cell design with differential transmission gate logic. The commercial toolchain is extended with in-house developed add-ons and makes use of two custom libraries with different device lengths to allow high speed vs. low leakage trade-offs. The design flow is used to prototype two highly efficient 32-bit ARM Cortex-M0 MCU systems in 40-nm CMOS. The core of the first prototype scales down to 190 mV and 0.8-MHz and reaches 16.07 pJ/cycle at 31.2-MHz and 440 mV. The second prototype benefits from the dual libraries and reduces core energy consumption by 50% at the same speed performance. Minimum energy operation is thus achieved at an even lower voltage (370 mV) with the M0 core consuming only 8.80 pJ/cycle at 13.7-MHz, breaking the sub-10-pJ/cycle barrier for a 6–35-MHz range.
Autors: Hans Reyserhove;Wim Dehaene;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Jul 2017, volume: 52, issue:7, pages: 1904 - 1914
Publisher: IEEE
 
» A Discontinuous Current-Source Gate Driver With Gate Voltage Boosting Capability
Abstract:
In this paper, a novel discontinuous current-source driver (CSD) is proposed, in which the power MOSFET gate-source voltage is increased to more than the drive supply voltage. The proposed CSD is able to recover gate energy dissipated in a conventional driver. In comparison to the conventional gate driver, the proposed CSD achieves fast switching speed to reduce switching losses. A wide range of operating duty cycle, low circulating losses, and high Cdv/dt immunity are other features of the proposed CSD. In comparison to previous discontinuous CSDs, the special advantage of the proposed circuit is power MOSFET gate voltage boosting, which leads to reduction of Rds(on) and, thus, the conduction loss. The proposed circuit is appropriate for voltage regulators (VRs) with synchronous rectifier and also it is suitable for two-stage 48-V power pod applications and low-voltage converters. Two-stage VR for laptop computer CPUs is another application of this gate driver circuit to improve light load performance. A prototype of the circuit operating at 1 MHz is implemented, and the experimental waveforms justify the theoretical analysis.
Autors: Iman Abdali Mashhadi;Ramin Rahimzadeh Khorasani;Ehsan Adib;Hosein Farzanehfard;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jul 2017, volume: 64, issue:7, pages: 5333 - 5341
Publisher: IEEE
 
» A Discontinuous Galerkin Augmented Electric Field Integral Equation for Multiscale Electromagnetic Scattering Problems
Abstract:
A discontinuous Galerkin (DG) augmented electric field integral equation method based on the domain decomposition is proposed in this paper for full-wave solution of multiscale targets. The conventional surface integral equation-based DG method allowing both conformal and nonconformal discretizations for multiscale structures suffers from low-frequency breakdown. By augmenting the DG-EFIE with current continuity equation, the proposed scheme can alleviate the low-frequency breakdown. In the augmented system, the electric field integral equation and the current continuity equation are discretized by using hybrid basis functions including Rao–Wilton–Glisson (RWG) and half RWG basis functions. Since the half RWG basis is not divergence conforming, line charge degrees of freedom on the adjoining edges are introduced in this paper. It is observed that the resulting linear system is well conditioned at low frequencies, which leads to a rapid convergence over wide frequency band. Numerical examples demonstrate the accuracy and efficiency of the augmented system.
Autors: Yibei Hou;Gaobiao Xiao;Xuezhe Tian;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jul 2017, volume: 65, issue:7, pages: 3615 - 3622
Publisher: IEEE
 
» A Distortion Outer Bound for Communicating Correlated Gaussian Sources Over a Gaussian MAC
Abstract:
In this letter, we consider two problems of sending a bivariate Gaussian source through a two-user Gaussian non-orthogonal multiple-access channel. We provide a new distortion outer bound for the considered joint source-channel coding problems, which significantly reduces the gap between inner and outer bounds of the distortion for correlation coefficients below a threshold. Furthermore, numerical results show, that under some conditions, our proposed outer bound matches with the inner bound obtained via the separate source-channel coding scheme, which proves the optimality of this scheme.
Autors: Mehdi Setayesh;Hamid Behroozi;Babak H. Khalaj;
Appeared in: IEEE Communications Letters
Publication date: Jul 2017, volume: 21, issue:7, pages: 1457 - 1460
Publisher: IEEE
 
» A Family of True Zero Voltage Zero Current Switching (ZVZCS) Nonisolated Bidirectional DC–DC Converter With Wide Soft Switching Range
Abstract:
This paper proposes a true zero voltage zero current switching (ZVZCS) nonisolated bidirectional dc–dc converter with reduced component count. An auxiliary resonant network—which comprises of an inductor, capacitor, diode, and two switches—provides the zero voltage switching transitions of the main switches at turn on and turn off instants. In addition, a pair of auxiliary inductors, which act as inductive snubbers, aids the zero current switching transitions. The proposed configuration is able to provide soft commutation for the main switches for a wide range of input voltage, switching frequency, and load current variations—thus significantly improving the efficiency profile over a wide operating window. Besides, the auxiliary switches are also soft commutated, while the reverse recovery loss induced by the high side diode is eliminated. The ZVZCS soft switching operation is demonstrated by a 150 W prototype converter; it is proven consistent with the waveforms derived from the theoretical analysis. Its performance is evaluated against the standard hard-switched boost, buck, and several other leading soft switching converters published in the recent literature. The maximum full load efficiency at 100 kHz is recorded at 98.2% and 97.5% in the boost and buck modes, respectively.
Autors: Ratil H. Ashique;Zainal Salam;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jul 2017, volume: 64, issue:7, pages: 5416 - 5427
Publisher: IEEE
 
» A Fast Calibration Method for Magnetometer Array and the Application of Ferromagnetic Target Localization
Abstract:
The vector magnetometer array is commonly used in ferromagnetic target detection and localization. Due to technological limitations, the accuracy of measurements is restricted by magnetometer errors, misalignment errors between magnetometers and the interference of soft iron and hard iron. In order to correct the measurement errors, a calibration method with less computation time is proposed. A magnetometer array is designed for ferromagnetic target detection and localization, which is calibrated by the proposed method. The results of our empirical evaluations confirm that the proposed method outperforms conventional calibration method both in terms of computation cost and accuracy. Different test specimens are used to test the detection range and the localization accuracy of the system. The array system compensated by the proposed method has a larger detection range.
Autors: Chen Wang;Xiaodong Qu;Xiaojuan Zhang;Wanhua Zhu;Guangyou Fang;
Appeared in: IEEE Transactions on Instrumentation and Measurement
Publication date: Jul 2017, volume: 66, issue:7, pages: 1743 - 1750
Publisher: IEEE
 
» A Fault-Injection Strategy for Traction Drive Control Systems
Abstract:
A traction drive control system (TDCS) plays an important role in safety running of high-speed trains. This paper presents a new fault-injection strategy for safety testing and fault diagnosis verification in the TDCS. First, the fault scenarios on the signal level of each faulty component are analyzed. Then, the fault-injection method based on signal conditioning is proposed, and the injected signal, reflecting the fault scenario at a fault point, is generated to simulate the fault scenarios. Subsequently, the injected signal benchmark is constructed for all faults in traction converters, traction motors, sensors, and traction control units. Finally, a fault-injection benchmark platform is developed to simulate various fault scenarios in the TDCS. The simulation and comparison results show that the presented strategy is effective and easy to implement.
Autors: Chunhua Yang;Chao Yang;Tao Peng;Xiaoyue Yang;Weihua Gui;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jul 2017, volume: 64, issue:7, pages: 5719 - 5727
Publisher: IEEE
 
» A Finite-Element-Based Fast Frequency Sweep Framework Including Excitation by Frequency-Dependent Waveguide Mode Patterns
Abstract:
This paper presents a frequency-sweep technique based on model-order reduction and finite elements, for the broadband analysis of structures fed by waveguides (WGs) possessing frequency-dependent modal field patterns. Standard order reduction requires the matrices and right-hand sides (RHSs) to exhibit affine frequency parameterization. This precondition is violated when the transverse fields of the WG modes vary with frequency. The proposed solution involves two steps. First, a reduced-order model (ROM) for the WG is constructed. It enables the accurate yet inexpensive computation of propagation characteristics. Second, order reduction is applied to the driven problem, wherein the reduced WG model is utilized to construct affine approximations to the matrices and RHSs. Since this process requires operations on reduced-order matrices only, it is computationally cheap and enables offline/online decomposition. Both impedance and scattering formulations are considered. For the latter, an alternative to the transfinite element method is proposed, which does not employ modal field patterns as shape functions. It avoids interior resonances and computes scattering parameters more efficiently when only a limited set of excitations is of interest. The resulting algebraic system is of somewhat larger dimension but easier to assemble. Its simple structure greatly facilitates the construction of the ROM.
Autors: Rolf Baltes;Alwin Schultschik;Ortwin Farle;Romanus Dyczij-Edlinger;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jul 2017, volume: 65, issue:7, pages: 2249 - 2260
Publisher: IEEE
 
» A Flexure-Based Parallel Actuation Dual-Stage System for Large-Stroke Nanopositioning
Abstract:
This paper presents a novel parallel actuation dual-stage system that delivers nanometric positioning over a large displacement. Unlike those traditional dual-stage designs, the translator of fine actuator in the proposed design is mechanically connected to the coarse translator via the flexure mechanism, while the actuation coils of both the coarse and fine actuators lay underneath the translators in parallel. The merits of the proposed parallel actuation dual-stage design are mainly twofold. First, both the coarse and fine actuators utilize the moving-magnet configuration, hence the translators do not need to carry any cables for power supply. Second, the coarse motion can exhibit better dynamics and energy efficiency due to the minimized moving size and weight. In this work, an analytical current–force model is established for the coarse actuator considering higher order harmonic magnetic field, and based on the proposed model, the force ripple of coarse actuator is quantitatively analyzed both in theory and in practical. Furthermore, a disturbance observer is employed in the dual-feedback configuration to deal with the uncertainties with the proved asymptotic stability. The experimental results show that the proposed dual-stage positioning system is capable to achieve 20 nm step resolution with a root mean square error of 13.15 nm, and the 5 mm point-to-point positioning error can achieve less than 40 nm.
Autors: Haiyue Zhu;Chee Khiang Pang;Tat Joo Teo;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jul 2017, volume: 64, issue:7, pages: 5553 - 5563
Publisher: IEEE
 
» A Fluidic-Based High-Pressure Sensor Interrogated by Microwave Fabry–Perot Interferometry
Abstract:
A fluidic-based sensor is proposed and demonstrated for high-pressure measurement. The sensor consists of a reservoir and a capillary outlet. The reservoir deforms under pressure manifesting the liquid level change in the capillary. Utilizing the built-in waveguide on the capillary, the liquid level is measured by microwave Fabry–Perot interferometry in the spectral domain. The applied pressure variation is monitored by the spectrum shift of the microwave interferogram. The pressure response of the sensor is tested up to 2000 psi, with a resolution of 2.5 psi, and repeatability within ±20 psi. Benefiting from rigidity in material and flexibility in dimension of the sensor structure, the sensor has good robustness and adjustable sensitivity and range for applications in high-pressure environments.
Autors: Wenge Zhu;Baokai Cheng;Yurong Li;Runar Nygaard;Hai Xiao;
Appeared in: IEEE Sensors Journal
Publication date: Jul 2017, volume: 17, issue:14, pages: 4388 - 4393
Publisher: IEEE
 
» A Frequency-Reconfigurable Dual-Band Low-Profile Monopolar Antenna
Abstract:
A concept of a low-profile monopolar antenna operating in two independently reconfigurable frequency bands is introduced in this paper. For the lower band, the design utilizes a center-fed patch with shorting rods at its edges, forcing the patch to radiate as an equivalent magnetic-current loop. For the upper band, another magnetic current loop is created by adding four symmetrical resonant slots on the patch, which radiates almost independently of the shorted patch. To allow coverage of a larger bandwidth, two sets of varactor diodes are used to independently control the resonance frequencies of the two bands. As a validation of the proposed concept, two antenna prototypes, with and without reconfigurabilities, have been optimized and fabricated. Measurement results show that the low-profile reconfigurable monopolar antenna achieves two independent tunable bands, with −10-dB-tuning ranges of 31% and 22% centered at about 0.9 and 1.7 GHz, respectively. The antenna height is only , where is the free-space wavelength at the minimum operating frequency. Importantly, stable omnidirectional patterns and vertical polarization are consistently achieved across both tuning ranges.
Autors: Nghia Nguyen-Trong;Andrew Piotrowski;Christophe Fumeaux;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Jul 2017, volume: 65, issue:7, pages: 3336 - 3343
Publisher: IEEE
 
» A Fully Integrated Broadband Sub-mmWave Chip-to-Chip Interconnect
Abstract:
A new type of broadband link enabling extremely high-speed chip-to-chip communication is presented. The link is composed of fully integrated sub-mmWave on-chip traveling wave power couplers and a low-cost planar dielectric waveguide. This structure is based on a differentially driven half-mode substrate integrated waveguide supporting the first higher order hybrid microstrip mode. The cross-sectional width of the coupler structure is tapered in the direction of wave propagation to increase the coupling efficiency and maintain a large coupling bandwidth while minimizing its on-die size. A rectangular dielectric waveguide, constructed from Rogers Corporation R3006 material, is codesigned with the on-chip coupler structure to minimize coupling loss. The coupling structure achieves an average insertion loss of 4.8 dB from 220 to 270 GHz, with end-to-end link measurements presented. This system provides a packaging-friendly, cost effective, and high performance planar integration solution for ultrabroadband chip-to-chip communication utilizing millimeter waves.
Autors: Jack W. Holloway;Luciano Boglione;Timothy M. Hancock;Ruonan Han;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Jul 2017, volume: 65, issue:7, pages: 2373 - 2386
Publisher: IEEE
 
» A Fully Integrated Multistage Cross-Coupled Voltage Multiplier With No Reversion Power Loss in a Standard CMOS Process
Abstract:
This brief presents a fully integrated cross-coupled voltage multiplier for boosting dc-to-dc converter applications. The proposed design applies a new structure of cross-coupled voltage doubler (CCVD) and a clock scheme that eliminates all of the reversion power loss and increases the power efficiency (PE). In addition, this design is scalable to multiple-stage voltage doubler (voltage multiplier) as the maximum gate-to-source/drain or drain-to-source voltage does not exceed the nominal power supply . As a result, such a design is compatible with the standard CMOS process without any overstress voltage. The proposed single-stage CCVD and three-stage cross-coupled voltage multiplier are implemented in 0.13- IBM CMOS process with maximum PE values of 88.16% and 80.2%, respectively. The maximum voltage conversion efficiency reaches 99.8% under the supply voltage of 1.2 V.
Autors: Xiaojian Yu;Kambiz Moez;I-Chyn Wey;Mohamad Sawan;Jie Chen;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Jul 2017, volume: 64, issue:7, pages: 737 - 741
Publisher: IEEE
 
» A Fully Integrated Silicon-Carbide Sigma–Delta Modulator Operating up to 500 °C
Abstract:
This paper presents the first fully integrated sigma–delta modulator implemented in an in-house silicon carbide (SiC) bipolar technology for high-temperature applications. A second-order 1-b continuous-time architecture is adopted. Dual-loop compensation technique is employed to accommodate one clock period comparator delay. The circuits are designed to have enough margins without degrading the modulator’s performance, considering the variation of device parameters over a large temperature range. The measurement results show that from room temperature to 500 °C, the modulator’s peak SNDR is constant around 30 dB at a clock speed of 512 kHz. The chip area of the modulator is mm with one metal layer. It consumes around 1 W from a 15 V power supply. This paper demonstrates the feasibility to further develop highly integrated SiC bipolar junction transistor integrated circuits for extremely high-temperature sensing applications.
Autors: Ye Tian;Carl-Mikael Zetterling;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Jul 2017, volume: 64, issue:7, pages: 2782 - 2788
Publisher: IEEE
 
» A General Framework for Predictors Based on Bounding Techniques and Local Approximation
Abstract:
This paper introduces a general framework for prediction based on nonparametric local estimation and bounding techniques. A set of historic input-output measurements of the system is stored in a database. When a prediction for a given point is required, data from the neighborhood of this point is retrieved and a prediction is formed. These prediction methods return an interval that bounds the considered system output. The width of the obtained interval prediction reflects the amount of information about the system available at the point to be predicted. In addiction, the midpoint of the interval prediction can be used as central estimate. The contribution of the paper is threefold. First, a general framework that covers previous methods proposed in the literature is presented. Second, the general properties of the framework are analyzed. Third, new predictors based on this framework are proposed. Finally, a benchmark example and a comparative study are provided for illustration purposes.
Autors: J. M. Bravo;T. Alamo;M. Vasallo;M. E. Gegúndez;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Jul 2017, volume: 62, issue:7, pages: 3430 - 3435
Publisher: IEEE
 
» A General Structure of Linear-Phase FIR Filters With Derivative Constraints
Abstract:
In this paper, a general structure of linear-phase finite impulse response filters, whose frequency responses satisfy given derivative constraints imposed upon an arbitrary frequency, is proposed. It is comprised of a linear combination of parallelly connected subfilters, called the cardinal filters, with weighted coefficients being the successive derivatives of the desired frequency response at the constrained frequency. An advantage of such a cardinal filters design is that only the weighted coefficients are relevant to the desired frequency response but not the cardinal filters; hence, a dynamic adjustment of the filter system becomes feasible. The key to derive the coefficients of cardinal filters is the determination of the power series expansion of certain trigonometric-related functions. By showing the elaborately chosen trigonometric-related functions satisfy specific differential equations, recursive formulas for the coefficients of cardinal filters are subsequently established, which make efficient their computations. At last, a simple enhancement of the cardinal filters design by incorporating the mean square error minimization is presented through examples.
Autors: Bo-You Yu;Peng-Hua Wang;Po-Ning Chen;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Jul 2017, volume: 64, issue:7, pages: 1839 - 1852
Publisher: IEEE
 
» A General Unified AC/DC Power Flow Algorithm With MTDC
Abstract:
The aim of this paper is to derive a general AC/DC power flow model with Voltage Source Converter Multi-Terminal High-Voltage Direct Current Systems (VSC MTDCs). The equations of AC, DC grids, and VSCs are formulated in augmented rectangular coordinates. The proposed model is composed of two nodal equations and two power constraints for each AC bus, as well as one nodal equation and one power constraint for each DC bus. In this model, the VSC equations are included in the AC and DC grid model—its power balance equation and one of the control equations are regarded as the power constraints of the AC bus connected to it, whereas the other control equation is regarded as the power constraint of the DC bus connected to it. Therefore, the number of equations of the proposed model is determined only by that of AC and DC buses, and the model is systematically well organized; the variety of VSC control strategies and AC/DC linking configurations does not influence the overall structure. The proposed approach enables to solve the load flow of the most general AC/MTDC, consisting of multiple AC and DC grids connected by VSCs, and is suitable for control strategies including the droop control and any new ones in the future. The model also leads to higher computational efficiency. By demonstrations on AC/DC power systems with several VSCs, this method is proved to be effective, flexible, and efficient.
Autors: Jingting Lei;Ting An;Zhengchun Du;Zheng Yuan;
Appeared in: IEEE Transactions on Power Systems
Publication date: Jul 2017, volume: 32, issue:4, pages: 2837 - 2846
Publisher: IEEE
 
» A Geographical Proximity Aware Multi-Path Routing Mechanism for Resilient Networking
Abstract:
Geographical correlated failures are threats that cause major interruptions and damage to networking systems. To mitigate this rarely addressed challenge, this letter presents a novel geographical location-aware route selection algorithm to support uninterrupted networking. The multi-path routing method developed calculates multiple paths that satisfy different constraints, while ensuring the prescribed geographical distance metric between selected paths. It is used with existing overlay routing mechanisms to maintain routes. In the evaluation against enhanced -shortest path algorithms, the new algorithm is shown to provide multi-paths with larger spatial separation and better potential to uninterrupted networking in geographical correlated failures.
Autors: Jinfu Wang;John Bigham;Chris Phillips;
Appeared in: IEEE Communications Letters
Publication date: Jul 2017, volume: 21, issue:7, pages: 1533 - 1536
Publisher: IEEE
 
» A Global Closed-Form Refinement for Consistent TLS Data Registration
Abstract:
Existing global registration methods are prominently iterative. They require iterations and can be sensitive to point densities and noise. In contrast, closed-form solutions provide a more robust estimation model and do not involve iterations. In this letter, we present a global closed-form refinement for the terrestrial laser scanner (TLS) data registration problem. Our proposed method segments the task in three key steps. First, the method exploits a plane-based approach to compute the transformation parameters, resulting in the pairwise registration between point clouds. Second, we place all rotation parameters into a common coordinate system exploring one operation of the quaternions’ properties. Third, we constrain the refined rotation parameters to globally refine the translation. The effectiveness of the proposed method is demonstrated with a TLS data set. Experiments have demonstrated that the proposed method can properly create a consistent 3-D map of outdoor environments with accuracy at the decimeter level.
Autors: Nadisson Luis Pavan;Daniel Rodrigues dos Santos;
Appeared in: IEEE Geoscience and Remote Sensing Letters
Publication date: Jul 2017, volume: 14, issue:7, pages: 1131 - 1135
Publisher: IEEE
 
» A Hierarchical Spatio-Temporal Model for Human Activity Recognition
Abstract:
There are two key issues in human activity recognition: spatial dependencies and temporal dependencies. Most recent methods focus on only one of them, and thus do not have sufficient descriptive power to recognize complex activity. In this paper, we propose a hierarchical spatio-temporal model (HSTM) to solve the problem by modeling spatial and temporal constraints simultaneously. The new HSTM is a two-layer hidden conditional random field (HCRF), where the bottom-layer HCRF aims at describing spatial relations in each frame and learning more discriminative representations, and the top-layer HCRF utilizes these high-level features to characterize temporal relations in the whole video sequence. The new HSTM takes advantage of the bottom layer as the building blocks for the top layer and it aggregates evidence from local to global level. A novel learning algorithm is derived to train all model parameters efficiently and its effectiveness is validated theoretically. Experimental results show that the HSTM can successfully classify human activities with higher accuracies on single-person actions (UCF) than other existing methods. More importantly, the HSTM also achieves superior performance on more practical interactions, including human–human interactional activities (UT-Interaction, BIT-Interaction, and CASIA) and human–object interactional activities (Gupta video dataset).
Autors: Wanru Xu;Zhenjiang Miao;Xiao-Ping Zhang;Yi Tian;
Appeared in: IEEE Transactions on Multimedia
Publication date: Jul 2017, volume: 19, issue:7, pages: 1494 - 1509
Publisher: IEEE
 
» A High-Efficiency Magnetically Insulated Transmission Line Oscillator
Abstract:
A novel magnetically insulated transmission line oscillator (MILO) with high efficiency has been proposed, based on a kind of conventional MILO. The new MILO has two typical characteristics. First, the width of the anode vanes decreases gradually, and especially, the extraction vane decreases to be the minimal. Therefore, the proportion of the electrons, which have little or no contribution to the beam–wave interaction, is decreased. As a result, the efficiency is enhanced. In addition, there is an extra extraction cavity designed behind the extraction vane. So the beam–wave interaction process is lengthened, and the extraction efficiency is enhanced. The results of the particle-in-cell simulation show that the power efficiency of this MILO can be elevated to be 20.5%, while it is only 14.4% for the conventional MILO.
Autors: Daibing Chen;Jie Wen;Zhangjie Luo;Aiming Yu;Yong Zhang;
Appeared in: IEEE Transactions on Plasma Science
Publication date: Jul 2017, volume: 45, issue:7, pages: 1723 - 1725
Publisher: IEEE
 
» A High-Efficiency Quasi-Two-Stage LED Driver With Multichannel Outputs
Abstract:
In this paper, a new active current balancing method for a light-emitting diode (LED) driver with multichannel outputs is proposed. In the proposed structure, a low-power nonisolated dc–dc converter in series with each LED string is used to regulate the LED string current. Different from conventional active current balancing methods, in the proposed method, the nonisolated dc–dc converters only process a small portion of the total output power. Thus, the cost and size can be greatly reduced. An adaptive bus voltage control method is also proposed to minimize the output power of the nonisolated dc–dc converters. The proposed method features good modularity, expandability, and individual current control capability. Performance of the proposed method is validated by the experimental results from an 80-W prototype with four channel outputs.
Autors: Junming Zhang;Ting Jiang;Xinke Wu;
Appeared in: IEEE Transactions on Industrial Electronics
Publication date: Jul 2017, volume: 64, issue:7, pages: 5875 - 5882
Publisher: IEEE
 

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