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Details, datasheet, quote on part number:HM62W4100HJP
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Datasheet text preview:
HM62W4100HC Series
4M High Speed SRAM (1-Mword × 4-bit)
ADE-203-1202C (Z) Rev. 2.0 Nov. 9, 2001 Description
The HM62W4100HC is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM62W4100HC is packaged in 400-mil 32-pin SOJ for high density surface mounting.
Features
· Single supply : 3.3 V ± 0.3 V · Access time : 10/12 ns (max) · Completely static memory No clock or timing strobe required · Equal access and cycle times · Directly TTL compatible All inputs and outputs · Operating current : 115/100 mA (max) · TTL standby current : 40 mA (max) · CMOS standby current: 5 mA (max) : 1 mA (max) (L-version) · Data retention current : 0.6 mA (max) (L-version) · Data retention voltage: 2 V (min) (L-version) · Center VCC and VSS type pin out
HM62W4100HC Series
Ordering Information
Type No. HM62W4100HCJP-10 HM62W4100HCJP-12 HM62W4100HCLJP-10 HM62W4100HCLJP-12 Access time 10 ns 12 ns 10 ns 12 ns Device marking HM62W4100CJP10 HM62W4100CJP12 HM62W4100CLJP10 HM62W4100CLJP12 Package 400-mil 32-pin plastic SOJ (CP-32DB)
Pin Arrangement
32-pin SOJ A0 A1 A2 A3 A4 I/O1 VCC VSS I/O2 A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 I/O4 VSS VCC I/O3 A14 A13 A12 A11 A10 NC
Pin Description
Pin name A0 to A19 I/O1 to I/O4 CS OE WE VCC VSS NC Function Address input Data input/output Chip select Output enable Write enable Power supply Ground No connection
Rev. 2, Nov. 2001, page 2 of 13
HM62W4100HC Series
Block Diagram
(LSB) A14 A13 A12 A5 A6 A7 A11 A10 A3 A1 (MSB) I/O1 . . . I/O4 A8 A9 A19 A17 A18 A15 A0 A2 A4 A16 (LSB) (MSB)
VCC Row decoder 1024-row × 64-column × 16-block × 4-bit (4,194,304 bits) VSS
CS Column I/O Input data control Column decoder CS
CS
Rev. 2, Nov. 2001, page 3 of 13
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