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Details, datasheet, quote on part number:HM62G36256BP
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Datasheet text preview:
HM62G36256A Series
9M Synchronous Fast Static RAM (256k-word × 36-bit)
ADE-203-1267B (Z) Preliminary Rev. 0.2 Sep. 28, 2001 Description
The HM62G36256A is a synchronous fast static RAM organized as 256-kword × 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119bump BGA. Note: All power supply and ground pins must be connected for proper operation of the device.
Features
· · · · · · · · · · · · 2.5 V ± 5% and 3.3 V ± 5% operation and 0.9 V (VREF) Internal self-timed late write Byte write control (4 byte write selects, one for each 9-bit) Optional ×18 configuration HSTL compatible I/O Programmable impedance output drivers User selective input trip-point Differential, HSTL clock inputs Asynchronous G output control Asynchronous sleep mode Limited set of boundary scan JTAG IEEE 1149.1 compatible Protocol: Single clock register-register mode
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specification.
HM62G36256A Series
Ordering Information
Type No. HM62G36256ABP-30 HM62G36256ABP-33 HM62G36256ABP-40 Access time 1.7 ns 1.7 ns 2.0 ns Cycle time 3.0 ns 3.3 ns 4.0 ns Package 119-bump 1. 27 mm 14 mm × 22 mm BGA (BP-119C)
Pin Arrangement
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc5 DQc4 VDDQ DQc8 DQc7 VDDQ DQd7 DQd8 VDDQ DQd4 DQd5 NC NC VDDQ 2 SA0 NC SA3 DQc0 DQc3 DQc1 DQc6 DQc2 VDD DQd2 DQd6 DQd1 DQd3 DQd0 SA7 NC TMS 3 SA1 SA2 SA4 VSS VSS VSS SWEc VSS VREF VSS SWEd VSS VSS VSS M1 SA9 TDI 4 NC NC VDD ZQ SS G NC NC VDD K K SWE SA8 SA10 VDD SA16 TCK 5 SA13 SA14 SA5 VSS VSS VSS SWEb VSS VREF VSS SWEa VSS VSS VSS M2 SA17 TDO 6 SA12 SA11 SA6 DQb0 DQb3 DQb1 DQb6 DQb2 VDD DQa2 DQa6 DQa1 DQa3 DQa0 SA15 NC NC 7 VDDQ NC NC DQb5 DQb4 VDDQ DQb8 DQb7 VDDQ DQa7 DQa8 VDDQ DQa4 DQa5 NC ZZ VDDQ
(Top view)
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HM62G36256A Series
Pin Description
Name VDD VSS VDDQ VREF K K SS SWE SAn SWEx G ZZ ZQ DQxn M1, M2 TMS TCK TDI TDO NC I/O type Supply Supply Supply Supply Input Input Input Input Input Input Input Input Input I/O Input Input Input Input Output -- Descriptions Core power supply Ground Output power supply Input reference: provides input reference voltage Clock input. Active high. Clock input. Active low. Synchronous chip select Synchronous write enable Synchronous address input Synchronous byte write enables Asynchronous output enable Power down mode select Output impedance control Synchronous data input/output Output protocol mode select Boundary scan test mode select Boundary scan test clock Boundary scan test data input Boundary scan test data output No connection 1 x = a, b, c, d n = 0, 1, 2...8 n = 0-17 x = a, b, c, d Notes
M1 VSS
M2 VDD
Protocol Synchronous register to register operation
Notes 2
Notes: 1. ZQ is to be connected to V SS via a resistance RQ where 225 RQ 275 . If ZQ = VDDQ or open, output buffer impedance will be maximum. 2. There is 1 protocol with mode pin. For this application, M1 and M2 need to connect to V SS and VDD, respectively. The state of the Mode control inputs must be set before power-up and must not change during device operation. Mode control inputs are not standard inputs and may not meet V IH or VIL specification. This SRAM is tested only in the synchronous register to register operation.
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