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Details, datasheet, quote on part number:HM62G36256BP-5
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Datasheet text preview:
HM62G36256 Series
8M Synchronous Fast Static RAM (256k-word × 36-bit)
ADE-203-1139 (Z) Preliminary Rev. 0.0 Jan. 10, 2000 Description
The HM62G36256 is a synchronous fast static RAM organized as 256-kword × 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119bump BGA. Note: All power supply and ground pins must be connected for proper operation of the device.
Features
· · · · · · · · · · · · · Power supply: 3.3 V +10%, 5% Clock frequency: 200 MHz to 250 MHz Internal self-timed late write Byte write control (4 byte write selects, one for each 9-bit) Optional ×18 configuration HSTL compatible I/O Programmable impedance output drivers User selective input trip-point Differential, HSTL clock inputs Asynchronous G output control Asynchronous sleep mode Limited set of boundary scan JTAG IEEE 1149.1 compatible Protocol: Single clock register-register mode
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications.
HM62G36256 Series
Ordering Information
Type No. HM62G36256BP-4 HM62G36256BP-5 Access time 2.1 ns 2.5 ns Cycle time 4.0 ns 5.0 ns Package 119-bump 1. 27 mm 14 mm × 22 mm BGA (BP-119A)
Pin Arrangement
119-bumps BGA
1 A
2
3
4
NC NC
5
6
7
VDDQ SA0 SA6
SA4 SA2 VDDQ SA8 SA9 NC NC
B
NC NC SA7
C
NC SA14 SA3 VDD SA5 SA1
D
DQc1 DQc0 VSS ZQ SS G VSS DQb0 DQb1 VSS DQb3 DQb2 VSS DQb4 VDDQ
E
DQc2 DQc3 VSS
F
VDDQ DQc4 VSS
G H
DQc6 DQc5 SWEc NC SWEb DQb5 DQb6 DQc7 DQc8 VSS NC VSS DQb8 DQb7
J
VDDQ VDD VREF VDD VREF VDD VDDQ
K
DQd7 DQd8 VSS K VSS DQa8 DQa7 SWEa DQa5 DQa6
L M N
DQd6 DQd5 SWEd K
VDDQ DQd4 VSS SWE VSS DQa4 VDDQ DQd2 DQd3 VSS SA17 VSS DQa3 DQa2
P
DQd1 DQd0 VSS SA16 VSS DQa0 DQa1
R
NC SA10 M1 VDD M2 SA11 NC ZZ
T
NC NC SA12 SA15 SA13 NC
U
VDDQ TMS TDI TCK TDO NC VDDQ
(Top view)
2
HM62G36256 Series
Pin Description
N am e VDD VSS VDDQ VREF K K SS SWE SAn SWEx G ZZ ZQ DQxn M1, M2 TMS TCK TDI TDO NC I/O type Supply Supply Supply Supply Input Input Input Input Input Input Input Input Input I/O Input Input Input Input Output -- Descriptions Core power supply Ground Output power supply Input reference: provides input reference voltage Clock input. Active high. Clock input. Active low. Synchronous chip select Synchronous write enable Synchronous address input Synchronous byte write enables Asynchronous output enable Power down mode select Output impedance control Synchronous data input/output Output protocol mode select Boundary scan test mode select Boundary scan test clock Boundary scan test data input Boundary scan test data output No connection 1 x = a, b, c, d n = 0, 1, 2...8 n = 0, 1, 2...17 x = a, b, c, d Notes
M1 VSS
M2 VDD
Protocol Synchronous register to register operation
Notes 2
Notes: 1. ZQ is to be connected to V SS via a resistance RQ where 150 RQ 300 , if ZQ = VDDQ or open, output buffer impedance will be maximum. A case of minimum impedance, it needs to connect over 120 between ZQ and V SS . 2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either VDD or VSS respectively. The state of the Mode control inputs must be set before power-up and must not change during device operation. Mode control inputs are not standard inputs and may not meet VIH or VIL specification. This SRAM is tested only in the synchronous register to register operation.
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