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Details, datasheet, quote on part number:HM5212325F-B60
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Datasheet text preview:
HM5212325F-B60
128M LVTTL interface SDRAM 100 MHz 1-Mword × 32-bit × 4-bank PC/100 SDRAM
ADE-203-1053A (Z) Rev. 1.0 Oct. 18, 1999 Description
The Hitachi HM5212325F is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.
Features
· · · · · · · · · Single chip wide bit solution (× 32) 3.3 V power supply Clock frequency: 100 MHz (max) LVTTL interface Extremely small foot print: 1.27 mm pitch Package: BGA (BP-108) 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 4/8/full page 2 variations of burst sequence Sequential (BL = 4/8/full page) Interleave (BL = 4/8) Programmable CAS latency: 2/3 Byte control by DQMB Refresh cycles: 4096 refresh cycles/64 ms 2 variations of refresh Auto refresh Self refresh
· · · ·
HM5212325F-B60
· Full page burst length capability Sequential burst Burst stop capability
Ordering Information
Type No. HM5212325FBP-B60* Frequency 100 MHz CAS latency 3 Package 14 mm × 22 mm 108 bump BGA (BP-108)
Note: 66 MHz operation at CAS latency = 2.
2
HM5212325F-B60
Pin Arrangement
108-bump BGA 1 A B C D E F G H J K L
DQ31
2
NC
3
NC
4
DQ24
5
VSS
6
DQ23
7
NC
8
NC
9
DQ16
DQ30
NC
NC
DQ25
VCC
DQ22
NC
NC
DQ17
DQ29
NC
NC
DQ26
VCC
DQ21
NC
NC
DQ18
DQ28 DQ MB3
NC
NC
DQ27
VSS
DQ20
NC
NC DQ MB2 RAS
DQ19
NC
NC
CKE
VCC
WE
A12
VCC
A10
A13
A7
A5
VCC
A1
A4
VSS
A2
A3
A8
A6
VSS
A0
A11
VSS
A9
CS
M Open N P R T U
NC
CLK
VCC
CAS
DQ MB0 NC NC DQ4 VSS DQ11 NC
NC
DQ MB1 DQ12
DQ3
NC
DQ2
NC
NC
DQ5
VCC
DQ10
NC
NC
DQ13
DQ1
NC
NC
DQ6
VCC
DQ9
NC
NC
DQ14
DQ0
NC
NC
DQ7
VSS
DQ8
NC
NC
DQ15
(Top view)
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