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Details, datasheet, quote on part number:M13L128168A
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| Part: | M13L128168A |
| Category: | Memory => DRAM => DDR SDRAM => 128 Mb |
| Description: | Org. = 8MbX16 ;; Description = DDR 3.3V ;; Refresh = ;; Speed/ Clock Freq. = 275/250/200 MHZ ;; Package = 66-TSOPII |
| Company: | EliteMT |
| Datasheet: | Download M13L128168A datasheet File size : 817 kB |
| Request For quote: | Find where to buy M13L128168A
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Datasheet text preview:
ESMT
Revision History
Revision 1.3 -Revise operation voltage. (page 5) Revision 1.2 -Changed tWTR from 1 tCK to 2 tCK. Revision 1.1 -Changed absolute max. voltage (VIN, VOUT ,VDD ,VDDQ) from 3.6V to 4.0V Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Symbol VIN, VOUT VDD VDDQ Value -0.5 ~ 4.0 -1.0 ~ 4.0 -0.5 ~ 4.0 Unit V V V
M13L128168A
-Changed operating VDD from 3.135V~3.6V to 3.135V~3.83V -Updated DC current specification Revision 1.0 (21 Oct. 2002) -No "preliminary" on title. -Added M13L128168A-3.6T Spec. -Changed VDDQ from 2.5V ± 5% to 2.375V ~ 2.8V Revision 0.4 (26 Sep. 2002) -Changed VDD from 3.3V ± 5% to 3.135V ~ 3.6V -Changed operating temperature from 70 °C to 65 °C Revision 0.3 (11 Jul. 2002) -Added DC Current Spec Revision 0.2 (29 May. 2002) -Independent of M13S128168A Revision 0.1 (3 May. 2002) -Original
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2003 Revision : 1.3 1/48
ESMT
DDR SDRAM
Features
JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe(DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE LDM/UDM for write masking only VDD = 3.135V-3.83V, VDDQ = 2.375V-2.8V Auto & Self refresh 15.6us refresh interval 1 DQS per byte (LDQS, UDQS) SSTL-2 I/O interface 66pin TSOPII package
M13L128168A
2M x 16 Bit x 4 Banks Double Data Rate SDRAM
ORDERING INFORMATION:
PRODUCT NO. M13L128168A-3.6T M13L128168A-4T M13L128168A-5T M13L128168A-6T MAX. FREQ 276MHz 250MHz 200MHz 166MHz 3.3V TSOP II VDD PACKAGE
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2003 Revision : 1.3 2/48
ESMT
Functional Block Diagram
CLK CLK CKE Address
Mode Register & Extended Mode Register
M13L128168A
Clock Generator
Bank D Bank C Bank B Row Decoder Row Address Buffer & Refresh Counter
Bank A
Sense Amplifier Control Logic
CS RAS CAS WE
Command Decoder
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Refresh Counter
DM
Column Decoder
DQ
CLK, CLK
DLL
DQS
DQS
Pin Arrangement
x16
VDD DQ 0 VDDQ DQ 1 DQ 2 VSSQ DQ 3 DQ 4 VDDQ DQ 5 DQ 6 VSSQ DQ 7 NC VDDQ LD QS NC VDD NC LD M WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
x16
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ 9 VDDQ DQ 8 NC VSSQ UDQ S NC VREF VSS UD M CL K CL K CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
66 PIN TSOP(II) (400mil x 875mil) (0.65 mm PIN PITCH)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2003 Revision : 1.3 3/48
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