|Description||ZIF600 - Pager Synthesizer And 4 FSK Demodulator|
|Datasheet||Download ZIF600B datasheet
The ZIF600 synthesiser is for channel selection in 4FSK pagers. A reference frequency is generated by an on-chip crystal oscillator with an AFC external trimming varacator controlled by a DAC. The ZIF600 digital demodulator uses DSP techniques to optimise the data extraction in the presence of noise and also generates an AFC output to adjust the crystal frequency. Separate power controls allow the system current consumption to be minimised. All functions are controlled by a serial bus with a simple programming format and with four control pins which are used to control the power up and power down functions of the blocks to allow sequenced wake up and optimised power consumption.RXQ RXI SRF DATA0 DATA1 VSSD VDDD VREF RBIAS PDOUT PLLC
DSC2 DSC1 DATA LE CLOCK VSSA VCOFIN VDDA REFOSCB TSS REFOSC VSSI
FEATURES s Low Voltage Operation, 3.3V s On-chip Reference Oscillator s Channel Select Synthesiser s Direct VCO input s 6400 Baud Digital 4FSK Demodulator s Serial Control Bus s Very Low Power Consumption s Small QSOP24 Package
APPLICATIONS s Pagers - including small form factor designs such as credit card pagers, watch pagers and PCMCIA applications s Low data rate receivers - security/remote control ABSOLUTE MAXIMUM RATINGS To be defined.
DATA PLLC SRF VREF RBIAS BIASES CONTROL LOGIC & POWER MANAGEMENT CLOCK DSC1 DSC2 LIMI DIGITAL DEMODULATOR LIMQ Demod. Clock AFC (DAC) DACOUT DATA SLICER DATA1 DATA0REFERENCE DIVIDER PHASE DETECTOR TWO MODULUS PRESCALER M AND A DIVIDERS PDOUT
These characteristics are guaranteed over the following conditions (unless otherwise stated): VDDD, VDDA to 1.6V (connected to REFOSCB via ext. resistor) and Tamb + 70°C Characteristic Supply current at VDDD,VDDA = 3V Supply current = 1.4V Min. Typ. 1 350 Max. Units µA V Conditions Synthesiser locked and demodulator active. VDD1 connected to REFOSCB via external resistor.
VREF bias voltage input range Logic input HIGH, pins DATA, CLOCK, LE, DSC1, DSC2, PLLC, SRF, RXI, RXQ Logic input HIGH, pins DATA, CLOCK, LE, DSC1, DSC2, PLLC, SRF, RXI, RXQ Input capacitance (signal pins) Input leakage (signal pins) Control bus CLOCK frequency Synthesiser charge pump output leakage, pin PDOUT Synthesiser charge pump output current, pin PDOUT Charge pump output compliance range, pin PDOUT Main synthesiser input frequency on VCOFIN input level
- pk MHz Pins REFOSC and REFOSCB Output current, IoH = 100µA Output current, IoL = 100µA. Not tested Output current 100nA VREF = 1.25V VDD 0.3V VSS + 0.3V Pin voltage: VSS to VDD pins include SRF, PLLC DSC1, DSC2
Logic output HIGH, pins DATA0, DATA1 Logic output LOW, pins DATA0, DATA1 Trim DAC output voltage, pin DACOUTRXI, RXQ pull-up current RXI, RXQ pull-up current Input leakage (signal) pins with pull-downs
Pin No. Pin Name RXQ RXI SRF DATA0 DATA1 VSSD VDDD VREF RBIAS PDOUT PLLC DACOUT VSS1 REFOSC TSS REFOSCB VDDA VCOFIN VSSA CLOCK LE DATA DSC1 DSC2 Pin Type In Out P In Out In Out G I/O In I/O G In Description Receiver "Quadrature" output Receiver "In Phase" output Symbol Rate Filter Data output to decoder Data output to decoder Digital Ground to 3.3V Digital Power Supply 1.25 Volt Reference from ZIF100 Bias setting Resistor 120k to VSSA max. parasitic capacitance = 5pF Charge pump output from synthesiser Synthesiser power down Trim DAC for crystal Ground (substrate) Reference Oscillator Test Scan Select, Normally logic 0 Reference Oscillator. External resistor to 3.3V Analog Power Supply VCO frequency input to synthesiser Analog Ground Control Bus Clock Control Bus Latch Enable Control Bus Data With DSC2 controls the operating mode of the demodulator With DSC1 controls the operating mode of the demodulator
The ZIF600 synthesiser is used to select the channel in 4FSK paging receivers and uses on-chip constant current charge pumps to drive an external passive loop filter. Common low cost reference crystals are used, at frequencies or 14.4MHz, and are divided to give the required or 25kHz channel spacings. The reference crystal oscillator uses external trimming to meet system requirements and is controlled by a DAC set by the digital demodulator. The digital demodulator takes the limited I and Q signals from the radio receiver and converts the 4-level FSK into 2 bit data output on pins DATA0 and DATA1. An AFC output from this demodulator is also included. Functions are controlled by a serial bus with a simple programming format and with four control pins to allow optimum power up sequences which help minimise the system current consumption. Crystal Comp. Total MHz freq. kHz division RD2 RD3
The reference frequency generated by the oscillator on pins REFOSC and REFOSCB is divided to give the comparison frequency clock. See Fig. 3. Ratio selection is five control bits RD1 (where LOW gives ÷ 8 mode), RD2 (where LOW gives ÷ 4 mode) and RD3 (where LOW gives ÷ 2 mode) which can be set to give the 8 options needed to get or 25kHz from either or 14.4MHz crystal, as in Table 2. The additional control bits RD4 and RD5 allow the option of further division to allow for an off chip frequency multiplier. If both RD4 and RD5 are set low then this division stage is bypassed. Other settings for RD4 and RD5 offer division or 4. Table 3 shows the additional division options available from RD4 and RD5. Power down options are available for both the synthesiser and demodulator, however the crystal oscillator and the reference divider must be kept running to give a timing signal to the demodulator whilst the demodulator is on.
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