|Category||Communication => Wireless => ASK/FFSK|
|Description||Pager Synthesizer And 4 FSK Demodulator|
|Datasheet||Download ZIF600 datasheet
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The ZIF600 synthesiser is for channel selection in 4FSK pagers. A reference frequency is generated by an on-chip crystal oscillator with an AFC external trimming varacator controlled by a DAC. The ZIF600 digital demodulator uses DSP techniques to optimise the data extraction in the presence of noise and also generates an AFC output to adjust the crystal frequency. Separate power controls allow the system current consumption to be minimised. All functions are controlled by a serial bus with a simple programming format and with four control pins which are used to control the power up and power down functions of the blocks to allow sequenced wake up and optimised power consumption.RXQ RXI SRF DATA0 DATA1 VSSD VDDD VREF RBIAS PDOUT PLLC
DSC2 DSC1 DATA LE CLOCK VSSA VCOFIN VDDA REFOSCB TSS REFOSC VSSI
FEATURES s Low Voltage Operation, 3.3V s On-chip Reference Oscillator s Channel Select Synthesiser s Direct VCO input s 6400 Baud Digital 4FSK Demodulator s Serial Control Bus s Very Low Power Consumption s Small QSOP24 Package
APPLICATIONS s Pagers - including small form factor designs such as credit card pagers, watch pagers and PCMCIA applications s Low data rate receivers - security/remote control ABSOLUTE MAXIMUM RATINGS To be defined.
DATA PLLC SRF VREF RBIAS BIASES CONTROL LOGIC & POWER MANAGEMENT CLOCK DSC1 DSC2 LIMI DIGITAL DEMODULATOR LIMQ Demod. Clock AFC (DAC) DACOUT DATA SLICER DATA1 DATA0REFERENCE DIVIDER PHASE DETECTOR TWO MODULUS PRESCALER M AND A DIVIDERS PDOUT
These characteristics are guaranteed over the following conditions (unless otherwise stated): VDDD, VDDA to 1.6V (connected to REFOSCB via ext. resistor) and Tamb + 70°C Characteristic Supply current at VDDD,VDDA = 3V Supply current = 1.4V Min. Typ. 1 350 Max. Units µA V Conditions Synthesiser locked and demodulator active. VDD1 connected to REFOSCB via external resistor.
VREF bias voltage input range Logic input HIGH, pins DATA, CLOCK, LE, DSC1, DSC2, PLLC, SRF, RXI, RXQ Logic input HIGH, pins DATA, CLOCK, LE, DSC1, DSC2, PLLC, SRF, RXI, RXQ Input capacitance (signal pins) Input leakage (signal pins) Control bus CLOCK frequency Synthesiser charge pump output leakage, pin PDOUT Synthesiser charge pump output current, pin PDOUT Charge pump output compliance range, pin PDOUT Main synthesiser input frequency on VCOFIN input level
- pk MHz Pins REFOSC and REFOSCB Output current, IoH = 100µA Output current, IoL = 100µA. Not tested Output current 100nA VREF = 1.25V VDD 0.3V VSS + 0.3V Pin voltage: VSS to VDD pins include SRF, PLLC DSC1, DSC2
Logic output HIGH, pins DATA0, DATA1 Logic output LOW, pins DATA0, DATA1 Trim DAC output voltage, pin DACOUTRXI, RXQ pull-up current RXI, RXQ pull-up current Input leakage (signal) pins with pull-downs
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