|Category||FPGAs/PLDs => FPGA (Field Programmable Gate Array)|
|Description||Virtex-e Field Programmable Gate Array|
|Datasheet||Download XCV600E-6BG560C datasheet
Fast, High-Density 1.8 V FPGA Family - Densities from 4 M system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant 33/ 66-MHz Highly Flexible SelectI/O+TM Technology - Supports 20 high-performance interface standards to 804 singled-ended I/Os or 344 differential I/O pairs for an aggregate bandwidth > 100 Gb/s Differential Signalling Support - LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL - Differential I/O signals can be input, output, or I/O - Compatible with standard differential devices - LVPECL and LVDS clock inputs for 300+ MHz clocks Proprietary High-Performance SelectLinkTM Technology - Double Data Rate (DDR) to Virtex-E link - Web-based HDL generation methodology Sophisticated SelectRAM+TM Memory Hierarchy Mb of internal configurable distributed RAM Kb of synchronous internal block RAM - True Dual-Port BlockRAM capability - Memory bandwidth to 1.66 Tb/s (equivalent bandwidth of over 100 RAMBUS channels) - Designed for high-performance Interfaces to External Memories - 200 MHz ZBT* SRAMs - 200 Mb/s DDR SDRAMs - Supported by free Synthesizable reference design
High-Performance Built-In Clock Management Circuitry - Eight fully digital Delay-Locked Loops (DLLs) - Digitally-Synthesized 50% duty cycle for Double Data Rate (DDR) Applications - Clock Multiply and Divide - Zero-delay conversion of high-speed LVPECL/LVDS clocks to any I/O standard Flexible Architecture Balances Speed and Density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input function - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode Supported by Xilinx FoundationTM and Alliance SeriesTM Development Systems - Further compile time reduction 50% - Internet Team Design (ITD) tool ideal for million-plus gate density designs - Wide selection of PC and workstation platforms SRAM-Based In-System Configuration - Unlimited re-programmability Advanced Packaging Options 0.8 mm Chip-scale 1.0 mm BGA 1.27 mm BGA - HQ/PQ µm 6-Layer Metal Process 100% Factory Tested
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The Virtex-E family offers to 43,200 logic cells in devices to 30% faster than the Virtex family. I/O performance is increased to 622 Mb/s using Source Synchronous data transmission architectures and synchronous system performance to 240 MHz using singled-ended SelectI/O technology. Additional I/O standards are supported, notably LVPECL, LVDS, and BLVDS, which use two pins per signal. Almost all signal pins can be used for these new standards. Virtex-E devices have Kb of faster (250 MHz) block SelectRAM, but the individual RAMs are the same size and structure as in the Virtex family. They also have eight DLLs instead of the four in Virtex devices. Each individual DLL is slightly improved with easier clock mirroring and 4x frequency multiplication. VCCINT, the supply voltage for the internal logic and memory, 1.8 V, instead 2.5 V for Virtex devices. Advanced processing and 0.18 µm design rules have resulted in smaller dice, faster speed, and lower power consumption. I/O pins are 3 V tolerant, and can 5 V tolerant with an external 100 resistor. PCI V is not supported. With the addition of appropriate external resistors, any pin can tolerate any voltage desired. Banking rules are different. With Virtex devices, all input buffers are powered by VCCINT. With Virtex-E devices, the LVTTL, LVCMOS2, and PCI input buffers are powered by the I/O supply voltage VCCO.
The Virtex-E family is not bitstream-compatible with the Virtex family, but Virtex designs can be compiled into equivalent Virtex-E devices. The same device in the same package for the Virtex-E and Virtex families are pin-compatible with some minor exceptions. See the data sheet pinout section for details.
The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 µm CMOS process. These advances make Virtex-E FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex-E family includes the nine members in Table 1. Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
Virtex-E devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the Virtex-E family to accommodate even the largest and most complex designs. Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Configuration data can be read from an external SPROM (master serial mode), or can be written into the FPGA (SelectMAPTM, slave serial, and JTAG modes). The standard Xilinx Foundation SeriesTM and Alliance SeriesTM Development systems deliver complete design support for Virtex-E, covering every aspect from behavioral and schematic entry, through simulation, automatic design translation and implementation, to the creation and downloading of a configuration bit stream.
Table 2: Performance for Common Circuit Functions Function Register-to-Register Adder Pipelined Multiplier Address Decoder 16:1 Multiplexer Parity Tree 5.9 ns Bits Virtex-E (-7)
Virtex-E devices provide better performance than previous generations of FPGAs. Designs can achieve synchronous system clock rates to 240 MHz including I/O or 622 Mb/s using Source Synchronous data transmission architechtures. Virtex-E I/Os comply fully with 3.3 V PCI specifications, and interfaces can be implemented that operate at 33 MHz or 66 MHz. While performance is design-dependent, many designs operate internally at speeds in excess of 133 MHz and can achieve over 311 MHz. Table 2 shows performance data for representative circuits, using worst-case timing parameters.Chip-to-Chip HSTL Class IV LVTTL,16mA, fast slew LVDS LVPECL
Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) XCV FG900 FG1156 XCV 94 158 XCV 200E XCV 300E XCV 400E XCV 600E XCV 1000E XCV 1600E XCV 2000E XCV 2600E XCV 3200E
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