|Description||Spartan and Spartan-xl Families Field Programmable Gate Arrays|
|Datasheet||Download XCS10XL-3CS100I datasheet
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Product Specification System level features - Available in both 5V and 3.3V versions - On-chip SelectRAMTM memory - Fully PCI compliant - Full readback capability for program verification and internal node observability - Dedicated high-speed carry logic - Internal 3-state bus capability - Eight global low-skew clock or signal networks - IEEE 1149.1-compatible Boundary Scan logic - Low cost plastic packages available in all densities - Footprint compatibility in common packages Fully supported by powerful Xilinx development system - Foundation Series: Integrated, shrink-wrap software - Alliance Series: Dozens of PC and workstation third party development systems supported - Fully automatic mapping, placement and routing
The SpartanTM and the Spartan-XL families are a high-volume production FPGA solution that delivers all the key requirements for ASIC replacement to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume, approach and in many cases are equivalent to mask programmed ASIC devices. The Spartan series is the result of more than 14 years of FPGA design experience and feedback from thousands of customers. By streamlining the Spartan series feature set, leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. The Spartan and Spartan-XL families in the Spartan series have ten members, as shown in Table 1.
Note: The Spartan series devices described in this data sheet include the 5V Spartan family and the 3.3V Spartan-XL family. See the separate data sheet for the 2.5V Spartan-II family. First ASIC replacement FPGA for high-volume production with on-chip RAM Density to 1862 logic cells or 40,000 system gates Streamlined feature set based on XC4000 architecture System performance beyond 80 MHz Broad set of AllianceCORETM and LogiCORETM predefined solutions available Unlimited reprogrammability Low cost
3.3V supply for low power with 5V tolerant I/Os Power down input Higher performance Faster carry logic More flexible high-speed clock network Latch capability in Configurable Logic Blocks Input fast capture latch Optional mux or 2-input function generator on outputs 24 mA output drive 5V and 3.3V PCI compliant Enhanced Boundary Scan Express Mode configuration Chip scale packaging Max. Total No. of Avail. Distributed Flip-flops User I/O RAM Bits
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays Logic Device XCS05 and XCS05XL XCS10 and XCS10XL XCS20 and XCS20XL XCS30 and XCS30XL XCS40 and XCS40XL Cells Max System Gates Typical Gate Range (Logic and RAM)(1) CLB Matrix x 28 Total CLBsNotes: 1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
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Spartan series FPGAs are implemented with a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and surrounded by a perimeter of programmable Input/Output Blocks (IOBs), as seen in Figure 1. They have generous routing resources to accommodate the most complex interconnect patterns. The devices are customized by loading configuration data into internal static memory cells. Re-programming is possible an unlimited number of times. The values stored in these
memory cells determine the logic functions and interconnections implemented in the FPGA. The FPGA can either actively read its configuration data from an external serial PROM (Master Serial mode), or the configuration data can be written into the FPGA from an external device (Slave Serial mode). Spartan series FPGAs can be used where hardware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 50,000 systems per month.
Spartan and Spartan-XL Families Field Programmable Gate Arrays The functionality of each circuit block is customized during configuration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA.
Spartan series devices achieve high-performance, low-cost operation through the use of an advanced architecture and semiconductor technology. Spartan and Spartan-XL devices provide system clock rates exceeding 80 MHz and internal performance in excess of 150 MHz. In contrast to other FPGA devices, the Spartan series offers the most cost-effective solution while maintaining leading-edge performance. In addition to the conventional benefit of high volume programmable logic solutions, Spartan series FPGAs also offer on-chip edge-triggered single-port and dual-port RAM, clock enables on all flip-flops, fast carry logic, and many other features. The Spartan/XL families leverage the highly successful XC4000 architecture with many of that family's features and benefits. Technology advancements have been derived from the XC4000XLA process developments.
The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simplified block diagram in Figure 2. There are three look-up tables (LUT) which are used as logic function generators, two flip-flops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Description, page 13.
Two x 1 memory look-up tables (F-LUT and G-LUT) are used to implement 4-input function generators, each offering unrestricted logic implementation of any Boolean function up to four independent input signals to G4). Using memory look-up tables the propagation delay is independent of the function implemented. A third 3-input function generator (H-LUT) can implement any Boolean function of its three inputs. Two of these inputs are controlled by programmable multiplexers (see box "A" of Figure 2). These inputs can come from the F-LUT or G-LUT outputs or from CLB inputs. The third input always comes from a CLB input. The CLB can, therefore, implement certain functions up to nine inputs, like parity checking. The three LUTs in the CLB can also be combined to do any arbitrarily defined Boolean function of five inputs.
The Spartan series uses a standard FPGA structure as shown in Figure 1, page 2. The FPGA consists of an array of configurable logic blocks (CLBs) placed in a matrix of routing channels. The input and output of signals is achieved through a set of input/output blocks (IOBs) forming a ring around the CLBs and routing channels. CLBs provide the functional elements for implementing the user's logic. IOBs provide the interface between the package pins and internal signal lines. Routing channels provide paths to interconnect the inputs and outputs of the CLBs and IOBs.
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