Details, datasheet, quote on part number: X76F100-3
CategoryMemory => Flash
DescriptionSecure Serialflash
CompanyXicor, Inc.
DatasheetDownload X76F100-3 datasheet


Features, Applications

FEATURES 64-bit password security One array (112-bytes) two passwords (16-bytes) --Read password --Write password Programmable passwords Retry counter register --Allows 8 tries before clearing of the array 32-bit response to reset (rst input) 8-byte sector Write Mode 1MHz clock rate 2-wire serial interface Low power CMOS to 5.5V operation --Standby current less than 1ľA --Active current less than 3 mA High reliability endurance: --100,000 write cycles Data retention: 100 years Available in: --8-lead PDIP, SOIC, MSOP, and smart car module

DESCRIPTION The is a Password Access Security Supervisor, containing one 896-bit Secure SerialFlash array. Access to the memory array can be controlled by two 64-bit passwords. These passwords protect read and write operations of the memory array. The X76F100 features a serial interface and software protocol allowing operation on a popular two wire bus. The bus signals are a clock Input (SCL) and a bidirectional data input and output (SDA). Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X76F100 also features a synchronous response to reset providing an automatic output of a hard-wired 32-bit data stream conforming to the industry standard for memory cards. The X76F100 utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

CS SCL SDA Chip Enable Data Transfer Array Access Enable Interface Logic Password Array and Password Verification Logic RST Reset Response Register Retry Counter 8K Byte SerialFlash Array 0 (Password Protected)

PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is an open drain serial data input/output pin. During a read cycle, data is shifted out on this pin. During a write cycle, data is shifted in on this pin. In all other cases, this pin in a high impedance state. Chip Select (CS) When CS is high, the X76F100 is deselected and the SDA pin is at high impedance and unless an internal write operation is underway, the X76F100 will be in standby mode. CS low enables the X76F100, placing it in the active mode. Reset (RST) RST is a device reset pin. When RST is pulsed high while CS is low the X76F100 will output 32 bits of fixed data which conforms to the standard for "synchronous response to reset". CS must remain LOW and the part must not in a write cycle for the response to reset to occur. See Figure If at any time during the response to reset CS goes HIGH, the response to reset will be aborted and the part will return to the standby state. The response to reset is "mask programmable" only! DEVICE OPERATION The X76F100 memory array consists of fourteen 8-byte sectors. Read or write access to the array always begins at the first address of the sector. Read operations then can continue indefinitely. Write operations must total 8-bytes. There are two primary modes of operation for the X76F100; Protected READ and protected WRITE. Protected operations must be performed with one of two 8byte passwords. The basic method of communication for the device is established by first enabling the device (CS LOW), generating a start condition, then transmitting a command, followed by the correct password. All parts will be shipped from the factory with all passwords equal to `0'. The user must perform ACK Polling to determine the validity of the password, before starting a data transfer (see Acknowledge Polling.) Only after the correct password is accepted and a ACK polling has been performed, can the data transfer occur.

To ensure the correct communication, RST must remain LOW under all conditions except when running a "Response to Reset sequence". Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device. If the in a nonvolatile write cycle a "no ACK" (SDA=High) response will be issued in response to loading of the command byte. If a stop is issued prior to the nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. The basic sequence is illustrated in Figure 1. PIN NAMES Symbol


Chip Select Input Serial Data Input/Output Serial Clock Input Reset Input Supply Voltage Ground No Connect

After each transaction is completed, the X76F100 will reset and enter into a standby mode. This will also be the response if an unsuccessful attempt is made to access a protected array. Figure 1. X76F100 Device Operation

Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 2 and Figure 3. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X76F100 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. A start may be issued to terminate the input of a control byte or the input data to be written. This will reset the device and leave it ready to begin a new read or write command. Because of the push/pull output, a start cannot be generated while the part is outputting data. Starts are inhibited while a write is in progress. Stop Condition All communications must be terminated by a stop condition. The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. As with starts, stops are inhibited when outputting data and while a write is in progress. Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. The X76F100 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write condition have been selected, the X76F100 will respond with an acknowledge after the receipt of each subsequent eight-bit word.

Retry Counter The X76F100 contains a retry counter. The retry counter allows 8 accesses with an invalid password before any action is taken. The counter will increment with any combination of incorrect passwords. If the retry counter overflows, the memory area and both of the passwords are cleared If a correct password is received prior to retry counter overflow, the retry counter is reset and access is granted. Device Protocol The X76F100 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as a receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X76F100 will be considered a slave in all applications.


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