Details, datasheet, quote on part number: TRU050-TDCCA
DescriptionComplete VCXO Based Phase-locked Loop
CompanyVectron International
DatasheetDownload TRU050-TDCCA datasheet
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Features, Applications

Output Frequencies to 65.536 MHz or 3.3Vdc Operation Tri-State Output Holdover on Loss of Signal Alarm VCXO with CMOS Outputs or 40/85C Temperature Range Ceramic SMD Package RoHS/Lead Free Compliant The TRU050, VCXO based PLL


The is a user-configurable crystal-based PLL integrated circuit. It includes a digital phase detector, op-amp, VCXO and additional integrated functions for use in digital synchronization applications. Loop filter software is available as well SPICE models for circuit simulation.


Frequency Translation Clock Smoothing NRZ Clock Recovery DSLAM, ADM, ATM, Aggregation, Optical Switching/Routing, Base Station Low Jitter PLL's

Parameter Output Frequency (ordering option) Out 1, 5V option Out 1, 3.3V option Supply Voltage +5 +3.3 Supply Current Output Logic Levels Output Logic High2 Output Logic Low2 Output Transition Times Rise Time2 Fall Time2 Input Logic Levels Output Logic High2 Output Logic Low2 Loss of Signal Indication Output Logic High2 Output Logic Low2 Nominal Frequency on Loss of Signal Output 1 Output 2 Symmetry or Duty Cycle3 Out 1 Out 2 RCLK Absolute Pull Range, ordering option over operating temp, aging, power supply

Test Conditions for APR (+5V option) Test Conditions for APR (+3.3V option) Gain Transfer Phase Detector Gain +5V option +3.3V Option Operating temperature, ordering option Control Voltage Leakage Current

1. A good quality 0.01uF in parrallel with 0.1 uf capacitor should be located as close to pin 16 to ground as possible. 2. Figure 1 defines these parameters. Figure 2 illustrates the equivalent five-gate TTL load and operating conditions under which these parameters are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time and duty cycle. 3. Symmetry is defined as (ON TIME/PERIOD with Vs=-1.4 V for both 5V and 3.3V operation.

Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied at these or any other conditions in excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability.

Parameter Power Supply Storage Temperature Soldering Temperature/Duration Clock and Data Input Range Symbol VDD Tstorage

Parameter Mechanical Shock Mechanical Vibration Solderability Gross and Fine Leak Resistance to Solvents Conditions MIL-STD-883, Method 2002 MIL-STD-883, Method 2007 MIL-STD-883, Method 2003 MIL-STD-883, Method 1014, 100% Tested MIL-STD-883, Method 2016

Although ESD protection circuitry has been designed into the TRU050, proper precautions should be taken when handling and mounting. VI employs a human body model and a charged-device model (CDM) for ESD susceptibility testing and design protection evaluation. ESD thresholds are dependent on the circuit parameters used to define the model.

Model Human Body Model Charged Device Model Minimum 1500V 1000V MIL-STD 3015 JESD 22-C101


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