Details, datasheet, quote on part number: TPS7A8101EVM-093
PartTPS7A8101EVM-093
CategoryProgrammers, Development Systems
TitleEval Board - Linear Voltage Regulator (ldos) Programmers, Development System
Description
CompanyTexas Instruments, Inc.
DatasheetDownload TPS7A8101EVM-093 datasheet
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Specifications 
Lead Free StatusLead Free
RoHS StatusRoHS Compliant

 

Features, Applications

Low-Noise, Wide-Bandwidth, High PSRR, Low-Dropout 1-A Linear Regulator
FEATURES

Low-Dropout 1-A Regulator with Enable Adjustable Output Voltage: 6.0 V Wide-Bandwidth High PSRR: at 1 kHz at 100 kHz at 1 MHz Low Noise: 23.5 VRMS typical to 100 kHz) Stable with a 4.7-F Capacitance Excellent Load/Line Transient Response 3% Overall Accuracy (over Load/Line/Temperature) Over-Current and Over-Temperature Protection Very Low Dropout: 170 mV Typical 1 A Package: 3-mm SON-8

DESCRIPTION

The TPS7A8101 low-dropout linear regulator (LDO) offers very good performance in noise and powersupply rejection ratio (PSRR) at the output. This LDO uses an advanced BiCMOS process and a PMOSFET pass device to achieve very low noise, excellent transient response, and excellent PSRR performance. The TPS7A8101 is stable with a 4.7-F ceramic output capacitor, and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations. This device is fully specified over the temperature range to +125°C and is offered 3-mm, SON-8 package with a thermal pad.

APPLICATIONS
IOUT= 10 mA IOUT= 100 mA IOUT= 750 mA IOUT= 10k 100k Frequency (Hz) 1M 10M

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT TPS7A8101yyyz (1) YYY is package designator. Z is package quantity. VOUT

For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com.

Over operating free-air temperature range (unless otherwise noted). (1)

VALUE MIN IN Voltage FB, NR EN OUT Current Temperature OUT Operating virtual junction, TJ Storage, Tstg Human body model (HBM) QSS 009-105 (JESD22-A114A) Charged device model (CDM) QSS 009-147 (JESD22-C101B.01) Internally Limited MAX +7.0 +3.6 VIN + 0.3

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods my affect device reliability. VEN absolute maximum rating is VIN +7.0 V, whichever is smaller. ESD testing is performed according to the respective JESD22 JEDEC standard.

TPS7A8101 THERMAL METRIC (2) JA JCtop JT JB JCbot Junction-to-ambient thermal resistance (4) Junction-to-case (top) thermal resistance Junction-to-board thermal resistance (6) Junction-to-top characterization parameter (7) Junction-to-board characterization parameter (8) Junction-to-case (bottom) thermal resistance (9)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the DRB package are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) The exposed pad is connected to the PCB ground layer through a 2×2 thermal via array. (b) The top and bottom copper layers are assumed to have a 5% thermal conductivity of copper representing a 20% copper coverage. (c) This data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with × 3in copper area. To understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction Temperature sections. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain JA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain JA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.


 

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