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Details, datasheet, quote on part number:TPS70245
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| Part: | TPS70245 |
| Category: | Power Management => Regulators => Linear Regulators => LDO (Low Drop Out) |
| Description: | Dual-output Low-dropout Voltage Regulators With Integrated SVS For Split Voltage Systems |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download TPS70245 datasheet File size : 482 kB |
| Request For quote: | Find where to buy TPS70245
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Datasheet text preview:
TPS70245, TPS70248, TPS70251, TPS70258, TPS70202 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS286B JUNE 2000 REVISED OCTOBER 2002
D Dual Output Voltages for Split-Supply D D D D D D
Applications Independent Enable Functions (See Part Number TPS701xx for Sequenced Outputs) Output Current Range of 500 mA on Regulator 1 and 250 mA on Regulator 2 Fast Transient Response Voltage Options Are 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable Outputs Open Drain Power-On Reset With 120-ms Delay Open Drain Power Good for Regulator 1 and Regulator 2
D Ultralow 190 µA (typ) Quiescent Current D 1 µA Input Current During Standby D Low Noise: 65 µVRMS Without Bypass D D D D D D
Capacitor Quick Output Capacitor Discharge Feature One Manual Reset Input 2% Accuracy Over Load and Temperature Undervoltage Lockout (UVLO) Feature 20-Pin PowerPAD TSSOP Package Thermal Shutdown Protection
PWP PACKAGE (TOP VIEW)
description
The TPS702xx is a low dropout voltage regulator with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 500 mA and 250 mA by regulator 1 and regulator 2 respectively. Quiescent current is typically 190 µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution.
TPS70251 PWP 5V 0.1 µF VIN1 VOUT1 VSENSE1 PG1 VIN2 0.1 µF >2 V 2 V 2 V 10 µF
NC VIN1 VIN1 MR EN1 EN2 RESET GND VIN2 VIN2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
NC VOUT1 VOUT1 VSENSE1/FB1 PG1 PG2 VSENSE2/FB2 VOUT2 VOUT2 NC
NC No internal connection
3.3 V
I/O
250 k PG1 250 k
<0.7 V RESET PG2
250 k RESET
EN1
EN1
PG2
EN2
VSENSE2 1.8 V 10 µF Core
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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TPS70245, TPS70248, TPS70251, TPS70258, TPS70202 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS286B JUNE 2000 REVISED OCTOBER 2002
description (continued)
The TPS702xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10 µF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 500 mA, and regulator 2 can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to both EN1 and EN2, both regulators are in sleep mode, thereby reducing the input current to 2 µA at TJ = 25°C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS702xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event of an undervoltage condition. RESET also indicates the status of the manual reset pin (MR). When MR is in the logic high state, RESET goes to a high impedance state after 120 ms delay. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR. The device has an undervoltage lockout UVLO circuit which prevents the internal regulators from turning on until VIN1 reaches 2.5V.
AVAILABLE OPTIONS TJ REGULATOR 1 VO (V) 3.3 V 3.3 V 40°C to 125°C to 125°C 3.3 V 3.3 V Adjustable (1.22 V to 5.5 V) REGULATOR 2 VO (V) 1.2 V 1.5 V 1.8 V 2.5 V Adjustable (1.22 V to 5.5 V) TSSOP (PWP) TPS70245PWP TPS70248PWP TPS70251PWP TPS70258PWP TPS70202PWP
NOTE: The TPS70202 is programmable using external resistor dividers (see application information) The PWP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS70202PWPR).
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TPS70245, TPS70248, TPS70251, TPS70258, TPS70202 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS286B JUNE 2000 REVISED OCTOBER 2002
detailed block diagram fixed voltage version
VIN1 (2 Pins) Current Sense 10 k ENA_1 VSENSE1 (see Note A) VOUT1 (2 Pins) UVLO 2.5 V
Shutdown
GND Reference Thermal Shutdown Vref Vref Shutdown VSENSE1 VPGD_1
+
ENA_1 FB1
PG1 Rising Edge Deglitch
VIN1
MR RESET UVLO ENA_1 Shutdown Shutdown VSENSE2 VPGD_2 Vref FB2 Rising Edge Deglitch PG2 Falling Edge Delay
EN1
EN2
ENA_2
+
ENA_2 ENA_2 10 k VOUT2 (2 Pins) VSENSE2 (see Note A)
Current Sense VIN2 (2 Pins)
NOTE A: For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT1 and VOUT2 respectively as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the application information section.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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