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Details, datasheet, quote on part number:TPS54373PWPR
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Datasheet text preview:
Typical Size 6,4 mm X 6,6 mm
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TPS54373
SLVS455A - JANUARY 2003 - REVISED JUNE 2003
3 V TO 6 V INPUT, 3 A OUTPUT SYNCHRONOUS BUCK SWITCHER WITH DISABLED SINKING DURING START UP
FEATURES D 60-m MOSFET Switches for High Efficiency D D D D D D
at 3-A Continuous Output Source or Sink Current Disabled Current Sinking During Start-Up Adjustable Output Voltage Down to 0.9 V With 1.0% Accuracy Wide PWM Frequency: Fixed 350 kHz, 550 kHz or Adjustable 280 kHz to 700 kHz Synchronizable to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Component Count
DESCRIPTION
As a member of the SWIFT family of dc/dc regulators, the TPS54373 low-input voltage high-output current synchronous buck PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that enables maximum performance and flexibility in choosing the output filter L and C components; an under-voltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an internally or externally set slow-start circuit to limit in-rush currents; and a power good output useful for processor/logic reset, fault signaling, and supply sequencing. For reliable power up in output precharge applications, the TPS54373 is designed to only source current during start-up. The TPS54373 is available in a thermally enhanced 20-pin TSSOP (PWP) PowerPAD package, which eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles.
APPLICATIONS D Low-Voltage, High-Density Distributed Power D D D
Systems Point of Load Regulation for High Performance DSPs, FPGAs, ASICs and Microprocessors Broadband, Networking and Optical Communications Infrastructure Power PC Series Processors
TYPICAL APPLICATION
START UP WAVEFORM
*
I/O Supply VIN PH TPS54373 BOOT PGND VBIAS VSENSE AGND COMP
*
Core Supply
RL = 1
VI = 3.3 V 1 V/div
VO = 1.8 V
* Optional
5.0 ms/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
TPS54373
SLVS455A - JANUARY 2003 - REVISED JUNE 2003
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA - 40°C to 85°C OUTPUT VOLTAGE Adjustable down to 0.9 V PACKAGE Plastic HTSSOP (PWP)(1) PART NUMBER TPS54373PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54373PWPR). See the application section of the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) TPS54373 VIN, SS/ENA, SYNC RT Input voltage range, VI VSENSE BOOT VBIAS, COMP, PWRGD Output voltage range, VO Source current, IO PH PH COMP, VBIAS PH Sink current, IS Voltage differential Operating virtual junction temperature range, TJ Storage temperature, Tstg COMP SS/ENA, PWRGD AGND to PGND -0.3 V to 7 V -0.3 V to 6 V -0.3 V to 4V -0.3 V to 17 V -0.3 V to 7 V -0.6 V to 10 V Internally limited 6 mA 6A 6 mA 10 mA ±0.3 V -40°C to 125°C -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN Input voltage, VI Operating junction temperature, TJ 3 -40 NOM MAX 6 125 UNIT V °C
DISSIPATION RATINGS(1)(2)
PACKAGE 20 Pin PWP with solder 20 Pin PWP without solder THERMAL IMPEDANCE JUNCTION-TO-AMBIENT 26 °C/W 57.5 °C/W TA = 25°C POWER RATING 3.85 W(3) 1.73 W TA = 70°C POWER RATING 2.12 W 0.96 W TA = 85°C POWER RATING 1.54 W 0.69 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002. (2) Test board conditions: 1. 3" x 3", 2 layers, thickness: 0.062" 2. 1.5 oz. copper traces located on the top of the PCB 3. 1.5 oz. copper ground plane on the bottom of the PCB 4. 10 thermal vias (see "Recommended Land Pattern" in applications section of this data sheet) (3) Maximum power dissipation may be limited by over current protection.
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TPS54373
SLVS455A - JANUARY 2003 - REVISED JUNE 2003
ELECTRICAL CHARACTERISTICS
TJ = -40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted) PARAMETER SUPPLY VOLTAGE, VIN Input voltage range, VIN fs = 350 kHz, SYNC 0.8 V, RT open, PH pin open I(Q) Quiescent current fs = 550 kHz, SYNC 2.5 V, RT open, PH pin open Shutdown, SS/ENA = 0 V UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO Stop threshold voltage, UVLO Hysteresis voltage, UVLO Rising and falling edge deglitch, UVLO(1) BIAS VOLTAGE Output voltage, VBIAS Output current, VBIAS (2) CUMULATIVE REFERENCE Vref Accuracy REGULATION Line regulation(1)(3) Load regulation(1)(3) OSCILLATOR Internally set--free running frequency SYNC 0.8 V, SYNC 2.5 V, RT open RT open 280 440 252 460 663 2.5 0.8 50 330 0.75 1 200 90% 700 350 550 280 500 700 420 660 308 540 762 V V ns kHz V V ns kHz kHz IL = 1.5 A,fs = 350 kHz, TJ = 85°C IL = 1.5 A,fs = 550 kHz, TJ = 85°C IL = 0 A to 3 A, fs = 350 kHz, TJ = 85°C IL = 0 A to 3 A, fs = 550 kHz, TJ = 85°C 0.882 0.891 0.900 0.07 0.07 0.03 0.03 V I(VBIAS) = 0 2.70 2.80 2.90 100 V µA 2.70 0.14 2.95 2.80 0.16 2.5 3.0 V V V µs 3.0 6.2 8.4 1 6.0 9.6 12.8 1.4 mA V TEST CONDITIONS MIN TYP MAX UNIT
%/V %/A
RT = 180 k (1% resistor to AGND)(1) Externally set--free running frequency range High level threshold, SYNC Low level threshold, SYNC Pulse duration, external synchronization, SYNC(1) Frequency range, SYNC(1) Ramp valley(1) Ramp amplitude (peak-to-peak)(1) Minimum controllable on time(1) Maximum duty cycle (1) Specified by design (2) Static resistive loads only (3) Specified by the circuit used in Figure 10 RT = 100 k (1% resistor to AGND) RT = 68 k (1% resistor to AGND)(1)
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