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Details, datasheet, quote on part number:TPS40020PWPR
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| Part: | TPS40020PWPR |
| Category: | Power Management => DC-DC Converters => DC-DC Switching |
| Description: | Enhanced Low Input Voltage (2.25V-5.5V) Buck<<<>>>dc-to-dc Controllers Are Designed For Non-isolated Synchronous Buck Regulators, Providing Enhanced Operation And Design Flexability Through User Programmability.<<<>>>features<<<>>>operating Input Voltage 2.25 V to 5.5 V <<<>>>Output Voltage as Low as 0.7 V <<<>>>1% Internal 0.7 V Reference <<<>>>Predictive Gate Drive N-channel MOSFET Drivers For Higher Efficiency <<<>>>Externally Adjustable Soft-start And Short Circuit Current Limit <<<>>>Programmable Fixed-frequency 100 KHz-to-1 MHZ Voltage-mode Control <<<>>>Source-Only Current or Source/sink Current <<<>>>Quick Response Output Transient Comparators With Power Good Indication Provide Output Status <<<>>>16-Pin Powerpad Package <<<>>>APPLICATIONS <<<>>>Networking Equipment <<<>>>Telecom Equipment <<<>>>Base Stations <<<>>>Servers <<<>>>DSP Power |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download TPS40020PWPR datasheet File size : 361 kB |
| Request For quote: | Find where to buy TPS40020PWPR
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Datasheet text preview:
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TPS40020 TPS40021
SLUS535B - MARCH 2003 - REVISED JANUARY 2004
ENHANCED, LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER
FEATURES D D D D
Operating Input Voltage 2.25 V to 5.5 V Output Voltage as Low as 0.7 V 1% Internal 0.7 V Reference Predictive Gate Drive N-Channel MOSFET Drivers for Higher Efficiency Circuit Current Limit
DESCRIPTION
The TPS4002x family of dc-to-dc controllers are designed for non-isolated synchronous buck regulators, providing enhanced operation and design flexability through user programmability. The TPS4002x utilizes a proprietary Predictive Gate Drive technology to minimize the diode conduction losses associated with the high-side and synchronous rectifier N-channel MOSFET transistions. The integrated charge pump with boost circuit provides a regulated 5-V gate drive for both the high side and synchronous rectifier N-channel MOSFETs. The use of the Predictive Gate Drive technology and charge pump/boost circuits combine to provide a highly efficient, smaller and less expensive converter. Design flexibility is provided through user programmability of such functions as: operating frequency, short circuit current detection thresholds, soft-start ramp time, and external synchronization frequency. The operating frequency is programmable using a single resistor over a frequency range of 100 kHz to 1 MHz. Higher operating frequencies yield smaller component values for a given converter power level as well as faster loop closure.
D Externally Adjustable Soft-Start and Short D Programmable Fixed-Frequency
100 KHz-to-1 MHz Voltage-Mode Control
D Source-Only Current or Source/Sink Current D Quick Response Output Transient
Comparators with Power Good Indication Provide Output Status
D 16-Pin PowerPAD Package APPLICATIONS D D D D D
Networking Equipment Telecom Equipment Base Stations Servers DSP Power
VDD VDD 2.25 V - 5.5 V 1 VOUT 2 3 4 5 6 7 8 TPS40020 ILIM/ SYNC VDD OSNS FB COMP SS/SD RT SGND BOOT1 16 HDRV SW BOOT2 PVDD LDRV PGND 15 14 13 12 11 10
VOUT
PWRGD 9
UDG-02094
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and Predictive Gate Drive are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TPS40020 TPS40021
SLUS535B - MARCH 2003 - REVISED JANUARY 2004
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DESCRIPTION (CONTINUED)
The short circuit current detection is programmable through a single resistor, allowing the short circuit current limit detection threshold to be easily tailored to accommodate different size (RDS(on)) MOSFETs. The short circuit current function provides pulse-by-pulse current limiting during soft-start and short term transient conditions as well as a fault counter to handle longer duration short circuit current conditions. If a fault is detected the controller shuts down for a period of time determined by six (6) consecutive soft-start cycles. The controller automatically retries the output every seventh (7th) soft-start cycle. In addition to determining the off time during a fault condition, the soft-start ramp provides a closed loop controlled ramp of the converter output during startup. Programmability allows the ramp rate to be adjusted for a wide variety of output L-C component values.
The output voltage transient comparators provide a quick response , first strike, approach to output voltage transients. The output voltage is sensed through a resistor divider at the OSNS pin. If an overvoltage condition is detected the HDRV gate drive is shut-off and the LDRV gate drive is turned on until the output is returned to regulation. Similarly, if an output undervoltage condition is sensed the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. In either case, the PowerGood open drain output pulls low to indicate an output voltage out of regulation condition. The PowerGood output can be daisy-chained to the SS/SD pin or enable pin of other controllers or converters for output voltage sequencing. The transient comparators can be disabled by simply tying the OSNS pin to VDD. The TPS4002x can be externally synchronized through the ILIM/SYNC pin up to 1.5× the free-running frequency. This allows multiple contollers to be synchronized to eliminate EMI concerns due to input beat frequencies between controllers.
INTERNAL BLOCK DIAGRAM
VDD OSNS
2 3
VDD 0.719 V VDD SS ACTIVE 0.659 V CHARGE PUMP 13 12 16 PREDICTIVE GATE DRIVE(tm) PWM LOGIC UVLO DRV FAULT 10 CLK SS ACTIVE CURRENT LIMIT COMPARATOR OC IRT - + SD 0.28 V SYNC UVLO UVLO + + 1V 1 ILIM/SYNC VDD PGND 11 LDRV DRV 15 14 PVDD BOOT2 PVDD BOOT1 HDRV SW
PWRGD
9
FB
4
0.69 V
+ + UVLO OSC CLK
PWM
COMP
5
RT
7
IRT
ISS SS/SD 6
SOFT START
FAULT COUNTER
DCHG UVLO
SGND
8
VDD
DISABLE
VDD
1.4 V
UDG-02092
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TPS40020 TPS40021
SLUS535B - MARCH 2003 - REVISED JANUARY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA - 40°C to 85°C (1) See page 7 for explanation. (2) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40020PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. LOAD CURRENT(1) SOURCE SOURCE/SINK PACKAGE Plastic HTSSOP (PWP)(2) Plastic HTSSOP (PWP)(2) PART NUMBER TPS40020PWP TPS40021PWP
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(4) TPS4002X SS/SD, VDD, PVDD, OSNS BOOT2, BOOT1 Input voltage range, VIN SW SWT (SW transient < 50 ns) FB, ILIM Output voltage range, VOUT Sink current, IS Operating virtual junction temperature range, TJ Storage temperature, Tstg COMP, PWRGD, RT PWRGD -0.3 to 6 VSW + 6 -3.0 to 10.5 -5 -0.3 to 6.0 -0.3 to 6 10 -40 to 125 -55 to 150 °C mA V UNIT
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 (4) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN Input voltage, VIN Operating junction temperature, TJ PWP PACKAGE(5)(6) (TOP VIEW) 2.25 -40 NOM MAX 5.5 85 UNIT V °C
ILIM/SYNC VDD OSNS FB COMP SS/SD RT SGND
1 2 3 4 5 6 7 8
THERMAL PAD
16 15 14 13 12 11 10 9
BOOT1 HDRV SW BOOT2 PVDD LDRV PGND PWRGD
(5) For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002. (6) PowerPADt heat slug must be connected to SGND (Pin 8), or electrically isolated from all other pins.
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