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Details, datasheet, quote on part number:TPS40009DGQR
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Datasheet text preview:
TPS40007 TPS40009
SLUS589A- NOVEMBER 2003 - REVISED MAY 2004
LOW INPUT HIGH EFFICIENCY SYNCHRONOUS BUCK CONTROLLER
FEATURES D Operating Input Voltage 2.25 V to 5.5 V D Output Voltage as Low as 0.7 V D 1% Internal 0.7 V Reference D Predictive Gate Drivet N-Channel MOSFET
Drivers for Higher Efficiency
D Externally Adjustable Soft-Start and D D D D D
Overcurrent Limit Fixed-Frequency Voltage-Mode Control - TPS40007, 300 kHz - TPS40009, 600 kHz Source/Sink with VOUT Prebias 10-Lead MSOP PowerPadt Package for Higher Performance Thermal Shutdown Internal Boostrap Diode
APPLICATIONS D Networking Equipment D Telecom Equipment D Base Stations D Servers D DSP Power D Power Modules DESCRIPTION
The TPS4000x are controllers for low-voltage, non-isolated synchronous buck regulators. These controllers drive an N-channel MOSFET for the primary buck switch, and an N-channel MOSFET for the synchronous rectifier switch, thereby achieving very high-efficiency power conversion. In addition, the device controls the delays from main switch off to rectifier turn-on and from rectifier turn-off to main switch turn-on in such a way as to minimize diode losses (both conduction and recovery) in the synchronous rectifier with TI's proprietary Predictive Gate Drivet technology. The reduction in these losses is significant and increases efficiency. For a given converter power level, smaller FETs can be used, or heat sinking can be reduced or even eliminated.
SIMPLIFIED APPLICATION DIAGRAM
VIN TPS40007 TPS40009 1 2 3 4 ILIM FB COMP SW SS/SD VDD 5 GND LDRV 7 6 8 BOOT 10 HDRV 9
VOUT
UDG-03161
PowerPADt and Predictive Gate Drivet are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, 2004 Texas Instruments Incorporated
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TPS40007 TPS40009
SLUS589A- NOVEMBER 2003 - REVISED MAY 2004
DESCRIPTION (continued)
The current-limit threshold is adjustable with a single resistor connected to the device. The TPS4000x controllers implement a closed-loop soft start function. Startup ramp time is set by a single external capacitor connected to the SS/SD pin. The SS/SD pin is also used for shutdown.
ORDERING INFORMATION
TA -40°C to 85°C (1) FREQUENCY 300 kHz 600 kHz PACKAGED DEVICES MSOP(1) (DGQ) TPS40007DGQ TPS40009DGQ
The DGQ package is available taped and reeled. Add R suffix to device type (e.g. TPS40007DGQR) to order quantities of 2,500 devices per reel and 80 units per tube.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(2) TPS4000x BOOT COMP, FB, ILIM, SS/SD Input voltage range, VIN SW SWT (SW transient < 50 ns) VDD Operating junction temperature range, TJ Storage temperature, Tstg VSW + 6.5 -0.3 to 6 -3 to 10.5 -5 6 -40 to 150 -55 to 150 °C V UNIT
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DGQ PACKAGE(3)(4) (TOP VIEW)
ILIM FB COMP SS/SD GND
1 2 3 4 5
10 9 8 7 6
BOOT HDRV SW VDD LDRV
ACTUAL SIZE 3,05mm x 4,98mm (3) (4) See technical brief SLMA002 for PCB guidelines for PowerPAD packages. PowerPADt heat slug should be connected to GND (pin 5).
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TPS40007 TPS40009
SLUS589A- NOVEMBER 2003 - REVISED MAY 2004
ELECTRICAL CHARACTERISTICS
temperature range, TA = -40_C to 85_C, VDD = 5.0 V, TA = TJ; all parameters measured at zero power dissipation (unless otherwise noted)
PARAMETER INPUT SUPPLY VDD VHGATE IDD UVLO Input voltage range High-side gate voltage Shutdown current Quiescent current Switching current Minimum on-voltage Hysteresis OSCILLATOR TPS40007 fOSC VRAMP PWM Maximum duty cycle(2) Minimum duty cycle Minimum controllable pulse width(1)(3) ERROR AMPLIFIER Line, VFB IFB VOH VOL IOH IOL GBW FB input voltage FB input bias current High-level output voltage Low-level output voltage Output source current Output sink current Gain bandwidth(1) FB = 0 V, FB =VDD, COMP = 0.7 V, COMP = 0.7 V, IOH = 1.0 mA IOL = 0.5 mA FB = GND FB = VDD 2.0 2 3 5 55 VDD = 5 V VDD = 2.25 V 2.25 V VDD 5.00 VDD = 3.3 V 11 9.5 -20 2 220 100 6 Temperature 0.690 0.693 0.700 0.700 30 2.5 0.08 6 8 10 85 15 13.0 0 19 16.5 20 VDD 330 mA MHz dB µA µA mV V ns ns 0.15 V 0.711 0.707 130 V nA TA = 25°C 100 TPS40007 TPS40009 FB = 0 V, VDD = 3.3 V 87.0% 83.0% 94.0% 93.0% 0% 150 ns Oscillator frequency Ramp voltage Ramp valley voltage TPS40009 2.25 V VDD 5.00 V VPEAK - VVALLEY 250 500 0.80 0.24 300 600 0.93 0.31 350 700 1.07 0.44 V kHz VBOOT - VSW SS/SD = 0 V, FB = 0.8 V No load at HDRV/LDRV 1.95 80 Outputs off 2.25 0.25 1.4 1.5 2.05 150 5.5 6 0.45 2.0 4.0 2.15 220 V mV mA V TEST CONDITIONS MIN TYP MAX UNIT
AOL Open loop gain SHORT CIRCUIT CURRENT PROTECTION ISINK ISINK VOS VILIM tON ILIM sink current ILIM sink current Offset voltage SW vs ILIM(1) Input voltage range Minimum HDRV pulse time in overcurrent SW leading edge blanking pulse in overcurrent detection(1)
tSS Soft-start capacitor cycles as fault timer(1) (1) Ensured by design. Not production tested. (2) Derate the maximum duty cycle by 3% for VDD < 3 V (3) Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses.
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