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Details, datasheet, quote on part number:TPIC6C595
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Datasheet text preview:
TPIC6C595 POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A JULY 1998 REVISED JULY 1999
D D D D D D D D
Low rDS(on) . . . 7 Typ Avalanche Energy . . . 30 mJ Eight Power DMOS Transistor Outputs of 100-mA Continuous Current 250-mA Current Limit Capability ESD Protection . . . 2500 V Output Clamp Voltage . . . 33 V Devices Are Cascadable Low Power Consumption
D OR N PACKAGE (TOP VIEW)
VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 CLR G
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
GND SRCK DRAIN7 DRAIN6 DRAIN5 DRAIN4 RCK SER OUT
description
The TPIC6C595 is a monolithic, medium-voltage, low-current power 8-bit shift register designed for use in systems that require relatively moderate load power such as LEDs. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other low-current or medium-voltage loads. logic symbol
G RCK CLR SRCK SER IN 8 10 7 15 2 R EN3 C2 SRG8 C1 1D 2 3 4 DRAIN0 DRAIN1
This device contains an 8-bit serial-in, parallel-out 5 DRAIN2 shift register that feeds an 8-bit D-type storage 6 DRAIN3 register. Data transfers through both the shift and 11 storage registers on the rising edge of the shift DRAIN4 12 register clock (SRCK) and the register clock DRAIN5 13 (RCK), respectively. The device transfers data out DRAIN6 the serial output (SER OUT) port on the rising 14 DRAIN7 2 edge of SRCK. The storage register transfers data 9 SER OUT to the output buffer when shift register clear (CLR) is high. When CLR is low, the input shift register is This symbol is in accordance with ANSI/IEEE Std 91-1984 cleared. When output enable (G) is held high, all and IEC Publication 617-12. data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The SER OUT allows for cascading of the data from the shift register to additional devices.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
TPIC6C595 POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A JULY 1998 REVISED JULY 1999
description (continued)
Outputs are low-side, open-drain DMOS transistors with output ratings of 33 V and 100 mA continuous sink-current capability. Each output provides a 250-mA maximum current limit at TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection. The device also provides up to 2500 V of ESD protection when tested using the human-body model and 200 V machine model. The TPIC6C595 is characterized for operation over the operating case temperature range of 40°C to 125°C.
logic diagram (positive logic)
G8 10 RCK 7 CLR D SRCK SER IN 15 2 C1 CLR D C2 CLR 4 DRAIN1
3
DRAIN0
D C1 CLR
D C2 CLR 5 DRAIN2
D C1 CLR
D C2 CLR 6 DRAIN3
D C1 CLR
D C2 CLR 11 DRAIN4
D C1 CLR
D C2 CLR 12 DRAIN5
D C1 CLR
D C2 CLR 13 DRAIN6
D C1 CLR
D C2 CLR 14 DRAIN7
D C1 CLR
D C2 CLR 9
16 SER OUT
GND
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TPIC6C595 POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A JULY 1998 REVISED JULY 1999
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT VCC TYPICAL OF ALL DRAIN OUTPUTS
DRAIN 33 V
Input 25 V 12 V 20 V
GND GND
absolute maximum ratings over recommended operating case temperature range (unless otherwise noted)
Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 250 mA Continuous drain current, each output, all outputs on, ID, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Peak drain current single output, IDM,TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Each power DMOS source is internally connected to GND. 3. Pulse duration 100 µs and duty cycle 2%. 4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 4). DISSIPATION RATING TABLE PACKAGE D N TC 25°C POWER RATING 1087 mW 1470 mW DERATING FACTOR ABOVE TC = 25°C 8.7 mW/°C 11.7 mW/°C TC = 125°C POWER RATING 217 mW 294 mW
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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