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Details, datasheet, quote on part number:TPIC6B596DW
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Datasheet text preview:
TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 MARCH 2000
D D D D D D D D
Low rDS(on) . . . 5 Avalanche Energy . . . 30 mJ Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage . . . 50 V Enhanced Cascading for Multiple Stages All Registers Cleared With Single Input Low Power Consumption
DW OR N PACKAGE (TOP VIEW)
description
The TPIC6B596 is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other mediumcurrent or high-voltage loads.
NC VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 SRCLR G GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
NC GND SER OUT DRAIN7 DRAIN6 DRAIN5 DRAIN4 SRCK RCK GND
NC No internal connection
logic symbol
G RCK SRCLR SRCK 9 12 8 13 R EN3 C2 SRG8 C1
This device contains an 8-bit serial-in, parallel-out 4 3 DRAIN0 2 1D SER IN shift register that feeds an 8-bit D-type storage 5 register. Data transfers through both the shift and DRAIN1 6 storage registers on the rising edge of the DRAIN2 7 shift-register clock (SRCK) and the register clock DRAIN3 (RCK), respectively. The storage register 14 DRAIN4 transfers data to the output buffer when shift15 DRAIN5 register clear (SRCLR) is high. When SRCLR is 16 low, all registers in the device are cleared. When DRAIN6 17 output enable (G) is held high, all data in the DRAIN7 2 18 output buffers is held low and all drain outputs are SER OUT off. When G is held low, data from the storage register is transparent to the output buffers. When This symbol is in accordance with ANSI/IEEE Std 91-1984 data in the output buffers is low, the DMOSand IEC Publication 617-12. transistor outputs are off. When data is high, the DMOS-transistor outputs have sink-current capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sinkcurrent capability. Each output provides a 500-mA typical current limit at TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection. The TPIC6B596 is characterized for operation over the operating case temperature range of 40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
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TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 MARCH 2000
logic diagram (positive logic)
G RCK SRCLR 9 12 8 D SRCK SER IN 13 C1 CLR 3 D C1 CLR D C2 CLR 6 DRAIN2 D C2 CLR 5 DRAIN1 4 DRAIN0
D C1 CLR
D C2 CLR 7 DRAIN3
D C1 CLR
D C2 CLR 14 DRAIN4
D C1 CLR
D C2 CLR 15 DRAIN5
D C1 CLR
D C2 CLR 16 DRAIN6
D C1 CLR
D C2 CLR 17 DRAIN7
D C1 CLR
D C2 CLR 10, 11, 19 GND
D C1 CLR 18 SER OUT
2
POST OFFICE BOX 655303
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TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 MARCH 2000
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT VCC TYPICAL OF ALL DRAIN OUTPUTS
DRAIN 50 V
Input 25 V 12 V 20 V
GND GND
absolute maximum ratings over recommended operating case temperature range (unless otherwise noted)
Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 500 mA Continuous drain current, each output, all outputs on, ID, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Peak drain current single output, IDM,TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Each power DMOS source is internally connected to GND. 3. Pulse duration 100 µs and duty cycle 2%. 4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 200 mH, IAS = 0.5 A (see Figure 4). DISSIPATION RATING TABLE PACKAGE DW N TC 25°C POWER RATING 1389 mW 1050 mW DERATING FACTOR ABOVE TC = 25°C 11.1 mW/°C 10.5 mW/°C TC = 125°C POWER RATING 278 mW 263 mW
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