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Details, datasheet, quote on part number:TPIC6B259DWR
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Datasheet text preview:
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 APRIL 1994 REVISED JULY 1995
D D D D D D D
Low rDS(on) . . . 5 Typical Avalanche Energy . . . 30 mJ Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage . . . 50 V Four Distinct Function Modes Low Power Consumption
DW OR N PACKAGE (TOP VIEW)
description
This power logic 8-bit addressable latch controls open-drain DMOS-transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multifunctional device capable of storing single-line data in eight addressable latches and 3-to-8 decoder or demultiplexer with active-low DMOS outputs.
NC VCC S0 DRAIN0 DRAIN1 DRAIN2 DRAIN3 S1 GND GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
NC CLR D DRAIN7 DRAIN6 DRAIN5 DRAIN4 G S2 GND
NC No internal connection FUNCTION TABLE INPUTS CLR G H H H L L L H L D H L X H OUTPUT OF ADDRESSED DRAIN L H Qio L EACH OTHER DRAIN Qio Qio Qio H FUNCTION Addressable Latch Memory 8-Line
Four distinct modes of operation are selectable by L LL Demultiplexer H H controlling the clear (CLR) and enable (G) inputs L HX H H Clear as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) LATCH SELECTION TABLE terminal is written into the addressed latch. The SELECT INPUTS DRAIN addressed DMOS-transistor output inverts the ADDRESSED S2 S1 S0 data input with all unaddressed DMOS-transistor L L L 0 outputs remaining in their previous states. In the L L H 1 memory mode, all DMOS-transistor outputs L H L 2 L H H remain in their previous states and are unaffected 3 H L L 4 by the data or address inputs. To eliminate the H L H 5 possibility of entering erroneous data in the latch, H H L 6 enable G should be held high (inactive) while the H H H 7 address lines are changing. In the 3-to-8 decoding H = high level, L = low level or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are off. In the clear mode, all outputs are off and unaffected by the address and data inputs. When data is low for a given output, the DMOS-transistor output is off. When data is high, the DMOS-transistor output has sink-current capability. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink-current capability. Each output provides a 500-mA typical current limit at TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection. The TPIC6B259 is characterized for operation over the operating case temperature range of 40°C to 125°C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 APRIL 1994 REVISED JULY 1995
logic symbol
S0 S1 S2 G D CLR 3 8 12 13 18 19 2 G8 Z9 Z10 0 8M 0/7
9,0D 10,0R 9,1D 10,1R 9,2D 10,2R 9,3D 10,3R 9,4D 10,4R 9,5D 10,5R 9,6D 10,6R 9,7D 10,7R This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
DRAIN0
5
DRAIN1
6
DRAIN2
7
DRAIN3
14
DRAIN4
15
DRAIN5
16
DRAIN6
17
DRAIN7
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 APRIL 1994 REVISED JULY 1995
logic diagram (positive logic)
4 DRAIN0 S0 3 D C1 CLR 5 DRAIN1 D C1 CLR 6 DRAIN2 D S1 8 C1 CLR 7 DRAIN3 D C1 CLR S2 12 D C1 CLR 15 DRAIN5 D C1 CLR 16 DRAIN6 D C1 CLR 18 D D G CLR 13 19 C1 CLR 9,10,11 GND 17 DRAIN7 14 DRAIN4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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