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Details, datasheet, quote on part number:TP3056BDW
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| Part: | TP3056BDW |
| Category: | Communication => Telephony => Codecs/Voice Codecs => POTS and Linecard Codecs |
| Description: | ti TP3056B, U-law And A-law, Single-ended Output, 2.048 MHZ |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download TP3056BDW datasheet File size : 294 kB |
| Request For quote: | Find where to buy TP3056BDW
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Datasheet text preview:
TP3056B MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
SLWS072A MAY 1998 REVISED AUGUST 1998
D
Complete PCM Codec and Filtering Systems Include: Transmit High-Pass and Low-Pass Filtering Receive Low-Pass Filter With (sin x)/x Correction Active RC Noise Filters µ-Law and A-Law Compatible Coder and Decoder Internal Precision Voltage Reference Serial I/O Interface Internal Autozero Circuitry
D D D D D D D
µ-Law/A-Law Operation Pin-Selectable ± 5 -V Operation Low Operating Power . . . 60 mW Typ Power-Down Mode . . . 5 mW Typ Automatic Power Down TTL- or CMOS-Compatible Digital Interface Maximizes Line Interface Card Circuit Density
description
The TP3056B monolithic serial interface combined PCM codec and filter device is comprised of a single-chip PCM codec (pulse code-modulated encoder and decoder) and analog filters. This device provides all the functions required to interface a full-duplex (2-wire) voice telephone circuit with a TDM (time-division-multiplexed) system. Primary applications include:
DW OR N PACKAGE (TOP VIEW)
VBB ANLG GND VFRO VCC FSR DR ASEL PDN
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VFXI + VFXI GSX TSX FSX DX BCLK MCLK
· · · · ·
Line interface for digital transmission and switching of T1/E1 carrier, PABX, and central office telephone systems Subscriber line concentrators Digital-encryption systems Digital voice-band data-storage systems Digital signal processing
The TP3056B is designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A conversion), and the appropriate filtering of analog signals in a PCM system. This device is intended to be used at the analog termination of a PCM line or trunk. It requires a master clock of 2.048 MHz, a transmit/receive data clock that is synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive frame-sync pulses. The TP3056B contains patented circuitry to achieve low transmit channel idle noise and is not recommended for applications in which the composite signals on the transmit side are below 55 dBm0. This device, available in 16-pin N PDIP (plastic dual-in-line package) and 16-pin DW SOIC (small outline IC) packages, is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
TP3056B MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
SLWS072A MAY 1998 REVISED AUGUST 1998
functional block diagram
14 GSX 15 VFXI 16 VFXI + Voltage Reference +
Analog Input
RC Active Filter
SwitchedCapacitor Band-Pass Filter
S/H DAC
Transmit Regulator OE
11 Digital DX Output
Analog Output
3 VFRO Power Amplifier
RC Active Filter
SwitchedCapacitor Low-Pass Filter
S/H DAC
Receive Regulator CLK
6 DR
Digital Input
Timing and Control 5V 4 VCC 1 VBB 5 V 9 2 ANLG GND MCLK PDN BCLK ASEL FSR FSX 8 10 7 5 12
13 TSX
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TP3056B MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
SLWS072A MAY 1998 REVISED AUGUST 1998
Terminal Functions
TERMINAL NAME ANLG GND ASEL BCLK DR DX FSR FSX GSX MCLK PDN TSX VBB VCC VFRO VFXI + VFXI NO. 2 7 10 6 11 5 12 14 9 8 13 1 4 3 16 15 O I I I I I O I I O I I O I/O DESCRIPTION Analog ground. All signals are referenced to ANLG GND. A-law/µ-law select. When ASEL is connected to VCC, A-law is selected. When ASEL is connected to GND or VBB, µ-law is selected. Transmit/receive bit clock. BCLK shifts PCM data out on DX during transmit and shifts PCM data in through DR during receive. BCLK can vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLK. Receive data input. PCM data is shifted into DR at the trailing edge of the BCLK following the FSR leading edge. DX is the 3-state PCM data output that is enabled by FSX. Data is shifted out on the rising edge of BCLK. Receive-frame sync pulse input. FSR enables BCLK to shift PCM data in DR. FSR is an 8-kHz pulse train (see Figures 1 and 2 for timing details). Transmit-frame sync pulse. FSX enables BCLK to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see Figures 1 and 2 for timing details). Analog output of the transmit input amplifier. GSX is used to set gain externally. Transmit/receive master clock. MCLK must be 2.048 MHz. Power down. When PDN is connected high, the device is powered down. When PDN is connected low or left floating, the device is powered up. PDN is internally tied low. Transmit channel time-slot strobe. TSX is an open-drain output that pulses low during the encoder time slot. Negative power supply. VBB = 5 V ± 5% Positive power supply. VCC = 5 V ± 5% Analog output of the receive channel power amplifier Noninverting input of the transmit input amplifier Inverting input of the transmit input amplifier
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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