Details, datasheet, quote on part number: TLK2208AGPV
PartTLK2208AGPV
CategoryCommunication => Fiber Optics => Transceivers => Gigabit Ethernet/Fibre Channel Transceivers
TitleGigabit Ethernet/Fibre Channel Transceivers
Descriptionti TLK2208A, Octal Gigabit Ethernet Transceiver
CompanyTexas Instruments, Inc.
DatasheetDownload TLK2208AGPV datasheet
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Features, Applications

(Gbps) Synchronizable Transceivers Low Power Consumption at 1.25 Gbps IEEE 802.3z Gigabit Ethernet Compliant Differential VML Transmit Outputs With No External Components Necessary. PECL Compatible Levels Programmable High-Speed Output Preemphasis Levels Selectable Parallel Interface Modes: - Nibble-Wide Double Data Rate (DDR) Clocking Interface - Multiplexed Channel DDR Clock Interface Selectable Clock Tolerance Compensation Selectable On-Chip 8b/10b IEEE 802.3z Compliant Encoder and Decoder JEDEC-Compliant 1.8-V LVCMOS (Extendable 2.5 V)

D 3.6-V Tolerant Inputs on Parallel I/O D Internal Series Termination on LVCMOS D Comprehensive Suite of Built-In

Outputs to Drive 50- Lines Testability Features (PRBS Generation and Verification, Serial Loopback, and Far-End Loopback) IEEE 802.3 Clause 22 Management Data Interface (MDIO) Support IEEE 1149.1 JTAG Support Hot-Plug Protection on Serial I/O No External Filter Components Required for PLLs Small Footprint 289-Terminal, 1,0-mm Ball-Pitch BGA Advanced Low-Power 0.18-m CMOS Technology Commercial Temperature Rating to 70C)

description

The TLK2208A is the third generation of Gigabit Ethernet transceivers from Texas Instruments combining high port density and ultralow power in a small form-factor footprint. The TLK2208A provides for high-speed full-duplex point-to-point data transmissions based on the IEEE 802.3z 1000-Mbps Ethernet specification. The TLK2208A supports data rates from 1.0 Gbps through 1.3 Gbps. The primary application of this device is to provide building blocks for developing point-to-point baseband data transmission over controlled impedance media of 50. The transmission media can be printed circuit board traces, copper cables or fiber-optical interface modules. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The TLK2208A performs the data encoding, decoding, serialization, deserialization, clock extraction, and clock tolerance compensation functions for a physical layer interface device. Each channel operates to 1.3 Gbps providing to 8.32 Gbps of aggregate data bandwidth over copper or optical-media interfaces. The TLK2208A supports two selectable reduced-pin-count double-data-rate (DDR) timing interfaces, nibble mode and multiplexed channel mode, to a protocol device. In the nibble interface mode, the parallel interface accepts nibble-wide unencoded or 8b/10b encoded data aligned to both the rising and falling edges of the transmit clock. In the multiplexed channel mode, the parallel interface accepts 8-bit-wide unencoded 10-bit-wide 8b/10b encoded data with channels C, E, and G aligned to the falling edge of the source synchronous transmit clock and channels D, F, and H aligned to the rising edge of the transmit clock. The receive path interface is done in the same manner.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

The TLK2208A aligns the recovered data clock frequency to the reference clock on each channel by means of a clock tolerance compensation circuit and internal FIFO that inserts or drops 20-bit IDLE codes as needed in the interpacket gap (IPG). In synchronous mode, the received data for all channels is aligned to a single receive data clock that is a buffered version of the reference clock. The TLK2208A supports a selectable IEEE 802.3z compliant 8b/10b encoder/decoder in all its modes of operation.

The TLK2208A automatically locks onto incoming data without the need to pre-lock.

The TLK2208A provides a comprehensive series of built-in tests for self-test purposes including loopback and PRBS generation and verification. An IEEE 1149.1 JTAG port is also supported to aid in board-manufacturing testing. The TLK2208A is housed in a small form-factor 1919-mm, 289-terminal BGA with 1,0-mm ball pitch. The ball out and footprint are compatible with those of the PMC-Sierra PM8352 8-channel transceiver. The TLK2208A is characterized to support the commercial temperature range to 70C. The TLK2208A consumes 1.3 W when operating at nominal conditions. The TLK2208A is designed to be hot-plug capable. A power-on reset puts the serial side output signal terminals TX+/TX- in the high-impedance state during power up.

Line Card RCLK 8 RX+ RDA..H[9:0] RX- TLK2208A MAC/ Packet Processor TCLKB 8


 

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