|Category||Interface and Interconnect|
|Description||Futurebus+ I/o Controller|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TFB2002BI datasheet
Industrial Temperature Version of the TFB2002B With an Operating Range to 85°C Provides Control Logic Necessary to Operate a Data Path Unit (TFB2022A) on Futurebus+ Parallel-Protocol Support Is Fully Compliant to Futurebus+ Standard (IEEE Std 896.11991) Interfaces Easily to a Variety of Popular Microprocessors Such as SPARCTM, 88xxx, 80x86, and Alpha AXPTM
Provides Full Support for Futurebus+ Cache Commands (for Memory or I/O Modules in Shared-Memory Systems) Capable of Handling a Single Outstanding Split Transaction Parallel-Protocol-Related CSR Locations Are Provided on Chip Offers Autonomous Control for Futurebus+ and Host-Module Reads and Writesdescription
The TFB2002BI I/O controller (IOC) is a member of the Texas Instruments Futurebus+ (FB+) chip set. This chip set provides a highly integrated approach to the Futurebus+ interface that reduces new-product design time, allows more functionality per circuit board, improves overall interface reliability, and reduces end-user down time through built-in test capabilities. The Futurebus+ chip set is capable of supporting or 64-bit data widths in any combination on both the host-bus interface (HIF) and Futurebus+. The address width is programmable be 32 bits or 36 bits (with either data width). The TFB2002BI contains the control logic necessary to translate Futurebus+ transactions into host bus transactions and vice versa. It contains a high-speed Futurebus+ handshake controller, a synchronous host bus controller, and reset-type determination logic. When combined with a TFB2022A Futurebus+ data path unit (DPU), the TFB2002BI provides a complete 64-bit-wide interface to the Futurebus+. The TFB2002BI provides the necessary control logic for the data path unit to provide a complete interface to the Futurebus+ for a Profile-B-compliant module. It may also be used on I/O or memory modules in a cache-coherent system. The TFB2002BI is offered a 208-pin plastic quad flat package (PPM). The TFB2002BI is characterized for operation over the industrial temperature range to 85°C.
NOTE: To maintain consistency with the notation used in the Futurebus+ standard (IEEE Std 11991), an active-low signal is denoted herein by use of the trailing asterisk on the signal name. SPARC is a trademark of Sun Microsystems, Inc. Alpha AXP is a trademark of Digital Equipment Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TSIZE1 TSIZE0 HSTRB* Vcc HMODE1 HMODE0 GND HADEC2 HADEC1 Vcc HADEC0 HAS* HIP* GND DMAMODE DATAAV* SPACEAV* Vcc NEWADDR* TR/W* DL1 GND DSACK1* DSACK0* Vcc FADEC2 FADEC1 GND FMODE2 FMODE1 Vcc FMODE0 FRD* FSTRB GND FACK SELECTED* BSTRDY* Vcc ADRCV ADDRV* GND STO7 STI7 GND STO6 STI6 POST OFFICE BOX 655303
TERMINAL NAME BSTAT< 1:0 NO. 206 207 I/O FROM/TO Host interface Host-interface status: LH LL I/O I I/O Host interface Host interface Host interface Normal Reserved Bus error Backoff/retry B k ff/ t DESCRIPTION
Burst ready Clock input. CLK is the processor clock for synchronous transactions on the host side. to 25 MHz is recommended. Host-interface data length: HH 64 bytes y 32 bytes 16 bytes 8 bytes b t Burst mode (TBST* = low): HL HH speed, 32-bit capable Low s eed, 32 bit burst ca able g speed, , 32-bit burst capable High Low speed, 64-bit burst capable High speed, 64-bit burst capable
Data acknowledge: Single mode (TBST* = high): HL HH Complete Com lete cycle, data bus port 32 Reserved Insert wait stateDW64* HAS* HBG* HBGACK* HBR* HDS* HIP* IGNORE*
Host interface Host interface Host interface Host interface Host interface Host interface Host interface Host interface
Host-interface data width of 64 (burst mode only) Host-interface address strobe Host-interface grant input Host-interface grant acknowledge Host-interface request output Host-interface data strobe Host-interface transaction in progress Ignore the current host transaction input. IGNORE* is supplied by the hostmemory decoder when an access to private memory occurs. IGNORE* is optional and should be tied high it is not used. Host interrupt output. When an enabled interrupt condition occurs, INT* is driven low. Interrupts are cleared by writing a one to the appropriate bit in the interrupt register. The interrupt goes high during the write cycle to the interrupt register even if another interrupt is pending. Also used from FB+ 2:0 > lines to a mastered HIF locked operation. These terminals are used as inputs when the IOC is a host-interface slave/FB+ master. Host cycle is locked (indivisible) Locked-command bits passed from the host interface to FB+ or from FB+ to the host interface via the 2:0 > lines during a mastered FB+ data phase in a locked operation. Also used from FB+ 2:0 > lines to a mastered HIF locked operation. These terminals are used as inputs when the IOC is a host interface slave/FB+ master.
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